WO2017197746A1 - 处理向液晶显示器提供的栅极电压信号的电路 - Google Patents

处理向液晶显示器提供的栅极电压信号的电路 Download PDF

Info

Publication number
WO2017197746A1
WO2017197746A1 PCT/CN2016/089796 CN2016089796W WO2017197746A1 WO 2017197746 A1 WO2017197746 A1 WO 2017197746A1 CN 2016089796 W CN2016089796 W CN 2016089796W WO 2017197746 A1 WO2017197746 A1 WO 2017197746A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
switch
level
output
connection end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/089796
Other languages
English (en)
French (fr)
Inventor
黄笑宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/128,193 priority Critical patent/US10170064B2/en
Publication of WO2017197746A1 publication Critical patent/WO2017197746A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present invention relates to a circuit and, more particularly, to a circuit for processing a gate voltage signal supplied to a liquid crystal display.
  • the liquid crystal display in which the gate drive is integrated in the array substrate (GOA) has been attracting attention.
  • the voltage falling speed of the gate voltage signal affects the reference voltage of the liquid crystal display, and the faster the voltage drop of the gate voltage signal affects the reference voltage of the liquid crystal display. The bigger.
  • the gate voltage signal is usually a square wave.
  • a gate driving voltage is supplied to a liquid crystal display through a PCB board, and therefore, a voltage falling speed for reducing a gate voltage signal can be added to the PCB (ie, A chamfering chip that chamfers the gate voltage signal to reduce the influence on the reference voltage of the liquid crystal display.
  • the gate voltage is generated on the array substrate, and there is not enough space to mount the chamfered chip on the substrate, the gate voltage signal cannot be adjusted, thereby affecting the display effect of the liquid crystal display.
  • the existing method of providing a gate voltage signal to a GOA liquid crystal display greatly affects the reference voltage of the liquid crystal display.
  • An exemplary embodiment of the present invention is to provide a circuit that processes a gate voltage signal supplied to a liquid crystal display.
  • the circuit can overcome the drawback that the gate voltage provided by the gate driving integrated on the array substrate (GOA) liquid crystal display greatly affects the reference voltage of the liquid crystal.
  • a circuit for processing a gate voltage signal supplied to a liquid crystal display comprising: an input output unit and a control unit, wherein the input output unit receives the gate voltage signal, and the control unit receives the control And according to the control of the control signal, the input/output unit outputs the first output signal during the first time period in each period based on the gate voltage signal, and outputs the second output signal during the second time period, during the third time period A third output signal is output, and a fourth output signal is output during the fourth time period.
  • the first time period, the second time period, the third time period, and the fourth time period are time-continuous time periods, and durations of the first time, the second time period, and the third time period
  • the sum of the lengths is equal to the duration of the active level of the gate voltage signal
  • the duration of the fourth period of time is equal to the length of the duration of the inactive level of the gate voltage signal.
  • a difference between a voltage value of the first output signal and a voltage value of an active level of the gate signal is within a first predetermined range, and a voltage value of the second output signal is less than a voltage value of the first output signal,
  • the voltage value of the three output signals is less than the voltage value of the second output signal, and the difference between the voltage value of the fourth output signal and the voltage level of the inactive level of the gate signal is within a second predetermined range.
  • control signal includes a first control signal and a second control signal, the period of the first control signal and the period of the second control signal being the same as the period of the gate voltage signal, wherein during the second time period A control signal has a first level and the second control signal has a second level, the first control signal has a second level during the third time period and the second control signal has a first level during other time periods
  • the first control signal and the second control signal each have a first level or both have a second level.
  • the first level is one of a high level and a low level
  • the second level is another level different from the first level in the high level and the low level.
  • the input/output unit includes: a first resistor, the first connection end receives the gate voltage signal, and the second connection end serves as an output first output signal, a second output signal, a third output signal, and a fourth output The output port of the signal.
  • the control unit includes: a first switch, a second switch, a third switch, and a fourth switch, wherein the first connection end of the first switch is connected to the second connection end of the first resistor, the first switch The second connection end is connected to the first connection end of the second switch, the control end of the first switch receives the first control signal, the second connection end of the second switch is grounded, and the control end of the second switch receives the second control signal, a first connection end of the three switch is connected to the second connection end of the first resistor, a second connection end of the third switch is connected to the first connection end of the fourth switch, and the control end of the third switch receives the first control signal, The second connection end of the fourth switch is grounded, and the control end of the fourth switch receives the second control signal.
  • the first switch and the fourth switch are both PMOS tubes, and the second switch and the third switch are both NOMS tubes.
  • the control end is a gate
  • the first connection end is one of a source stage and a drain
  • the second connection end is a source Different in level and drain The other one at the first connection end.
  • the circuit is arranged to drive a fan-out region of the liquid crystal display integrated in the array substrate.
  • a gate voltage signal can be lowered by changing a gate voltage signal to a different value during different periods of each period The voltage drops at a rate that reduces the effect on the reference voltage of the liquid crystal display.
  • FIG. 1 illustrates a block diagram of circuitry for processing a gate voltage signal provided to a liquid crystal display, in accordance with an exemplary embodiment of the present invention
  • FIG. 2 illustrates a circuit diagram of a circuit that processes a gate voltage signal provided to a liquid crystal display, in accordance with an exemplary embodiment of the present invention
  • FIG. 3 illustrates a first equivalent circuit diagram of a circuit that processes a gate voltage signal supplied to a liquid crystal display, in accordance with an exemplary embodiment of the present invention
  • FIG. 4 illustrates a second equivalent circuit diagram of a circuit that processes a gate voltage signal supplied to a liquid crystal display, in accordance with an exemplary embodiment of the present invention
  • FIG. 5 illustrates a diagram of an output signal of a circuit of a gate voltage signal supplied to a liquid crystal display, according to an exemplary embodiment of the present invention
  • FIG. 6 illustrates a circuit diagram of a circuit that processes a gate voltage signal supplied to a liquid crystal display, in accordance with another exemplary embodiment of the present invention
  • FIG. 7 illustrates a diagram of a circuit that processes a gate voltage signal supplied to a liquid crystal display in a liquid crystal display according to an exemplary embodiment of the present invention.
  • FIG. 1 illustrates a block diagram of circuitry for processing a gate voltage signal provided to a liquid crystal display, in accordance with an exemplary embodiment of the present invention.
  • FIG. 7 illustrates a diagram of a circuit for processing a gate voltage signal supplied to a liquid crystal display in a liquid crystal display according to an exemplary embodiment of the present invention.
  • the display panel 1 of the GOA liquid crystal display is connected to the PCB board 3 through the source-level driving chips 2-1, 2-2, 2-3, and 2-4.
  • the gate drive is integrated on the left side of the display area 1-1, that is, the gate voltage signal is supplied from the left side to the liquid crystal display. Therefore, the circuit of the present invention for processing the gate voltage signal supplied to the liquid crystal display can be arranged in the GOA liquid crystal.
  • the fan out area 1-2 on the left side of the display area 1-1 of the display is processed to process the gate voltage signal.
  • the gate voltage signal may be a square wave having a predetermined period.
  • the gate voltage signal can have an active level (eg, a high level) and an inactive level (eg, a low level) in one cycle.
  • the gate voltage signal can have the same period of time as the liquid crystal display displays one frame.
  • a circuit for processing a gate voltage signal supplied to a liquid crystal display includes an input-output unit 10 and a control unit 20.
  • the input-output unit 10 receives the gate voltage signal
  • the control unit 20 receives the control signal and causes the input-output unit 10 to be based on the gate voltage signal during the first time period in each cycle according to the control of the control signal.
  • the first output signal is output
  • the second output signal is output during the second time period
  • the third output signal is output during the third time period
  • the fourth output signal is output during the fourth time period.
  • the control signal received by the control unit 20 may include a first control signal and a second control signal, the period of the first control signal and the period of the second control signal being the same as the period of the gate voltage signal.
  • the first control signal and the second control signal are square waves.
  • the first control signal may have a first level and the second control signal has a second level during the second time period
  • the first control signal may have a second level and a second during the third time period
  • the control signal has a first level during which the first control signal and the second control signal may each have a first level or both have a second level.
  • the first level may be one of a high level and a low level
  • the second level is another level different from the first level in the high level and the low level.
  • the sum of the lengths of time of the first time period, the second time period, the third time period, and the fourth time period is the length of time of one cycle (ie, the period of the signal output by the input-output unit 10), and the length of time is The period of the period of the gate voltage signal is the same.
  • the first time period, the second time period, the third time period, and the fourth time period are time periods that are consecutive in time, and durations of the first time, the second time period, and the third time period The sum is equal to the duration of the active level of the gate voltage signal, and the duration of the fourth period of time is equal to the duration of the inactive level of the gate voltage signal.
  • the voltage value of the first output signal may be close to the voltage value of the active level of the gate voltage signal, and the voltage value of the second output signal and the voltage value of the third output signal may be lower than the effective level of the gate voltage signal.
  • the voltage value, and the voltage value of the fourth output signal can be close to the voltage level of the inactive level of the gate voltage signal, so that the speed of the voltage drop of the gate voltage signal can be reduced.
  • a difference between a voltage value of the first output signal and a voltage value of an active level of the gate signal is within a first predetermined range
  • a voltage value of the second output signal is less than a voltage value of the first output signal
  • a third The voltage value of the output signal is less than the voltage value of the second output signal
  • the difference between the voltage value of the fourth output signal and the voltage value of the inactive level of the gate signal is within a second predetermined range.
  • the input-output unit 10 may include a first resistor. Specifically, the first connection end of the first resistor receives the gate voltage signal, and the second connection end of the first resistor serves as an output first output signal, a second output signal, a third output signal, and a fourth output The output port of the signal.
  • the control unit 20 may include a first switch, a second switch, a third switch, and a fourth switch.
  • the first connection end of the first switch is connected to the second connection end of the first resistor
  • the second connection end of the first switch is connected to the first connection end of the second switch
  • the control end of the first switch receives The first control signal.
  • the second connection end of the second switch is grounded, and the control end of the second switch receives the second control signal.
  • the first connection end of the third switch is connected to the second connection end of the first resistor
  • the second connection end of the third switch is connected to the first connection end of the fourth switch
  • the control end of the third switch receives the first control signal .
  • the second connection end of the fourth switch is grounded, and the control end of the fourth switch receives the second control signal.
  • the first switch and the fourth switch are both PMOS transistors
  • the second switch and the third switch are both NOMS tubes.
  • the control end may be a gate
  • the first connection end may be one of a source stage and a drain
  • the second connection The end may be another one of the source stage and the drain different from the first connection end.
  • FIG. 2 illustrates a circuit diagram of a circuit that processes a gate voltage signal provided to a liquid crystal display, in accordance with an exemplary embodiment of the present invention.
  • the input-output unit 10 may include a first resistor R1, and the first connection end of the first resistor R1 serves as an input port (Input) to receive a gate voltage signal from the point C, the first resistor R1
  • the second connection end serves as an output port for outputting the first output signal, the second output signal, the third output signal, and the fourth output signal.
  • the control unit 20 may include a first PMOS transistor D1, a first NMOS transistor D2, a second NMOS transistor E1, and a second POMS tube E2.
  • the source (or drain) of the first PMOS transistor D1 is connected to the second connection of the first resistor R1, and the drain (or source) of the first PMOS transistor D1 is connected to the source of the first NMOS transistor D2 ( Or the drain), the gate of the first PMOS transistor D1 receives the first control signal A.
  • the drain (or source stage) of the first NMOS transistor D2 is grounded, and the gate of the first NMOS transistor D2 receives the second control signal B.
  • the source (or drain) of the second NMOS transistor E1 is connected to the second connection terminal of the first resistor R1, and the drain of the second NMOS transistor E1 (or source level) is connected to the source stage (or drain) of the second PMOS transistor E2, and the gate of the second NMOS transistor E1 receives the first control signal A.
  • the drain (or source stage) of the second PMOS transistor E2 is grounded, and the gate of the second PMOS transistor E2 receives the second control signal B.
  • the first control signal A and the second control signal B have the same level (eg, during the first time period and the fourth time period in one cycle)
  • the first PMOS transistor D1 of the D branch And the first NMOS transistor D2 is disconnected
  • the second NMOS transistor E1 and the second PMOS transistor E2 of the E branch are both disconnected.
  • the output end of the first resistor R1 can output the voltage value of the gate voltage signal. The voltage value is close.
  • the first PMOS transistor D1 and the first NMOS of the D branch The tube D2 is both turned on and connected to the ground, or the second NMOS tube E1 and the second PMOS tube E2 of the E branch are both turned on and connected to the ground.
  • the first PMOS transistor D1, the first NMOS transistor D2, the second NMOS transistor E1, and the second POMS tube E2 each have a certain resistance value, when the D branch or the E branch is connected to the ground, The voltage at the output port of a resistor R1 will decrease.
  • the D branch when the first control signal A has a low level (eg, 0V) and the second control signal B has a high level (eg, 3.3V) during a second time period in one cycle, the D branch The first PMOS transistor D1 and the first NMOS transistor D2 of the path are both turned on and connected to the ground, and the second NMOS transistor E1 and the second PMOS transistor E2 of the E branch are both disconnected.
  • the circuit for processing the gate voltage signal supplied to the liquid crystal display according to an exemplary embodiment of the present invention is equivalent to the circuit of FIG.
  • FIG. 3 illustrates a first equivalent circuit diagram of a circuit that processes a gate voltage signal supplied to a liquid crystal display, according to an exemplary embodiment of the present invention.
  • the second resistor Rd is the equivalent resistance of the first PMOS transistor D1 of the D branch, the first NMOS transistor D2, and the connection line
  • the third resistor Rc is the first resistor R1 and the first resistor. The equivalent resistance of the connection line between the first connection end of the device R1 and the input port and the connection line between the second connection end and the output port of the first resistor R1.
  • the output port outputs a voltage value of Rd / (Rd + Rc), and therefore, the voltage of the signal output from the output port can be adjusted by adjusting the resistance values of Rc and Rd.
  • the circuit for processing the gate voltage signal supplied to the liquid crystal display is equivalent to the circuit of FIG.
  • FIG. 4 illustrates a second equivalent circuit diagram of a circuit that processes a gate voltage signal supplied to a liquid crystal display, according to an exemplary embodiment of the present invention.
  • the fourth resistor Re is the equivalent resistance of the second NMOS transistor E1 and the second PMOS transistor E2 of the E branch and the connection line
  • the third resistor Rc is the first resistor R1 and the first resistor.
  • the voltage value output by the output port is Re/(Re+Rc), and therefore, the voltage of the signal output from the output port is adjusted by adjusting the resistance values of Rc and Re.
  • the gate voltage signal is a square wave with an active level of 33V and an inactive level of -7V.
  • An example of the output signal output from the input/output unit 10 will be described below by taking the gate voltage signal as an example.
  • FIG. 5 illustrates a diagram of an output signal of a circuit of a gate voltage signal supplied to a liquid crystal display, according to an exemplary embodiment of the present invention.
  • the period of the output signal output from the output port of the input-output unit 10 is T (that is, the period of the gate voltage signal is T).
  • the first control signal A and the second control signal B have the same level, the D branch is disconnected and the E branch is disconnected, and the output voltage of the output port of the input/output unit 10 is close to 33V.
  • An output signal, where the difference between the voltage value of the first output signal and the voltage value of the high level of the gate voltage signal may be within a first predetermined range (eg, (-10%, 0)).
  • the output port of the input-output unit 10 has a second output signal of an output voltage value of approximately 22V.
  • the level of the first control signal A is inverted and the second control signal B is inverted.
  • the first control signal A and the second control signal B are again at the same level, the D branch is disconnected and the E branch is disconnected, and the output voltage value of the output port of the input/output unit 10 is close to -7V.
  • the fourth output signal where the difference between the voltage value of the fourth output signal and the low voltage value of the gate voltage signal may be within a second predetermined range (eg, (-10%, 0)).
  • the voltage value of the effective level of the gate voltage signal and the voltage value of the inactive level shown in FIG. 5 are only examples, and the voltage value and the inactive level of the effective level of the gate voltage signal are according to actual needs.
  • the voltage value can also be other values.
  • the voltage value of the second output signal and the voltage value of the third output signal are also only examples, and the resistance values of the second resistor Rd, the third resistor Rc, and/or the fourth resistor Re may also be changed according to actual needs.
  • the voltage value of the second output signal and the voltage value of the third output signal are changed to other values.
  • FIG. 6 illustrates a circuit diagram of a circuit that processes a gate voltage signal supplied to a liquid crystal display, in accordance with another exemplary embodiment of the present invention.
  • processing a gate provided to a liquid crystal display according to another exemplary embodiment of the present invention
  • the circuit of the pole voltage signal removes the first resistor Rc in FIG. 2, and the line resistance between the input port (Input) and the output port (Output) of the input-output unit 10 is equivalent to the third resistor. Rc, therefore, by adjusting Rd and Re in Figs. 4 and 5, the circuit of Fig. 6 can still be made to output an output signal having the waveform of the output signal in Fig. 5.
  • a gate voltage signal can be lowered by changing a gate voltage signal to a different value during different periods of each period The voltage drops at a rate that reduces the effect on the reference voltage of the liquid crystal display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种处理向液晶显示器提供的栅极电压信号的电路，包括：输入输出单元（10）和控制单元（20），其中，输入输出单元接收所述栅极电压信号（Input），控制单元（20）接收控制信号（A、B）并根据控制信号（A、B）的控制，使输入输出单元（10）基于栅极电压信号（Input）在每个周期内的第一时间段期间（T1）输出第一输出信号，第二时间段期间（T2）输出第二输出信号，第三时间段期间（T3）输出第三输出信号，第四时间段期间（T4）输出第四输出信号。在根据该处理向液晶显示器提供的栅极电压信号的电路中，可通过在每个周期的不同时间段期间将栅极电压信号改变为不同的值来降低栅极电压信号的电压的下降速度，从而降低对液晶显示器的基准电压的影响。

Description

处理向液晶显示器提供的栅极电压信号的电路 技术领域
本发明涉及一种电路，更具体地讲，涉及一种处理向液晶显示器提供的栅极电压信号的电路。
背景技术
随着科技的发展，电子产品的屏幕更加趋于超窄边框的趋势。因此，栅极驱动集成于阵列基板(GOA)的液晶显示器日益受到人们的关注。
在通过栅极电压信号驱动液晶显示器的过程中，栅极电压信号的电压下降速度会对液晶显示器的基准电压造成影响，栅极电压信号的电压下降越快，对液晶显示器的基准电压的影响程度越大。
栅极电压信号通常为方波，在传统的液晶显示器中，通过PCB板向液晶显示器提供栅极驱动电压，因此，可在PCB板上添加用于降低栅极电压信号的电压下降速度(即，对栅极电压信号进行削角)的削角芯片，从而降低对液晶显示器的基准电压的影响。
然而，在GOA液晶显示器中，由于在阵列基板上产生栅极电压，并且没有足够的空间在基板上安装削角芯片，因此，不能对栅极电压信号进行调整，从而影响液晶显示器的显示效果。
因此，现有的向GOA液晶显示器提供栅极电压信号的方式会较大程度影响液晶显示器的基准电压。
发明内容
本发明的示例性实施例在于提供一种处理向液晶显示器提供的栅极电压信号的电路。所述电路能够克服现有的向栅极驱动集成于阵列基板(GOA)液晶显示器提供的栅极电压对液晶器的基准电压造成很大影响的缺陷。
根据本发明示例性实施例，提供一种处理向液晶显示器提供的栅极电压信号的电路，包括：输入输出单元和控制单元，其中，输入输出单元接收所述栅极电压信号，控制单元接收控制信号并根据控制信号的控制，使输入输出单元基于栅极电压信号在每个周期内的第一时间段期间输出第一输出信号，第二时间段期间输出第二输出信号，第三时间段期间输出第三输出信号，第四时间段期间输出第四输出信号。
可选地，第一时间段、第二时间段、第三时间段和第四时间段是在时间上连续的时间段，并且，第一时间、第二时间段和第三时间段的持续时间长度之和与所述栅极电压信号的有效电平的持续时间长度相等，第四时间段的持续时间长度与所述栅极电压信号的无效电平的持续时间长度相等。
可选地，第一输出信号的电压值与所述栅极信号的有效电平的电压值之差在第一预定范围内，第二输出信号的电压值小于第一输出信号的电压值，第三输出信号的电压值小于第二输出信号的电压值，并且第四输出信号的电压值与所述栅极信号的无效电平的电压值之差在第二预定范围内。
可选地，控制信号包括第一控制信号和第二控制信号，第一控制信号的周期和第二控制信号的周期与所述栅极电压信号的周期相同，其中，在第二时间段期间第一控制信号具有第一电平并且第二控制信号具有第二电平，在第三时间段期间第一控制信号具有第二电平并且第二控制信号具有第一电平，在其它时间段期间第一控制信号和第二控制信号均具有第一电平或均具有第二电平。
可选地，第一电平为高电平和低电平之一，第二电平为高电平和低电平中不同于第一电平的另一电平。
可选地，输入输出单元包括：第一电阻器，第一连接端接收所述栅极电压信号，第二连接端作为输出第一输出信号、第二输出信号、第三输出信号和第四输出信号的输出端口。
可选地，控制单元包括：第一开关、第二开关、第三开关和第四开关，其中，第一开关的第一连接端连接到第一电阻器的第二连接端，第一开关的第二连接端连接到第二开关的第一连接端，第一开关的控制端接收第一控制信号，第二开关的第二连接端接地，第二开关的控制端接收第二控制信号，第三开关的第一连接端连接到第一电阻器的第二连接端，第三开关的第二连接端连接到第四开关的第一连接端，第三开关的控制端接收第一控制信号，第四开关的第二连接端接地，第四开关的控制端接收第二控制信号。
可选地，第一开关和第四开关均为PMOS管，第二开关和第三开关均为NOMS管。
可选地，针对第一开关、第二开关、第三开关和第四开关中每个开关：控制端为栅极，第一连接端为源级和漏极之一，第二连接端为源级和漏极中不同 于第一连接端的另外一个。
可选地，所述电路布置于栅极驱动集成于阵列基板的液晶显示器的扇出区域。
在根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路中，可通过在每个周期的不同时间段期间将栅极电压信号改变为不同的值来降低栅极电压信号的电压的下降速度，从而降低对液晶显示器的基准电压的影响。
附图说明
通过下面结合示例性地示出实施例的附图进行的描述，本发明示例性实施例的上述和其他目的和特点将会变得更加清楚，其中：
图1示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的框图；
图2示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的电路图；
图3示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的第一等效电路图；
图4示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的第二等效电路图；
图5示出根据本发明示例性实施例的向液晶显示器提供的栅极电压信号的电路的输出信号的示图；
图6示出根据本发明另一示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的电路图；
图7示出根据本发明示例性实施例的在液晶显示器布置处理向液晶显示器提供的栅极电压信号的电路的示图。
具体实施方式
以下，将参照附图更充分地描述本发明的示例性实施例，示例性实施例在附图中示出。然而，可以以许多不同的形式实施示例性实施例，并且不应被解 释为局限于在此阐述的示例性实施例。相反，提供这些实施例从而本公开将会彻底和完整，并将完全地将示例性实施例的范围传达给本领域的技术人员。
图1示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的框图。
作为示例，本发明的处理向液晶显示器提供的栅极电压信号的电路布置于栅极驱动集成于阵列基板(GOA,Gate on array)的液晶显示器的扇出区域。例如，图7示出根据本发明示例性实施例的在液晶显示器布置处理向液晶显示器提供的栅极电压信号的电路的示图。如图7所示，GOA液晶显示器的显示面板1通过源级驱动芯片2-1、2-2、2-3和2-4连接到PCB板3。栅极驱动集成在显示区域1-1的左侧，即，从左侧向液晶显示器提供栅极电压信号，因此，本发明的处理向液晶显示器提供的栅极电压信号的电路可布置于GOA液晶显示器的显示区域1-1左侧的扇出区域(Fan out area)1-2，从而对栅极电压信号进行处理。
这里，栅极电压信号可以是具有预定周期的方波。栅极电压信号可在一周期内具有有效电平(例如，高电平)和无效电平(例如，低电平)。作为示例，栅极电压信号可具有与液晶显示器显示一帧的时间长度相同的周期。
参照图1，根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路包括：输入输出单元10和控制单元20。
具体地讲，输入输出单元10接收所述栅极电压信号，控制单元20接收控制信号并根据控制信号的控制，使输入输出单元10基于栅极电压信号在每个周期内的第一时间段期间输出第一输出信号，第二时间段期间输出第二输出信号，第三时间段期间输出第三输出信号，第四时间段期间输出第四输出信号。
这里，作为示例，控制单元20接收的控制信号可包括第一控制信号和第二控制信号，第一控制信号的周期和第二控制信号的周期与所述栅极电压信号的周期相同。例如，第一控制信号和第二控制信号为方波。具体地讲，在第二时间段期间第一控制信号可具有第一电平并且第二控制信号具有第二电平，在第三时间段期间第一控制信号可具有第二电平并且第二控制信号具有第一电平，在其它时间段期间第一控制信号和第二控制信号可均具有第一电平或均具有第二电平。这里，作为示例，第一电平可为高电平和低电平之一，第二电平为高电平和低电平中不同于第一电平的另一电平。
这里，第一时间段、第二时间段、第三时间段和第四时间段的时间长度之和为一个周期(即，输入输出单元10输出的信号的周期)的时间长度，该时间长度与栅极电压信号的周期的时间长度相同。
作为示例，第一时间段、第二时间段、第三时间段和第四时间段是在时间上连续的时间段，并且，第一时间、第二时间段和第三时间段的持续时间长度之和与所述栅极电压信号的有效电平的持续时间长度相等，第四时间段的持续时间长度与所述栅极电压信号的无效电平的持续时间长度相等。
这里，第一输出信号的电压值可以与栅极电压信号的有效电平的电压值接近，第二输出信号的电压值和第三输出信号的电压值可低于栅极电压信号的有效电平的电压值，并且第四输出信号的电压值可与栅极电压信号的无效电平的电压值接近，从而可减小栅极电压信号的电压降低的速度。
作为示例，第一输出信号的电压值与所述栅极信号的有效电平的电压值之差在第一预定范围内，第二输出信号的电压值小于第一输出信号的电压值，第三输出信号的电压值小于第二输出信号的电压值，并且第四输出信号的电压值与所述栅极信号的无效电平的电压值之差在第二预定范围内。
在实际应用的电路中，输入输入输出单元10可包括：第一电阻器。具体地讲，第一电阻器的第一连接端接收所述栅极电压信号，第一电阻器的第二连接端作为输出第一输出信号、第二输出信号、第三输出信号和第四输出信号的输出端口。
控制单元20可包括：第一开关、第二开关、第三开关和第四开关。具体地讲，第一开关的第一连接端连接到第一电阻器的第二连接端，第一开关的第二连接端连接到第二开关的第一连接端，第一开关的控制端接收第一控制信号。第二开关的第二连接端接地，第二开关的控制端接收第二控制信号。第三开关的第一连接端连接到第一电阻器的第二连接端，第三开关的第二连接端连接到第四开关的第一连接端，第三开关的控制端接收第一控制信号。第四开关的第二连接端接地，第四开关的控制端接收第二控制信号。
这里，为了根据如上所述的控制信号在不同时间段提供第一输出信号、第二输出信号、第三输入信号和第四输出信号，作为示例，第一开关和第四开关均为PMOS管，第二开关和第三开关均为NOMS管。更具体地讲，针对第一开关、第二开关、第三开关和第四开关中每个开关：控制端可为栅极，第一连接端可为源级和漏极之一，第二连接端可为源级和漏极中不同于第一连接端的另外一个。
图2示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的电路图。
如图2所示，输入输出单元10可包括第一电阻器R1，第一电阻器R1的第一连接端作为输入端口(Input)来从C点接收栅极电压信号，第一电阻器R1的第二连接端作为输出第一输出信号、第二输出信号、第三输出信号和第四输出信号的输出端口(Output)。
控制单元20可包括第一PMOS管D1、第一NMOS管D2、第二NMOS管E1和第二POMS管E2。第一PMOS管D1的源级(或漏极)连接到第一电阻器R1的第二连接端，第一PMOS管D1的漏极(或源级)连接到第一NMOS管D2的源级(或漏极)，第一PMOS管D1的栅极接收第一控制信号A。第一NMOS管D2的漏极(或源级)接地，第一NMOS管D2的栅极接收第二控制信号B。第二NMOS管E1的源级(或漏极)连接到第一电阻器R1的第二连接端，第二NMOS管E1的漏极 (或源级)连接到第二PMOS管E2的源级(或漏极)，第二NMOS管E1的栅极接收第一控制信号A。第二PMOS管E2的漏极(或源级)接地，第二PMOS管E2的栅极接收第二控制信号B。
具体地讲，当第一控制信号A和第二控制信号B具有相同的电平时(例如，在一个周期中的第一时间段和第四时间段期间)，D支路的第一PMOS管D1和第一NMOS管D2均断开，E支路的第二NMOS管E1和第二PMOS管E2均断开,此时，第一电阻器R1的输出端可输出与栅极电压信号的电压值接近的电压值。
当第一控制信号A和第二控制信号B具有不同的电平时(例如，在一个周期中的第二时间段和第三时间段期间)，D支路的第一PMOS管D1和第一NMOS管D2均导通并连接到地，或者E支路的第二NMOS管E1和第二PMOS管E2均导通并连接到地。此时，由于第一PMOS管D1、第一NMOS管D2、第二NMOS管E1和第二POMS管E2均具有一定的电阻值，因此，当D支路或E支路连接到地时，第一电阻器R1的输出端口处的电压会减小。
在一个示例中，当在一个周期中的第二时间段期间第一控制信号A具有低电平(例如，0V)并且第二控制信号B具有高电平(例如，3.3V)时，D支路的第一PMOS管D1和第一NMOS管D2均导通并连接到地，E支路的第二NMOS管E1和第二PMOS管E2均断开。此时，根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路等效为图3的电路。
图3示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的第一等效电路图。
如图3所示，第二电阻器Rd为D支路的第一PMOS管D1、第一NMOS管D2及连接线的等效电阻，第三电阻器Rc为第一电阻器R1、第一电阻器R1的第一连接端与输入端口之间的连接线以及第一电阻器R1的第二连接端与输出端口之间的连接线的等效电阻。
因此，在第二时间段期间，输出端口输出的电压值为Rd/(Rd+Rc)，因此，可通过调整Rc和Rd的阻值来调整输出端口输出的信号的电压。
在另一示例中，当在一个周期中的第三时间段期间第一控制信号A具有高电平(例如，3.3V)并且第二控制信号B具有低电平(例如，0V)时，D支路的第一PMOS管D1和第一NMOS管D2均断开，E支路的第二NMOS管E1和第二PMOS管E2均导通并连接到地。此时，根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路等效为图4的电路。
图4示出根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的第二等效电路图。
如图4所示，第四电阻器Re为E支路的第二NMOS管E1、第二PMOS管E2及连接线的等效电阻，第三电阻器Rc为第一电阻器R1、第一电阻器R1的第一连接端与输入端口之间的连接线以及第一电阻器R1的第二连接端与输出端口之间的连接线的等效电阻。
因此，在第三时间段期间，输出端口输出的电压值为Re/(Re+Rc)，因此，通过调整Rc和Re的阻值来调整输出端口输出的信号的电压。
通常，栅极电压信号为有效电平是33V无效电平是-7V的方波。以下以该栅极电压信号为例说明输入输出单元10输出的输出信号的示例。
图5示出根据本发明示例性实施例的向液晶显示器提供的栅极电压信号的电路的输出信号的示图。
如图5所示，输入输出单元10的输出端口输出的输出信号的周期为T(即，栅极电压信号的周期为T)。
在第一时间段T1期间，第一控制信号A和第二控制信号B电平相同，D支路断开且E支路断开，输入输出单元10的输出端口输出电压值为接近33V的第一输出信号，这里，第一输出信号的电压值与栅极电压信号的高电平的电压值之差可在第一预定范围(例如，(-10％，0))内。
在第二时间段T2期间，第一控制信号A和第二控制信号B电平不相同，D支路导通(例如，Rd＝2Rc)或E支路导通(例如，Re＝2Rc)，输入输出单元10的输出端口输出电压值为接近22V的第二输出信号。
在第三时间段T3期间，第一控制信号A的电平反相并且第二控制信号B电平反向，此时，D支路和E支路中的另一支路导通(例如，Re＝1/2Rc或者Rd＝1/2Rc)，输入输出单元10的输出端口输出电压值为接近11V的第二输出信号。
在第四时间段T4期间，第一控制信号A和第二控制信号B电平再次相同，D支路断开且E支路断开，输入输出单元10的输出端口输出电压值为接近-7V的第四输出信号，这里，第四输出信号的电压值与栅极电压信号的低电平的电压值之差可在第二预定范围(例如，(-10％，0))内。
应该理解，图5中示出的栅极电压信号的有效电平的电压值和无效电平的电压值仅是示例，根据实际需要，栅极电压信号的有效电平的电压值和无效电平的电压值还可以是其它值。第二输出信号的电压值和第三输出信号的电压值也仅是示例，还可根据实际需要，通过改变第二电阻器Rd、第三电阻器Rc和/或第四电阻器Re的电阻值来将第二输出信号的电压值和第三输出信号的电压值改变为其它值。
此外，由于需要使第一输出信号的电压值与栅极信号的有效电平的电压值之差尽可能小，并且需要使第四输出信号的电压值与栅极信号的无效电平的电压值之差尽可能小，因此需要使第三电阻器Rc的电阻值比较小。所以，在实际应用中，当输入输出单元10的导线的电阻能够满足Rc的阻值要求时，可省略图2中的第一电阻器R1，从而可进一步减小电路在液晶面板上所需的面积。
图6示出根据本发明另一示例性实施例的处理向液晶显示器提供的栅极电压信号的电路的电路图。
如图6所示，根据本发明另一示例性实施例的处理向液晶显示器提供的栅 极电压信号的电路去掉了图2中的第一电阻器Rc，此时输入输出单元10的输入端口(Input)与输出端口(Output)之间的连线的线阻等效为第三电阻器Rc，因此，通过调整图4和图5中的Rd和Re，仍可使图6中的电路输出具有图5中的输出信号的波形的输出信号。
在根据本发明示例性实施例的处理向液晶显示器提供的栅极电压信号的电路中，可通过在每个周期的不同时间段期间将栅极电压信号改变为不同的值来降低栅极电压信号的电压的下降速度，从而降低对液晶显示器的基准电压的影响。
尽管已经参照其示例性实施例具体显示和描述了本发明，但是本领域的技术人员应该理解，在不脱离权利要求所限定的本发明的精神和范围的情况下，可以对其进行形式和细节上的各种改变。

Claims (10)

  1. 一种处理向液晶显示器提供的栅极电压信号的电路，包括：输入输出单元和控制单元，
    其中，输入输出单元接收所述栅极电压信号，控制单元接收控制信号并根据控制信号的控制，使输入输出单元基于栅极电压信号在每个周期内的第一时间段期间输出第一输出信号，第二时间段期间输出第二输出信号，第三时间段期间输出第三输出信号，第四时间段期间输出第四输出信号。
  2. 如权利要求1所述的电路，其中，第一时间段、第二时间段、第三时间段和第四时间段是在时间上连续的时间段，并且，第一时间、第二时间段和第三时间段的持续时间长度之和与所述栅极电压信号的有效电平的持续时间长度相等，第四时间段的持续时间长度与所述栅极电压信号的无效电平的持续时间长度相等。
  3. 如权利要求1所述的电路，其中，第一输出信号的电压值与所述栅极信号的有效电平的电压值之差在第一预定范围内，第二输出信号的电压值小于第一输出信号的电压值，第三输出信号的电压值小于第二输出信号的电压值，并且第四输出信号的电压值与所述栅极信号的无效电平的电压值之差在第二预定范围内。
  4. 如权利要求1所述的电路，其中，控制信号包括第一控制信号和第二控制信号，第一控制信号的周期和第二控制信号的周期与所述栅极电压信号的周期相同，
    其中，在第二时间段期间第一控制信号具有第一电平并且第二控制信号具有第二电平，在第三时间段期间第一控制信号具有第二电平并且第二控制信号具有第一电平，在其它时间段期间第一控制信号和第二控制信号均具有第一电平或均具有第二电平。
  5. 如权利要求4所述的电路，其中，第一电平为高电平和低电平之一，第二电平为高电平和低电平中不同于第一电平的另一电平。
  6. 如权利要求4所述的电路，其中，输入输出单元包括：
    第一电阻器，第一连接端接收所述栅极电压信号，第二连接端作为输出第一输出信号、第二输出信号、第三输出信号和第四输出信号的输出端口。
  7. 如权利要求6所述的电路，其中，控制单元包括：第一开关、第二开 关、第三开关和第四开关，
    其中，第一开关的第一连接端连接到第一电阻器的第二连接端，第一开关的第二连接端连接到第二开关的第一连接端，第一开关的控制端接收第一控制信号，
    第二开关的第二连接端接地，第二开关的控制端接收第二控制信号，
    第三开关的第一连接端连接到第一电阻器的第二连接端，第三开关的第二连接端连接到第四开关的第一连接端，第三开关的控制端接收第一控制信号，
    第四开关的第二连接端接地，第四开关的控制端接收第二控制信号。
  8. 如权利要求7所述的电路，其中，
    第一开关和第四开关均为PMOS管，第二开关和第三开关均为NOMS管。
  9. 如权利要求8所述的电路，其中，针对第一开关、第二开关、第三开关和第四开关中每个开关：
    控制端为栅极，第一连接端为源级和漏极之一，第二连接端为源级和漏极中不同于第一连接端的另外一个。
  10. 如权利要求1所述的电路，其中，所述电路布置于栅极驱动集成于阵列基板的液晶显示器的扇出区域。
PCT/CN2016/089796 2016-05-20 2016-07-12 处理向液晶显示器提供的栅极电压信号的电路 Ceased WO2017197746A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/128,193 US10170064B2 (en) 2016-05-20 2016-07-12 Circuit for processing gate voltage signal supplied for liquid crystal display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610339044.6 2016-05-20
CN201610339044.6A CN105761701B (zh) 2016-05-20 2016-05-20 处理向液晶显示器提供的栅极电压信号的电路

Publications (1)

Publication Number Publication Date
WO2017197746A1 true WO2017197746A1 (zh) 2017-11-23

Family

ID=56324182

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/089796 Ceased WO2017197746A1 (zh) 2016-05-20 2016-07-12 处理向液晶显示器提供的栅极电压信号的电路

Country Status (3)

Country Link
US (1) US10170064B2 (zh)
CN (1) CN105761701B (zh)
WO (1) WO2017197746A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105957491A (zh) 2016-07-14 2016-09-21 深圳市华星光电技术有限公司 I2c传输电路及显示装置
CN117746815A (zh) * 2024-01-31 2024-03-22 京东方科技集团股份有限公司 一种电压生成电路及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917465A (en) * 1993-03-17 1999-06-29 Fujitsu Limited Display unit employing phase transition liquid crystal and method of driving the display unit
US20020000966A1 (en) * 2000-07-03 2002-01-03 Yasuyuki Kudo Liquid crystal display device
CN1692398A (zh) * 2002-12-27 2005-11-02 三洋电机株式会社 有源矩阵型液晶显示设备
CN101312016A (zh) * 2007-05-22 2008-11-26 北京京东方光电科技有限公司 多级电平驱动装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH063647A (ja) * 1992-06-18 1994-01-14 Sony Corp アクティブマトリクス型液晶表示装置の駆動方法
US7002542B2 (en) * 1998-09-19 2006-02-21 Lg.Philips Lcd Co., Ltd. Active matrix liquid crystal display
KR100687336B1 (ko) * 2003-03-25 2007-02-27 비오이 하이디스 테크놀로지 주식회사 액정구동장치 및 그 구동방법
KR101100889B1 (ko) * 2005-02-26 2012-01-02 삼성전자주식회사 액정표시장치와 그 구동방법
CN101770750B (zh) * 2008-12-26 2012-01-25 北京京东方光电科技有限公司 液晶显示器及其控制方法
US8072409B2 (en) * 2009-02-25 2011-12-06 Au Optronics Corporation LCD with common voltage driving circuits
US8599618B2 (en) * 2011-12-02 2013-12-03 Cypress Semiconductor Corp. High voltage tolerant row driver
US9224486B1 (en) * 2014-06-20 2015-12-29 Freescale Semiconductor, Inc. Control gate driver for use with split gate memory cells
CN104795040B (zh) * 2015-04-30 2017-05-10 京东方科技集团股份有限公司 用于显示装置的关机残影改善电路、阵列基板、显示装置
CN105118472A (zh) * 2015-10-08 2015-12-02 重庆京东方光电科技有限公司 像素阵列的栅极驱动装置及其驱动方法
CN105405423B (zh) * 2015-12-15 2019-01-15 深圳市华星光电技术有限公司 栅极驱动装置及其阵列基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917465A (en) * 1993-03-17 1999-06-29 Fujitsu Limited Display unit employing phase transition liquid crystal and method of driving the display unit
US20020000966A1 (en) * 2000-07-03 2002-01-03 Yasuyuki Kudo Liquid crystal display device
CN1692398A (zh) * 2002-12-27 2005-11-02 三洋电机株式会社 有源矩阵型液晶显示设备
CN101312016A (zh) * 2007-05-22 2008-11-26 北京京东方光电科技有限公司 多级电平驱动装置

Also Published As

Publication number Publication date
US10170064B2 (en) 2019-01-01
US20180174537A1 (en) 2018-06-21
CN105761701B (zh) 2018-10-30
CN105761701A (zh) 2016-07-13

Similar Documents

Publication Publication Date Title
US9383841B2 (en) Shift register circuit
CN104021769B (zh) 一种移位寄存器、栅线集成驱动电路及显示屏
US10593286B2 (en) Shift register, gate driving circuit, display panel and driving method
EP3223268B1 (en) Shift register unit and driving method therefor, shift register, and display device
JP6775691B2 (ja) Ｇｏａ駆動回路及び液晶表示装置
US9306572B2 (en) Output buffer, gate electrode driving circuit and method for controlling the same
KR101989721B1 (ko) 액정 디스플레이 장치 및 그 게이트 드라이버
US10043585B2 (en) Shift register unit, gate drive device, display device, and control method
US20150154927A1 (en) Gate driver-on-array driving circuit and driving method
CN105609137A (zh) 移位寄存器、栅线集成驱动电路、阵列基板及显示装置
CN103177682B (zh) 一种显示驱动电路及其驱动方法、显示装置
WO2018040405A1 (zh) 一种液晶显示器的栅极开启电压产生装置
CN105652535A (zh) 一种栅极驱动电路及显示面板
CN103606359A (zh) 一种驱动电路及其移位寄存器
CN104599630B (zh) 一种驱动电路及发光控制电路、显示面板、显示装置
CN101510411B (zh) 显示装置及其修复方法
WO2018133468A1 (zh) 移位寄存器电路、goa电路和显示装置及其驱动方法
TWI443624B (zh) 重置電路
WO2017197746A1 (zh) 处理向液晶显示器提供的栅极电压信号的电路
CN102592553B (zh) 重置电路
CN106935174B (zh) 栅极驱动集成电路及包括栅极驱动集成电路的显示装置
CN105139815A (zh) 一种下传控制电路及其goa电路
CN101981611B (zh) 在液晶显示器的源极驱动器芯片产生帧起始脉冲信号的方法
CN103956130B (zh) 显示器及其放电控制电路
CN106205522B (zh) 移位寄存器及其驱动方法、栅极驱动装置以及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15128193

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16902126

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16902126

Country of ref document: EP

Kind code of ref document: A1