WO2017185563A1 - 一种 d 类音频功率放大器、芯片及其失真检测电路 - Google Patents

一种 d 类音频功率放大器、芯片及其失真检测电路 Download PDF

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Publication number
WO2017185563A1
WO2017185563A1 PCT/CN2016/094858 CN2016094858W WO2017185563A1 WO 2017185563 A1 WO2017185563 A1 WO 2017185563A1 CN 2016094858 W CN2016094858 W CN 2016094858W WO 2017185563 A1 WO2017185563 A1 WO 2017185563A1
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module
logic operation
signal
input end
output
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PCT/CN2016/094858
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English (en)
French (fr)
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翟理
余丹
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深圳市纳芯威科技有限公司
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Publication of WO2017185563A1 publication Critical patent/WO2017185563A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3264—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits in audio amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications

Definitions

  • the present invention belongs to the technical field of audio power amplifiers, and in particular, to a class D audio power amplifier, a chip and a distortion detecting circuit thereof. Background technique
  • the working principle of the class D audio power amplifier is as follows: The input analog audio signal outputs a PWM signal through a pulse width modulator, and the PWM signal is driven by a pulse pusher to drive the pulse power amplifier, and the output signal of the pulse power amplifier is low-pass filtered. After the filter is filtered, the speaker sounds.
  • Class D audio power amplifiers work in a state of high performance, with a high efficiency, theoretically 100%, so they are widely used in portable electronic devices such as mobile phones and tablet computers.
  • a preamplifier is generally placed in front of the pulse width modulator to amplify the input analog audio signal, and the amplified analog audio signal is pulse width modulated and pulsed signal amplified. And after filtering, the speaker is sounded.
  • the amplitude of the input analog audio signal is too large, after amplification by the preamplifier and pulse width modulation, the peak-to-peak value of the amplified analog audio signal exceeds the peak-to-peak value of the modulated triangular wave. Therefore, the simulation of the final filtered output is performed.
  • the signal has severe clipping distortion relative to the originally input analog audio signal. When the long turns work in a distorted state, it will cause great harm to the audio power amplifier and the speaker. Therefore, it is necessary to design a distortion detecting circuit to avoid the occurrence of output signal distortion.
  • the sampling signal is sampled, the sampled signal is analog-to-digital converted, and the feedback circuit outputs a control signal according to the analog-to-digital converted signal to change the feedback resistance of the preamplifier.
  • the distortion detection circuit needs to design a complete sampling and analog-to-digital conversion circuit.
  • the structure of the distortion detection circuit is relatively complicated, so that the area of the audio power amplification chip is large and the power consumption is high. Therefore, in the prior art, there is a problem that the area of the class D audio power amplifying chip is large and the power consumption is high due to the complicated structure of the distortion detecting circuit.
  • An object of the present invention is to provide a distortion detecting circuit, which aims to solve the distortion detection method existing in the prior art.
  • the circuit structure is complicated, which leads to the problem of large area and high power consumption of the class D audio power amplifier chip.
  • the present invention is implemented as a distortion detecting circuit of a class D audio power amplifier, the class D audio power amplifier further includes a pulse width modulation module, and the pulse width modulation module performs analog audio input on the amplified differential input.
  • the signal is modulated and outputs two PWM signals, and the distortion detecting circuit includes a first logic operation triggering module, a second logic operation triggering module, and a logic operation module.
  • the first input end of the first logic operation triggering module and the first input end of the second logic operation triggering module are connected to the first output end of the pulse width modulation module, the first logic The second input end of the operation trigger module and the second input end of the second logic operation trigger module are connected in common and connected to the second output end of the pulse width modulation module, where the first logic operation trigger module is The third input end and the third input end of the second logical operation triggering module are connected in common and receive a set signal, and the output end of the first logical operation triggering module and the output end of the second logical operation triggering module respectively The first input end and the second input end of the logic operation module are connected.
  • the first logic operation triggering module outputs a first logic operation and a first triggering process on the two PWM signals, and outputs a first pulse signal
  • the second logic operation triggering module is configured to the two PWM signals Performing a second logic operation and a second trigger process, and outputting a second pulse signal, when the analog audio signal output by the class D audio power amplifier is distorted, the logic operation module is configured to the first pulse signal and the first The second pulse signal performs a third logic operation and outputs a distortion indication signal from its output terminal.
  • Another object of the present invention is to provide a class D audio power amplifier, including a preamplifier module, a pulse width modulation module, an output stage power amplifying module, and a gain attenuating module, the preamplifier module pair differential input
  • the analog audio signal is amplified and outputs a differential amplified analog audio signal
  • the pulse width modulation module pulse width modulates the differential amplified analog audio signal and outputs two PWM signals
  • the output stage power amplification module pairs the two channels
  • the PWM signal is amplified and filtered
  • the D-type audio power amplifier further includes the above-described distortion detecting circuit.
  • the distortion detecting circuit outputs the distortion indicating signal
  • the gain attenuating module outputs a corresponding control signal to the front according to the distortion indicating signal.
  • An amplification module the preamplifier module reduces the differential input according to the control signal The amplification amplitude of the analog audio signal.
  • Another object of the present invention is to provide a class D audio power amplifying chip including the above-described class D audio power amplifier.
  • the distortion detecting circuit includes a first logic operation triggering module, a second logic operation triggering module, and a logic operation module, and the first logic operation triggering module performs the first two-way PW M signal output by the pulse width modulation module. After the logic operation and the first trigger processing, the first pulse signal is output, and the second logic operation triggering module performs the second logic operation and the second trigger processing on the two P WM signals, and outputs the second pulse signal.
  • the logic operation module When the analog audio signal outputted by the class D audio power amplifier is distorted, the logic operation module performs a third logic operation on the first pulse signal and the second pulse signal to output a distortion indication signal.
  • the distortion detection circuit detects the distortion phenomenon through logic operation and trigger processing, and the circuit structure is simple, effectively reducing the power consumption of the circuit and reducing the chip area.
  • FIG. 1 is a schematic structural diagram of a distortion detecting circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a distortion detecting circuit according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a distortion detecting circuit according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a distortion detecting circuit according to another embodiment of the present invention.
  • FIG. 5 is a related waveform diagram of a pulse width modulation module according to another embodiment of the present invention.
  • FIG. 6 is a waveform diagram of a first pulse and a second pulse according to another embodiment of the present invention.
  • FIG. 7 is a third pulse and a fourth pulse waveform diagram according to another embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a class D audio power amplifier according to another embodiment of the present invention.
  • FIG. 1 shows a structure of a distortion detecting circuit according to an embodiment of the present invention. For convenience of description, only parts related to the embodiment of the present invention are shown, which are described in detail as follows:
  • the class D audio power amplifier includes a pulse width modulation module 30, the pulse width modulation module 30 modulates the amplified differential input analog audio signal and outputs two PWM signals, and the class D audio power amplifier further includes a distortion detecting circuit 10,
  • the distortion detecting circuit 10 includes a first logic operation triggering module 100, a second logic operation triggering module 200, and a logic operation module 300.
  • the first input end of the first logical operation triggering module 100 and the first input end of the second logical operation triggering module 200 are connected to the first output end of the pulse width modulation module 30, and the first logical operation triggering module 100
  • the second input end is coupled to the second input end of the second logic operation triggering module 200 and is connected to the second output end of the pulse width modulation module 30.
  • the first logic operation triggers the third input end of the module 100 and the second logic.
  • the third input end of the operation triggering module 200 is connected to and receives the set signal, and the output end of the first logical operation triggering module 100 and the output end of the second logical operation triggering module 200 are respectively connected with the first input end of the logic operation module 300.
  • the second input is connected.
  • the first logic operation triggering module 100 performs a first logic operation and a first trigger process on the two PWM signals to output a first pulse signal
  • the second logic operation trigger module 200 performs a second logic operation on the two PWM signals. After the second triggering process, the second pulse signal is output.
  • the logic operation module 300 performs the third logic operation on the first pulse signal and the second pulse signal, and outputs the output signal. Output distortion indication signal.
  • the first logic operation is a NAND operation
  • the second logic operation is an OR operation
  • the third logic operation is an OR operation
  • the set signal is a high level signal.
  • the amplified and processed differential amplified analog audio signal has a peak-to-peak value greater than the pulse width modulation module 30.
  • the peak-to-peak value of the triangular carrier ⁇ , the two PWM signals output by the pulse width modulation module 30 respectively have a plurality of high-level or low-level continuous ⁇ lengths longer than the PWM signal period, and the two PWM signals are amplified and low-pass filtered.
  • the output analog audio signal is subjected to clipping distortion.
  • the distortion detecting circuit 10 further includes an oscillating module 400, an output end of the oscillating module 400, a chirp signal end of the first logic operation triggering module 100, and a second logic operation.
  • the chirp signal terminals of the trigger module 200 are connected.
  • the oscillation module 400 outputs a pulse signal of a fixed frequency to provide a first clock operation trigger module 100 and a second logic operation trigger module 200, and the first logic operation trigger module 100 and the second logic operation trigger module
  • the cesium clock signal of 200 is the same.
  • the distortion detecting circuit 10 further includes an oscillating module 400 and an inverting module 500, and an output end of the oscillating module 400 and a chirp signal end of the first logic operation triggering module 100.
  • the output end of the oscillating module 400 is connected to the input end of the inverting module 500, and the output end of the inverting module 500 is connected to the chirp signal end of the second logical operation triggering module 200.
  • the inverting module 500 is an inverter G1, and the input end and the output end of the inverter G1 are an input end and an output end of the inverting module 500, respectively.
  • the oscillating module 400 outputs a pulse signal of a fixed frequency to provide a first clock signal to the first logic operation triggering module 100 and the second logic operation triggering module 200, and the first logic operation triggers the ⁇ clock signal of the module 100 and the second logic operation triggering module 200
  • the clock signal has the opposite phase.
  • the purpose of setting the opposite phase of the two-clock signal is to ensure that the first logical operation trigger module 100 or the second logic operation trigger module 200 is triggered by the interference spike pulse in the cuckoo clock signal, and the output of the logic operation module 300 is ensured.
  • the signal is an accurate distortion indication signal.
  • the logic operation module 300 is a first OR gate G2, and the first input terminal, the second input terminal, and the output terminal of the first OR gate G2 are respectively logic operation modules. The first input, the second input, and the output of the 300.
  • the logic operation module 300 performs a logical OR operation on the pulse signal output by the first logic operation trigger module 100 and the pulse signal output by the second logic operation trigger module 200, and outputs the operation result, when the class D audio power amplifier
  • the output analog audio signal is distorted, and the logic operation module 300 outputs a distortion indication signal to indicate the occurrence of a distortion phenomenon, and the distortion indication signal is a high and low level alternate pulse signal, wherein the high level continuous length is approximately equal to the distortion length.
  • the logic operation module 300 When the analog audio signal output by the class D audio power amplifier is not distorted, the logic operation module 300 always outputs a low level signal.
  • the first logical operation triggering module 100 includes a NAND gate 101 and a first triggering unit 102.
  • the first input end and the second input end of the NAND gate 101 respectively For the first logical operation
  • the first input end and the second input end of the trigger module 100, the output end of the NAND gate 101 is connected to the reset end of the first trigger unit 102, and the input, output and output ends of the first trigger unit 102
  • the first logical operation triggers the chopping signal end, the third input end, and the output end of the module 100.
  • the first trigger unit 102 is the first D flip-flop dl
  • the reset terminal RS1, the clock terminal CL1, the input terminal D1, and the output terminal Q1 of the first D flip-flop dl are respectively the first trigger unit 102.
  • the NAND gate 101 performs a NAND logic operation on the input two PWM signals, and outputs the operation result to the reset terminal RS1 of the first D flip-flop dl.
  • the two PWM signals output by the pulse width modulation module 30 respectively have a plurality of high levels or low levels that are longer than the PWM signal period, and the NAND gate 101 After performing the NAND logic operation on the two PWM signals, the output includes a plurality of pulse signals of a high level longer than the PWM signal period to the reset terminal RS1 of the first D flip-flop d1.
  • the high level ⁇ length in the pulse signal is also greater than the ⁇ clock signal period of the first D flip-flop dl, so that the first D flip-flop dl can perform the set operation, since the input terminal D1 of the first D flip-flop dl is always The high level signal is input. Therefore, in the high level of the pulse signal output from the NAND gate 101, when the rising edge of the sigma signal arrives, the output terminal Q1 of the first D flip-flop dl outputs a high level.
  • the high level of the first D flip-flop dl output reflects the bottom distortion (distortion near the valley) in the analog audio signal output from the Class D audio power amplifier.
  • the second logical operation triggering module 200 includes a second OR gate 20 1 and a second trigger unit 202, and a first input end and a second input of the second OR gate 201.
  • the input ends are respectively a first input end and a second input end of the second logic operation trigger module 200, and the output end of the second OR gate 201 is connected to the reset end of the second trigger unit 202, and the chirp clock of the second trigger unit 202
  • the input end, the input end and the output end are respectively a chirp signal end, a third input end and an output end of the second logic operation trigger module 200.
  • the second trigger unit 202 is a second D flip-flop d2, and the reset terminal RS2, the clock terminal CL2, the input terminal D2, and the output terminal Q2 of the second D flip-flop d2 are respectively the second trigger unit 202.
  • the second OR gate 201 performs a logical operation on the input two PWM signals, and outputs the operation result to the reset terminal RS2 of the second D flip-flop d2.
  • the two PWM signals output by the pulse width modulation module 30 respectively appear in multiple segments. If the length is greater than the high level or the low level of the PWM signal period, the second OR gate 201 performs a logical operation on the two PWM signals, and outputs a pulse signal having a plurality of high levels that are longer than the PWM signal period.
  • the high level ⁇ length in the pulse signal is also greater than the ⁇ clock signal period of the second D flip-flop d2, so that the second D flip-flop d2 can perform the set operation, since the input terminal D2 of the second D flip-flop d2 is always The high level signal is input. Therefore, in the high level section of the pulse signal outputted by the second OR gate 201, when the rising edge of the chirp signal comes, the output terminal Q2 of the second D flip-flop d2 outputs a high level.
  • the high level length outputted by the second D flip-flop d2 reflects the top distortion (distortion near the peak) in the analog audio signal output by the class D audio power amplifier.
  • the triangular carrier waveform of the pulse width modulation module 30, the differential amplified input waveform, and the output two PWM signal waveforms are as shown in FIG. 5, as shown in FIG.
  • the waveform is taken as an example of a half cycle of the differential input analog audio signal.
  • the operation in the other sections is the same as that in the half cycle.
  • the second pulse signal V2 is output after the two PWM signals are executed or logically operated, and the waveforms of the first pulse signal VI and the second pulse signal V2 are as shown in FIG. 6.
  • the high level ⁇ length in the first pulse signal VI is greater than the ⁇ clock signal period of the first D flip-flop dl
  • the high level ⁇ length in the second pulse signal V2 is greater than the ⁇ clock signal period of the second D flip-flop d2.
  • the high level in the first pulse signal VI and the high level in the second pulse signal V2 can cause the first D flip-flop d1 and the second D flip-flop d2 to perform a set operation, respectively, due to the first D flip-flop dl
  • the input terminal D1 and the input terminal D2 of the second D flip-flop d2 always input a high level signal, and therefore, in the high level of the first pulse signal VI and the second pulse signal V2, when the rising edge of the chirp signal
  • the output terminal Q1 of the first D flip-flop dl and the output terminal Q2 of the second D flip-flop d2 both output a high level, and the pulse waveform V3 outputted by the output terminal Q1 and the pulse waveform V4 outputted by the output terminal Q2 are as shown in FIG.
  • the first OR gate G2 performs a logical OR operation on the pulse waveform V3 and the pulse waveform V4 and outputs a distortion indication signal as shown in FIG. 8.
  • the high level ⁇ length in the distortion indication signal and the output of the class D audio power amplifier The common distortion lengths of the top and bottom distortions in the analog audio signal are approximately equal.
  • the present invention also provides a class D audio power amplifier, as shown in FIG. 9, the class D audio power amplifier includes The preamplifier module 20, the pulse width modulation module 30, the output stage power amplification module 40 and the gain attenuation module 50, the preamplifier module 20 amplifies the differential input analog audio signal and outputs a differential amplified analog audio signal, and the pulse width modulation module 30 The differentially amplified analog audio signal is pulse width modulated and outputs two PWM signals.
  • the output stage power amplification module 40 amplifies and filters the two PWM signals, and the class D audio power amplifier further includes a distortion detecting circuit 10.
  • the distortion detecting circuit 10 When the analog audio signal outputted by the filtering process is distorted, the distortion detecting circuit 10 outputs a distortion indicating signal, and the gain attenuating module 50 outputs a corresponding control signal to the preamplifying module 20 according to the distortion indicating signal, and the preamplifying module 20 according to the preamplifying module 20
  • the control signal reduces the amplification amplitude of the differential input analog audio signal.
  • the gain attenuation module 50 outputs a corresponding control signal to the preamplifier module 20 according to the continuous length of the high level in the distortion indication signal, and the preamplifier module 20 reduces the amplification of the differential input analog audio signal according to the control signal.
  • the present invention also provides a class D audio power amplifying chip including the above class D audio power amplifier.
  • the distortion detecting circuit includes a first logic operation triggering module, a second logic operation triggering module, and a logic operation module, and the first logic operation triggering module performs the first two-way PW M signal output by the pulse width modulation module. After the logic operation and the first trigger processing, the first pulse signal is output, and the second logic operation triggering module performs the second logic operation and the second trigger processing on the two P WM signals, and outputs the second pulse signal.
  • the logic operation module When the analog audio signal outputted by the class D audio power amplifier is distorted, the logic operation module performs a third logic operation on the first pulse signal and the second pulse signal to output a distortion indication signal.
  • the distortion detection circuit detects the distortion phenomenon through logic operation and trigger processing, and the circuit structure is simple, effectively reducing the power consumption of the circuit and reducing the chip area.

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Abstract

失真检测电路(10)包括第一逻辑运算触发模块(100)、第二逻辑运算触发模块(200)及逻辑运算模块(300)，第一逻辑运算触发模块(100)对脉冲宽度调制模块(30)输出的两路PWM信号执行第一逻辑运算和第一触发处理后输出第一脉冲信号，第二逻辑运算触发模块(200)对两路PWM信号执行第二逻辑运算和第二触发处理后输出第二脉冲信号，当D类音频功率放大器输出的模拟音频信号发生失真现象时，逻辑运算模块(300)对第一脉冲信号和第二脉冲信号执行第三逻辑运算后输出失真指示信号。失真检测电路(10)通过逻辑运算和触发处理检测失真，电路结构简单，有效降低了电路功耗和减小了芯片面积。

Description

说明书 发明名称：一种 D类音频功率放大器、 芯片及其失真检测电路 技术领域
[0001] 本发明属于音频功率放大器技术领域， 尤其涉及一种 D类音频功率放大器、 芯 片及其失真检测电路。 背景技术
[0002] D类音频功率放大器的工作原理为： 输入的模拟音频信号经脉冲宽度调制器输 出 PWM信号， 该 PWM信号经脉冲推动器驱动脉冲功率放大器工作， 脉冲功率放 大器的输出信号经低通滤波器滤波输出后带动扬声器发声。 D类音频功率放大器 工作于幵关状态， 具有较高的效率， 理论上可达到 100%， 因此被广泛应用于手 机、 平板电脑等便携电子设备中。
[0003] 在 D类音频功率放大器的设计中， 一般会在脉冲宽度调制器前放置前置放大器 ， 以对输入的模拟音频信号进行放大， 放大后的模拟音频信号经脉冲宽度调制 、 脉冲信号放大及滤波后带动扬声器发声音。 当输入的模拟音频信号的幅值过 大吋， 经前置放大器放大后在脉冲宽度调制吋， 放大后的模拟音频信号的峰峰 值超过了调制三角波的峰峰值， 因此， 最终经滤波输出的模拟信号相对于最初 输入的模拟音频信号会出现严重的削顶失真。 当长吋间工作于失真状态下， 则 会对音频功率放大器和扬声器产生很大危害， 因此， 需要设计失真检测电路以 避免输出信号失真现象的发生。
[0004] 对于现有技术所提供的失真检测方案， 其是采用对输出信号采样、 对采样信号 进行模数转换、 反馈电路根据模数转换后的信号输出控制信号以改变前置放大 器的反馈电阻的方案， 失真检测电路中需要设计完整的采样和模数转换电路， 失真检测电路结构较为复杂， 从而使得音频功率放大芯片的面积大且功耗高。 因此现有技术存在因失真检测电路结构复杂而导致 D类音频功率放大芯片的面积 大且功耗高的问题。
技术问题
[0005] 本发明的目的在于提供一种失真检测电路， 旨在解决现有技术存在的因失真检 测电路结构复杂而导致 D类音频功率放大芯片的面积大且功耗高的问题。
问题的解决方案
技术解决方案
[0006] 本发明是这样实现的， 一种 D类音频功率放大器的失真检测电路， 所述 D类音 频功率放大器还包括脉冲宽度调制模块， 所述脉冲宽度调制模块对放大后的差 分输入模拟音频信号进行调制并输出两路 PWM信号， 所述失真检测电路包括第 一逻辑运算触发模块、 第二逻辑运算触发模块及逻辑运算模块。
[0007] 所述第一逻辑运算触发模块的第一输入端和所述第二逻辑运算触发模块的第一 输入端共接于所述脉冲宽度调制模块的第一输出端， 所述第一逻辑运算触发模 块的第二输入端和所述第二逻辑运算触发模块的第二输入端共接并与所述脉冲 宽度调制模块的第二输出端相连接， 所述第一逻辑运算触发模块的第三输入端 和所述第二逻辑运算触发模块的第三输入端共接并接收置位信号， 所述第一逻 辑运算触发模块的输出端和所述第二逻辑运算触发模块的输出端分别与所述逻 辑运算模块的第一输入端和第二输入端相连接。
[0008] 所述第一逻辑运算触发模块对所述两路 PWM信号执行第一逻辑运算和第一触 发处理后输出第一脉冲信号， 所述第二逻辑运算触发模块对所述两路 PWM信号 执行第二逻辑运算和第二触发处理后输出第二脉冲信号， 当所述 D类音频功率放 大器输出的模拟音频信号发生失真吋， 所述逻辑运算模块对所述第一脉冲信号 和所述第二脉冲信号执行第三逻辑运算后由其输出端输出失真指示信号。
[0009] 本发明的另一目的还在于提供一种 D类音频功率放大器， 包括前置放大模块、 脉冲宽度调制模块、 输出级功率放大模块及增益衰减模块， 所述前置放大模块 对差分输入模拟音频信号进行放大并输出差分放大模拟音频信号， 所述脉冲宽 度调制模块对所述差分放大模拟音频信号进行脉冲宽度调制并输出两路 PWM信 号， 所述输出级功率放大模块对所述两路 PWM信号进行放大及滤波处理后输出 ， 所述 D类音频功率放大器还包括上述的失真检测电路。
[0010] 当所述滤波处理输出的模拟音频信号发生失真吋， 所述失真检测电路输出所述 失真指示信号， 所述增益衰减模块根据所述失真指示信号输出相应的控制信号 至所述前置放大模块， 所述前置放大模块根据所述控制信号降低对所述差分输 入模拟音频信号的放大幅度。
[0011] 本发明的另一目的还在于提供一种包括上述 D类音频功率放大器的 D类音频功 率放大芯片。
发明的有益效果
有益效果
[0012] 在本发明中， 失真检测电路包括第一逻辑运算触发模块、 第二逻辑运算触发模 块及逻辑运算模块， 第一逻辑运算触发模块对脉冲宽度调制模块输出的两路 PW M信号执行第一逻辑运算和第一触发处理后输出第一脉冲信号， 第二逻辑运算触 发模块对两路 PWM信号执行第二逻辑运算和第二触发处理后输出第二脉冲信号
， 当 D类音频功率放大器输出的模拟音频信号发生失真现象吋， 逻辑运算模块对 第一脉冲信号和第二脉冲信号执行第三逻辑运算后输出失真指示信号。 失真检 测电路通过逻辑运算和触发处理检测失真现象， 电路结构简单， 有效降低了电 路功耗和减小了芯片面积。
对附图的简要说明
附图说明
[0013] 图 1是本发明实施例提供的失真检测电路的结构示意图；
[0014] 图 2是本发明另一实施例提供的失真检测电路的结构示意图；
[0015] 图 3是本发明另一实施例提供的失真检测电路的结构示意图；
[0016] 图 4是本发明另一实施例提供的失真检测电路的结构示意图；
[0017] 图 5是本发明另一实施例提供的脉冲宽度调制模块的相关波形图；
[0018] 图 6是本发明另一实施例提供的第一脉冲和第二脉冲波形图；
[0019] 图 7是本发明另一实施例提供的第三脉冲和第四脉冲波形图；
[0020] 图 8是本发明另一实施例提供的第一或门输出波形图；
[0021] 图 9是本发明另一实施例提供的 D类音频功率放大器的结构示意图。
本发明的实施方式
[0022] 为了使本发明的目的、 技术方案及优点更加清楚明白， 以下结合附图及实施例 ， 对本发明进行进一步详细说明。 应当理解， 此处所描述的具体实施例仅仅用 以解释本发明， 并不用于限定本发明。
[0023] 图 1示出了本发明实施例提供的失真检测电路的结构， 为了便于说明， 仅示出 了与本发明实施例相关的部分， 详述如下：
[0024] D类音频功率放大器包括脉冲宽度调制模块 30， 脉冲宽度调制模块 30对放大后 的差分输入模拟音频信号进行调制并输出两路 PWM信号， D类音频功率放大器 还包括失真检测电路 10， 失真检测电路 10包括第一逻辑运算触发模块 100、 第二 逻辑运算触发模块 200及逻辑运算模块 300。
[0025] 第一逻辑运算触发模块 100的第一输入端和第二逻辑运算触发模块 200的第一输 入端共接于脉冲宽度调制模块 30的第一输出端， 第一逻辑运算触发模块 100的第 二输入端和第二逻辑运算触发模块 200的第二输入端共接并与脉冲宽度调制模块 30的第二输出端相连接， 第一逻辑运算触发模块 100的第三输入端和第二逻辑运 算触发模块 200的第三输入端共接并接收置位信号， 第一逻辑运算触发模块 100 的输出端和第二逻辑运算触发模块 200的输出端分别与逻辑运算模块 300的第一 输入端和第二输入端相连接。
[0026] 第一逻辑运算触发模块 100对两路 PWM信号执行第一逻辑运算和第一触发处理 后输出第一脉冲信号， 第二逻辑运算触发模块 200对两路 PWM信号执行第二逻辑 运算和第二触发处理后输出第二脉冲信号， 当 D类音频功率放大器输出的模拟音 频信号发生失真吋， 逻辑运算模块 300对第一脉冲信号和第二脉冲信号执行第三 逻辑运算后由其输出端输出失真指示信号。
[0027] 具体的， 第一逻辑运算为与非运算， 第二逻辑运算为或运算， 第三逻辑运算为 或运算， 置位信号为高电平信号。
[0028] 具体的， 当 D类音频功率放大器的差分输入模拟音频信号 （为差分正弦信号） 的幅值较大， 其经放大处理后的差分放大模拟音频信号的峰峰值大于脉冲宽度 调制模块 30三角载波的峰峰值吋， 脉冲宽度调制模块 30输出的两路 PWM信号中 分别出现多段持续吋长大于 PWM信号周期的高电平或低电平， 该两路 PWM信号 经过放大及低通滤波处理后由 D类音频功率放大器输出， 输出的模拟音频信号发 生削顶失真。 [0029] 作为本发明一实施例， 如图 2所示， 失真检测电路 10还包括振荡模块 400， 振荡 模块 400的输出端与第一逻辑运算触发模块 100的吋钟信号端以及第二逻辑运算 触发模块 200的吋钟信号端相连接。
[0030] 具体的， 振荡模块 400输出固定频率的脉冲信号为第一逻辑运算触发模块 100和 第二逻辑运算触发模块 200提供吋钟信号， 第一逻辑运算触发模块 100和第二逻 辑运算触发模块 200的吋钟信号相同。
[0031] 作为本发明一实施例， 如图 3所示， 失真检测电路 10还包括振荡模块 400和反相 模块 500， 振荡模块 400的输出端与第一逻辑运算触发模块 100的吋钟信号端相连 接， 振荡模块 400的输出端与反相模块 500的输入端相连接， 反相模块 500的输出 端与第二逻辑运算触发模块 200的吋钟信号端相连接。
[0032] 具体的， 反相模块 500为反相器 Gl， 反相器 G1的输入端和输出端分别为反相模 块 500的输入端和输出端。 振荡模块 400输出固定频率的脉冲信号为第一逻辑运 算触发模块 100和第二逻辑运算触发模块 200提供吋钟信号， 第一逻辑运算触发 模块 100的吋钟信号与第二逻辑运算触发模块 200的吋钟信号的相位相反。 设置 两吋钟信号的相位相反的目的是， 当出现吋钟信号中的干扰尖刺脉冲误触发第 一逻辑运算触发模块 100或第二逻辑运算触发模块 200现象吋， 保证逻辑运算模 块 300输出的信号为准确的失真指示信号。
[0033] 作为本发明一实施例， 如图 4所示， 逻辑运算模块 300为第一或门 G2， 第一或门 G2的第一输入端、 第二输入端及输出端分别为逻辑运算模块 300的第一输入端、 第二输入端及输出端。
[0034] 具体的， 逻辑运算模块 300对第一逻辑运算触发模块 100输出的脉冲信号和第二 逻辑运算触发模块 200输出的脉冲信号执行逻辑或运算， 并输出运算结果， 当 D 类音频功率放大器输出的模拟音频信号发生失真吋， 逻辑运算模块 300输出失真 指示信号以指示失真现象的发生， 失真指示信号为高低电平交替的脉冲信号， 其中高电平持续吋长与失真吋长近似相等， 当 D类音频功率放大器输出的模拟音 频信号没有失真吋， 逻辑运算模块 300始终输出低电平信号。
[0035] 作为本发明一实施例， 如图 4所示， 第一逻辑运算触发模块 100包括与非门 101 和第一触发单元 102， 与非门 101的第一输入端和第二输入端分别为第一逻辑运 算触发模块 100的第一输入端和第二输入端， 与非门 101的输出端与第一触发单 元 102的复位端相连接， 第一触发单元 102的吋钟输入端、 输入端及输出端分别 为第一逻辑运算触发模块 100的吋钟信号端、 第三输入端及输出端。
[0036] 具体的， 第一触发单元 102为第一 D触发器 dl， 第一 D触发器 dl的复位端 RS1、 吋钟端 CL1、 输入端 Dl及输出端 Q1分别为第一触发单元 102的复位端、 吋钟输入 端、 输入端及输出端。
[0037] 具体的， 与非门 101对输入的两路 PWM信号执行与非逻辑运算， 并输出运算结 果至第一 D触发器 dl的复位端 RS1。 当 D类音频功率放大器输出的模拟音频信号 发生失真吋， 脉冲宽度调制模块 30输出的两路 PWM信号中分别出现多段持续吋 长大于 PWM信号周期的高电平或低电平， 与非门 101对该两路 PWM信号执行与 非逻辑运算后， 输出含有多段持续吋长大于 PWM信号周期的高电平的脉冲信号 至第一 D触发器 dl的复位端 RS1。 该脉冲信号中的高电平吋长也大于第一 D触发 器 dl的吋钟信号周期， 因此可使第一 D触发器 dl执行置数操作， 由于第一 D触发 器 dl的输入端 D1始终输入高电平信号， 因此， 在与非门 101输出的脉冲信号的高 电平吋段内， 当吋钟信号的上升沿到来吋第一 D触发器 dl的输出端 Q1输出高电平 。 第一 D触发器 dl所输出的高电平吋长反映了 D类音频功率放大器输出的模拟音 频信号中的底部失真 （波谷附近失真） 吋长。
[0038] 作为本发明一实施例， 如图 4所示， 第二逻辑运算触发模块 200包括第二或门 20 1和第二触发单元 202， 第二或门 201的第一输入端和第二输入端分别为第二逻辑 运算触发模块 200的第一输入端和第二输入端， 第二或门 201的输出端与第二触 发单元 202的复位端相连接， 第二触发单元 202的吋钟输入端、 输入端及输出端 分别为第二逻辑运算触发模块 200的吋钟信号端、 第三输入端及输出端。
[0039] 具体的， 第二触发单元 202为第二 D触发器 d2， 第二 D触发器 d2的复位端 RS2、 吋钟端 CL2、 输入端 D2及输出端 Q2分别为第二触发单元 202的复位端、 吋钟输入 端、 输入端及输出端。
[0040] 具体的， 第二或门 201对输入的两路 PWM信号执行或逻辑运算， 并输出运算结 果至第二 D触发器 d2的复位端 RS2。 当 D类音频功率放大器输出的模拟音频信号 发生失真吋， 脉冲宽度调制模块 30输出的两路 PWM信号中分别出现多段持续吋 长大于 PWM信号周期的高电平或低电平， 第二或门 201对该两路 PWM信号执行 或逻辑运算后， 输出含有多段持续吋长大于 PWM信号周期的高电平的脉冲信号 至第二 D触发器 d2的复位端 RS2。 该脉冲信号中的高电平吋长也大于第二 D触发 器 d2的吋钟信号周期， 因此可使第二 D触发器 d2执行置数操作， 由于第二 D触发 器 d2的输入端 D2始终输入高电平信号， 因此， 在第二或门 201输出的脉冲信号的 高电平吋段内， 当吋钟信号的上升沿到来吋第二 D触发器 d2的输出端 Q2输出高电 平。 第二 D触发器 d2所输出的高电平吋长反映了 D类音频功率放大器输出的模拟 音频信号中的顶部失真 （波峰附近失真） 吋长。
[0041] 以下结合图 4对失真检测电路 10的工作原理进行说明， 详述如下：
[0042] 当 D类音频功率放大器输出的模拟音频信号发生失真吋， 脉冲宽度调制模块 30 的三角载波波形、 差分放大输入波形及输出的两路 PWM信号波形如图 5所示， 图 5中所示波形以差分输入模拟音频信号的半个周期为例， 其他吋段内的工作原理 与该半个周期内的工作原理相同。 两路 PWM信号中分别出现持续吋长大于 PWM 信号周期的高电平和低电平， 与非门 101对该两路 PWM信号执行与非逻辑运算后 输出第一脉冲信号 VI， 第二或门 202对该两路 PWM信号执行或逻辑运算后输出 第二脉冲信号 V2， 第一脉冲信号 VI和第二脉冲信号 V2的波形如图 6所示。 第一 脉冲信号 VI中的高电平吋长大于第一 D触发器 dl的吋钟信号周期， 第二脉冲信号 V2中的高电平吋长大于第二 D触发器 d2的吋钟信号周期， 因此第一脉冲信号 VI 中的高电平和第二脉冲信号 V2中的高电平可分别使第一 D触发器 dl和第二 D触发 器 d2执行置数操作， 由于第一 D触发器 dl的输入端 D1和第二 D触发器 d2的输入端 D2始终输入高电平信号， 因此， 在第一脉冲信号 VI和第二脉冲信号 V2的高电平 吋段内， 当吋钟信号的上升沿到来吋第一 D触发器 dl的输出端 Q1和第二 D触发器 d2的输出端 Q2均输出高电平， 输出端 Q1输出的脉冲波形 V3和输出端 Q2输出的脉 冲波形 V4如图 7所示。 第一或门 G2对脉冲波形 V3和脉冲波形 V4执行逻辑或运算 并输出失真指示信号， 失真指示信号如图 8所示， 失真指示信号中的高电平吋长 与 D类音频功率放大器输出的模拟音频信号中顶部失真和底部失真的共同失真吋 长近似相等。
[0043] 本发明还提供一种 D类音频功率放大器， 如图 9所示， D类音频功率放大器包括 前置放大模块 20、 脉冲宽度调制模块 30、 输出级功率放大模块 40及增益衰减模 块 50， 前置放大模块 20对差分输入模拟音频信号进行放大并输出差分放大模拟 音频信号， 脉冲宽度调制模块 30对差分放大模拟音频信号进行脉冲宽度调制并 输出两路 PWM信号， 输出级功率放大模块 40对两路 PWM信号进行放大及滤波处 理后输出， D类音频功率放大器还包括失真检测电路 10。
[0044] 当滤波处理输出的模拟音频信号发生失真吋， 失真检测电路 10输出失真指示信 号， 增益衰减模块 50根据失真指示信号输出相应的控制信号至前置放大模块 20 ， 前置放大模块 20根据控制信号降低对差分输入模拟音频信号的放大幅度。
[0045] 具体的， 增益衰减模块 50根据失真指示信号中高电平的持续吋长输出相应的控 制信号至前置放大模块 20， 前置放大模块 20根据控制信号降低对差分输入模拟 音频信号的放大幅度， 其中， 前置放大模块 20可采用控制其输出端不断短路的 方式来降低对差分输入模拟音频信号的放大幅度。
[0046] 本发明还提供了一种包括上述 D类音频功率放大器的 D类音频功率放大芯片。
[0047] 在本发明中， 失真检测电路包括第一逻辑运算触发模块、 第二逻辑运算触发模 块及逻辑运算模块， 第一逻辑运算触发模块对脉冲宽度调制模块输出的两路 PW M信号执行第一逻辑运算和第一触发处理后输出第一脉冲信号， 第二逻辑运算触 发模块对两路 PWM信号执行第二逻辑运算和第二触发处理后输出第二脉冲信号
， 当 D类音频功率放大器输出的模拟音频信号发生失真现象吋， 逻辑运算模块对 第一脉冲信号和第二脉冲信号执行第三逻辑运算后输出失真指示信号。 失真检 测电路通过逻辑运算和触发处理检测失真现象， 电路结构简单， 有效降低了电 路功耗和减小了芯片面积。
[0048] 以上所述仅为本发明的较佳实施例而已， 并不用以限制本发明， 凡在本发明的 精神和原则之内所作的任何修改、 等同替换和改进等， 均应包含在本发明的保 护范围之内。

Claims

权利要求书
[权利要求 1] 一种 D类音频功率放大器的失真检测电路， 所述 D类音频功率放大器 还包括脉冲宽度调制模块， 所述脉冲宽度调制模块对放大后的差分输 入模拟音频信号进行调制并输出两路 PWM信号， 其特征在于， 所述 失真检测电路包括第一逻辑运算触发模块、 第二逻辑运算触发模块及 逻辑运算模块；
所述第一逻辑运算触发模块的第一输入端和所述第二逻辑运算触发模 块的第一输入端共接于所述脉冲宽度调制模块的第一输出端， 所述第 一逻辑运算触发模块的第二输入端和所述第二逻辑运算触发模块的第 二输入端共接并与所述脉冲宽度调制模块的第二输出端相连接， 所述 第一逻辑运算触发模块的第三输入端和所述第二逻辑运算触发模块的 第三输入端共接并接收置位信号， 所述第一逻辑运算触发模块的输出 端和所述第二逻辑运算触发模块的输出端分别与所述逻辑运算模块的 第一输入端和第二输入端相连接；
所述第一逻辑运算触发模块对所述两路 PWM信号执行第一逻辑运算 和第一触发处理后输出第一脉冲信号， 所述第二逻辑运算触发模块对 所述两路 PWM信号执行第二逻辑运算和第二触发处理后输出第二脉 冲信号， 当所述 D类音频功率放大器输出的模拟音频信号发生失真吋 ， 所述逻辑运算模块对所述第一脉冲信号和所述第二脉冲信号执行第 三逻辑运算后由其输出端输出失真指示信号。
[权利要求 2] 如权利要求 1所述的失真检测电路， 其特征在于， 所述失真检测电路 还包括振荡模块；
所述振荡模块的输出端与所述第一逻辑运算触发模块的吋钟信号端以 及所述第二逻辑运算触发模块的吋钟信号端相连接。
[权利要求 3] 如权利要求 1所述的失真检测电路， 其特征在于， 所述失真检测电路 还包括振荡模块和反相模块；
所述振荡模块的输出端与所述第一逻辑运算触发模块的吋钟信号端相 连接， 所述振荡模块的输出端与所述反相模块的输入端相连接， 所述 反相模块的输出端与所述第二逻辑运算触发模块的吋钟信号端相连接 如权利要求 1所述的失真检测电路， 其特征在于， 所述逻辑运算模块 为第一或门；
所述第一或门的第一输入端、 第二输入端及输出端分别为所述逻辑运 算模块的第一输入端、 第二输入端及输出端。
如权利要求 2或 3任一项所述的失真检测电路， 其特征在于， 所述第一 逻辑运算触发模块包括与非门和第一触发单元；
所述与非门的第一输入端和第二输入端分别为所述第一逻辑运算触发 模块的第一输入端和第二输入端， 所述与非门的输出端与所述第一触 发单元的复位端相连接， 所述第一触发单元的吋钟输入端、 输入端及 输出端分别为所述第一逻辑运算触发模块的吋钟信号端、 第三输入端 及输出端。
如权利要求 2或 3任一项所述的失真检测电路， 其特征在于， 所述第二 逻辑运算触发模块包括第二或门和第二触发单元；
所述第二或门的第一输入端和第二输入端分别为所述第二逻辑运算单 元的第一输入端和第二输入端， 所述第二或门的输出端与所述第二触 发单元的复位端相连接， 所述第二触发单元的吋钟输入端、 输入端及 输出端分别为所述第二逻辑运算触发模块的吋钟信号端、 第三输入端 及输出端。
如权利要求 5所述的失真检测电路， 其特征在于， 所述第一触发单元 为第一 D触发器， 所述第一 D触发器的复位端、 吋钟端、 输入端及输 出端分别为所述第一触发单元的复位端、 吋钟输入端、 输入端及输出 如权利要求 6所述的失真检测电路， 其特征在于， 所述第二触发单元 为第二 D触发器， 所述第二 D触发器的复位端、 吋钟端、 输入端及输 出端分别为所述第二触发单元的复位端、 吋钟输入端、 输入端及输出 [权利要求 9] 一种 D类音频功率放大器， 包括前置放大模块、 脉冲宽度调制模块、 输出级功率放大模块及增益衰减模块， 所述前置放大模块对差分输入 模拟音频信号进行放大并输出差分放大模拟音频信号， 所述脉冲宽度 调制模块对所述差分放大模拟音频信号进行脉冲宽度调制并输出两路 PWM信号， 所述输出级功率放大模块对所述两路 PWM信号进行放大 及滤波处理后输出， 其特征在于， 所述 D类音频功率放大器还包括权 利要求 1至 8任一项所述的失真检测电路；
当所述滤波处理输出的模拟音频信号发生失真吋， 所述失真检测电路 输出所述失真指示信号， 所述增益衰减模块根据所述失真指示信号输 出相应的控制信号至所述前置放大模块， 所述前置放大模块根据所述 控制信号降低对所述差分输入模拟音频信号的放大幅度。
[权利要求 10] —种 D类音频功率放大芯片， 其特征在于， 所述 D类音频功率放大芯 片包括权利要求 9所述的 D类音频功率放大器。
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