WO2017181581A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2017181581A1
WO2017181581A1 PCT/CN2016/098882 CN2016098882W WO2017181581A1 WO 2017181581 A1 WO2017181581 A1 WO 2017181581A1 CN 2016098882 W CN2016098882 W CN 2016098882W WO 2017181581 A1 WO2017181581 A1 WO 2017181581A1
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Prior art keywords
slit
electrode
pixel
sub
array substrate
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PCT/CN2016/098882
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English (en)
French (fr)
Inventor
刘晓那
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/541,739 priority Critical patent/US10401685B2/en
Publication of WO2017181581A1 publication Critical patent/WO2017181581A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the display mode of the liquid crystal display mainly includes Fringe Field Switching (FFS) technology, High Aperture Ratio Advanced-Super Dimensional Switching (HADS) technology, and plane switching (In-Plane Switching). , IPS) technology, Vertical Alignment (VA) technology, etc.
  • FFS Fringe Field Switching
  • HADS High Aperture Ratio Advanced-Super Dimensional Switching
  • VA Vertical Alignment
  • the disadvantage of the FFS mode is that since the pixel electrode adopts the slit electrode 10 as shown in FIG. 1, a dark region as shown in FIG. 2 is generated at the edge of the sub-pixel, which affects the sub-pixel transmittance.
  • the common electrode adopts a slit electrode, and the corner position of the slit electrode is adjusted from the long side position of the sub-pixel to the short side position of the sub-pixel, and the light leakage simulation diagram is as shown in FIG. 3, and it can be seen that the dark area problem is improved. , but the improvement effect is limited.
  • the embodiment of the present invention provides an array substrate, a manufacturing method thereof, and a display device, which can solve the problem that the dark area of the sub-pixel edge is too large, thereby improving the transmittance and improving the liquid crystal efficacy.
  • At least one embodiment of the present invention provides an array substrate including: a slit electrode, wherein the slit electrode includes a plurality of slits, one end of each of the slits being open.
  • At least one embodiment of the present invention also provides a display device including the array substrate according to at least one embodiment of the present invention.
  • At least one embodiment of the present invention further provides a method for fabricating an array substrate, comprising: a process of forming a slit electrode, the process of forming a slit electrode, comprising: depositing an electrode material layer; forming a slit electrode by using a mask process, On the mask used in the mask process, a portion corresponding to the slit of the slit electrode extends to the edge of the sub-pixel so that one end of the slit of the slit electrode formed is opened.
  • FIG. 1 is a schematic structural view of an FFS mode array substrate
  • Figure 2 is a simulation diagram of light leakage in FFS mode
  • Figure 3 is a schematic diagram of a HADS mode light leakage
  • FIG. 4 is a schematic structural diagram of an FFS mode array substrate according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional structural diagram of an FFS mode display device according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a HADS mode array substrate according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional structural diagram of a HADS mode display device according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a dual domain sub-pixel of an FFS mode according to an embodiment of the present invention.
  • FIG. 9 is a schematic view of a slit electrode of a HADS having a corner design
  • FIG. 10 is a schematic diagram of a HADS mode sub-pixel with a corner design according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an FFS mode dual domain sub-pixel according to an embodiment of the present invention.
  • Figure 12 is a schematic view showing the detail of the slit corner design in the embodiment of the present invention.
  • the array substrate includes a slit electrode 10, and the slit 111 of the slit electrode 10 is open at one end.
  • 11 in FIG. 4 is a data line, and 12 is a gate line.
  • One sub-pixel 01 is shown in FIG.
  • the sub-pixel 01 can be composed of a plurality of gate lines 12 and a plurality of data lines 11 are defined, but are not limited thereto.
  • One sub-pixel 01 includes, for example, a gate line, a data line, a pixel electrode, and a switching element.
  • the switching element is, for example, a thin film transistor.
  • the sub-pixel 01 is the smallest unit in the array substrate for display.
  • the slit electrode 10 includes a plurality of electrode strips 101.
  • the plurality of electrode strips 101 are electrically connected.
  • adjacent two electrode strips 101 are parallel to each other.
  • Between adjacent two electrode strips 101 is a slit 111, and an opening of the slit 111 between one of the electrode strips 101 and two adjacent electrode strips 101 is located on a different side of the slit electrode 10, for example, in a slit
  • the opposite sides include, for example, the left and right sides, the upper side and the lower side. As shown in FIG.
  • the slit 111 between the electrode strip 1010 and the two electrode strips adjacent thereto is a slit 1111 and a slit 1112, respectively, and the opening of the slit 1111 and the opening of the slit 1112 are located at the slit electrode 10.
  • the opening of the slit 1111 and the opening of the slit 1112 are located on the right and left sides of the sub-pixel 01, respectively.
  • the slit electrode in the sub-pixel 01, includes an electrode trace having a plurality of bent structures.
  • the slit electrode 10 shown in FIG. 4 is an electrode trace as a whole, and the electrode trace has a plurality of bent structures.
  • the slit electrode may further include a plurality of electrode traces having a plurality of bent structures.
  • the slit electrode in Fig. 8 includes two electrode traces having a plurality of bent structures.
  • the conventional slit electrode is as shown in FIG. 1.
  • the two ends of the slit 111 are closed structures.
  • the slit 111 located at the edge of the sub-pixel is used.
  • the closed position design was improved to have a certain corner structure.
  • the inventors found that the sub-pixel edge would produce a dark area during the actual test, as shown in FIGS. 2 and 3.
  • one end of the slit 111 in the slit electrode 10 is opened, that is, an open structure is adopted, and the edge of the sub-pixel can be opened along the slit or the corner of the original sub-pixel has a corner shape.
  • the design is opened along the corner of the end of the slit; the other end retains the closed structure, and the closed structure still adopts the design of the corner of the sub-pixel edge so that the various portions of the slit electrode 10 can still be electrically connected together while avoiding A tearing (Tracing Mura) problem occurs when the finger is pressed.
  • the slit electrode 10 includes a plurality of slits 111. This embodiment does not limit which end portion of the slits are open-ended, as long as the respective portions of the slit electrode 10 can be electrically connected together. Just fine.
  • the slit electrode 10 may also include a closed slit, which is not limited in this embodiment.
  • a slit electrode 10 has the following structure: a zigzag trace in a sub-pixel region, and a corner of the zigzag trace may be located at two long edge edges of the sub-pixel as shown in FIG. 4; As shown in FIG. 10, they are respectively located at the two short side edges of the sub-pixel.
  • the zigzag traces in the sub-pixel region may be closed at the beginning end of the odd-line slit 111, and closed at the beginning end of the even-row slit 111. Of course, it may also be an odd-line slit 111.
  • the start end is closed at the end, and the start end of the even line slit 111 is closed at the end.
  • the slit electrode is improved, and one end of the slit is opened to reduce the occlusion of the sub-pixel edge, thereby solving the problem that the dark area of the sub-pixel edge is too large, thereby achieving the transmission. Increase the rate and improve the liquid crystal efficiency.
  • the FFS mode display device includes an array substrate 20, a color filter substrate 30, and a liquid crystal 40.
  • the color filter substrate 30 includes a base substrate 31 and is disposed on the base substrate 31.
  • the FFS mode array substrate 20 includes a base substrate 21 and a common electrode 22, a gate insulating layer 23, and a source/drain metal layer 24 disposed on the base substrate 21 (corresponding to the data lines 11, for example, source, drain, and data lines)
  • the layer is formed, the insulating layer 25 and the pixel electrode 26, the pixel electrode 26 is a slit electrode, and the slit 111 of the slit electrode is opened at the start end or the end end.
  • the simulated leakage pattern of the FFS mode display device is compared with that of FIG. 2, and the dark area of the left and right edges of the sub-pixel is greatly reduced, and the transmittance is improved.
  • the HADS mode display device includes an array substrate 20, a color filter substrate 30, and a liquid crystal 40.
  • the color filter substrate 30 includes a base substrate 31 and is disposed on the base substrate 31.
  • the HADS array substrate 20 includes a base substrate 21 and a common electrode 22, a gate insulating layer 23, and a source/drain metal layer 24 disposed on the base substrate 21 (corresponding to the data line 11, for example, the source, the drain, and the data line are in the same layer
  • the insulating layer 25 and the pixel electrode 26 are formed, and the common electrode 22 is a slit electrode, and the slit 111 thereon is opened at the start end or the end end.
  • the simulated leakage pattern of the HADS mode display device is compared with that of FIG. 3, and the dark area of the upper and lower edges of the sub-pixel is also reduced, and the transmittance is improved.
  • the solution of this embodiment can also be applied to dual-domain and multi-domain sub-pixels, taking a two-domain sub-pixel as an example, as shown in FIG. 8, which is a two-domain sub-pixel of FFS mode, in the first region of the sub-pixel, the slit
  • the slit 111 of the electrode 10 extends in the first direction; in the second region of the sub-pixel, the slit 111 of the slit electrode 10 extends in the second direction, and the first direction is not parallel to the second direction. Due to the narrowness of the slit electrode 10
  • the slits 111 have different extending directions, and after the power is driven, the orientations of the liquid crystals of the first and second regions of the sub-pixel are not uniform, and a double domain is formed. Dual domain and multi-domain sub-pixels can improve the problem of narrow viewing angles.
  • the slit 111 of the slit electrode 10 may have a different shape, that is, the shape of the slit 111 of the slit electrode 10 may be changed.
  • the slit 111 may be at both ends of the slit electrode. Including the corner, as shown in FIG. 9, is a schematic diagram of a slit electrode of HADS.
  • the slit 111 has an open structure at one end, as long as the end of the slit (one end of the open structure, the right end in the figure) extends along the corner of the slit until the closed structure is opened; One end of the opening maintains the original corner structure unchanged, as shown in FIG.
  • FIG. 11 is a schematic diagram of a dual-domain FFS mode sub-pixel provided by an embodiment of the present invention, and one end of the slit 111 is opened in a corner direction.
  • the array substrate provided by the embodiment of the invention opens one end of the slit to reduce the occlusion of the edge of the sub-pixel, and solves the problem that the dark area of the sub-pixel edge is too large, thereby improving the transmittance.
  • the embodiment of the invention further provides a display device comprising any of the above array substrates.
  • the dark area generated by the edge of the sub-pixel of the display device is small, the transmittance is high, and energy saving is saved.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a watch, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the invention further provides a method for manufacturing an array substrate, comprising: a step of forming a slit electrode, the step of forming a slit electrode comprising: step one, depositing an electrode material layer; and step two, using a mask process to form a narrow
  • the slit electrode, the mask plate used in the mask process, the portion corresponding to the slit of the slit electrode extends to the edge of the sub-pixel so that the slit of the formed slit electrode is open at one end.
  • the method for manufacturing an array substrate according to the embodiment further improves the process of forming the slit electrode, and modifies the mask plate forming the slit electrode pattern, and correspondingly the slit of the slit electrode corresponding to the slit electrode.
  • the embodiment extends to the edge of the sub-pixel so that the slit formed at one end is open, and the embodiment of the present invention is not limited except for the conventional method.
  • the slit of the slit electrode is opened at one end, which can reduce the occlusion of the edge of the sub-pixel, and solve the problem that the area of the dark region generated by the edge of the sub-pixel is too large, thereby improving the transmittance.
  • the method before the step of forming the slit electrode, the method further includes: designing the slit electrode, for example, the outer contour of the slit electrode, the width and shape of the slit, The number of slits at one end and the size and shape of the opening at the opening are designed in such a way that the dark area of the edge of the sub-pixel is minimized and the transmittance is the highest.
  • the design also involves the design of the first angle ( ⁇ 1), the second angle ( ⁇ 2) and the corner height h of the corner. The design standard is still to minimize the dark area of the sub-pixel edge and increase Transmittance.

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Abstract

一种阵列基板及其制造方法、显示装置。阵列基板包括狭缝电极（10），狭缝电极（10）包括多个狭缝（111），每个狭缝（111）的一端开口，解决了子像素边缘暗区面积过大的问题，进而实现透过率提升，从而提升了液晶光效。

Description

阵列基板及其制造方法、显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制造方法、显示装置。
背景技术
通常，液晶显示器的显示模式主要包括边缘场开关(Fringe Field Switching，FFS)技术、高开口率高级超维场开关(High Aperture ratio Advanced-Super Dimensional Switching，HADS)技术、平面转换(In-Plane Switching，IPS)技术、垂直配向(Vertical Alignment，VA)技术等。FFS模式的弊端在于，由于像素电极采用如图1所示的狭缝电极10，会在子像素边缘产生如图2所示的暗区，影响子像素透过率。HADS模式中，公共电极采用狭缝电极，并将狭缝电极的拐角位置由子像素长边位置调整到子像素短边位置，其漏光模拟图如图3所示，可以看出暗区问题得到改善，但改善效果有限。
发明内容
本发明的实施例提供一种阵列基板及其制造方法、显示装置，可解决子像素边缘暗区面积过大的问题，进而实现透过率提升，提升液晶光效。
本发明至少一实施例提供一种阵列基板，包括：狭缝电极，其中，所述狭缝电极包括多个狭缝，每个所述狭缝的一端开口。
本发明至少一实施例还提供一种显示装置，包括本发明至少一实施例所述的阵列基板。
本发明至少一实施例还提供一种阵列基板的制造方法，包括：形成狭缝电极的工序，所述形成狭缝电极工序，包括：沉积电极材料层；利用掩膜工艺，形成狭缝电极，掩膜工艺使用的掩膜板上，与所述狭缝电极的狭缝对应的部分延伸至子像素边缘，以使形成的所述狭缝电极的狭缝一端开口。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种FFS模式阵列基板的结构示意图；
图2为一种FFS模式漏光模拟图；
图3为一种HADS模式漏光模拟图；
图4为本发明实施例提供的FFS模式阵列基板的结构示意图；
图5为本发明实施例提供的FFS模式显示装置的剖面结构示意图；
图6为本发明实施例提供的HADS模式阵列基板的结构示意图；
图7为本发明实施例提供的HADS模式显示装置的剖面结构示意图；
图8为本发明实施例提供的FFS模式的双畴子像素示意图；
图9为一种具有拐角设计的HADS的狭缝电极示意图；
图10为本发明实施例提供的具有拐角设计的HADS模式子像素的示意图；
图11为本发明实施例提供的FFS模式双畴子像素的示意图；
图12为本发明实施例中狭缝拐角设计细节示意图。
附图标记：
10-狭缝电极，111-狭缝，11-数据线，12-栅线，20-阵列基板，30-彩膜基板，40-液晶，31-衬底基板，32-彩膜层，21-衬底基板，22-公共电极，23-栅绝缘层，24-源漏金属层，25-绝缘层，26-像素电极；101-电极条；1010-电极条；1111、1112-狭缝；01-子像素。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明至少一实施例提供一种阵列基板，参照图4所示，该阵列基板包括狭缝电极10，该狭缝电极10的狭缝111一端开口。图4中的11为数据线，12为栅线。图4中示出了一个子像素01。例如，子像素01可以由多条栅线 12和多条数据线11限定而得，但不限于此。一个子像素01例如包括一条栅线、一条数据线、一个像素电极和一个开关元件。开关元件例如为薄膜晶体管。子像素01为阵列基板中最小的用以进行显示的单元。
如图4所示，狭缝电极10包括多个电极条101。多个电极条101电连接。例如，在同一畴内，相邻的两个电极条101互相平行。相邻两个电极条101之间为狭缝111，其中一个电极条101和与其相邻的两个电极条101之间的狭缝111的开口位于狭缝电极10的不同侧，例如位于狭缝电极10的相对侧。相对侧例如包括左侧和右侧，上侧和下侧。如图4所示，电极条1010和与其相邻的两个电极条之间的狭缝111分别为狭缝1111和狭缝1112，狭缝1111的开口和狭缝1112的开口位于狭缝电极10的不同侧，狭缝1111的开口和狭缝1112的开口分别位于子像素01的右侧和左侧。
如图4所示，在子像素01内，狭缝电极包括具有多个弯折结构的电极走线。图4中示出的狭缝电极10整体上即为一条电极走线，该电极走线具有多个弯折结构。例如当子像素具有多个畴时，在子像素01内，狭缝电极还可以包括多个具有多个弯折结构的电极走线。图8中的狭缝电极包括两条具有多个弯折结构的电极走线。
通常的狭缝电极如图1所示，狭缝111的两端是封闭结构，为了改善产品显示品质，避免手指按下会出现显示扭曲(Tracing Mura)的问题，位于子像素边缘的狭缝111闭合位置设计改进为具有一定拐角结构，如图9所示，发明人发现实际测试时子像素边缘会产生暗区，如图2和图3所示。本发明一实施例中将狭缝电极10中的狭缝111的一端打开，即采用开放式结构，在子像素边缘可采用沿着狭缝走向打开或保留原有子像素边缘有拐角形貌的设计，沿着狭缝末端的拐角走向打开；另一端保留封闭结构，封闭结构仍采用子像素边缘有拐角形貌的设计，以使狭缝电极10的各个部分仍然能够电连接在一起，同时避免手指按下会出现显示扭曲(Tracing Mura)问题。
可以理解的是，狭缝电极10包括多个狭缝111，本实施例对具体哪些狭缝的哪一端部采用开放式结构不做限定，只要保证狭缝电极10的各个部分能够电连接在一起即可。狭缝电极10也可以包括封闭的狭缝，本实施例对此不作限定。例如，一种狭缝电极10的结构如下：在子像素区域内的之字形走线，之字形走线的拐角可以如图4所示，分别位于子像素的两个长边边缘；也可 以如图10所示，分别位于子像素的两个短边边缘。
在子像素区域内的之字形走线，可以是奇数行狭缝111的起始端封闭末尾端打开，偶数行狭缝111的起始端打开末尾端封闭，当然，也可以是奇数行狭缝111的起始端打开末尾端封闭，偶数行狭缝111的起始端封闭末尾端打开。
本发明实施例提供的阵列基板，对狭缝电极进行了改进，将狭缝的一端开口，以降低子像素边缘的遮挡，解决子像素边缘产生的暗区面积过大的问题，进而实现透过率提升，提升液晶光效。
为了本领域技术人员更好的理解本发明实施例提供的技术方案，下面通过具体的实施例对阵列基板结构进行详细说明。
本发明一实施例中，如图4和图5所示，FFS模式显示装置包括阵列基板20和彩膜基板30和液晶40，彩膜基板30包括衬底基板31和设置于衬底基板31上的彩膜层32。FFS模式阵列基板20包括衬底基板21和设置于衬底基板21上的公共电极22、栅绝缘层23、源漏金属层24(对应数据线11，例如，源极、漏极和数据线同层形成)、绝缘层25和像素电极26，像素电极26为狭缝电极，且狭缝电极的狭缝111在起始端或末尾端开口。FFS模式显示装置的模拟漏光图与图2对比，子像素左右两侧边缘的暗区面积大大减小，透过率提升。
本发明另一实施例中，如图6和图7所示，HADS模式显示装置包括阵列基板20、彩膜基板30和液晶40，彩膜基板30包括衬底基板31和设置于衬底基板31上的彩膜层32。HADS阵列基板20包括衬底基板21和设置于衬底基板21上的公共电极22、栅绝缘层23、源漏金属层24(对应数据线11，例如，源极、漏极和数据线同层形成)、绝缘层25和像素电极26，公共电极22为狭缝电极，且其上的狭缝111在起始端或末尾端开口。HADS模式显示装置的模拟漏光图与图3对比，同样在子像素的上下两侧边缘的暗区面积减小，透过率提升。
本实施例方案还可以应用于双畴及多畴子像素，以双畴子像素为例，见图8所示，为FFS模式的双畴子像素，在子像素的第一区域内，狭缝电极10的狭缝111沿第一方向延伸；在子像素的第二区域内，狭缝电极10的狭缝111沿第二方向延伸，且第一方向与第二方向不平行。由于狭缝电极10的狭 缝111延伸方向不同，加电驱动后，该子像素的第一、第二区域液晶的取向并不一致，形成双畴。双畴及多畴子像素可以改善视角过窄问题。
另外，具体实施时，狭缝电极10的狭缝111可为不同的形状，即狭缝电极10的狭缝111形状可以变化，例如为了克服Trace Mura，狭缝电极中狭缝111两端还可包括拐角，如图9所示，为一种HADS的狭缝电极示意图。应用本实施例的方案时，狭缝111一端采用开放式结构，只要在狭缝末端(开放式结构的一端，如图中的右端)沿狭缝的拐角趋势延伸继续直至打开封闭结构为止；未开口的一端保持原有拐角结构不变，具体如图10所示。再例如，图11所示，为本发明实施例提供的双畴FFS模式子像素示意图，狭缝111的一端沿拐角方向打开。
本发明实施例提供的阵列基板，将狭缝的一端开口，以降低子像素边缘的遮挡，解决子像素边缘产生的暗区面积过大的问题，进而实现透过率提升。
本发明实施例还提供一种显示装置，其包括上述任意一种阵列基板。所述显示装置子像素边缘产生的暗区面积小，透过率高，节能省电。所述显示装置可以为：液晶面板、电子纸、手机、手表、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例还提供一种阵列基板的制造方法，包括：形成狭缝电极的工序，所述形成狭缝电极工序包括：步骤一、沉积电极材料层；步骤二、利用掩膜工艺，形成狭缝电极，掩膜工艺使用的掩膜板上，与所述狭缝电极的狭缝对应的部分延伸至子像素边缘，以使形成的狭缝电极的狭缝一端开口。
本实施例还提供的阵列基板制造方法，对形成狭缝电极的工序进行了改进，将形成狭缝电极图形的掩膜板做了改动，将掩膜板上与狭缝电极的狭缝对应的部分延伸至子像素边缘，以使形成的狭缝一端开口，除此之外与通常方法大致类似，本发明的实施例不做限定。利用本实施例阵列基板制造方法，形成狭缝电极的狭缝一端开口，可以降低子像素边缘的遮挡，解决通常子像素边缘产生的暗区面积过大的问题，进而实现透过率提升。
例如，作为本发明实施例上述制造方法的一种改进，形成狭缝电极工序之前，还包括：对狭缝电极进行设计，例如可以是对狭缝电极的外轮廓、狭缝的宽度、形状、一端开口狭缝的数目以及开口处开口的大小形状等进行设计，设计标准为使子像素边缘的暗区面积最小，透过率最高。如图12所示， 如果狭缝末端存在拐角，设计时还涉及对拐角的第一角度(θ1)、第二角度(θ2)和拐角高度h的设计，设计标准仍然是尽量减小子像素边缘的暗区面积，增加透过率。
当然，本领域技术人员可以理解的是，对狭缝电极进行优化设计时，除要求子像素边缘的暗区面积尽量减小之外，同时也要兼顾设计后狭缝电极处驱动电场能够符合其它设计要求，因此实际操作中，实际上只能使子像素边缘的暗区面积尽量减小，不一定能达到最小的理想化目标。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。
本专利申请要求于2016年4月21日递交的中国专利申请第201610258014.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种阵列基板，包括：狭缝电极，其中，所述狭缝电极包括多个狭缝，每个所述狭缝的一端开口。
  2. 根据权利要求1所述的阵列基板，其中，相邻两个狭缝的开口分别位于子像素的相对侧。
  3. 根据权利要求1所述的阵列基板，其中，在子像素内，所述狭缝电极包括具有多个弯折结构的电极走线。
  4. 根据权利要求1所述的阵列基板，其中，所述狭缝电极为像素电极，或者，所述狭缝电极为公共电极。
  5. 根据权利要求1所述的阵列基板，其中，子像素为双畴子像素，在所述子像素的第一区域内，所述狭缝电极的狭缝沿第一方向延伸；在所述子像素的第二区域内，所述狭缝电极的狭缝沿第二方向延伸，且所述第一方向与所述第二方向不平行。
  6. 根据权利要求3所述的阵列基板，其中，所述电极走线的拐角分别位于子像素的两个长边边缘。
  7. 根据权利要求3所述的阵列基板，其中，所述电极走线的拐角分别位于子像素的两个短边边缘。
  8. 一种显示装置，包括权利要求1-7任一项所述的阵列基板。
  9. 一种阵列基板的制造方法，包括：形成狭缝电极的工序，所述形成狭缝电极工序，包括：
    沉积电极材料层；
    利用掩膜工艺，形成狭缝电极，其中，掩膜工艺使用的掩膜板上，与所述狭缝电极的狭缝对应的部分延伸至子像素边缘，以使形成的所述狭缝电极的狭缝一端开口。
  10. 根据权利要求9所述的制造方法，其中，形成所述狭缝电极工序之前，还包括：
    对所述狭缝电极进行设计，设计标准为使所述子像素边缘的暗区面积最小，透过率最大。
  11. 根据权利要求9所述的制造方法，其中，相邻两个狭缝的开口分别 位于子像素的相对侧。
  12. 根据权利要求9所述的制造方法，其中，在子像素内，所述狭缝电极包括具有多个弯折结构的电极走线。
  13. 根据权利要求12所述的制造方法，其中，所述电极走线的拐角分别位于子像素的两个长边边缘。
  14. 根据权利要求12所述的制造方法，其中，所述电极走线的拐角分别位于子像素的两个短边边缘。
  15. 根据权利要求9-14任一项所述的制造方法，其中，所述狭缝电极为像素电极，或者，所述狭缝电极为公共电极。
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