WO2019041922A1 - 阵列基板及制造方法、显示面板及制造方法、显示装置 - Google Patents

阵列基板及制造方法、显示面板及制造方法、显示装置 Download PDF

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Publication number
WO2019041922A1
WO2019041922A1 PCT/CN2018/089005 CN2018089005W WO2019041922A1 WO 2019041922 A1 WO2019041922 A1 WO 2019041922A1 CN 2018089005 W CN2018089005 W CN 2018089005W WO 2019041922 A1 WO2019041922 A1 WO 2019041922A1
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Prior art keywords
substrate
reflective layer
layer
disposed
array substrate
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PCT/CN2018/089005
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English (en)
French (fr)
Inventor
王洪润
祝明
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/335,649 priority Critical patent/US20200026133A1/en
Publication of WO2019041922A1 publication Critical patent/WO2019041922A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a manufacturing method thereof, a display panel, a manufacturing method, and a display device.
  • the display device is a device for displaying characters, numbers, symbols, pictures, or images formed by at least two combinations of characters, numbers, symbols, and pictures, and provides greater convenience for people's life and work.
  • the display device usually includes a display panel.
  • a general display panel such as a liquid crystal display panel, generally includes an array substrate (Array substrate), a color filter substrate (Color filter substrate, a CF substrate or a color filter substrate), and an array substrate and color filter.
  • the liquid crystal layer between the substrates is applied to the light passing through the liquid crystal layer by the filter layer on the color filter substrate to realize colorization of the display device.
  • the filter layer cannot completely cover the area other than the thin film transistor in the corresponding pixel region (ie, the effective display area of the pixel region), for example, for flexibility.
  • the filter layer in the bend region of the flexible reflective display panel may not completely cover the area other than the thin film transistor in the corresponding pixel region, thereby causing display. Light leakage from the panel.
  • an array substrate including: a substrate substrate on which a reflective layer is disposed; a filter layer disposed on a side of the reflective layer away from the substrate; and a pixel electrode Provided on a side of the filter layer away from the reflective layer.
  • the array substrate further includes a thin film transistor between the substrate substrate and the reflective layer; at least one of the reflective layer and the filter layer covers the thin film transistor At least part of it.
  • the array substrate further includes: a plurality of gate lines disposed in the same layer as the gate of the thin film transistor; a plurality of data lines disposed across the plurality of gate lines, and a source of the thin film transistor And a drain layer disposed in the same layer; and a black matrix disposed on a side of the thin film transistor away from the base substrate, wherein the plurality of data lines and the plurality of gate lines disposed at the intersection define the plurality of first regions
  • the black matrix defines a plurality of open regions, and an orthographic projection of each of the first regions on the base substrate falls within an orthographic projection of the corresponding open region on the base substrate.
  • the array substrate further includes: a plurality of gate lines disposed in the same layer as the gate of the thin film transistor; a plurality of data lines disposed across the plurality of gate lines, and a source of the thin film transistor And a drain layer disposed in the same layer; and a black matrix disposed on a side of the thin film transistor away from the base substrate, wherein the plurality of data lines and the plurality of gate lines disposed at the intersection define the plurality of first regions
  • the black matrix defines a plurality of open regions, and an orthographic projection of each of the first regions on the base substrate coincides with an orthographic projection of a corresponding open region on the base substrate.
  • a thin film transistor is disposed in each of the first regions, and an orthographic projection of at least one of the reflective layer and the filter layer on the substrate substrate and a plurality of open regions are lined The orthographic projections on the base substrate substantially coincide.
  • the reflective layer and the filter layer are both disposed in a plurality of open regions, and the orthographic projections of the reflective layer and the filter layer on the substrate are both lined with a plurality of open regions.
  • the orthographic projections on the base substrate substantially coincide.
  • an orthographic projection of the reflective layer on the substrate substantially completely covers the substrate, the black matrix and the filter layer being disposed on the reflective layer away from the substrate On one side, the filter layer is disposed in a plurality of open regions, and the orthographic projection of the filter layer on the base substrate substantially coincides with the orthographic projection of the plurality of open regions on the substrate.
  • the array substrate further includes: a common electrode disposed on a side of the filter layer away from the reflective layer.
  • the reflective layer is a metallic reflective layer.
  • a display panel comprising: the array substrate according to any of the preceding embodiments, and an opposite substrate disposed opposite to the array substrate and disposed at a pixel electrode away from the substrate On one side, a common electrode is disposed on a surface of the opposite substrate facing the array substrate.
  • a display panel includes: the array substrate according to the foregoing embodiment, and an opposite substrate disposed in parallel with the array substrate, and disposed at the pixel electrode and the common electrode away from the substrate One side of the substrate.
  • a display device is provided, wherein the display device includes the display panel as described in the foregoing embodiments.
  • a method of fabricating an array substrate includes: providing a substrate; forming a reflective layer on the substrate; forming a filter layer on a side of the reflective layer away from the substrate; And forming a pixel electrode on a side of the filter layer away from the reflective layer.
  • the manufacturing method before the forming a reflective layer on the base substrate, the manufacturing method further includes: forming a thin film transistor on the base substrate; wherein the reflective layer is disposed on the thin film transistor away from the base substrate At one side, at least one of the reflective layer and the filter layer covers at least a portion of the thin film transistor.
  • the method of fabricating the array substrate further includes: forming a plurality of gate lines on the substrate; forming a plurality of gate lines on the substrate substrate a data line; and forming a black matrix on a side of the thin film transistor away from the base substrate, wherein the intersecting multi-data lines and gate lines define a plurality of first regions, the black matrix defining a plurality Opening regions, each of the first regions having an orthographic projection on the substrate substrate falls within an orthographic projection of the corresponding opening region on the substrate, or each of the first regions is in the The orthographic projection on the base substrate coincides with the orthographic projection of the corresponding open area on the substrate.
  • the black matrix is formed before forming a reflective layer, the reflective layer and the filter layer are formed in the plurality of open regions, and the reflective layer and the filter layer are on the base substrate
  • the orthographic projections are substantially coincident with the orthographic projections of the plurality of open regions on the substrate.
  • the black matrix is formed after forming a reflective layer and forming a filter layer, an orthographic projection of the reflective layer on the substrate substantially completely covering the substrate, the black matrix And the filter layer is formed on a side of the reflective layer away from the substrate, the filter layer is formed in the plurality of open regions, the orthographic projection of the filter layer on the base substrate and the plurality of openings The orthographic projections of the regions on the substrate of the substrate substantially coincide.
  • the method of fabricating the array substrate further includes: forming a common electrode on a side of the filter layer away from the reflective layer.
  • a method of manufacturing a display panel comprising: the method for fabricating an array substrate according to any of the preceding embodiments, providing a counter substrate, and forming a common electrode on the opposite substrate; And a pair of the array substrate and the opposite substrate.
  • a method of fabricating a display panel including the method of fabricating an array substrate as described in the foregoing embodiments, provides a counter substrate, and a counter array substrate and a counter substrate.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of a reflective layer layout in a plan view of the array substrate of FIG. 1;
  • FIG. 3 is a schematic structural view of a layout of a reflective layer in a plan view of the array substrate of FIG. 1;
  • FIG. 4 is a schematic cross-sectional view of another array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural view of a reflective layer layout in a plan view of the array substrate of FIG. 4;
  • FIG. 6 is a schematic structural view of a reflective layer layout in a plan view of the array substrate of FIG. 4;
  • FIG. 7 is a schematic cross-sectional structural view of still another display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional structural view of still another display panel according to an embodiment of the present disclosure.
  • 9-13 are flowcharts of a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • the related art adopts a COA (Color Filter On Array) technology.
  • the filter layer is integrated on the array substrate, so that the filter layer can completely cover the area other than the thin film transistor in the corresponding pixel region when the display panel is bent, thereby preventing the display panel from leaking light.
  • COA Color Filter On Array
  • the Applicant has found that due to the structure of the display panel and the limitation of the operation mode in the related art, a voltage is applied to the pixel electrode and the common electrode in the display panel, respectively, and the voltage difference generated between the pixel electrode and the common electrode is used to drive the liquid crystal layer. When the liquid crystal is deflected, a large voltage difference is usually required to drive the liquid crystal deflection, resulting in an increase in power consumption of the display panel.
  • An embodiment of the present disclosure provides an array substrate, including: a substrate substrate, a reflective layer, a filter layer, and a pixel electrode.
  • the reflective layer is disposed on the base substrate, and the filter layer is disposed on the reflective layer away from the substrate.
  • the side, and the pixel electrode are disposed on a side of the filter layer away from the reflective layer.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of a reflective layer layout in a top view of the array substrate of FIG. 1
  • FIG. 3 is a top view of the array substrate of FIG. FIG. 1 , FIG. 2 and FIG. 3
  • an embodiment of the present disclosure provides an array substrate including a substrate substrate 1 , a reflective layer 15 , a filter layer 18 , and a pixel electrode 23 .
  • the common electrode 21 wherein the reflective layer 15 and the filter layer 18 are sequentially disposed on the base substrate 1, that is, the filter layer 18 is located on a side of the reflective layer 15 away from the base substrate 1, and the pixel electrode 23 and the common electrode 21 are both Located on the side of the filter layer 18 away from the reflective layer 15.
  • the array substrate provided in this embodiment is applied to a display panel of a reflective display device.
  • a filter layer is adopted by using COA technology.
  • 18 is integrated on the array substrate, and the common electrode 21 is also integrated on the array substrate.
  • the array substrate in this embodiment is, for example, an FFS (Fringe Field Switching) mode array substrate.
  • the array substrate provided in this embodiment includes a base substrate 1, a reflective layer 15, a filter layer 18, a pixel electrode 23, and a common electrode 21, and the reflective layer 15 and the filter layer 18 are sequentially disposed on the base substrate 1. That is, the filter layer 18 is located on the side of the reflective layer 15 away from the substrate 1, and the pixel electrode 23 and the common electrode 21 are located above the filter layer 18, that is, the pixel electrode 23 and the common electrode 21 are located at the filter layer 18 away from the reflective layer.
  • the arrangement of the pixel electrode 23 and the common electrode 21 can be set according to actual needs. For example, referring to FIG. 1 , the common electrode 21 can be located between the filter layer 18 and the pixel electrode 23 .
  • the common electrode 21 is formed on the third passivation layer 19, and then the fourth passivation layer 22 is formed, and the fourth passivation layer 22 covers the third blunt layer.
  • the layer 19 and the common electrode 21 are then formed on the fourth passivation layer 22 to form the pixel electrode 23.
  • the reflective layer 15 and the filter layer 18 are sequentially disposed on the base substrate 1.
  • the pixel electrode 23 and the common electrode 21 are disposed on the side of the filter layer 18 away from the reflective layer 15, and thus
  • the electric field generated between the pixel electrode 23 and the common electrode 21 does not pass through the filter layer 18, and thus the filter
  • the light layer 18 does not adversely affect the voltage difference generated between the pixel electrode 23 and the common electrode 21, so that the voltage difference required when driving the liquid crystal deflection can be reduced, thereby reducing the power consumption of the display panel.
  • the reflective layer 15 functions only to reflect light, and does not function as, for example, an electrode, and the function of the reflective layer 15 is single, so that the structure of the reflective layer 15 can be conveniently set. At the same time, it is also possible to prevent the reflection layer from adversely affecting the potential of the pixel electrode 23 or the common electrode 21 when the reflective layer 15 functions as an electrode.
  • the structure of the reflective layer 15 can be various.
  • the array substrate provided in this embodiment includes a plurality of gate lines 12 and a plurality of data lines 13 defined by intersections. a plurality of first regions 24, each of which is provided with a thin film transistor 11, each of the first regions 24 corresponding to a pixel electrode 23 and a common electrode 21, and a gate 111 of the thin film transistor 11 and a corresponding gate
  • the line 12 is electrically connected
  • the source 114 of the thin film transistor 11 is electrically connected to the corresponding data line 13
  • the drain 115 of the thin film transistor 11 is connected to the corresponding pixel electrode 23, and the thin film transistor 11 is located between the base substrate 1 and the reflective layer 15.
  • the orthographic projection of the reflective layer 15 on the base substrate 1 is located within the orthographic projection of the first region 24 on the base substrate 1, and the reflective layer 15 covers the region other than the thin film transistor 11 in the first region, and the reflective layer 15 is further Covering at least a portion of the thin film transistor 11, for example, the reflective layer 15 may cover a region other than the thin film transistor 11 in the first region 24 and a partial region of the thin film transistor 11, and at this time, the coverage area of the reflective layer 15 is smaller than that corresponding to the first region Area, or, referring to FIG. 1 and FIG. 2, the orthographic projection of the reflective layer 15 on the substrate 1 coincides with the orthographic projection of the first region 24 on the substrate 1, and the reflective layer 15 may cover the entire first region. That is, the reflective layer 15 simultaneously covers a region other than the thin film transistor 11 in the first region and the thin film transistor 11.
  • the thin film transistor 11 is formed in the first region 24 on the base substrate 1.
  • the thin film transistor 11 includes a gate 111, a gate insulating layer 112, an active layer 113, a source 114, and
  • the drain electrode 115, the gate electrode 111 and the gate line 12 are disposed in the same layer, and the gate electrode 111 is electrically connected to the corresponding gate line 12, and the gate insulating layer 112 covers the gate electrode 111, the gate line 12 and the substrate substrate 1, and it is also understood
  • the base substrate 1 on which the gate electrode 111 and the gate line 12 are formed is substantially completely covered for the gate insulating layer 112.
  • the TFT 114 and the drain 115 are disposed in the same layer as the data line 13, and the source 114 is electrically connected to the corresponding data line 13, the drain 115 is connected to the corresponding pixel electrode 23, and the first passivation layer is formed on the thin film transistor 11. 14.
  • the first passivation layer 14 covers the source 114, the drain 115, the active layer 113, the data line 13, the gate line 12, and the gate insulating layer 112. It can also be understood that the first passivation layer 14 is substantially completely covered. a substrate substrate 1 having a thin film transistor 11, a gate line 12, and a data line 13, and a first passivation layer 14 on the substrate substrate 1 in FIG.
  • the projection substantially completely covers the base substrate 1; the reflective layer 15 is formed on the first passivation layer 14, and the reflective layer 15 may cover an area on the first passivation layer 14 corresponding to a region other than the thin film transistor 11 in the first region 24. And a region corresponding to at least a partial region of the thin film transistor 11, for example, the reflective layer 15 may cover a region on the first passivation layer 14 corresponding to a region other than the thin film transistor 11 in the first region 24, and the thin film transistor 11 a region corresponding to the drain 115; or, the reflective layer 15 may cover a region of the first passivation layer 14 corresponding to the first region 24, at this time, the reflective layer 15 covers the first passivation layer 14 and the first region A region corresponding to a region other than the thin film transistor 11 and a region corresponding to the thin film transistor 11.
  • the thin film transistor 11 is disposed between the reflective layer 15 and the base substrate 1, and the reflective layer 15 covers a region other than the thin film transistor 11 in the first region and at least a partial region of the thin film transistor 11, and thus can be incident by the reflective layer 15.
  • the light to the thin film transistor 11 is also reflected, so that the effective display region of the pixel region includes a region other than the thin film transistor 11 in the first region and at least a portion of the thin film transistor 11, and the effective display region of the pixel region in the related art includes only In the first region, the area of the effective display region of the pixel region is increased as compared with the region other than the thin film transistor, thereby increasing the aperture ratio of the display device.
  • the array substrate further includes a black matrix 17 disposed on a side of the thin film transistor 11 facing away from the base substrate 1.
  • the black matrix 17 can be disposed. Preventing light leakage in the area between two adjacent pixel regions, improving the contrast of the display device, and improving the picture display quality of the display device.
  • the black matrix 17 corresponds to the gate line 12 and the data line 13, respectively, defining a plurality of open regions 25, the open regions 25 defining the size of the pixel regions, and each of the open regions 25 corresponding to a first region 24.
  • the reflective layer 15 and the filter layer 18 are both disposed in the plurality of open regions 25, and the orthographic projections of the reflective layer 15 and the filter layer 18 on the base substrate are on the substrate substrate with the plurality of open regions 25
  • the orthographic projections are basically coincident.
  • the orthographic projection of each of the first regions 24 on the substrate substrate coincides with the orthographic projection of the corresponding opening region 25 on the substrate substrate, that is, referring to FIG. 2, the black matrix 17 corresponds to
  • the orthogonal projection of the portion of the gate line 12 on the base substrate 1 coincides with the orthographic projection of the gate line 12 on the base substrate 1, that is, the width of the portion of the black matrix 17 corresponding to the gate line 12 is equal to the width of the gate line 12
  • the orthographic projection of the portion of the black matrix 17 corresponding to the data line 13 on the base substrate 1 coincides with the orthographic projection of the data line 13 on the base substrate 1, that is, the portion of the black matrix 17 corresponding to the data line 13 on the base substrate 1
  • the upper width is equal to the width of the data line
  • the area of each of the open areas 25 is equal to the area of each of the first areas.
  • the effective display area of the pixel region includes a region other than the thin film transistor 11 in the first region and at least a portion of the thin film transistor 11, and the effective display region of the pixel region in the related art includes only the first region.
  • the area of the effective display area of the pixel area is increased as compared with the area other than the thin film transistor, thereby increasing the aperture ratio of the display device.
  • the orthographic projection of each first region 24 on the substrate substrate falls within the orthographic projection of the corresponding open region 25 on the substrate substrate. That is, referring to FIG. 3, the orthographic projection of the black matrix 17 corresponding to the portion of the gate line 12 on the substrate substrate 1 falls within the orthographic projection of the gate line 12 on the base substrate 1, that is, the black matrix 17 corresponds to the gate.
  • the width of the portion of the line 12 is smaller than the width of the gate line 12, and/or the orthographic projection of the portion of the black matrix 17 corresponding to the data line 13 on the substrate substrate 1 falls within the orthographic projection of the data line 13 on the substrate substrate 1.
  • the width of the portion of the black matrix 17 corresponding to the data line 13 on the base substrate 1 is smaller than the width of the data line, and at this time, the area of each of the opening regions 25 is larger than the area of each of the first regions 24.
  • the area of the reflective layer 15 and the filter layer 18 located in the opening region 25 is larger than the area of the first region, and the effective display region of the pixel region includes the area of the entire first region and at least a portion of the gate line and / Or the area of at least a portion of the data line further increases the area of the effective display area of the pixel area, thereby further increasing the aperture ratio of the display device.
  • the position of the black matrix 17 can be set according to the structure of the reflective layer 15.
  • a first passivation layer 14 is disposed between the thin film transistor 11 and the reflective layer 15, and the first passivation is performed.
  • the layer 14 completely covers the base substrate 1; the reflective layer 15 is located on the first passivation layer 14, and the reflective layer 15 covers only the region of the first region 24 other than the thin film transistor 11 and at least a portion of the thin film transistor 11, at this time
  • the black matrix 17 may be formed on the first passivation layer 14 together with the reflective layer 15, that is, the black matrix 17 and the reflective layer 15 are both disposed adjacent to each other on the first passivation layer 14 and are in direct contact with the first passivation layer 14. .
  • FIG. 4 is a schematic cross-sectional view of another array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural view of a reflective layer layout in a plan view of the array substrate of FIG. 4
  • FIG. 6 is a top view of the array substrate of FIG.
  • the structure of the reflective layer in the viewing angle is shown in FIG. 4-6.
  • the reflective layer 15 substantially completely covers the substrate 1 in comparison with the previous embodiment.
  • the array substrate provided in this embodiment includes a plurality of first regions 24 defined by a plurality of gate lines 12 and a plurality of data lines 13 respectively, and each of the first regions is provided with a thin film transistor 11 and each first The region 24 corresponds to a pixel electrode 23 and a common electrode 21, and the thin film transistor 11 is formed in the first region 24 on the base substrate 1.
  • the thin film transistor 11 includes a gate electrode 111, a gate insulating layer 112, an active layer 113, and a source.
  • the gate 114 and the drain 115, the gate 111 and the gate line 12 are disposed in the same layer, and the gate 111 is electrically connected to the corresponding gate line 12, and the gate insulating layer 112 covers the gate 111, the gate line 12 and the substrate substrate 1, It can also be understood that the gate insulating layer 112 substantially completely covers the substrate substrate 1 on which the gate electrode 111 and the gate line 12 are formed, and the orthographic projection of the gate insulating layer 112 on the substrate substrate 1 in FIG. 4 substantially completely covers the substrate. 1.
  • the source 114, the drain 115 and the data line 13 are disposed in the same layer, and the source 114 is electrically connected to the corresponding data line 13, the drain 115 is electrically connected to the corresponding pixel electrode 23, and the thin film transistor 11 is further formed.
  • a passivation layer 14, the first passivation layer 14 covers the source 114, the drain 115, the active layer 113, and the number According to the line 13 and the gate insulating layer 112, it can also be understood that the first passivation layer 14 substantially completely covers the base substrate 1 on which the thin film transistor 11, the gate line 12, and the data line 13 are formed, and the first passivation layer in FIG.
  • the orthographic projection on the base substrate 1 completely covers the base substrate 1; the reflective layer 15 is formed on the first passivation layer 14, and the reflective layer 15 completely covers the first passivation layer 14, and it can also be understood that the reflective layer 15 is basically Fully covering the substrate 1 , the orthographic projection of the reflective layer 15 on the substrate 1 in FIG. 4 substantially completely covers the substrate 1 , and the orthographic projection of the reflective layer 15 on the substrate 1 is adjacent to the first passivation layer 14 The orthographic projections on the base substrate 1 substantially coincide. At this time, referring to FIGS. 5 and 6, the reflective layer 15 simultaneously covers the pixel regions, the gate lines, and the data lines.
  • the reflective layer 15 substantially completely covers the base substrate 1, and thus the light incident on the thin film transistor 11 can also be reflected by the reflective layer 15 such that the effective display area of the pixel region includes all the regions in the first region 24, and related art
  • the effective display area of the pixel area includes only the area of the effective display area of the pixel area in the first area except for the thin film transistor, thereby increasing the aperture ratio of the display device; in addition, the reflective layer 15 substantially completely covers the base substrate. 1.
  • the use of light incident on the array substrate can be improved, and the picture display quality of the display device can be improved.
  • the array substrate further includes a black matrix 17 disposed on a side of the thin film transistor 11 facing away from the base substrate 1.
  • the black matrix 17 can be disposed. Preventing light leakage in the area between two adjacent pixel regions, improving the contrast of the display device, and improving the picture display quality of the display device.
  • the black matrix 17 corresponds to the gate line 12 and the data line 13, respectively, and defines a plurality of open areas 25, the open area 25 defines the size of the pixel area, each open area 25 corresponds to a first area 24, and the filter layer 18 is
  • the orthographic projection on the substrate substrate substantially coincides with the orthographic projection of the plurality of open regions 25 on the substrate.
  • the orthographic projection of each of the first regions 24 on the substrate substrate coincides with the orthographic projection of the corresponding opening region 25 on the substrate substrate, that is, referring to FIG. 5, the black matrix 17 corresponds to
  • the orthogonal projection of the portion of the gate line 12 on the base substrate 1 coincides with the orthographic projection of the gate line 12 on the base substrate 1, that is, the width of the portion of the black matrix 17 corresponding to the gate line 12 is equal to the width of the gate line 12, and
  • the orthographic projection of the portion of the black matrix 17 corresponding to the data line 13 on the base substrate 1 coincides with the orthographic projection of the data line 13 on the base substrate 1, that is, the portion of the black matrix 17 corresponding to the data line 13 on the base substrate 1
  • the upper width is equal to the width of the data line
  • the area of each of the open areas 25 is equal to the area of each of the first areas 24.
  • the effective display area of the pixel region includes a region other than the thin film transistor 11 in the first region 24 and at least a portion of the thin film transistor 11, and the effective display region of the pixel region in the related art includes only the first region.
  • the area of the effective display area of the pixel area is increased as compared with the area other than the thin film transistor, thereby increasing the aperture ratio of the display device.
  • the orthographic projection of each first region 24 on the substrate substrate falls within the orthographic projection of the corresponding open region 25 on the substrate substrate. That is, referring to FIG. 6, the orthographic projection of the black matrix 17 corresponding to the portion of the gate line 12 on the base substrate 1 falls within the orthographic projection of the gate line 12 on the base substrate 1, that is, the black matrix 17 corresponds to the gate.
  • the width of the portion of the line 12 is smaller than the width of the gate line 12, and/or the orthographic projection of the portion of the black matrix 17 corresponding to the data line 13 on the substrate substrate 1 falls within the orthographic projection of the data line 13 on the substrate substrate 1.
  • the width of the portion of the black matrix 17 corresponding to the data line 13 on the base substrate 1 is smaller than the width of the data line, and at this time, the area of each of the opening regions 25 is larger than the area of each of the first regions.
  • the area of the filter layer 18 located in the open area 25 is larger than the area of the first area
  • the effective display area of the pixel area includes the area of the entire first area and at least a portion of the gate line and/or the data line. At least a portion of the area further increases the area of the effective display area of the pixel area, thereby further increasing the aperture ratio of the display device.
  • the position of the black matrix 17 can be set according to the structure of the reflective layer 15.
  • a first passivation layer 14 is disposed between the thin film transistor 11 and the reflective layer 15, and the first passivation is performed.
  • the layer 14 substantially completely covers the base substrate 1; the reflective layer 15 is located on the first passivation layer 14, and the reflective layer 15 substantially completely covers the base substrate 1.
  • the reflective layer 15 is located on the first passivation layer 14 and Covering the entire first passivation layer 14, at this time, a second passivation layer 16 is formed on the reflective layer 15, and the second passivation layer 16 substantially completely covers the reflective layer 15, and it can also be understood that the second passivation layer 16 is completely
  • the base substrate 1 is covered, the black matrix 17 is located on the second passivation layer 16, the filter layer 18 is also located on the second passivation layer 16, and the black matrix 17 may be formed together with the filter layer 18 on the second passivation layer 16.
  • the black matrix 17 and the filter layer 18 are both disposed adjacent to each other on the second passivation layer 16 and are in direct contact with the second passivation layer 16.
  • the orthographic projection of the pixel electrode 23 and the common electrode 21 disposed in the pixel region on the substrate substrate 1 may not cover the orthographic projection of the thin film transistor 11 on the substrate substrate 1, or As shown in FIG. 1 or FIG. 4, the orthographic projection of at least one of the pixel electrode 23 and the common electrode 21 on the base substrate 1 may cover at least a part of the orthographic projection of the thin film transistor 11 on the base substrate 1, for example
  • the orthographic projection of the pixel electrode 23 and the common electrode 21 on the base substrate 1 completely covers the orthographic projection of the thin film transistor 11 on the base substrate 1, so that the coverage area of the electric field generated between the pixel electrode 23 and the common electrode 21 can be increased.
  • the area of the effective display area of the pixel area is increased, and the aperture ratio of the display device is increased to increase the utilization of light incident into the array substrate, thereby improving the picture display quality of the display device.
  • the plurality of common electrodes 21 corresponding to the plurality of first regions 24 may be connected to each other as an integral transparent electrode structure, and the positional relationship between the pixel electrode 24 and the common electrode 21 is not limited to those illustrated in FIGS. 1 and 4 . In the case shown, the positions of the two can be interchanged.
  • the material of the reflective layer 15 may be various.
  • the material of the reflective layer 15 may be an organic material having a reflective function, an inorganic material, a metal, or the like.
  • the material of the reflective layer 15 is selected.
  • the metal, that is, the reflective layer 15 is a metal reflective layer.
  • the material of the filter layer 18 may be a color resin.
  • the material of the filter layer 18 of the array substrate includes a red resin, a green resin, and a blue resin, and the red resin is deposited. In the pixel region where red is displayed, green resin is deposited in the pixel region for displaying green, and blue resin is deposited in the pixel region for displaying blue.
  • an embodiment of the present disclosure provides a display panel including the array substrate provided by the foregoing embodiments.
  • the display panel provided by the embodiment of the present disclosure includes the array substrate provided in the embodiment, and the opposite substrate parallel to and opposite to the substrate substrate 1 of the array substrate, wherein the array substrate can adopt the method shown in FIG.
  • the array substrate, that is, the reflective layer 15 covers only the region other than the thin film transistor 11 in the first region and at least a portion of the thin film transistor 11, or the array substrate may also adopt the array substrate shown in FIG. 4, that is, the reflective layer 15 is basically The base substrate 1 is completely covered.
  • the display panel provided in this embodiment has the same advantages as the related art in the array substrate provided in the foregoing embodiments, and details are not described herein again.
  • An embodiment of the present invention provides an array substrate, which is different from the array substrate in the foregoing embodiment, in which the common electrode 21 is not disposed on the array substrate, and the array substrate in this embodiment is, for example, TN (Twisted Nematic) mode or MVA ( Multi-domain Vertical Alignment) array substrate.
  • TN Transmission Nematic
  • MVA Multi-domain Vertical Alignment
  • the array substrate provided in this embodiment includes a first substrate 10 and a reflective layer 15 , a filter layer 18 , and a pixel electrode 23 disposed on the substrate 1 .
  • the reflective layer 15, the filter layer 18, and the pixel electrode 23 are sequentially disposed on the base substrate 10, and the common electrode 21 is disposed on the opposite substrate 2 disposed in parallel with the array substrate.
  • the display panel having the array substrate provided in this embodiment is operated, after applying a voltage to the pixel electrode 23 and the common electrode 21, the electric field generated between the pixel electrode 23 and the common electrode 21 does not pass through the filter layer 18, and thus the filter is filtered.
  • the layer 18 does not adversely affect the voltage difference generated between the pixel electrode 23 and the common electrode 21, so that the voltage difference required when driving the liquid crystal deflection can be reduced, thereby reducing the power consumption of the display panel.
  • the reflective layer 15 functions only to reflect light, and does not function as, for example, an electrode, and the function of the reflective layer 15 is single, so that the structure of the reflective layer 15 can be conveniently set. At the same time, it is also possible to prevent an adverse effect on the potential of the pixel electrode 23 or the common electrode 21 when the reflective layer 15 functions as an electrode.
  • the structure of the reflective layer 15 can be set according to actual needs.
  • the reflective layer 15 can adopt a structure similar to the reflective layer 15 of the array substrate shown in FIGS. 1-3.
  • the array substrate provided in this embodiment further includes a plurality of first regions 24 defined by a plurality of gate lines 12 and a plurality of data lines 13 respectively.
  • Each of the first regions 24 is provided with a thin film transistor 11 and each first region. 24 corresponds to a pixel electrode 23, and the thin film transistor 11 is located between the base substrate 10 and the reflective layer 15.
  • the gate 111 of the thin film transistor 11 is electrically connected to the corresponding gate line 12, and the source 114 of the thin film transistor 11 and corresponding data
  • the line 13 is electrically connected
  • the drain 115 of the thin film transistor 11 is electrically connected to the corresponding pixel electrode 23
  • the reflective layer 15 covers a region other than the thin film transistor 11 in the first region 24 and at least a portion of the thin film transistor 11, and at the same time, filtering
  • the layer 18 also covers a region other than the thin film transistor 11 in the first region and at least a portion of the thin film transistor 11, the front projection of the filter layer 18 on the substrate substrate 1 and the front projection of the reflective layer 15 on the base substrate 10. Shadows can basically coincide.
  • the array substrate further includes a black matrix 17 on a side of the thin film transistor 11 facing away from the substrate 1, the black matrix 17
  • the setting can prevent the light leakage phenomenon in the area between the adjacent two pixel areas, improve the contrast of the display device, and improve the picture display quality of the display device.
  • the black matrix 17 corresponds to the gate line 12 and the data line 13, respectively, defining a plurality of open regions 25, the open regions 25 defining the size of the pixel regions, and each of the open regions 25 corresponding to a first region 24.
  • the reflective layer 15 and the filter layer 18 are both disposed in the plurality of open regions 25, and the orthographic projections of the reflective layer 15 and the filter layer 18 on the base substrate 1 are combined with the plurality of open regions 25 on the substrate.
  • the orthographic projections on the top are basically coincident.
  • the orthographic projection of each of the first regions 24 on the substrate substrate coincides with the orthographic projection of the corresponding opening region 25 on the substrate substrate, at which time each of the opening regions 25 has an area and each first Area 24 is equal in area.
  • the effective display area of the pixel region includes a region other than the thin film transistor 11 in the first region and at least a portion of the thin film transistor 11, and the effective display region of the pixel region in the related art includes only the first region.
  • the area of the effective display area of the pixel area is increased as compared with the area other than the thin film transistor, thereby increasing the aperture ratio of the display device.
  • the orthographic projection of each first region 24 on the substrate substrate falls within the orthographic projection of the corresponding open region 25 on the substrate substrate.
  • the area of each of the opening regions 25 is larger than the area of each of the first regions 24.
  • the area of the reflective layer 15 and the filter layer 18 located in the first opening 25 is larger than the area of the first area
  • the effective display area of the pixel area includes the area of the entire first area and at least a portion of the gate line.
  • the area of at least a portion of the data line further increases the area of the effective display area of the pixel area, thereby further increasing the aperture ratio of the display device.
  • the position of the black matrix 17 can be set according to the structure of the reflective layer 15.
  • a first passivation layer 14 is disposed between the thin film transistor 11 and the reflective layer 15, and the first passivation is performed.
  • the layer 14 completely covers the base substrate 1; the reflective layer 15 is located on the first passivation layer 14, and the reflective layer 15 covers only the region of the first region except the thin film transistor 11 and at least a portion of the thin film transistor 11, at this time, black
  • black The matrix 17 may be formed on the first passivation layer 14 together with the reflective layer 15, that is, the black matrix 17 and the reflective layer 15 are both disposed adjacent to each other on the first passivation layer 14 and are in direct contact with the first passivation layer 14.
  • the reflective layer 15 may adopt the structure of the reflective layer 15 as shown in FIG. 4-6.
  • the display panel provided by the embodiment further includes a plurality of gate lines. 12 and a plurality of data lines 13 intersecting to define a plurality of first regions 24, each of which is provided with a thin film transistor 11, each of the first regions 24 corresponds to a pixel electrode 23, and the thin film transistor 11 is located on the base substrate
  • the gate 111 of the thin film transistor 11 is electrically connected to the corresponding gate line 12
  • the source 114 of the thin film transistor 11 is electrically connected to the corresponding data line 13
  • the drain 115 of the thin film transistor 11 corresponds to
  • the pixel electrode 23 is electrically connected
  • the reflective layer 15 substantially completely covers the base substrate 1.
  • the orthographic projection of the reflective layer 15 on the base substrate 1 in FIG. 8 completely covers the base substrate 10, that is, the reflective layer 15 completely covers the first region and the gate.
  • the line 12 and the data line 13, the filter layer 18 covers a region other than the thin film transistor 11 in the first region and at least a portion of the thin film transistor 11.
  • the array substrate further includes a black matrix 17 on a side of the thin film transistor 11 facing away from the base substrate 1, and a black matrix 17
  • the setting can prevent the light leakage phenomenon in the area between the adjacent two pixel areas, improve the contrast of the display device, and improve the picture display quality of the display device.
  • the black matrix 17 corresponds to the gate line 12 and the data line 13, respectively, and defines a plurality of open areas 25, the open area 25 defines the size of the pixel area, each open area 25 corresponds to a first area 24, and the filter layer 18 is
  • the orthographic projection on the substrate substrate substantially coincides with the orthographic projection of the plurality of open regions 25 on the substrate.
  • the orthographic projection of each of the first regions 24 on the substrate substrate coincides with the orthographic projection of the corresponding opening region 25 on the substrate substrate, at which time each of the opening regions 25 has an area and each first The area is equal.
  • the effective display area of the pixel region includes a region other than the thin film transistor 11 in the first region and at least a portion of the thin film transistor 11, and the effective display region of the pixel region in the related art includes only the thin film in the first region. Compared with the area other than the transistor, the area of the effective display area of the pixel area is increased, thereby increasing the aperture ratio of the display device.
  • the orthographic projection of each first region 24 on the substrate substrate falls within the orthographic projection of the corresponding open region 25 on the substrate substrate.
  • the area of each of the opening regions 25 is larger than the area of each of the first regions 24.
  • the area of the filter layer 18 located in the first opening 25 is larger than the area of the first area
  • the effective display area of the pixel area includes the area of the entire first area and at least a portion of the gate line and/or the data line. The area of at least a portion further increases the area of the effective display area of the pixel area, thereby further increasing the aperture ratio of the display device.
  • the position of the black matrix 17 can be set according to the structure of the reflective layer 15.
  • a first passivation layer 14 is disposed between the thin film transistor 11 and the reflective layer 15, and the first passivation is performed.
  • the layer 14 substantially completely covers the base substrate 1; the reflective layer 15 is located on the first passivation layer 14, and the reflective layer 15 substantially completely covers the base substrate 1.
  • the reflective layer 15 is located on the first passivation layer 14 and Covering the entire first passivation layer 14, at this time, a second passivation layer 16 is formed on the reflective layer 15, and the second passivation layer 16 substantially completely covers the reflective layer 15, and it can also be understood that the second passivation layer 16 is completely
  • the base substrate 1 is covered, the black matrix 17 is located on the second passivation layer 16, the filter layer 18 is also located on the second passivation layer 16, and the black matrix 17 may be formed together with the filter layer 18 on the second passivation layer 16.
  • the black matrix 17 and the filter layer 18 are both disposed adjacent to each other on the second passivation layer 16 and are in direct contact with the second passivation layer 16.
  • the material of the reflective layer 15 may be various.
  • the material of the reflective layer 15 may be an organic material having a reflective function, an inorganic material, a metal, or the like.
  • the material of the reflective layer 15 is selected.
  • the metal, that is, the reflective layer 15 is a metal reflective layer.
  • the material of the filter layer 18 may be a color resin.
  • the material of the filter layer 18 of the array substrate includes a red resin, a green resin, and a blue resin, and the red resin is deposited. In the pixel region where red is displayed, green resin is deposited in the pixel region for displaying green, and blue resin is deposited in the pixel region for displaying blue.
  • An embodiment of the present disclosure provides a display panel.
  • the display device includes the array substrate according to the foregoing embodiment, and the structure thereof is as shown in FIG. 7 or FIG. 8 , and the display panel further includes opposite sides parallel to the array substrate.
  • the substrate 2 and the common electrode 21 are disposed on a surface of the opposite substrate 2 facing the array substrate.
  • the display panel provided in this embodiment has the same advantages as the related art in the array substrate provided in the foregoing embodiments, and details are not described herein again.
  • the array substrate and the display panel provided in the above embodiments of the present disclosure can be applied to a reflective display device, for example, a flexible reflective display device or a rigid reflective display device.
  • a reflective display device for example, a flexible reflective display device or a rigid reflective display device.
  • the filter layer is disposed on the array substrate and is adjacent to the reflective layer, the flexible reflective display device When bent, the amount of deformation of the filter layer at the bend is substantially the same as the amount of deformation of the reflective layer, so that occurrence of light leakage between adjacent two pixel regions in the flexible reflective display device can be prevented.
  • An embodiment of the present disclosure provides a method for fabricating an array substrate for manufacturing the array substrate of the foregoing embodiment. As shown in FIG. 9, the method for manufacturing the array substrate includes:
  • Step S10 providing a substrate.
  • Step S20 forming a reflective layer on the base substrate.
  • Step S30 forming a filter layer on a side of the reflective layer away from the substrate.
  • Step S40 forming a pixel electrode on a side of the filter layer away from the reflective layer.
  • the pixel electrode is disposed on a side of the filter layer away from the reflective layer, and thus the display panel having the array substrate is respectively applied with a voltage signal to the pixel electrode and the common electrode.
  • the electric field generated between the pixel electrode and the common electrode does not pass through the filter layer, and thus the filter layer does not adversely affect the voltage difference generated between the pixel electrode and the common electrode, thereby reducing the deflection when driving the liquid crystal.
  • the required voltage difference which in turn reduces the power consumption of the display panel.
  • the method for manufacturing the array substrate further comprises: forming a thin film transistor on the substrate.
  • the reflective layer is disposed on a side of the thin film transistor away from the base substrate, and at least one of the reflective layer and the filter layer covers at least a portion of the thin film transistor.
  • the method for manufacturing the array substrate further includes:
  • Step S11 forming a plurality of gate lines and a gate of the thin film transistor on the base substrate, and a plurality of gate lines and a gate of the thin film transistor are simultaneously formed by the same patterning process.
  • Step S12 forming a gate insulating layer covering the substrate substrate on which the gate electrode and the gate line are formed.
  • Step S13 forming an active layer of the thin film transistor on the gate insulating layer.
  • Step S14 forming a plurality of data lines disposed across the plurality of gate lines and a source and a drain of the thin film transistor, wherein the plurality of data lines and the source and the drain of the thin film transistor are simultaneously formed by the same patterning process, the source and the drain The poles are in contact with the active layer, respectively.
  • Step S15 forming a first passivation layer covering the substrate substrate on which the gate insulating layer, the active layer, the source, the drain, and the data line are formed.
  • the method for manufacturing the array substrate further includes:
  • Step S16 forming a black matrix on the first passivation layer.
  • the black matrix defines a plurality of openings, and a subsequently formed reflective layer and a filter layer are formed in the plurality of open regions, and the orthographic projection of the reflective layer and the filter layer on the base substrate are combined with a plurality of openings
  • the orthographic projections of the regions on the substrate of the substrate substantially coincide.
  • step S20 the reflective layer substantially completely covers the substrate, after the reflective layer is formed in step 20, before step S30, before the filter layer is formed, as shown in FIG. 11, the array substrate is fabricated.
  • the method also includes:
  • Step S21 forming a second passivation layer, and the second passivation layer covers the reflective layer.
  • Step S22 forming a black matrix on the second passivation layer.
  • the black matrix defines a plurality of openings, and a subsequently formed filter layer is formed in the plurality of open regions, the orthographic projection of the filter layer on the base substrate and the plurality of open regions on the substrate
  • the orthographic projections are basically coincident.
  • the method for manufacturing the array substrate further includes:
  • Can include:
  • Step S31 forming a third passivation layer, the third passivation layer substantially completely covering the substrate substrate on which the filter layer is formed.
  • step S32 a via hole is formed at a position corresponding to the drain.
  • Step S33 forming a pixel electrode, and the pixel electrode is electrically connected to the drain through the via hole.
  • the method for manufacturing the array substrate further includes:
  • Step S311 forming a common electrode on the third passivation layer.
  • Step S312 forming a fourth passivation layer, the fourth passivation layer substantially completely covering the substrate substrate on which the common electrode is formed.
  • Another embodiment of the present invention further provides a method of manufacturing a display panel, including the method for fabricating the array substrate.
  • the manufacturing method of the display panel further includes:
  • the box array substrate and the opposite substrate are the same substrate.
  • the common electrode is disposed on the opposite substrate, and the method of manufacturing the display panel further includes forming a common electrode on the opposite substrate.

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Abstract

一种阵列基板及制造方法、显示面板及制造方法、显示装置，其中阵列基板包括：衬底基板，反射层，设置在所述衬底基板上；滤光层，设置在反射层远离衬底基板的一侧；以及像素电极，设置在所述滤光层远离所述反射层的一侧。

Description

阵列基板及制造方法、显示面板及制造方法、显示装置
相关申请的交叉引用
本申请要求2017年8月28日提交中国专利局的专利申请201710752621.9的优先权，其全部内容通过引用合并于本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及制造方法、显示面板及制造方法、显示装置。
背景技术
显示装置是一种用于显示文字、数字、符号、图片，或者由文字、数字、符号和图片中至少两种组合形成的图像等画面的装置，为人们的生活、工作提供较大的便利性。显示装置通常包括显示面板，通常的显示面板，例如液晶显示面板，一般包括阵列基板(Array基板)、彩色滤光基板(Color Filter基板，CF基板或彩膜基板)及位于阵列基板和彩色滤光基板之间的液晶层，利用彩色滤光基板上的滤光层对经液晶层后的光作用，实现显示装置的彩色化。然而，由于制造工艺、显示面板的类型等，显示面板在使用时，滤光层不能完全覆盖对应的像素区内除薄膜晶体管之外的区域(即像素区的有效显示区)，例如，对于柔性反射式显示面板来说，当弯折柔性反射式显示面板时，柔性反射式显示面板的弯折区内滤光层可能不能完全覆盖对应的像素区内除薄膜晶体管之外的区域，因而造成显示面板的漏光。
公开内容
根据本公开的一方面，提供一种阵列基板，包括：衬底基板，反射层，设置在所述衬底基板上；滤光层，设置在反射层远离衬底基板的一侧；以及像素电极，设置在所述滤光层远离所述反射层的一侧。
在一些实施例中，所述阵列基板还包括薄膜晶体管，所述薄膜晶体管位于所述衬底基板与所述反射层之间；所述反射层和滤光层中的至少一个覆盖所述薄膜晶体管的至少一部分。
在一些实施例中，所述阵列基板还包括：多条栅线，与薄膜晶体管的栅极同层设置；多条数据线，与所述多条栅线交叉设置，并且与薄膜晶体 管的源极和漏极同层设置；以及黑矩阵，设置在所述薄膜晶体管远离所述衬底基板的一侧，其中，所述交叉设置的多条数据线和多条栅极线限定多个第一区域，所述黑矩阵限定多个开口区域，每个所述第一区域在所述衬底基板上的正投影落入对应的开口区域在所述衬底基板上的正投影内。
在一些实施例中，所述阵列基板还包括：多条栅线，与薄膜晶体管的栅极同层设置；多条数据线，与所述多条栅线交叉设置，并且与薄膜晶体管的源极和漏极同层设置；以及黑矩阵，设置在所述薄膜晶体管远离所述衬底基板的一侧，其中，所述交叉设置的多条数据线和多条栅极线限定多个第一区域，所述黑矩阵限定多个开口区域，每个所述第一区域在所述衬底基板上的正投影与对应的开口区域在所述衬底基板上的正投影重合。
在一些实施例中，每个所述第一区域内设置有一个薄膜晶体管，所述反射层和滤光层中的至少一个在所述衬底基板上的正投影与多个开口区域在所衬底基板上的正投影基本重合。
在一些实施例中，所述反射层和滤光层均设置在多个开口区域内，所述反射层和滤光层在所述衬底基板上的正投影均与多个开口区域在所衬底基板上的正投影基本重合。
在一些实施例中，所述反射层在所述衬底基板上的正投影基本完全覆盖所述衬底基板，所述黑矩阵和所述滤光层设置在所述反射层远离衬底基板的一侧，滤光层设置在多个开口区域内，所述滤光层在所述衬底基板上的正投影与多个开口区域在所衬底基板上的正投影基本重合。
在一些实施例中，阵列基板还包括：公共电极，设置在所述滤光层远离所述反射层的一侧。
在一些实施例中，所述反射层为金属反射层。
根据本公开的另一方面，提供一种显示面板，包括：任一前述实施例所述的阵列基板，以及对置基板，与所述阵列基板平行相对设置，且设置在像素电极远离衬底基板的一侧，其中，对置基板面向阵列基板的面上设置有公共电极。
根据本公开的又一方面，一种显示面板，包括：如前述实施例所述的阵列基板，以及对置基板，与所述阵列基板平行相对设置，且设置在像素电极和公共电极远离衬底基板的一侧。
根据本公开的再一方面，提供一种显示装置，其中，所述显示装置包括如前述实施例所述的显示面板。
根据本公开的进一步的一方面，提供一种阵列基板的制造方法，包括：提供衬底基板；在衬底基板上形成反射层；在反射层远离衬底基板的一侧上形成滤光层；以及在所述滤光层远离所述反射层的一侧上形成像素电极。
在一些实施例中，在衬底基板上形成反射层之前，所述制造方法还包括：在衬底基板上形成薄膜晶体管；其中，所述反射层设置在所述薄膜晶体管远离所述衬底基板的一侧，所述反射层和滤光层中的至少一个覆盖所述薄膜晶体管的至少一部分。
在一些实施例中，所述的阵列基板的制造方法，还包括：在所述衬底基板上形成多条栅线；在所述衬底基板上形成与所述多条栅线交叉设置的多条数据线；以及在所述薄膜晶体管远离所述衬底基板的一侧形成黑矩阵，其中，所述交叉设置的多数据线和栅极线限定多个第一区域，所述黑矩阵限定多个开口区域，每个所述第一区域在所述衬底基板上的正投影落入对应的开口区域在所衬底基板上的正投影内，或者，所述每个第一区域在所述衬底基板上的正投影与对应的开口区域在所衬底基板上的正投影重合。
在一些实施例中，所述黑矩阵在形成反射层之前形成，所述反射层和滤光层形成在所述多个开口区域内，所述反射层和滤光层在所述衬底基板上的正投影均与多个开口区域在所衬底基板上的正投影基本重合。
在一些实施例中，所述黑矩阵在形成反射层之后及形成滤光层之前形成，所述反射层在所述衬底基板上的正投影基本完全覆盖所述衬底基板，所述黑矩阵和所述滤光层形成在所述反射层远离衬底基板的一侧，滤光层形成在多个开口区域内，所述滤光层在所述衬底基板上的正投影与多个开口区域在所衬底基板上的正投影基本重合。
在一些实施例中，所述的阵列基板的制造方法，还包括：在所述滤光层远离所述反射层的一侧形成公共电极。
根据本公开的另进一步的一方面，提供一种显示面板的制造方法，包括：如任一前述实施例所述的阵列基板的制造方法，提供对置基板，在对置基板上形成公共电极；以及对盒阵列基板和对置基板。
根据本公开的又进一步的一方面，提供一种显示面板的制造方法，包 括：如前述实施例所述的阵列基板的制造方法，提供对置基板，以及对盒阵列基板和对置基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开一实施例提供的一种阵列基板的截面结构示意图；
图2为图1中阵列基板的俯视视角中的反射层布局的结构示意图；
图3为图1中阵列基板的俯视视角中的反射层布局的结构示意图；
图4为本公开一实施例提供的另一种阵列基板的截面结构示意图；
图5为图4中阵列基板的俯视视角中的反射层布局的结构示意图；
图6为图4中阵列基板的俯视视角中的反射层布局的结构示意图；
图7为本公开一实施例提供的又一种显示面板的截面结构示意图；
图8为本公开一实施例提供的再一种显示面板的截面结构示意图；
图9-13为本公开一实施例提供的阵列基板的制造方法的流程图。
具体实施方式
为了进一步说明本公开实施例提供的阵列基板及制造方法、显示面板及制造方法、显示装置，下面结合说明书附图进行详细描述。
为了解决因滤光层不能完全覆盖对应的像素区内除薄膜晶体管之外的区域而造成显示面板的漏光，相关技术采用COA(Color Filter On Array，彩色滤光层集成在阵列基板上)技术，将滤光层集成在阵列基板上，使得显示面板弯折时滤光层依然可以完全覆盖对应的像素区内除薄膜晶体管之外的区域，进而防止显示面板漏光。然而，申请人发现，由于相关技术中显示面板的结构以及工作方式的限制，在分别向显示面板内像素电极和公共电极施加电压，利用像素电极与公共电极之间产生的电压差驱动液晶层中液晶偏转时，通常需要较大的电压差才能驱动液晶偏转，造成显示面板的功耗增加。
本公开一实施例提供一阵列基板，包括：衬底基板，反射层，滤光层和像素电极，反射层设置在所述衬底基板上，滤光层设置在反射层远离衬底基板的一侧，以及像素电极，设置在所述滤光层远离所述反射层的一侧。 采用本公开中的阵列基板的显示面板在工作时，像素电极与公共电极之间产生的电场不会穿过滤光层，因而滤光层不会对像素电极与公共电极之间产生的电压差造成不良影响，从而可以降低在驱动液晶偏转时所需要的电压差，进而降低显示面板的功耗。
图1为本公开一实施例提供的一种阵列基板的截面结构示意图，图2为图1中阵列基板的俯视视角中的反射层布局的结构示意图，图3为图1中阵列基板的俯视视角中的反射层布局的结构示意图；请参阅图1、图2和图3，本公开的一实施例提供一种阵列基板，包括衬底基板1、反射层15、滤光层18、像素电极23和公共电极21；其中，反射层15和滤光层18依次设置在衬底基板1上，即滤光层18位于反射层15远离衬底基板1的一侧，像素电极23和公共电极21均位于滤光层18远离反射层15的一侧。
举例来说，请继续参阅图1、图2及图3，本实施例提供的阵列基板应用于反射式显示装置的显示面板中，本实施例提供的阵列基板中，采用COA技术将滤光层18集成在阵列基板上，同时将公共电极21也集成在阵列基板上，本实施例中的阵列基板例如是FFS(Fringe Field Switching)模式的阵列基板。
具体地，本实施例提供的阵列基板包括衬底基板1、反射层15、滤光层18、像素电极23和公共电极21，反射层15和滤光层18依次设置在衬底基板1上，即滤光层18位于反射层15远离衬底基板1的一侧，像素电极23和公共电极21位于滤光层18的上方，即像素电极23和公共电极21均位于滤光层18远离反射层15的一侧，其中，像素电极23和公共电极21的设置方式可以根据实际需要进行设定，例如，请继续参阅图1，公共电极21可以位于滤光层18与像素电极23之间，此时，可以在滤光层18上形成第三钝化层19，然后在第三钝化层19上形成公共电极21，然后形成第四钝化层22，第四钝化层22覆盖第三钝化层19和公共电极21，然后在第四钝化层22上形成像素电极23。
本实施例提供的阵列基板中，将反射层15和滤光层18依次设置在衬底基板1上，像素电极23和公共电极21均设置在滤光层18远离反射层15的一侧，因而具有本实施例提供的阵列基板的显示面板工作时，分别向 像素电极23和公共电极21施加电压信号后，像素电极23与公共电极21之间产生的电场不会穿过滤光层18，因而滤光层18不会对像素电极23与公共电极21之间产生的电压差造成不良影响，从而可以降低在驱动液晶偏转时所需要的电压差，进而降低显示面板的功耗。
另外，在本实施例提供的阵列基板中，反射层15仅起到反射光的作用，而不起其它作用例如充当电极，反射层15的功能单一，从而可以方便对反射层15的结构进行设置，同时还可以防止因反射层15充当电极时反射层对像素电极23或公共电极21的电位造成不良影响。
在本实施例中，反射层15的结构可以为多种，例如，请继续参阅图1和图2，本实施例提供的阵列基板包括由多条栅线12和多条数据线13交叉限定出的多个第一区域24，每个第一区域24内设置有薄膜晶体管11、每个第一区域24对应于一像素电极23和一公共电极21，薄膜晶体管11的栅极111与对应的栅线12电连接，薄膜晶体管11的源极114与对应的数据线13电连接，薄膜晶体管11的漏极115与对应的像素电极23连接；薄膜晶体管11位于衬底基板1与反射层15之间，反射层15在衬底基板1上的正投影位于第一区域24在衬底基板1上的正投影之内，反射层15覆盖第一区域内除薄膜晶体管11以外的区域，反射层15还覆盖薄膜晶体管11的至少一部分，例如，反射层15可以覆盖第一区域24内除薄膜晶体管11以外的区域以及薄膜晶体管11的部分区域，此时，反射层15的覆盖面积小于对应第一区域的面积，或者，请参阅图1和图2，反射层15在衬底基板1上的正投影与第一区域24在衬底基板1上的正投影重合，反射层15可以覆盖整个第一区域，即反射层15同时覆盖第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11。
具体地，请参阅图1-3，薄膜晶体管11形成在衬底基板1上的第一区域24内，薄膜晶体管11包括栅极111、栅极绝缘层112、有源层113、源极114和漏极115，栅极111和栅线12同层设置，且栅极111与对应的栅线12电连接，栅极绝缘层112覆盖栅极111、栅线12和衬底基板1，也可以理解为栅极绝缘层112基本完全覆盖形成有栅极111和栅线12的衬底基板1，图1中栅极绝缘层112在衬底基板1上的正投影基本完全覆盖衬底基板1，源极114和漏极115与数据线13同层设置，且源极114与对 应的数据线13电连接，漏极115与对应的像素电极23连接，薄膜晶体管11上还形成有第一钝化层14，第一钝化层14覆盖源极114、漏极115、有源层113、数据线13、栅线12以及栅极绝缘层112，也可以理解为第一钝化层14基本完全覆盖形成有薄膜晶体管11、栅线12、数据线13的衬底基板1，图1中第一钝化层14在衬底基板1上的正投影基本完全覆盖衬底基板1；反射层15形成在第一钝化层14上，反射层15可以覆盖第一钝化层14上与第一区域24内除薄膜晶体管11以外的区域对应的区域、以及与薄膜晶体管11的至少部分区域对应的区域，例如，反射层15可以覆盖第一钝化层14上与第一区域24内除薄膜晶体管11以外的区域对应的区域、以及与薄膜晶体管11的漏极115对应的区域；或者，反射层15可以覆盖第一钝化层14上与第一区域24对应的区域，此时，反射层15覆盖第一钝化层14上与第一区域内除薄膜晶体管11以外的区域对应的区域、以及与薄膜晶体管11对应的区域。
将薄膜晶体管11设置在反射层15和衬底基板1之间，且反射层15覆盖第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，因而可以利用反射层15将入射至薄膜晶体管11处的光也反射，使得像素区的有效显示区包括第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，与相关技术中像素区的有效显示区仅包括第一区域内除薄膜晶体管以外的区域相比，增加了像素区的有效显示区的面积，从而提高显示装置的开口率。
在本公开的一实施例中，如图1-3所示，阵列基板中还包括有黑矩阵17，黑矩阵17位于薄膜晶体管11背向衬底基板1的一侧，黑矩阵17的设置可以防止相邻的两个像素区之间的区域出现漏光的现象，提高显示装置的对比度，改善显示装置的画面显示质量。黑矩阵17分别与栅线12和数据线13对应，限定多个开口区域25，开口区域25限定了像素区的尺寸，每个开口区域25对应一第一区域24。反射层15和滤光层18均设置在多个开口区域25内，且反射层15和滤光层18在所述衬底基板上的正投影均与多个开口区域25在所衬底基板上的正投影基本重合。
在一示例中，每个第一区域24在所述衬底基板上的正投影与对应的开口区域25在衬底基板上的正投影重合，也就是说，参见图2，黑矩阵 17对应于栅线12的部分在衬底基板1上的正投影与栅线12在衬底基板1上的正投影重合，即黑矩阵17对应于栅线12的部分的宽度等于栅线12的宽度，并且黑矩阵17对应于数据线13的部分在衬底基板1上的正投影与数据线13在衬底基板1上的正投影重合，即黑矩阵17对应于数据线13的部分在衬底基板1上的宽度等于数据线的宽度，此时每个开口区域25面积与每个第一区域面积相等。在这种情况下，像素区的有效显示区包括第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，与相关技术中像素区的有效显示区仅包括第一区域内除薄膜晶体管以外的区域相比，增加了像素区的有效显示区的面积，从而提高显示装置的开口率。
在本公开的另一示例中，每个第一区域24在所述衬底基板上的正投影落入对应的开口区域25在衬底基板上的正投影内。也就是说，参见图3，黑矩阵17对应于栅线12的部分在衬底基板1上的正投影落入栅线12在衬底基板1上的正投影内，即黑矩阵17对应于栅线12的部分的宽度小于栅线12的宽度，和/或黑矩阵17对应于数据线13的部分在衬底基板1上的正投影落入数据线13在衬底基板1上的正投影内，即黑矩阵17对应于数据线13的部分在衬底基板1上的宽度小于数据线的宽度，此时每个开口区域25面积大于每个第一区域24面积。在这种情形下，位于开口区域内25的反射层15和滤光层18的面积大于第一区域面积，像素区的有效显示区包括了整个第一区域的面积及栅线的至少一部分和/或数据线的至少一部分的面积，进一步增加了像素区的有效显示区的面积，从而进一步提高显示装置的开口率。
在本实施例中，黑矩阵17的位置可以根据反射层15的结构进行设置，例如，请参阅图1，薄膜晶体管11与反射层15之间设置有第一钝化层14，第一钝化层14完全覆盖衬底基板1；反射层15位于第一钝化层14上，且反射层15仅覆盖第一区域24内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，此时，黑矩阵17可以与反射层15一起形成在第一钝化层14上，即黑矩阵17和反射层15均位于第一钝化层14上邻接设置且均与第一钝化层14直接接触。
图4为本公开一实施例提供的另一种阵列基板的截面结构示意图，图 5为图4中阵列基板的俯视视角中的反射层布局的结构示意图，图6为图4中阵列基板的俯视视角中的反射层布局的结构示意图；请参阅图4-6，相较于前述实施例，在本公开一实施例提供的另一种阵列基板中，反射层15基本完全覆盖衬底基板1。具体地，本实施例提供的阵列基板包括由多条栅线12和多条数据线13交叉限定出的多个第一区域24，每个第一区域内设置有薄膜晶体管11、每个第一区域24对应于一像素电极23和一公共电极21，薄膜晶体管11形成在衬底基板1上第一区域24内，薄膜晶体管11包括栅极111、栅极绝缘层112、有源层113、源极114和漏极115，栅极111和栅线12同层设置，且栅极111与对应的栅线12电连接，栅极绝缘层112覆盖栅极111、栅线12和衬底基板1，也可以理解为栅极绝缘层112基本完全覆盖形成有栅极111和栅线12的衬底基板1，图4中栅极绝缘层112在衬底基板1上的正投影基本完全覆盖衬底基板1，源极114、漏极115和数据线13同层设置，且源极114与对应的数据线13电连接，漏极115与对应的像素电极23电连接；薄膜晶体管11上还形成有第一钝化层14，第一钝化层14覆盖源极114、漏极115、有源层113、数据线13以及栅极绝缘层112，也可以理解为第一钝化层14基本完全覆盖形成有薄膜晶体管11、栅线12、数据线13的衬底基板1，图4中第一钝化层14在衬底基板1上的正投影完全覆盖衬底基板1；反射层15形成在第一钝化层14上，反射层15完全覆盖第一钝化层14，也可以理解为反射层15基本完全覆盖衬底基板1，图4中反射层15在衬底基板1上的正投影基本完全覆盖衬底基板1，反射层15在衬底基板1上的正投影与第一钝化层14在衬底基板1上的正投影基本重合，此时，请参阅图5和6，反射层15同时覆盖像素区、栅线和数据线。
反射层15基本完全覆盖衬底基板1，因而可以利用反射层15将入射至薄膜晶体管11处的光也反射，使得像素区的有效显示区包括第一区域24内所有的区域，与相关技术中像素区的有效显示区仅包括第一区域内除薄膜晶体管以外的区域相比，增加像素区的有效显示区的面积，从而提高显示装置的开口率；另外，反射层15基本完全覆盖衬底基板1，可以提高对入射至阵列基板的光的利用，改善显示装置的画面显示质量。
在本公开的一实施例中，如图4-6所示，阵列基板中还包括有黑矩阵 17，黑矩阵17位于薄膜晶体管11背向衬底基板1的一侧，黑矩阵17的设置可以防止相邻的两个像素区之间的区域出现漏光的现象，提高显示装置的对比度，改善显示装置的画面显示质量。黑矩阵17分别与栅线12和数据线13对应，限定多个开口区域25，开口区域25限定了像素区的尺寸，每个开口区域25对应一第一区域24，滤光层18在所述衬底基板上的正投影与多个开口区域25在所衬底基板上的正投影基本重合。
在一示例中，每个第一区域24在所述衬底基板上的正投影与对应的开口区域25在衬底基板上的正投影重合，也就是说，参见图5，黑矩阵17对应于栅线12的部分在衬底基板1上的正投影与栅线12在衬底基板1上的正投影重合，即黑矩阵17对应于栅线12的部分的宽度等于栅线12的宽度，并且黑矩阵17对应于数据线13的部分在衬底基板1上的正投影与数据线13在衬底基板1上的正投影重合，即黑矩阵17对应于数据线13的部分在衬底基板1上的宽度等于数据线的宽度，此时每个开口区域25面积与每个第一区域24面积相等。在这种情况下，像素区的有效显示区包括第一区域24内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，与相关技术中像素区的有效显示区仅包括第一区域内除薄膜晶体管以外的区域相比，增加了像素区的有效显示区的面积，从而提高显示装置的开口率。
在本公开的另一示例中，每个第一区域24在所述衬底基板上的正投影落入对应的开口区域25在衬底基板上的正投影内。也就是说，参见图6，黑矩阵17对应于栅线12的部分在衬底基板1上的正投影落入栅线12在衬底基板1上的正投影内，即黑矩阵17对应于栅线12的部分的宽度小于栅线12的宽度，和/或黑矩阵17对应于数据线13的部分在衬底基板1上的正投影落入数据线13在衬底基板1上的正投影内，即黑矩阵17对应于数据线13的部分在衬底基板1上的宽度小于数据线的宽度，此时每个开口区域25面积大于每个第一区域面积。在这种情形下，位于开口区域25内的滤光层18的面积大于第一区域面积，像素区的有效显示区包括了整个第一区域的面积及栅线的至少一部分和/或数据线的至少一部分的面积，进一步增加了像素区的有效显示区的面积，从而进一步提高显示装置的开口率。
在本实施例中，黑矩阵17的位置可以根据反射层15的结构进行设置，例如，请参阅图4，薄膜晶体管11与反射层15之间设置有第一钝化层14，第一钝化层14基本完全覆盖衬底基板1；反射层15位于第一钝化层14上，且反射层15基本完全覆盖衬底基板1，也可以理解为反射层15位于第一钝化层14上且覆盖整个第一钝化层14，此时，则在反射层15上形成第二钝化层16，第二钝化层16基本完全覆盖反射层15，也可以理解为第二钝化层16完全覆盖衬底基板1，黑矩阵17位于第二钝化层16上，滤光层18也位于第二钝化层16上，黑矩阵17可以与滤光层18一起形成在第二钝化层16上，即黑矩阵17和滤光层18均位于第二钝化层16上邻接设置且均与第二钝化层16直接接触。
需要说明的是，在上述实施例中，设置在像素区中的像素电极23和公共电极21在衬底基板1上的正投影可以不覆盖薄膜晶体管11在衬底基板1上的正投影，或者，如图1或图4所示，像素电极23和公共电极21中的至少一个在衬底基板1上的正投影可以覆盖薄膜晶体管11在衬底基板1上的正投影中的至少一部分，例如像素电极23和公共电极21在衬底基板1上的正投影完全覆盖薄膜晶体管11在衬底基板1上的正投影，如此可以增加像素电极23与公共电极21之间产生的电场的覆盖面积，增加了像素区的有效显示区的面积，提高显示装置的开口率，以增加对入射至阵列基板内的光的利用，改善显示装置的画面显示质量。
需要注意的是，对应多个第一区域24的多个公共电极21可以相互连接作为一整体透明电极结构，像素电极24和公共电极21之间的位置关系并不限定与图1和图4所示的情形，两者位置可以互换。
需要注意的是，反射层15的材料可以为多种，例如，反射层15的材料可以为具有反光功能的有机材料、无机材料、金属等，在本公开实施例中，反射层15的材料选用金属，即反射层15为金属反射层。
需要注意的是，滤光层18的材料可以为彩色树脂，具体地，在一实施例中，阵列基板的滤光层18的材料包括红色树脂、绿色树脂和蓝色树脂，红色树脂沉积在用于显示红色的像素区内，绿色树脂沉积在用于显示绿色的像素区内，蓝色树脂沉积在用于显示蓝色的像素区内。
本公开一实施例提供一种显示面板，所述显示面板包括前述实施例提 供的阵列基板。具体地，本公开的实施例提供的显示面板包括如实施例提供的阵列基板、以及与阵列基板的衬底基板1平行且相对的对置基板，其中，阵列基板可以采用图1中所示的阵列基板，即反射层15仅覆盖第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，或者，阵列基板也可以采用图4中所示的阵列基板，即反射层15基本完全覆盖衬底基板1。
本实施例提供的显示面板与前述实施例提供的阵列基板相对于相关技术所具有的优势相同，在此不再赘述。
本发明一实施例提供一阵列基板，与前述实施例中的阵列基板不同的是，公共电极21不设置在阵列基板上，本实施例中的阵列基板例如是TN(Twisted Nematic)模式或MVA(Multi-domain Vertical Alignment)模式的阵列基板。
具体地，请参阅图7和图8，本实施例提供的阵列基板包括：第一衬底基板10以及依次设置在衬底基板1上的反射层15、滤光层18和像素电极23。
本实施例提供的阵列基板中，将反射层15、滤光层18和像素电极23依次设置在衬底基板10上，公共电极21设置与阵列基板平行对置设置的对置基板2上，因而具有本实施例提供的阵列基板的显示面板工作时，分别向像素电极23和公共电极21施加电压后，像素电极23与公共电极21之间产生的电场不会穿过滤光层18，因而滤光层18不会对像素电极23与公共电极21之间产生的电压差造成不良影响，从而可以降低在驱动液晶偏转时所需要的电压差，进而降低显示面板的功耗。
另外，在本实施例提供的阵列基板中，反射层15仅起到反射光的作用，而不起其它作用例如充当电极，反射层15的功能单一，从而可以方便对反射层15的结构进行设置；同时还可以防止因反射层15充当电极时对像素电极23或公共电极21的电位造成不良影响。
在本实施例中，反射层15的结构可以根据实际需要进行设置，例如，请参阅图7，反射层15可以采用类似如图1-3所示阵列基板的反射层15的结构，具体地，本实施例提供的阵列基板还包括由多条栅线12和多条数据线13交叉限定出的多个第一区域24，每个第一区域24内设置有薄膜 晶体管11、每个第一区域24对应于一像素电极23，薄膜晶体管11位于衬底基板10与反射层15之间，薄膜晶体管11的栅极111与对应的栅线12电连接，薄膜晶体管11的源极114与对应的数据线13电连接，薄膜晶体管11的漏极115与对应的像素电极23电连接，反射层15覆盖第一区域24内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，同时，滤光层18也覆盖第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，滤光层18在衬底基板1上的正投影与反射层15在衬底基板10上的正投影可以基本重合。
在本公开的一实施例中，参见图7，并参考图2和3，阵列基板中还包括有黑矩阵17，黑矩阵17位于薄膜晶体管11背向衬底基板1的一侧，黑矩阵17的设置可以防止相邻的两个像素区之间的区域出现漏光的现象，提高显示装置的对比度，改善显示装置的画面显示质量。黑矩阵17分别与栅线12和数据线13对应，限定多个开口区域25，开口区域25限定了像素区的尺寸，每个开口区域25对应一第一区域24。反射层15和滤光层18均设置在多个开口区域25内，且反射层15和滤光层18在所述衬底基板1上的正投影均与多个开口区域25在所衬底基板上的正投影基本重合。
在一示例中，每个第一区域24在所述衬底基板上的正投影与对应的开口区域25在衬底基板上的正投影重合，此时每个开口区域25面积与每个第一区域24面积相等。在这种情况下，像素区的有效显示区包括第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，与相关技术中像素区的有效显示区仅包括第一区域内除薄膜晶体管以外的区域相比，增加了像素区的有效显示区的面积，从而提高显示装置的开口率。
在本公开的另一示例中，每个第一区域24在所述衬底基板上的正投影落入对应的开口区域25在衬底基板上的正投影内。此时每个开口区域25面积大于每个第一区域24面积。在这种情形下，位于第一开口内25的反射层15和滤光层18的面积大于第一区域面积，像素区的有效显示区包括了整个第一区域的面积及栅线的至少一部分和/或数据线的至少一部分的面积，进一步增加了像素区的有效显示区的面积，从而进一步提高显示装置的开口率。
在本实施例中，黑矩阵17的位置可以根据反射层15的结构进行设置，例如，请参阅图7，薄膜晶体管11与反射层15之间设置有第一钝化层14，第一钝化层14完全覆盖衬底基板1；反射层15位于第一钝化层14上，且反射层15仅覆盖第一区域内除薄膜晶体管11的区域以及薄膜晶体管11的至少部分区域，此时，黑矩阵17可以与反射层15一起形成在第一钝化层14上，即黑矩阵17和反射层15均位于第一钝化层14上邻接设置且均与第一钝化层14直接接触。
根据本公开的另一实施例，请参阅图8，反射层15可以采用如图4-6所示的反射层15的结构，具体地，本实施例提供的显示面板还包括由多条栅线12和多条数据线13交叉限定出的多个第一区域24，每个第一区域内设置有薄膜晶体管11、每个第一区域24对应于一像素电极23，薄膜晶体管11位于衬底基板1与反射层15之间，薄膜晶体管11的栅极111与对应的栅线12电连接，薄膜晶体管11的源极114与对应的数据线13电连接，薄膜晶体管11的漏极115与对应的像素电极23电连接，反射层15基本完全覆盖衬底基板1，图8中反射层15在衬底基板1上的正投影完全覆盖衬底基板10，即反射层15完全覆盖第一区域、栅线12和数据线13，滤光层18覆盖第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域。
在本公开的一实施例中，参见图8，并参考图5和6，阵列基板中还包括有黑矩阵17，黑矩阵17位于薄膜晶体管11背向衬底基板1的一侧，黑矩阵17的设置可以防止相邻的两个像素区之间的区域出现漏光的现象，提高显示装置的对比度，改善显示装置的画面显示质量。黑矩阵17分别与栅线12和数据线13对应，限定多个开口区域25，开口区域25限定了像素区的尺寸，每个开口区域25对应一第一区域24，滤光层18在所述衬底基板上的正投影与多个开口区域25在所衬底基板上的正投影基本重合。
在一示例中，每个第一区域24在所述衬底基板上的正投影与对应的开口区域25在衬底基板上的正投影重合，此时每个开口区域25面积与每个第一区域面积相等。在这种情况下，像素区有效显示区包括第一区域内除薄膜晶体管11以外的区域以及薄膜晶体管11的至少部分区域，与相关技术中像素区的有效显示区仅包括第一区域内除薄膜晶体管以外的区域 相比，增加了像素区的有效显示区的面积，从而提高显示装置的开口率。
在本公开的另一示例中，每个第一区域24在所述衬底基板上的正投影落入对应的开口区域25在衬底基板上的正投影内。此时每个开口区域25面积大于每个第一区域24面积。在这种情形下，位于第一开口内25的滤光层18的面积大于第一区域面积，像素区的有效显示区包括了整个第一区域的面积及栅线的至少一部分和/或数据线的至少一部分的面积，进一步增加了像素区的有效显示区的面积，从而进一步提高显示装置的开口率。
在本实施例中，黑矩阵17的位置可以根据反射层15的结构进行设置，例如，请参阅图8，薄膜晶体管11与反射层15之间设置有第一钝化层14，第一钝化层14基本完全覆盖衬底基板1；反射层15位于第一钝化层14上，且反射层15基本完全覆盖衬底基板1，也可以理解为反射层15位于第一钝化层14上且覆盖整个第一钝化层14，此时，则在反射层15上形成第二钝化层16，第二钝化层16基本完全覆盖反射层15，也可以理解为第二钝化层16完全覆盖衬底基板1，黑矩阵17位于第二钝化层16上，滤光层18也位于第二钝化层16上，黑矩阵17可以与滤光层18一起形成在第二钝化层16上，即黑矩阵17和滤光层18均位于第二钝化层16上邻接设置且均与第二钝化层16直接接触。
需要注意的是，反射层15的材料可以为多种，例如，反射层15的材料可以为具有反光功能的有机材料、无机材料、金属等，在本公开实施例中，反射层15的材料选用金属，即反射层15为金属反射层。
需要注意的是，滤光层18的材料可以为彩色树脂，具体地，在一实施例中，阵列基板的滤光层18的材料包括红色树脂、绿色树脂和蓝色树脂，红色树脂沉积在用于显示红色的像素区内，绿色树脂沉积在用于显示绿色的像素区内，蓝色树脂沉积在用于显示蓝色的像素区内。
本公开一实施例提供一种显示面板，所述显示装置包括前述实施例所述的阵列基板，其结构如图7或图8所示，该显示面板还包括与阵列基板平行对置的对置基板2，公共电极21设置在对置基板2朝向阵列基板的面上。
本实施例提供的显示面板与前述实施例提供的阵列基板相对于相关 技术所具有的优势相同，在此不再赘述。
值得一提的是，本公开的上述实施例中提供的阵列基板、显示面板均可以应用于反射式显示装置，例如，柔性反射式显示装置或刚性反射式显示装置中。当本公开的实施例提供的阵列基板或显示面板均可以应用于柔性反射式显示装置时，由于滤光层设置在阵列基板上，且与反射层相邻叠置，因而当柔性反射式显示装置弯折时，弯折处滤光层的变形量与反射层的变形量基本相同，因而可以防止柔性反射式显示装置中相邻的两个像素区之间发生漏光现象的产生。
本公开一实施例提供一种阵列基板的制造方法，用于制造前述实施例中的阵列基板，如图9所示，所述阵列基板的制造方法包括：
步骤S10、提供衬底基板。
步骤S20、在衬底基板上形成反射层。
步骤S30、在反射层远离衬底基板的一侧上形成滤光层。
步骤S40、在所述滤光层远离所述反射层的一侧上形成像素电极。
采用本实施例的阵列基板制造方法制造的阵列基板中，像素电极设置在滤光层远离反射层的一侧，因而具有该阵列基板的显示面板工作时，分别向像素电极和公共电极施加电压信号后，像素电极与公共电极之间产生的电场不会穿过滤光层，因而滤光层不会对像素电极与公共电极之间产生的电压差造成不良影响，从而可以降低在驱动液晶偏转时所需要的电压差，进而降低显示面板的功耗。
在一实施例中，在步骤S10、提供衬底基板之后，步骤S20、形成反射层之前，所述阵列基板的制造方法还包括：在衬底基板上形成薄膜晶体管。所述反射层设置在所述薄膜晶体管远离所述衬底基板的一侧，所述反射层和滤光层中的至少一个覆盖所述薄膜晶体管的至少一部分。
在一实施例中，在步骤S10、提供衬底基板之后，步骤S20、形成反射层之前，如图10所示，所述阵列基板的制造方法还包括：
步骤S11、在衬底基板上形成多条栅线和薄膜晶体管的栅极、多条栅线与薄膜晶体管的栅极采用同一构图工艺同时形成。
步骤S12、形成栅极绝缘层，栅极绝缘层覆盖形成有栅极和栅线的衬底基板。
步骤S13、在栅极绝缘层形成薄膜晶体管的有源层。
步骤S14、形成与多条栅线交叉设置的多条数据线以及薄膜晶体管的源极、漏极，多条数据线与薄膜晶体管的源极和漏极采用同一构图工艺同时形成，源极和漏极分别与有源层接触。
步骤S15、形成第一钝化层，第一钝化层覆盖形成有栅极绝缘层、有源层、源极、漏极和数据线的衬底基板。
在一实施例中，在步骤20形成反射层之前，如图10所示，所述阵列基板的制造方法还包括：
步骤S16、在第一钝化层上形成黑矩阵。
黑矩阵限定多个的开口，后续形成的反射层和滤光层形成在所述多个开口区域内，所述反射层和滤光层在所述衬底基板上的正投影均与多个开口区域在所衬底基板上的正投影基本重合。
在另一实施例中，在步骤S20中，反射层基本完全覆盖衬底基板，在步骤20形成反射层之后，步骤S30、形成滤光层之前，如图11所示，所述阵列基板的制造方法还包括：
步骤S21、形成第二钝化层，第二钝化层覆盖反射层。
步骤S22、在第二钝化层上形成黑矩阵。
黑矩阵限定多个的开口，后续形成的滤光层形成在所述多个开口区域内，所述滤光层在所述衬底基板上的正投影与多个开口区域在所衬底基板上的正投影基本重合。
在一实施例中，在步骤S30、形成滤光层之后，步骤S40、形成像素电极之前，如图12所示，所述阵列基板的制造方法还包括：
可以包括：
步骤S31、形成第三钝化层，第三钝化层基本完全覆盖形成有滤光层的衬底基板。
步骤S32、在与漏极对应的位置形成过孔。
步骤S33、形成像素电极，像素电极通过过孔与漏极电连接。
在另一实施例中，在步骤S31、形成第三钝化层之后，步骤S32、形成过孔之前，如图13所示，所述阵列基板的制造方法还包括：
步骤S311、在第三钝化层上形成公共电极。
步骤S312、形成第四钝化层，第四钝化层基本完全覆盖形成有公共电极的衬底基板。
本发明另一实施例还提供一种显示面板的制造方法，其包括前述阵列基板的制造方法。显示面板的制造方法，还包括：
提供对置基板；
对盒阵列基板和对置基板。
在一些实施例中，公共电极设置在对置基板上，此时显示面板的制造方法，还包括在对置基板上形成公共电极。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，
    反射层，设置在所述衬底基板上；
    滤光层，设置在反射层远离衬底基板的一侧；以及
    像素电极，设置在所述滤光层远离所述反射层的一侧。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括薄膜晶体管，所述薄膜晶体管位于所述衬底基板与所述反射层之间；所述反射层和滤光层中的至少一个覆盖所述薄膜晶体管的至少一部分。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    多条栅线，与薄膜晶体管的栅极同层设置；
    多条数据线，与所述多条栅线交叉设置，并且与薄膜晶体管的源极和漏极同层设置；以及
    黑矩阵，设置在所述薄膜晶体管远离所述衬底基板的一侧，
    其中，
    所述交叉设置的多条数据线和多条栅极线限定多个第一区域，所述黑矩阵限定多个开口区域，每个所述第一区域在所述衬底基板上的正投影落入对应的开口区域在所述衬底基板上的正投影内。
  4. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    多条栅线，与薄膜晶体管的栅极同层设置；
    多条数据线，与所述多条栅线交叉设置，并且与薄膜晶体管的源极和漏极同层设置；以及
    黑矩阵，设置在所述薄膜晶体管远离所述衬底基板的一侧，
    其中，所述交叉设置的多条数据线和多条栅极线限定多个第一区域，所述黑矩阵限定多个开口区域，每个所述第一区域在所述衬底基板上的正投影与对应的开口区域在所述衬底基板上的正投影重合。
  5. 根据权利要求3或4所述的阵列基板，其中，每个所述第一区域内设置有一个薄膜晶体管，所述反射层和滤光层中的至少一个在所述衬底基板上的正投影与多个开口区域在所衬底基板上的正投影基本重合。
  6. 根据权利要求5所述的阵列基板，其中，所述反射层和滤光层均 设置在多个开口区域内，所述反射层和滤光层在所述衬底基板上的正投影均与多个开口区域在所衬底基板上的正投影基本重合。
  7. 根据权利要求5所述的阵列基板，其中，所述反射层在所述衬底基板上的正投影基本完全覆盖所述衬底基板，所述黑矩阵和所述滤光层设置在所述反射层远离衬底基板的一侧，滤光层设置在多个开口区域内，所述滤光层在所述衬底基板上的正投影与多个开口区域在所衬底基板上的正投影基本重合。
  8. 根据权利要求5所述的阵列基板，还包括：
    公共电极，设置在所述滤光层远离所述反射层的一侧。
  9. 根据权利要求1所述的阵列基板，其中，所述反射层为金属反射层。
  10. 一种显示面板，包括：
    如权利要求1-7或9中任一所述的阵列基板，以及
    对置基板，与所述阵列基板平行相对设置，且设置在像素电极远离衬底基板的一侧，
    其中，对置基板面向阵列基板的面上设置有公共电极。
  11. 一种显示面板，包括：
    如权利要求8所述的阵列基板，以及
    对置基板，与所述阵列基板平行相对设置，且设置在像素电极和公共电极远离衬底基板的一侧。
  12. 一种显示装置，其中，所述显示装置包括如权利要求10或11所述的显示面板。
  13. 一种阵列基板的制造方法，包括：
    提供衬底基板；
    在衬底基板上形成反射层；
    在反射层远离衬底基板的一侧上形成滤光层；以及
    在所述滤光层远离所述反射层的一侧上形成像素电极。
  14. 根据权利要求13所述的制造方法，其中，在衬底基板上形成反射层之前，所述制造方法还包括：
    在衬底基板上形成薄膜晶体管；
    其中，所述反射层设置在所述薄膜晶体管远离所述衬底基板的一侧，所述反射层和滤光层中的至少一个覆盖所述薄膜晶体管的至少一部分。
  15. 根据权利要求14所述的阵列基板的制造方法，还包括：
    在所述衬底基板上形成多条栅线；
    在所述衬底基板上形成与所述多条栅线交叉设置的多条数据线；以及
    在所述薄膜晶体管远离所述衬底基板的一侧形成黑矩阵，
    其中，所述交叉设置的多数据线和栅极线限定多个第一区域，所述黑矩阵限定多个开口区域，每个所述第一区域在所述衬底基板上的正投影落入对应的开口区域在所衬底基板上的正投影内，或者，所述每个第一区域在所述衬底基板上的正投影与对应的开口区域在所衬底基板上的正投影重合。
  16. 根据权利要求15所述的阵列基板的制造方法，其中，
    所述黑矩阵在形成反射层之前形成，所述反射层和滤光层形成在所述多个开口区域内，所述反射层和滤光层在所述衬底基板上的正投影均与多个开口区域在所衬底基板上的正投影基本重合。
  17. 根据权利要求15所述的阵列基板的制造方法，其中，
    所述黑矩阵在形成反射层之后及形成滤光层之前形成，所述反射层在所述衬底基板上的正投影基本完全覆盖所述衬底基板，所述黑矩阵和所述滤光层形成在所述反射层远离衬底基板的一侧，滤光层形成在多个开口区域内，所述滤光层在所述衬底基板上的正投影与多个开口区域在所衬底基板上的正投影基本重合。
  18. 根据权利要求13所述的阵列基板的制造方法，还包括：
    在所述滤光层远离所述反射层的一侧形成公共电极。
  19. 一种显示面板的制造方法，包括：
    如权利要求13-17中任一所述的阵列基板的制造方法，
    提供对置基板，在对置基板上形成公共电极；以及
    对盒阵列基板和对置基板。
  20. 一种显示面板的制造方法，包括：
    如权利要求18所述的阵列基板的制造方法，
    提供对置基板，以及
    对盒阵列基板和对置基板。
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