WO2017177735A1 - 阵列基板及其制备方法、传感器和探测设备 - Google Patents

阵列基板及其制备方法、传感器和探测设备 Download PDF

Info

Publication number
WO2017177735A1
WO2017177735A1 PCT/CN2017/070747 CN2017070747W WO2017177735A1 WO 2017177735 A1 WO2017177735 A1 WO 2017177735A1 CN 2017070747 W CN2017070747 W CN 2017070747W WO 2017177735 A1 WO2017177735 A1 WO 2017177735A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
layer
array substrate
substrate
thin film
Prior art date
Application number
PCT/CN2017/070747
Other languages
English (en)
French (fr)
Inventor
林家强
Original Assignee
京东方科技集团股份有限公司
Ka图像
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, Ka图像 filed Critical 京东方科技集团股份有限公司
Priority to JP2017538380A priority Critical patent/JP6924698B2/ja
Priority to KR1020177026551A priority patent/KR102002444B1/ko
Priority to US15/544,704 priority patent/US10224353B2/en
Priority to EP17737456.8A priority patent/EP3444842B1/en
Publication of WO2017177735A1 publication Critical patent/WO2017177735A1/zh
Priority to US16/249,251 priority patent/US10622388B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H01L31/022475—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of indium tin oxide [ITO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H01L31/022483—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of zinc oxide [ZnO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, a sensor, and a detection device.
  • Photoelectric sensors have the advantages of high precision, fast response, non-contact, measurable parameters and simple structure. They are widely used in detection and control. For example, photoelectric sensors can be applied to soot turbidity monitors, bar code scanning pens, product counters, photoelectric smoke alarms, rotational speed measuring instruments, laser weapons, and the like.
  • the photosensor includes an array substrate including a thin film transistor and a photodiode.
  • the photodiode receives light and converts the optical signal into an electrical signal through a photovoltaic effect, and controls the storage and reading of the electrical signal by turning off and turning on the thin film transistor, thereby implementing detection or control functions. Therefore, the performance of thin film transistors is very important in photoelectric sensors. Among them, signal interference and light leakage are the key factors affecting the performance of thin film transistors.
  • the photoelectric sensor In order to obtain a better signal-to-noise ratio, the photoelectric sensor usually adds a signal shielding metal layer to the thin film transistor, and then applies a stable voltage to the signal shielding metal layer to shield the sensing electrode from generating electric field on the source and the drain. Current, thereby reducing the effect on the performance of the thin film transistor.
  • sensors use more layers in the manufacturing process and more process steps, thereby increasing production costs.
  • At least one embodiment of the present invention provides an array substrate, a preparation method thereof, a sensor, and a detection device.
  • the array substrate can be used for sensors and detecting devices.
  • the first metal layer and the passivation layer can be patterned in the same patterning process, and the manufacturing process is combined to facilitate production, and the production cost is saved.
  • At least one embodiment of the present invention provides an array substrate comprising: a substrate; a thin film transistor disposed on the substrate, the thin film transistor including a source and an active layer; and a passivation layer disposed on the substrate a thin film transistor; a first metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a via structure extending through the insulating layer, the first metal layer, and a passivation layer; a detecting unit disposed on the insulating layer, the detecting unit includes a second metal layer; wherein the second metal layer is in direct contact with the source through the via structure.
  • the array substrate further includes: a groove penetrating the first metal layer and the passivation layer, and the groove is parallel to the substrate The direction of the substrate is between the via structure and the active layer, and the first metal layer is broken at the groove to form different portions spaced apart from each other.
  • a projection of the first metal layer on the substrate substrate and a projection of the thin film transistor on the substrate substrate at least partially coincide.
  • the detecting unit further includes a bias electrode spaced apart from the second metal layer, and the second metal layer and the bias electrode A semiconductor layer that is in contact with each other.
  • a transparent conductive layer is disposed on the second metal layer.
  • the thickness of the transparent conductive layer is greater than the thickness of the second metal layer.
  • the transparent conductive layer includes any one of ITO and IZO.
  • the material of the insulating layer is any one of an organic resin, silicon nitride, and silicon oxide.
  • the insulating layer has a thickness of 1-4 ⁇ m.
  • the material of the first metal layer and the second metal layer is any one or a combination of molybdenum, aluminum, and copper.
  • At least one embodiment of the present invention also provides a sensor comprising the array substrate of any of the embodiments of the present invention.
  • At least one embodiment of the present invention also provides a detecting apparatus comprising the sensor of any of the embodiments of the present invention.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, comprising: forming a thin film transistor on a substrate, the thin film transistor including a source and an active layer; and sequentially depositing a passivation layer on the thin film transistor a film and a first metal layer film; performing a first patterning process on the first metal layer film and the passivation layer film to form a first metal layer, a passivation layer, and located at the first a first connection hole and a groove in the metal layer and the passivation layer, the first connection hole exposing a portion of the source, the first metal layer being broken at the groove to form a space therebetween a different portion; forming an insulating layer film on the first metal layer, the passivation layer, the first connection hole, and the groove and performing a second patterning process to form an insulating layer pattern and a second connection hole
  • the first connection hole and the second connection hole communicate to form a via structure; a detecting unit is formed on the base substrate on which the via structure
  • the first metal layer film and the passivation layer film are etched by using a first etchant.
  • the first metal layer film and the first etchant and the third etchant are respectively used
  • the passivation layer film is etched.
  • the groove is located between the via structure and the active layer in a direction parallel to the substrate.
  • a projection of the first metal layer on the substrate substrate and a projection of the thin film transistor on the substrate substrate at least partially coincide.
  • the method further includes: forming a transparent conductive layer on the second metal layer.
  • the transparent conductive layer includes any one of ITO and IZO.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of an array substrate according to an example of the present invention.
  • FIG. 3 is a schematic cross-sectional view of an array substrate according to an example of the present invention.
  • FIG. 4 is a schematic cross-sectional view showing a via structure according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for preparing an array substrate according to an embodiment of the present invention.
  • 6a-6j are schematic cross-sectional views showing different stages of an array substrate in a manufacturing process according to an embodiment of the invention.
  • At least one embodiment of the present invention provides an array substrate comprising: a substrate; a thin film transistor disposed on the substrate, the thin film transistor including a source and an active layer; and a passivation layer disposed on the thin film transistor; a metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a via structure penetrating the insulating layer, the first metal layer and the passivation layer; and a detecting unit disposed on the insulating layer
  • the detecting unit includes a second metal layer; wherein the second metal layer is in direct contact with the source through the via structure.
  • the array substrate can be used for sensors and detection devices.
  • the first metal layer and the passivation layer can be patterned in the same patterning process.
  • the one-time patterning process can include photoresist coating and exposure. And development, and one or more etchings, removal of photoresist, and the like.
  • Embodiments in accordance with the present invention incorporate manufacturing processes that facilitate production while saving production costs.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention.
  • the array substrate 100 includes: a substrate substrate 101; a thin film transistor 102 disposed on the substrate substrate 101, the thin film transistor 102 includes a source 1025 and an active layer 1023; a passivation layer 104 is disposed on the thin film transistor 102; a first metal layer 105 disposed on the passivation layer 104; an insulating layer 106 disposed on the first metal layer 105; a via structure 107 extending through the insulating layer 106, the first metal layer 105, and the passivation
  • the layer 104 is disposed on the insulating layer 106.
  • the detecting unit 103 includes a second metal layer 1031. The second metal layer 1031 is in direct contact with the source 1025 through the via structure 107.
  • the array substrate further includes a groove 108 penetrating through the first metal layer 105 and the passivation layer 104, and the groove 108 is located in the via structure 107 in a direction parallel to the substrate 101.
  • the first metal layer 105 is broken at the grooves 108 to form different portions spaced apart from each other.
  • the recess 108 is formed over the source 1025, and after the first metal layer 105 is broken at the recess 108, a first portion located adjacent the via structure 107 and a second portion spaced from the first portion may be formed.
  • the recess 108 divides the first metal layer 105 into different portions spaced apart from each other, and there is no electrical connection between the first portion and the second portion of the first metal layer 105 that are spaced apart from each other.
  • the first portion of the first metal layer 105 can help the second metal layer 1031 and the source 1025 to conduct better at the via structure 107; the second portion of the first metal layer 105 can be applied with a regulated voltage to reduce the second
  • the electric field of the metal layer 1031 affects the thin film transistor 102 while shielding the thin film transistor 102 from light.
  • the thin film transistor 102 further includes a gate 1021, a gate insulating layer 1022 covering the gate 1021, and a drain 1024.
  • the second portion of the first metal layer 105 may be applied with a stable voltage to shield the second portion.
  • the electric field of the metal layer 1031 is at the drain 1024, the source 1025, and the drain 1024.
  • the induced current generated on the connected data lines reduces the influence of the electric field of the second metal layer 1031 on the thin film transistor 102.
  • the projection of the first metal layer 105 on the substrate 101 at least partially coincides with the projection of the thin film transistor 102 on the substrate 101, at least the first metal layer 105 on the substrate 101.
  • the projection covers the projection of the drain 1024 and the active layer 1023 on the substrate.
  • the ratio of the on-state current to the off-state current of the thin film transistor is required to be more than 10 7 or more. Since the illumination may seriously affect the switching characteristics of the thin film transistor, the active device of the TFT is shielded to meet the above-mentioned requirements.
  • the ratio of the off-state current so at least to be able to shield the active layer 1023, so that at least the projection of the first metal layer 105 on the substrate 101 covers the projection of the active layer 1023 on the substrate;
  • Layer 105 is to shield the induced current on drain 1024, so at least the projection of first metal layer 105 on substrate 101 covers the projection of drain 1024 on the substrate.
  • the detecting unit 103 further includes a bias electrode 1032 spaced apart from the second metal layer 1031 and a semiconductor layer 1033 that is in contact with both the second metal layer 1031 and the bias electrode 1032.
  • the spacing arrangement herein means that the second metal layer 1031 and the bias electrode 1032 are not in direct contact, and the second metal layer 1031 and the bias electrode 1032 may be juxtaposed in a direction parallel to the substrate 101.
  • the structure may also adopt a structure in which the second metal layer 1031 and the bias electrode 1032 are disposed in parallel in a direction perpendicular to the substrate 101, that is, the second metal layer 1031 and the bias electrode 1032 sandwich the semiconductor layer. Set between them.
  • the structure shown in FIG. 1 is a structure in which the second metal layer 1031 and the bias electrode 1032 are juxtaposed in a direction parallel to the base substrate 101.
  • an a-Si semiconductor layer may be disposed on the second metal layer 1031 and the bias electrode 1032 and in a space region therebetween, and the second metal layer 1031 and the bias voltage may be disposed.
  • An insulating film is disposed on the electrode 1032, which prevents the second metal layer 1031 and the bias electrode 1032 from being oxidized, and the presence of the insulating film can also make the electrons and holes separately distinct.
  • the bias electrode 1032 is completely covered by the a-Si semiconductor layer, and when the bias electrode 1032 receives the high voltage electrical signal, the bias electrode 1032 can apply a high voltage to the a-Si semiconductor layer, and when visible light is irradiated to the a- In the Si semiconductor layer, the a-Si semiconductor layer can convert the optical signal into an electrical signal, and is connected to the source 1025 of the thin film transistor 102 at the via structure 107 through the second metal layer 1031, and conducts an electrical signal to the thin film transistor 102. The output of the electrical signal is controlled by the thin film transistor 102.
  • the bias electrode 1032 The material may be metal or other conductive material without limiting the biasing property of the bias electrode 1032.
  • the material of the bias electrode 1032 may be a conductive metal such as molybdenum, aluminum or copper or an alloy formed by any combination thereof; the material of the bias electrode 1032 may also be ITO, AZO, IZO, conductive resin, graphene film. Conductive materials such as carbon nanotube films.
  • FIG. 2 is a schematic cross-sectional view of an array substrate according to an example of the present invention.
  • the structure shown in FIG. 2 is a structure in which the second metal layer 1031 and the bias electrode 1032 are disposed in parallel in a direction perpendicular to the base substrate 101, that is, the semiconductor layer 1033 is provided on the second metal layer 1031, and the semiconductor layer 1033 is provided.
  • the electrode 1032 is biased.
  • the bias electrode 1032 should be a transparent conductive material.
  • the bias electrode 1032 can be made of ITO, IZO, AZO, conductive resin, graphene film, carbon nanotube. A material such as a film is formed.
  • the thickness of the second metal layer 1031 is 0.03-0.06 ⁇ m, for example, 0.05 ⁇ m
  • the thickness of the bias electrode 1032 is 0.05-0.1 ⁇ m, for example, 0.08 ⁇ m.
  • a transparent conductive layer 1034 may also be disposed on the second metal layer 1031.
  • the transparent conductive layer 1034 has good flexibility and high conductivity, and can ensure normal conduction of electrical signals.
  • a high-thickness insulating layer 106 is applied to the thin film transistor, and the first metal layer 105 is disposed at the same time.
  • the sensing electrode that is, the thickness of the second metal layer 1031 is required to be thinner, and the thinner second metal layer 1031 can reduce the possible area of leakage and reduce leakage current.
  • the second metal layer 1031 When the second metal layer 1031 is in communication with the thin film transistor across the high-thickness insulating layer, since the physical structure of the high-thickness insulating layer and the thickness of the second metal layer 1031 are thin, the second metal layer 1031 is easily broken to cause conduction. A problem of difficulty, especially at the corner, is that the second metal layer 1031 is easily broken.
  • the transparent conductive layer 1034 is provided on the second metal layer 1031, the problem that the second metal layer 1031 is broken and the conduction cannot be prevented can be prevented.
  • a transparent conductive layer 1034 needs to be disposed on the peripheral electrode, so that the transparent conductive layer 1034 is not provided on the second metal layer 1031.
  • FIG. 3 is a schematic cross-sectional view of an array substrate according to an example of the present invention.
  • the thickness of the transparent conductive layer 1034 is greater than the thickness of the second metal layer 1031.
  • the transparent conductive layer 1034 has a thickness of 0.08 to 0.15 ⁇ m, for example, 0.1 ⁇ m.
  • the transparent conductive layer 1034 may include any one of ITO and IZO, and may be any of transparent conductive materials such as AZO, conductive resin, graphene film, and carbon nanotube film.
  • the insulating layer 106 may be an organic insulating layer such as an organic resin or the like; or may be an inorganic insulating layer such as silicon nitride, silicon oxide or the like.
  • the insulating layer 106 has a thickness of 1-4 [mu]m, for example 1.5 [mu]m.
  • the high-thickness insulating layer 106 shields the noise signal, and the high-thickness insulating layer 106 also serves to flatten.
  • the material of the first metal layer 105 and the second metal layer 1031 is any one or any alloy of metals such as molybdenum, aluminum, and copper.
  • FIG. 4 is a schematic cross-sectional view of a via structure according to an embodiment of the present invention, the via structure 107 including a first portion, a second portion, and a third portion.
  • the first portion, the second portion, and the third portion sequentially have a first size 201, a second size 202, and a third formed on the side of the passivation layer 104, the first metal layer 105, and the insulating layer 106 away from the substrate 101 Size 203.
  • the first size 201 is less than or equal to the second size 202
  • the second size 202 is less than or equal to the third size 203
  • a gap is formed between the passivation layer 104 and the first metal layer 105.
  • a step 204 is formed with a second step 205 between the first metal layer 105 and the insulating layer 106.
  • the first step 204 and the second step 205 make the via structure 107 smooth, thereby facilitating deposition of the second metal layer 1031 in FIG. 1 to FIG. 3, and the second metal layer 1031 is more difficult to break, reinforcing the second metal.
  • the conduction performance of layer 1031 is provided.
  • the embodiment provides a sensor which is a photoelectric sensor which is a sensor using a photoelectric element as a detecting element. It first converts the changes measured by the outside into changes in the optical signal, and then further converts the optical signal into an electrical signal by means of the optoelectronic component.
  • the receiver and the detecting circuit of the sensor integrally include any of the array substrates in the first embodiment.
  • the sensor may further include a scintillator layer or a phosphor layer disposed at an end of the detection unit that receives the radiation or light in the array substrate for converting the radiation into light, in the array substrate
  • the detection unit can sense The converted light produces a corresponding electrical signal.
  • the sensor provided by this embodiment can be used to detect different rays by selecting the type of scintillator layer or phosphor layer.
  • the embodiment provides a detecting device, including a detecting device and a control system, wherein the detecting device includes the sensor in the second embodiment.
  • the detection device can be used for ray measurement and detection, industrial automatic control, photometric measurement, etc. in the visible or near-infrared band; and mainly used for missile guidance, infrared thermal imaging, infrared remote sensing, etc. in the infrared band.
  • the embodiment provides a method for preparing an array substrate, comprising: forming a thin film transistor on a substrate, the thin film transistor including a source and an active layer; and sequentially depositing a passivation layer film and a first metal layer film on the thin film transistor Performing a first patterning process on the first metal layer film and the passivation layer film to form a first metal layer, a passivation layer, a first connection hole and a groove in the first metal layer and the passivation layer, the first connection The hole exposes a portion of the source, the first metal layer is broken at the groove to form different portions spaced apart from each other; an insulating layer film is formed on the first metal layer, the passivation layer, the first connection hole, and the groove a patterning process to form an insulating layer pattern and a second connection hole, wherein the first connection hole and the second connection hole communicate to form a via structure; and the detection unit is formed on the base substrate on which the via structure is formed, and the detection unit includes The second metal layer, the second metal
  • each patterning process may include substrate cleaning, photoresist coating, exposure, development, etching, photoresist removal (eg, stripping), and the like.
  • FIG. 5 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention, and describes a process of the method for fabricating the array substrate.
  • FIG. 6a-6j are schematic cross-sectional views showing different stages of an array substrate in a manufacturing process according to an embodiment of the invention.
  • a photoresist pattern corresponding to the gate electrode 1021, the gate line, or the like is formed on the metal layer film, and the metal layer film is patterned by using the photoresist pattern as an etching mask to form a gate on the base substrate 101.
  • the pole 1021, the gate line, and the like are schematic cross-sectional views showing different stages of an array substrate in a manufacturing process according to an embodiment of the invention.
  • the base substrate 101 is a transparent insulator, and the material for the base substrate 101 includes a glass substrate and a quartz substrate or other suitable materials; the gate metal film may use a metal such as Cr, W, Ti, Ta, Mo, Al, Cu, or the like. And alloys thereof, which may be formed by chemical vapor deposition (CVD) or sputtering.
  • CVD chemical vapor deposition
  • a capping gate 1021 is formed on a substrate substrate on which a gate electrode 1021, a gate line, or the like is formed.
  • the gate insulating layer 1022 of the gate line which is used as the material of the gate insulating layer 1022, includes SiNx and SiOx or other suitable materials.
  • the gate insulating layer 1022 has a thickness of 0.35 to 0.5 ⁇ m, for example, 0.4 ⁇ m.
  • an amorphous silicon layer at least partially overlapping the gate electrode 1021 in a direction perpendicular to the main surface of the base substrate 101 is formed on the base substrate on which the gate insulating layer 1022 is formed.
  • the formation process of the amorphous silicon layer comprises: depositing an amorphous silicon film by chemical vapor deposition, forming a photoresist film on the amorphous silicon film, and patterning the photoresist film by photolithography to be amorphous A photoresist pattern is formed on the silicon film, and the amorphous silicon film is patterned by using the photoresist pattern as an etch mask.
  • the active layer 1023 has a thickness of 0.03-0.06 ⁇ m, for example, 0.05 ⁇ m.
  • a source/drain metal layer film (not shown) is formed on the surface of the entire base substrate 101 on which the gate electrode 1021, the gate insulating layer 1022, and the active layer 1023 are formed, for example, by CVD or sputtering. Processing formed. Then, a photoresist is coated on the surface of the source and drain metal layer films, and a photoresist pattern is formed on the source and drain metal layer films by exposure, development, and the like, and the photoresist pattern is used as an etching mask source, The drain metal layer film is patterned to form a source 1025 and a drain 1024 on the insulating layer.
  • the material of the source and drain metal layers includes a single layer film of aluminum lanthanum (AlNd) alloy, tungsten molybdenum alloy (WMo), aluminum (Al), copper (Cu), molybdenum (Mo) or chromium (Cr), or these A composite film composed of any combination of metallic materials.
  • AlNd aluminum lanthanum
  • WMo tungsten molybdenum alloy
  • Al aluminum
  • Cu copper
  • Mo molybdenum
  • Cr chromium
  • a passivation layer film 104' and a first metal layer film 105' are sequentially deposited on the thin film transistor, and then coated on the surface of the first metal layer film 105'.
  • the photoresist is coated, and the photoresist is patterned to form a photoresist pattern on the first metal layer film 105', and the photoresist pattern is used as an etching mask for the first metal layer film 105' and the passivation layer.
  • the film 104' is patterned.
  • a first metal layer 105, a passivation layer 104, a first connection hole 1071, and a groove 108 are formed on the thin film transistor.
  • the material of the passivation layer film 104' includes an inorganic insulating film such as silicon nitride, silicon oxide, or the like, and has a thickness of 0.15 to 0.25 ⁇ m, for example, 0.2 ⁇ m.
  • the passivation layer film is deposited by a chemical vapor deposition method, and the material of the first metal layer film includes any one of molybdenum, aluminum, copper or an alloy formed thereof, for example, aluminum copper alloy, aluminum molybdenum alloy, copper molybdenum Alloy, molybdenum aluminum copper alloy.
  • the first etchant may be used for the first metal layer film 105' and the passivation layer.
  • the film 104' is etched.
  • the first etchant is, for example, a mixed corrosive ion, and is a mixed solution containing ammonium fluoride (NH 4 F), hydrofluoric acid (HF), or the like.
  • the first metal layer film 105' and the passivation layer film 104' are etched using a second etchant and a third etchant, respectively.
  • the first metal layer film 105' and the passivation layer film 104' are etched by the same mask, but after etching the first metal layer film with the second etchant, the etchant is replaced by the third moment.
  • the etchant further etches the passivation layer film 104'.
  • the second etchant comprises a solution of water, nitric acid, phosphoric acid and acetic acid, wherein the content of each acid has a certain range limitation, for example, the weight percentage of nitric acid is between 0.1% and 4%.
  • the weight percentage of phosphoric acid is between 50% and 78%, and the weight percentage of acetic acid is between 0.1% and 15%.
  • the weight percent of nitric acid is, for example, 1.5%
  • the weight percent of phosphoric acid is, for example, 70%
  • the weight percent of acetic acid is, for example, 10%
  • the remainder of the etchant is water
  • the water is, for example, deionized water.
  • the etchant may further include an azole compound as an inhibitor to stabilize the etching rate of the metal ion chelating agent.
  • the metal ion chelating agent is, for example, citric acid, oxalic acid, ethylenediaminetetraacetic acid or trans-cyclohexenediaminetetracarboxylic acid.
  • the third etchant includes an alkali solution such as KOH for wet etching, and may also include a gas such as SF 6 , O 2 for dry etching.
  • Step 204 the presence of the first step 204 makes the first connection hole 1071 gentle.
  • the first connection hole 1071 includes a first portion and a second portion. The first portion and the second portion sequentially have a first size 201 and a portion formed on the passivation layer 104 and the first metal layer 105 away from the substrate 101 side.
  • the second dimension 202 is less than or equal to the second dimension 202.
  • the first metal layer film and the passivation layer film are etched by the first patterning process to form a pattern including the first metal layer 105, the passivation layer 104, the first connection hole 1071 and the groove 108, thereby saving process steps and saving Cost of production.
  • an insulating layer film 106' is deposited on the base substrate 101 on which the first metal layer 105, the passivation layer 104, the first connection hole 1071 and the groove 108 are formed, and then in the insulating film 106'
  • the surface is coated with a photoresist, and the photoresist is patterned to form a photoresist pattern on the insulating film 106', and the insulating film is patterned by using the photoresist pattern as an etching mask to form the insulating layer 106.
  • a second connection hole 1072 wherein the first connection hole 1071 and the second connection hole 1072 communicate with each other to form a via structure.
  • the material of the insulating layer 106 is any one of an organic resin, silicon nitride, and silicon oxide.
  • the second connection hole 1072 includes a third portion having a third dimension 203 formed on the insulating layer 106 away from the side of the substrate 101.
  • the second dimension 202 is less than or equal to the third dimension 203
  • a second step 205 is formed between the first metal layer 105 and the insulating layer 106. The presence of the second step 205 makes the via structure 107 more gradual, thereby facilitating the deposition of the second metal layer, while the second metal layer is less susceptible to breakage, enhancing the conduction performance of the second metal layer.
  • a second metal layer film (not shown) is deposited on the base substrate 101 on which the via structure 107 and the insulating layer 106 are formed, and then a photoresist is coated on the surface of the second metal layer film, and The photoresist is patterned to form a photoresist pattern on the second metal layer film, and the second metal layer film is patterned using the photoresist pattern as an etch mask to form a pattern of the second metal layer 1031.
  • the second metal layer 1031 is in direct contact with the source 1025 at the via structure 107.
  • the biasing electrode 1032 of the light transmissive or opaque material is formed by the same patterning process, and will not be described herein.
  • the method of fabricating the array substrate may further include forming a transparent conductive layer (not shown) on the second metal layer.
  • the transparent conductive layer may be ITO, AZO, IZO, a transparent conductive resin, a graphene film, a carbon nanotube film, or the like.
  • an a-Si semiconductor layer 1033 is formed on the base substrate 101 on which the second metal layer 1031 and the bias electrode 1032 are formed.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, a sensor, and a detecting device.
  • At least one embodiment of the present invention provides an array substrate comprising: a substrate; a thin film transistor disposed on the substrate, the thin film transistor including a source and an active layer; and a passivation layer disposed on the thin film transistor; a metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a via structure penetrating the insulating layer, the first metal layer and the passivation layer; and a detecting unit disposed on the insulating layer, the detecting unit A second metal layer is included; wherein the second metal layer is in direct contact with the source through the via structure.
  • the array substrate and the sensor and the detecting device including the same have the following advantages: the array substrate can be used for a sensor and a detecting device, and the first metal layer and the passivation layer can be used in the same patterning process during the fabrication of the array substrate The composition is combined and the production process is combined to facilitate production while saving production costs.

Abstract

一种阵列基板及其制备方法、传感器和探测设备。该阵列基板包括：衬底基板(101)；薄膜晶体管(102)，设置于所述衬底基板(101)上，所述薄膜晶体管(102)包括源极(1025)和有源层(1023)；钝化层(104)，设置于所述薄膜晶体管(102)上；第一金属层(105)，设置于所述钝化层(104)上；绝缘层(106)，设置于所述第一金属层(105)上；过孔结构(107)，贯穿所述绝缘层(106)、所述第一金属层(105)和所述钝化层(104)；检测单元(103)，设置于所述绝缘层(106)上，所述检测单元(103)包括第二金属层(1031)；其中，所述第二金属层(1031)通过所述过孔结构(107)与所述源极(1025)直接接触。在制作该结构的阵列基板的过程中，可在同一构图工艺中对第一金属层和钝化层进行构图，合并了制作工序，便于生产，同时节省了生产成本。

Description

阵列基板及其制备方法、传感器和探测设备 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、传感器和探测设备。
背景技术
光电传感器具有精度高、反应快、非接触、可测参数多、结构简单等优点，其在检测和控制中应用非常广泛。例如，光电传感器可应用于烟尘浊度监测仪、条形码扫描笔、产品计数器、光电式烟雾报警器、转速测量仪、激光武器等方面。
光电传感器包括阵列基板，阵列基板包括薄膜晶体管和光电二极管。光电二极管接收光并通过光伏效应将光信号转化为电信号，通过关闭和导通薄膜晶体管分别控制电信号的存储和读取，从而实现检测或控制功能。因此，薄膜晶体管的性能在光电传感器中非常重要。其中，信号干扰和漏光是影响薄膜晶体管的性能的关键因素。
光电传感器为了获得更好的信噪比，通常在薄膜晶体管上增加信号屏蔽金属层，然后给信号屏蔽金属层施加一稳定电压，来屏蔽传感电极的电场在源极和漏极上产生的感应电流，从而减弱对薄膜晶体管性能的影响。但这类传感器在制作过程中使用的层数较多，工艺步骤多，从而增加了生产成本。
发明内容
本发明至少一实施例提供一种阵列基板及其制备方法、传感器和探测设备。该阵列基板可用于传感器和探测设备，在阵列基板的制作过程中，可在同一构图工艺中对第一金属层和钝化层进行构图，合并了制作工序，便于生产，同时节省了生产成本。
本发明至少一个实施例提供一种阵列基板，包括：衬底基板；薄膜晶体管，设置于所述衬底基板上，所述薄膜晶体管包括源极和有源层；钝化层，设置于所述薄膜晶体管上；第一金属层，设置于所述钝化层上；绝缘层，设置于所述第一金属层上；过孔结构，贯穿所述绝缘层、所述第一金属层和所 述钝化层；检测单元，设置于所述绝缘层上，所述检测单元包括第二金属层；其中，所述第二金属层通过所述过孔结构与所述源极直接接触。
例如，在本发明一实施例提供的阵列基板中，所述阵列基板还包括：贯穿所述第一金属层和所述钝化层的凹槽，且所述凹槽在平行于所述衬底基板的方向上位于所述过孔结构和所述有源层之间，所述第一金属层在所述凹槽处断开以形成彼此间隔的不同部分。
例如，在本发明一实施例提供的阵列基板中，所述第一金属层在所述衬底基板上的投影与所述薄膜晶体管在所述衬底基板上的投影至少部分重合。
例如，在本发明一实施例提供的阵列基板中，所述检测单元还包括与所述第二金属层间隔设置的偏压电极、以及与所述第二金属层和所述偏压电极均接触的半导体层。
例如，在本发明一实施例提供的阵列基板中，所述第二金属层上设置有透明导电层。
例如，在本发明一实施例提供的阵列基板中，所述透明导电层的厚度大于所述第二金属层的厚度。
例如，在本发明一实施例提供的阵列基板中，所述透明导电层包括ITO、IZO中的任意一种。
例如，在本发明一实施例提供的阵列基板中，所述绝缘层的材料为有机树脂、氮化硅和氧化硅中的任意一种。
例如，在本发明一实施例提供的阵列基板中，所述绝缘层的厚度为1-4μm。
例如，在本发明一实施例提供的阵列基板中，所述第一金属层、所述第二金属层的材料为钼、铝、铜中的任意一种或组合。
本发明至少一个实施例还提供一种传感器，包括本发明任一实施例所述的阵列基板。
本发明至少一个实施例还提供一种探测设备，包括本发明任一实施例所述的传感器。
本发明至少一个实施例还提供一种阵列基板的制备方法，包括：在衬底基板上形成薄膜晶体管，所述薄膜晶体管包括源极和有源层；在所述薄膜晶体管上依次沉积钝化层薄膜和第一金属层薄膜；对所述第一金属层薄膜和所述钝化层薄膜进行第一构图工艺以形成第一金属层、钝化层、位于所述第一 金属层和所述钝化层中的第一连接孔和凹槽，所述第一连接孔露出所述源极的一部分，所述第一金属层在所述凹槽处断开以形成彼此间隔的不同部分；在所述第一金属层、所述钝化层、所述第一连接孔和所述凹槽上形成绝缘层薄膜并进行第二构图工艺以形成绝缘层图案和第二连接孔，其中所述第一连接孔和所述第二连接孔连通以形成过孔结构；在形成有所述过孔结构的衬底基板上形成检测单元，所述检测单元包括第二金属层，所述第二金属层通过所述过孔结构与所述源极直接接触。
例如，在本发明一实施例提供的阵列基板的制备方法中，在所述第一构图工艺中，采用第一刻蚀剂对所述第一金属层薄膜和所述钝化层薄膜进行刻蚀。
例如，在本发明一实施例提供的阵列基板的制备方法中，在所述第一构图工艺中，采用第二刻蚀剂和第三刻蚀剂分别对所述第一金属层薄膜和所述钝化层薄膜进行刻蚀。
例如，在本发明一实施例提供的阵列基板的制备方法中，所述凹槽在平行于所述衬底基板的方向上位于所述过孔结构和所述有源层之间。
例如，在本发明一实施例提供的阵列基板的制备方法中，所述第一金属层在所述衬底基板上的投影与所述薄膜晶体管在所述衬底基板上的投影至少部分重合。
例如，在本发明一实施例提供的阵列基板的制备方法中，还包括：在所述第二金属层上形成透明导电层。
例如，在本发明一实施例提供的阵列基板的制备方法中，所述透明导电层包括ITO、IZO中的任意一种。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的一种阵列基板的截面示意图；
图2为本发明一示例提供的一种阵列基板的截面示意图；
图3为本发明一示例提供的一种阵列基板的截面示意图；
图4为本发明一实施例提供的过孔结构的截面示意图；
图5为本发明一实施例提供的一种阵列基板的制备方法的流程图；
图6a-6j为本发明一实施例提供的一种阵列基板在制作过程中的不同阶段的截面示意图。
附图标记：
100-阵列基板；101-衬底基板；102-薄膜晶体管；1021-栅极；1022-栅绝缘层；1023-有源层；1024-漏极；1025-源极；103-检测单元；1031-第二金属层；1032-偏压电极；1033-半导体层；1034-透明导电层；104-钝化层；104’-钝化层薄膜；105-第一金属层；105’-第一金属层薄膜；106-绝缘层；106’-绝缘层薄膜；107-过孔结构；1071-第一连接孔；1072-第二连接孔；108-凹槽；201-第一尺寸；202-第二尺寸；203-第三尺寸；204-第一台阶；205-第二台阶。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明至少一实施例提供一种阵列基板，包括：衬底基板；薄膜晶体管，设置于衬底基板上，薄膜晶体管包括源极和有源层；钝化层，设置于薄膜晶体管上；第一金属层，设置于钝化层上；绝缘层，设置于第一金属层上；过孔结构，贯穿绝缘层、第一金属层和钝化层；检测单元，设置于绝缘层上， 该检测单元包括第二金属层；其中，第二金属层通过过孔结构与源极直接接触。
该阵列基板可用于传感器和探测设备，在阵列基板的制作过程中，可在同一构图工艺中对第一金属层和钝化层进行构图，例如，一次构图工艺可以包括光刻胶涂覆、曝光和显影、以及一次或多次刻蚀、光刻胶的去除等步骤。根据本发明的实施例合并了制作工序，便于生产，同时节省了生产成本。
下面通过几个实施例进行说明。
实施例一
本实施例提供一种阵列基板。图1为本发明一实施例提供的一种阵列基板的截面示意图。该阵列基板100包括：衬底基板101；薄膜晶体管102，设置于衬底基板101上，该薄膜晶体管102包括源极1025和有源层1023；钝化层104，设置于该薄膜晶体管102上；第一金属层105，设置于该钝化层104上；绝缘层106，设置于该第一金属层105上；过孔结构107，贯穿该绝缘层106、该第一金属层105和该钝化层104；检测单元103，设置于绝缘层106上，该检测单元103包括第二金属层1031；其中，第二金属层1031通过过孔结构107与源极1025直接接触。
例如，如图1所示，该阵列基板还包括：贯穿第一金属层105和钝化层104的凹槽108，且该凹槽108在平行于衬底基板101的方向上位于过孔结构107和有源层1023之间，第一金属层105在凹槽108处断开以形成彼此间隔的不同部分。该凹槽108形成在源极1025的上方，第一金属层105在凹槽108处断开后，可以形成位于过孔结构107附近的第一部分和与第一部分间隔的第二部分。也就是说，凹槽108将第一金属层105分割为彼此间隔的不同部分，第一金属层105彼此间隔的第一部分和第二部分之间没有电性连接。第一金属层105的第一部分可以帮助第二金属层1031和源极1025在过孔结构107处更好地导通；第一金属层105的第二部分可以被施加一稳定电压来减少第二金属层1031的电场对薄膜晶体管102产生的影响，同时可以为薄膜晶体管102遮光。
例如，如图1所示，薄膜晶体管102还包括栅极1021、覆盖栅极1021的栅绝缘层1022、漏极1024，第一金属层105的第二部分可以被施加一稳定电压来屏蔽第二金属层1031的电场在漏极1024、源极1025和与漏极1024 连接的数据线上产生的感应电流，从而来减少第二金属层1031的电场对薄膜晶体管102产生的影响。
例如，如图1所示，第一金属层105在衬底基板101上的投影与薄膜晶体管102在衬底基板101上的投影至少部分重合，至少第一金属层105在衬底基板101上的投影覆盖漏极1024和有源层1023在衬底基板上的投影。一般要求薄膜晶体管的开态电流与关态电流之比要达到107以上，由于光照会严重影响薄膜晶体管的开关特性，对TFT的有源器件进行遮光才能满足上述要求中薄膜晶体管的开态电流与关态电流之比，所以至少要能为有源层1023遮光，所以至少第一金属层105在衬底基板101上的投影覆盖有源层1023在衬底基板上的投影；同时第一金属层105要屏蔽漏极1024上的感应电流，所以至少第一金属层105在衬底基板101上的投影覆盖漏极1024在衬底基板上的投影。
检测单元103还包括与第二金属层1031间隔设置的偏压电极1032、以及与第二金属层1031和偏压电极1032均接触的半导体层1033。此处的间隔设置是指第二金属层1031和偏压电极1032没有直接的接触，既可以采用第二金属层1031和偏压电极1032在平行于衬底基板101的方向上并列设置的结构，也可以采用第二金属层1031和偏压电极1032在垂直于衬底基板101的方向上平行设置的结构，也就是说，第二金属层1031和偏压电极1032将半导体层夹设在它们之间。
例如，图1所示的结构是采用第二金属层1031和偏压电极1032在平行于衬底基板101的方向上并列设置的结构。在此并列设置的结构中，在第二金属层1031和偏压电极1032之上和它们之间的间隔区域内均可以设置a-Si半导体层，也可以在第二金属层1031和偏压电极1032上设置绝缘膜，该绝缘膜可以防止第二金属层1031和偏压电极1032被氧化，同时该绝缘膜的存在也可以使电子和空穴分开地更明显。偏压电极1032被a-Si半导体层完全覆盖，当偏压电极1032接受高压电信号时，该偏压电极1032可以对a-Si半导体层施加高电压，当有可见光照射到a-Si半导体层时，a-Si半导体层可以将光信号转化为电信号，通过第二金属层1031在过孔结构107处与薄膜晶体管102的源极1025连接，而将电信号传导至薄膜晶体管102中，并由薄膜晶体管102来控制电信号的输出。在这种并列设置的结构中，偏压电极1032 的材料可以是金属，也可以是其他的导电材料，而不限制偏压电极1032具有透光性能。例如，偏压电极1032的材料可以为钼、铝、铜等导电金属或由它们任意组合形成的合金；偏压电极1032的材料也可以为ITO、AZO、IZO、导电树脂、石墨烯薄膜、碳纳米管薄膜等导电材料。
例如，图2为本发明一示例提供的一种阵列基板的截面示意图。图2所示的结构是在垂直于衬底基板101的方向上第二金属层1031和偏压电极1032平行设置的结构，即第二金属层1031上设置半导体层1033，半导体层1033上设置偏压电极1032。此时，为了保证半导体层1033能够接受光照，该偏压电极1032应该为透明的导电材料，例如，偏压电极1032可以由ITO、IZO、AZO、导电树脂、石墨烯薄膜、碳纳米管薄膜等材料形成。
例如，在图1和图2所示的结构中，第二金属层1031的厚度为0.03-0.06μm，例如0.05μm，偏压电极1032的厚度为0.05-0.1μm，例如0.08μm。
例如，如图3所示，还可以在第二金属层1031上设置透明导电层1034。透明导电层1034的柔韧性好、导电性高，可以保证电信号正常的导通。在电信号传输时，由于给偏压电极1032施加的高压电会对薄膜晶体管的电信号造成干扰，所以在薄膜晶体管上加上高厚度的绝缘层106，同时设置第一金属层105，来对薄膜晶体管上的杂信号进行屏蔽。检测单元为了获得较低的杂讯，传感电极即第二金属层1031的厚度要求较薄，较薄的第二金属层1031可以减少漏电的可能面积，减少漏电流。当第二金属层1031跨越高厚度的绝缘层与薄膜晶体管连通时，由于高厚度绝缘层的物理结构以及第二金属层1031的厚度较薄，容易使第二金属层1031发生断裂而造成导通不良的问题，特别是在拐角处第二金属层1031容易断裂。当在第二金属层1031上设置透明导电层1034后，可防止第二金属层1031断裂而导致的无法导通的问题。
同时，在整个工艺过程中，在周边区为保证电极不被氧化，也需要在周边电极上设置一层透明导电层1034，所以在第二金属层1031上设置透明导电层1034并没有多出额外的工序。
例如，图3为本发明一示例提供的一种阵列基板的截面示意图。如图3所示，该透明导电层1034的厚度大于第二金属层1031的厚度。例如该透明导电层1034的厚度为0.08-0.15μm，例如0.1μm。为防止第二金属层1031断裂而导致的无法导通的问题，透明导电层1034沿着第二金属层1031的图 案设计。为了避免产生漏电杂讯，透明导电层1034与半导体层1033不直接连接。
例如，如图3所示，该透明导电层1034可包括ITO、IZO中的任意一种，也可以为AZO、导电树脂、石墨烯薄膜、碳纳米管薄膜等透明导电材料中的任意一种。
例如，如图1至图3所示，绝缘层106可以是有机绝缘层，如有机树脂等；也可以是无机绝缘层，如氮化硅、氧化硅等。
例如，如图1至图3所示，绝缘层106的厚度为1-4μm，例如1.5μm。高厚度的绝缘层106对杂讯号做了屏蔽，同时高厚度的绝缘层106也起到了平坦化的作用。
例如，如图1至图3所示，第一金属层105、第二金属层1031的材料为钼、铝、铜等金属中的任意一种或任意合金。
例如，为了更清楚地说明过孔结构107的特点，图4给出了本发明一实施例提供的过孔结构的截面示意图，该过孔结构107包括第一部分、第二部分和第三部分，第一部分、第二部分和第三部分依次具有形成在钝化层104、第一金属层105和绝缘层106上的远离衬底基板101一侧的第一尺寸201、第二尺寸202和第三尺寸203。
例如，如图4所示，该第一尺寸201小于或等于第二尺寸202，第二尺寸202小于或等于第三尺寸203，且在钝化层104和第一金属层105之间形成有第一台阶204，在第一金属层105和绝缘层106之间形成有第二台阶205。第一台阶204、第二台阶205使过孔结构107变得平缓，从而更利于图1至图3中第二金属层1031的沉积，第二金属电层1031更不易断裂，增强了第二金属层1031的导通性能。
实施例二
本实施例提供一种传感器，该传感器是一种光电传感器，它是采用光电元件作为检测元件的传感器。它首先把外界被测量的变化转换成光信号的变化，然后借助光电元件进一步将光信号转换成电信号。传感器的接收器和检测电路一体包括实施例一中的任一阵列基板。例如，传感器还可以包括闪烁体层或荧光体层，该闪烁体层或荧光体层设置于阵列基板中检测单元的接受射线或光的端部，用于将射线转化为光，阵列基板中的检测单元可以感测到 该转化的光并且产生相应的电信号。通过选择闪烁体层或荧光体层的类型可以使本实施例提供的传感器用于探测不同的射线。
实施例三
本实施例提供一种探测设备，包括探测装置和控制系统，其中，探测装置包括实施例二中的传感器。例如，该探测设备可在可见光或近红外波段用于射线测量和探测、工业自动控制、光度计量等；在红外波段主要用于导弹制导、红外热成像、红外遥感等方面。
实施例四
本实施例提供一种阵列基板的制备方法，包括：在衬底基板上形成薄膜晶体管，该薄膜晶体管包括源极和有源层；在薄膜晶体管上依次沉积钝化层薄膜和第一金属层薄膜；对第一金属层薄膜和钝化层薄膜进行第一构图工艺以形成第一金属层、钝化层、位于第一金属层和钝化层中的第一连接孔和凹槽，第一连接孔露出源极的一部分，第一金属层在凹槽处断开以形成彼此间隔的不同部分；在第一金属层、钝化层、第一连接孔和凹槽上形成绝缘层薄膜并进行第二构图工艺以形成绝缘层图案和第二连接孔，其中第一连接孔和第二连接孔连通以形成过孔结构；在形成有过孔结构的衬底基板上形成检测单元，检测单元包括第二金属层，第二金属层通过过孔结构与源极直接接触。
例如，每一次构图工艺可以包括基板清洗、光刻胶涂覆、曝光、显影、刻蚀、光刻胶去除(例如，剥离)等。图5为本发明一实施例提供的阵列基板的制备方法的流程图，描述了上述阵列基板制备方法的过程。
图6a～6j为本发明一实施例提供的一种阵列基板在制作过程中的不同阶段的截面示意图。参见图6a，提供一种衬底基板101，在衬底基板101上形成一层金属层薄膜(未示出)，在金属层薄膜的整个表面涂覆光刻胶(未示出)，通过曝光、显影等工序以在金属层薄膜上形成与栅极1021、栅线等对应的光刻胶图案，利用光刻胶图案作为蚀刻掩膜对金属层薄膜构图，以在衬底基板101上形成栅极1021、栅线等。该衬底基板101是透明绝缘体，用于衬底基板101的材料包括玻璃基板和石英基板或其他适合的材料；栅极金属薄膜可以使用Cr、W、Ti、Ta、Mo、Al、Cu等金属及其合金，该金属层可以通过化学气相沉积(CVD)或溅射处理形成。
参见图6b，在形成有栅极1021、栅线等的衬底基板上形成覆盖栅极1021、 栅线的栅绝缘层1022，被用作栅绝缘层1022的材料包括SiNx和SiOx或其他适合的材料。该栅绝缘层1022的厚度为0.35-0.5μm，例如0.4μm。
参见图6c，在形成有栅绝缘层1022的衬底基板上形成与栅极1021在垂直于衬底基板101的主表面的方向上至少部分重叠的非晶硅层。该非晶硅层的形成过程包括：采用化学气相沉积的方法沉积非晶硅薄膜，再在非晶硅薄膜上形成光刻胶膜，通过光刻处理对光刻胶膜构图，以在非晶硅薄膜上形成光刻胶图案，利用光刻胶图案作为蚀刻掩膜对非晶硅薄膜进行构图形有源层1023，该有源层1023的厚度为0.03-0.06μm，例如0.05μm。
参见图6d，在形成有栅极1021、栅绝缘层1022和有源层1023的整个衬底基板101的表面上形成源、漏金属层薄膜(未示出)，例如，可以通过CVD或溅射处理形成。然后在源、漏金属层薄膜的表面涂覆光刻胶，通过曝光、显影等工序以在源、漏金属层薄膜上形成光刻胶图案，利用该光刻胶图案作为蚀刻掩膜对源、漏金属层薄膜构图，以在绝缘层上形成源极1025和漏极1024。源、漏金属层的材料包括铝钕(AlNd)合金、钨钼合金(WMo)，铝(Al)、铜(Cu)、钼(Mo)或铬(Cr)的单层膜，也可以是这些金属材料任一组合所构成的复合膜。
参见图6e至6f，在源极1025和漏极1024形成后，在薄膜晶体管上依次沉积钝化层薄膜104’和第一金属层薄膜105’，然后在第一金属层薄膜105’的表面涂覆光刻胶，并对光刻胶构图，以在第一金属层薄膜105’上形成光刻胶图案，利用该光刻胶图案作为蚀刻掩膜对第一金属层薄膜105’和钝化层薄膜104’进行构图。以在薄膜晶体管上形成第一金属层105、钝化层104、第一连接孔1071和凹槽108。
该钝化层薄膜104’的材料包括无机绝缘膜，例如氮化硅、氧化硅等，其厚度为0.15-0.25μm，例如0.2μm。该钝化层薄膜采用化学气相沉积的方法沉积，该第一金属层薄膜的材料包括钼、铝、铜中的任意一种或它们形成的合金，例如，铝铜合金、铝钼合金、铜钼合金、钼铝铜合金。
例如，利用该光刻胶图案作为蚀刻掩膜对第一金属层薄膜105’和钝化层薄膜104’进行构图时，可采用第一刻蚀剂对第一金属层薄膜105’和钝化层薄膜104’进行刻蚀。该第一刻蚀剂例如为混合腐蚀性离子，是包含氟化铵(NH4F)、氢氟酸(HF)等的混合溶液。通过控制刻蚀时间来保证在钝化 层薄膜下的源极不被刻蚀掉。
例如，采用第二刻蚀剂和第三刻蚀剂分别对第一金属层薄膜105’和钝化层薄膜104’进行刻蚀。第一金属层薄膜105’和钝化层薄膜104’采用同一个掩膜进行刻蚀，只是在用第二刻蚀剂刻蚀完第一金属层薄膜后，把刻蚀剂换成第三刻蚀剂再对钝化层薄膜104’进行刻蚀。
例如，该第二刻蚀剂包括：水、硝酸、磷酸及醋酸形成的溶液，其中各酸的含量有一定的范围限制，例如，硝酸的重量百分比介于0.1％至4％。磷酸的重量百分比介于50％至78％，醋酸的重量百分比介于0.1％至15％。在一示例中，硝酸的重量百分比例如是1.5％，磷酸的重量百分比例如是70％，醋酸的重量百分比例如是10％，刻蚀剂的剩余部分为水，水例如是去离子水。进一步，该刻蚀剂还可以包括作为抑制剂的唑化合物，用以稳定刻蚀速率的金属离子螯合剂。金属离子螯合剂例如是柠檬酸、草酸、乙二胺四乙酸或反-环己烯二胺四酸等。
例如，该第三刻蚀剂包括：用于湿法刻蚀的KOH等碱溶液，也可包括用于干法刻蚀的SF6，O2等气体。
例如，如图6f所示，由于刻蚀剂对钝化层104和第一金属层105的刻蚀程度并不完全相同，所以在钝化层104和第一金属层105之间形成了第一台阶204。第一台阶204的存在使第一连接孔1071变得平缓。该第一连接孔1071包括第一部分和第二部分，第一部分和第二部分依次具有形成在钝化层104、第一金属层105上的远离衬底基板101一侧的第一尺寸201和第二尺寸202，该第一尺寸201小于或等于第二尺寸202。
通过第一构图工艺刻蚀第一金属层薄膜和钝化层薄膜形成包括第一金属层105、钝化层104、第一连接孔1071和凹槽108的图形，节省了工艺步骤，同时节约了生产成本。
参见图6g至6h，在形成有第一金属层105、钝化层104、第一连接孔1071和凹槽108的衬底基板101上沉积绝缘层薄膜106’，然后在绝缘层薄膜106’的表面涂覆光刻胶，并对光刻胶构图,以在绝缘层薄膜106’上形成光刻胶图案，利用该光刻胶图案作为蚀刻掩膜对绝缘层薄膜进行构图，以形成绝缘层106和第二连接孔1072，其中第一连接孔1071和第二连接孔1072连通形成过孔结构。绝缘层106的材料为有机树脂、氮化硅和氧化硅中的任意一种。
例如，参见图6h，第二连接孔1072包括第三部分，第三部分具有形成在绝缘层106上的远离衬底基板101一侧的第三尺寸203。其中，第二尺寸202小于或等于第三尺寸203，且在第一金属层105和绝缘层106之间形成第二台阶205。第二台阶205的存在使过孔结构107变得更平缓，从而更利于第二金属层的沉积，同时第二金属电层更不易断裂，增强了第二金属层的导通性能。
如图6i，在形成有过孔结构107和绝缘层106的衬底基板101上沉积第二金属层膜(未示出)，然后在第二金属层膜的表面涂覆光刻胶，并对光刻胶构图,以在第二金属层膜上形成光刻胶图案，利用该光刻胶图案作为蚀刻掩膜对第二金属层膜进行构图，以形成第二金属层1031的图案。第二金属层1031与源极1025在过孔结构107处直接接触。再利用同样的构图工艺形成透光或不透光材料的偏压电极1032，在此不再赘述。
例如，阵列基板的制备方法还可以包括在第二金属层上形成透明导电层(未示出)。例如，该透明导电层可以为ITO、AZO、IZO、透明的导电树脂、石墨烯薄膜、碳纳米管薄膜等。
如图6j，在形成有第二金属层1031和偏压电极1032的衬底基板101上形成a-Si半导体层1033。
本发明的实施例提供一种阵列基板及其制备方法、传感器和探测设备。本发明至少一个实施例提供一种阵列基板，包括：衬底基板；薄膜晶体管，设置于衬底基板上，该薄膜晶体管包括源极和有源层；钝化层，设置于薄膜晶体管上；第一金属层，设置于钝化层上；绝缘层，设置于第一金属层上；过孔结构，贯穿绝缘层、第一金属层和钝化层；检测单元，设置于绝缘层上，检测单元包括第二金属层；其中，第二金属层通过过孔结构与源极直接接触。该阵列基板以及包含该阵列基板的传感器和探测设备具有以下有益效果：该阵列基板可用于传感器和探测设备，在阵列基板的制作过程中可在同一构图工艺中对第一金属层和钝化层进行构图，合并了制作工序，便于生产，同时节省了生产成本。
有以下几点需要说明：
(1)为表示清楚，并没有给出阵列基板、传感器和探测设备的全部结构。为实现传感器和探测设备的必要功能，本领域技术人员可以根据具体应用场 景进行设置其他未示出的结构，本发明对此不做限制。本公开的附图也只涉及到本发明实施例涉及到的结构，其他结构可在本公开的基础上参考通常设计。
(2)在彼此不冲突的情况下，本发明的不同示例中的特征可以相互组合。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年4月13日递交的中国专利申请第201610229060.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (19)

  1. 一种阵列基板，包括：
    衬底基板；
    薄膜晶体管，设置于所述衬底基板上，所述薄膜晶体管包括源极和有源层；
    钝化层，设置于所述薄膜晶体管上；
    第一金属层，设置于所述钝化层上；
    绝缘层，设置于所述第一金属层上；
    过孔结构，贯穿所述绝缘层、所述第一金属层和所述钝化层；
    检测单元，设置于所述绝缘层上，所述检测单元包括第二金属层；
    其中，所述第二金属层通过所述过孔结构与所述源极直接接触。
  2. 根据权利要求1所述的阵列基板，还包括：
    贯穿所述第一金属层和所述钝化层的凹槽，且所述凹槽在平行于所述衬底基板的方向上位于所述过孔结构和所述有源层之间，所述第一金属层在所述凹槽处断开以形成彼此间隔的不同部分。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第一金属层在所述衬底基板上的投影与所述薄膜晶体管在所述衬底基板上的投影至少部分重合。
  4. 根据权利要求1-3中任一项所述的阵列基板，其中，所述检测单元还包括与所述第二金属层间隔设置的偏压电极、以及与所述第二金属层和所述偏压电极均接触的半导体层。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，所述第二金属层上设置有透明导电层。
  6. 根据权利要求5所述的阵列基板，其中，所述透明导电层的厚度大于所述第二金属层的厚度。
  7. 根据权利要求6所述的阵列基板，其中，所述透明导电层包括ITO、IZO中的任意一种。
  8. 根据权利要求1-7中任一项所述的阵列基板，其中，所述绝缘层的材料为有机树脂、氮化硅和氧化硅中的任意一种。
  9. 根据权利要求8所述的阵列基板，其中，所述绝缘层的厚度为1-4μm。
  10. 根据权利要求1-9中任一项所述的阵列基板，其中，所述第一金属层、所述第二金属层的材料为钼、铝、铜中的任意一种或组合。
  11. 一种传感器，包括权利要求1-10中任一项所述的阵列基板。
  12. 一种探测设备，包括权利要求11所述的传感器。
  13. 一种阵列基板的制备方法，包括：
    在衬底基板上形成薄膜晶体管，所述薄膜晶体管包括源极和有源层；
    在所述薄膜晶体管上依次沉积钝化层薄膜和第一金属层薄膜；
    对所述第一金属层薄膜和所述钝化层薄膜进行第一构图工艺以形成第一金属层、钝化层、位于所述第一金属层和所述钝化层中的第一连接孔和凹槽，所述第一连接孔露出所述源极的一部分，所述第一金属层在所述凹槽处断开以形成彼此间隔的不同部分；
    在所述第一金属层、所述钝化层、所述第一连接孔和所述凹槽上形成绝缘层薄膜并进行第二构图工艺以形成绝缘层图案和第二连接孔，其中所述第一连接孔和所述第二连接孔连通以形成过孔结构；
    在形成有所述过孔结构的衬底基板上形成检测单元，所述检测单元包括第二金属层，所述第二金属层通过所述过孔结构与所述源极直接接触。
  14. 根据权利要求13所述的制备方法，其中，在所述第一构图工艺中，采用第一刻蚀剂对所述第一金属层薄膜和所述钝化层薄膜进行刻蚀。
  15. 根据权利要求13所述的制备方法，其中，在所述第一构图工艺中，采用第二刻蚀剂和第三刻蚀剂分别对所述第一金属层薄膜和所述钝化层薄膜进行刻蚀。
  16. 根据权利要求13-15中任一项所述的制备方法，其中，所述凹槽在平行于所述衬底基板的方向上位于所述过孔结构和所述有源层之间。
  17. 根据权利要求13-16中任一项所述的制备方法，其中，所述第一金属层在所述衬底基板上的投影与所述薄膜晶体管在所述衬底基板上的投影至少部分重合。
  18. 根据权利要求13-17中任一项所述的制备方法，还包括：在所述第二金属层上形成透明导电层。
  19. 根据权利要求18所述的制备方法，其中，所述透明导电层包括ITO、IZO中的任意一种。
PCT/CN2017/070747 2016-04-13 2017-01-10 阵列基板及其制备方法、传感器和探测设备 WO2017177735A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2017538380A JP6924698B2 (ja) 2016-04-13 2017-01-10 アレイ基板及びその製造方法、センサ並びに検出機器
KR1020177026551A KR102002444B1 (ko) 2016-04-13 2017-01-10 어레이 기판 및 그 제조 방법, 센서 및 검출 디바이스
US15/544,704 US10224353B2 (en) 2016-04-13 2017-01-10 Manufacturing method for an array substrate
EP17737456.8A EP3444842B1 (en) 2016-04-13 2017-01-10 Array substrate, manufacturing method therefor, sensor, and detection device
US16/249,251 US10622388B2 (en) 2016-04-13 2019-01-16 Array substrate sensor and detection device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610229060.XA CN105720063B (zh) 2016-04-13 2016-04-13 阵列基板及其制备方法、传感器和探测设备
CN201610229060.X 2016-04-13

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US15/544,704 A-371-Of-International US10224353B2 (en) 2016-04-13 2017-01-10 Manufacturing method for an array substrate
US16/249,251 Division US10622388B2 (en) 2016-04-13 2019-01-16 Array substrate sensor and detection device

Publications (1)

Publication Number Publication Date
WO2017177735A1 true WO2017177735A1 (zh) 2017-10-19

Family

ID=56160996

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/070747 WO2017177735A1 (zh) 2016-04-13 2017-01-10 阵列基板及其制备方法、传感器和探测设备

Country Status (6)

Country Link
US (2) US10224353B2 (zh)
EP (1) EP3444842B1 (zh)
JP (1) JP6924698B2 (zh)
KR (1) KR102002444B1 (zh)
CN (1) CN105720063B (zh)
WO (1) WO2017177735A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720063B (zh) 2016-04-13 2019-02-15 京东方科技集团股份有限公司 阵列基板及其制备方法、传感器和探测设备
CN105789324B (zh) 2016-04-15 2019-05-03 京东方科技集团股份有限公司 传感器及其制造方法、电子设备
CN109713076A (zh) * 2019-02-21 2019-05-03 京东方科技集团股份有限公司 平板探测基板及其制备方法、平坦探测器
CN110176519B (zh) * 2019-06-17 2021-08-06 京东方科技集团股份有限公司 一种平板探测器及其制作方法
CN113597528B (zh) * 2019-09-19 2023-09-29 京东方科技集团股份有限公司 灯条、背光组件和显示装置
CN111312777B (zh) * 2020-02-26 2023-12-15 合肥鑫晟光电科技有限公司 显示基板、显示面板、显示装置和显示基板的制作方法
US11281046B2 (en) * 2020-03-17 2022-03-22 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Backlight module, manufacturing method thereof, and display device
CN112713161B (zh) * 2020-12-30 2023-10-31 武汉华星光电技术有限公司 一种阵列基板及其制备方法
WO2022252008A1 (zh) * 2021-05-31 2022-12-08 京东方科技集团股份有限公司 X射线探测器及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030010922A1 (en) * 2001-07-12 2003-01-16 Jung-Kee Yoon Switching device of an X-ray sensor and method for manufacturing the same
CN1748314A (zh) * 2003-02-14 2006-03-15 佳能株式会社 固态图像拾取设备和辐射图像拾取设备
CN105720063A (zh) * 2016-04-13 2016-06-29 京东方科技集团股份有限公司 阵列基板及其制备方法、传感器和探测设备
CN105789324A (zh) * 2016-04-15 2016-07-20 京东方科技集团股份有限公司 传感器及其制造方法、电子设备
CN205488128U (zh) * 2016-04-13 2016-08-17 京东方科技集团股份有限公司 阵列基板、传感器和探测设备
CN205508828U (zh) * 2016-04-15 2016-08-24 京东方科技集团股份有限公司 传感器及电子设备

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197660A (ja) * 1997-09-19 1999-04-09 Semiconductor Energy Lab Co Ltd イメージセンサおよびそれを用いた装置
KR100617029B1 (ko) 2001-12-29 2006-08-30 엘지.필립스 엘시디 주식회사 액정표시장치의 제조방법
TW544946B (en) 2002-07-12 2003-08-01 Hannstar Display Corp Manufacturing method of X-ray inspecting instrument array unit
KR101171175B1 (ko) * 2004-11-03 2012-08-06 삼성전자주식회사 도전체용 식각액 및 이를 이용한 박막 트랜지스터표시판의 제조 방법
US7479655B2 (en) * 2006-01-31 2009-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP5280671B2 (ja) * 2006-12-20 2013-09-04 富士フイルム株式会社 画像検出器および放射線検出システム
JP2009252835A (ja) * 2008-04-02 2009-10-29 Fujifilm Corp 電磁波検出素子
CN102655095B (zh) 2011-06-01 2014-10-15 京东方科技集团股份有限公司 薄膜晶体管及阵列基板的制造方法
KR20130006999A (ko) * 2011-06-28 2013-01-18 삼성디스플레이 주식회사 박막 트랜지스터 및 이의 제조 방법
US9082925B2 (en) * 2013-03-13 2015-07-14 Sunpower Corporation Methods for wet chemistry polishing for improved low viscosity printing in solar cell fabrication
JP2014225524A (ja) * 2013-05-15 2014-12-04 キヤノン株式会社 検出装置の製造方法、その検出装置、及び、検出システム
US9780140B2 (en) * 2013-08-07 2017-10-03 Sharp Kabushiki Kaisha X-ray image sensor substrate
US20150364626A1 (en) * 2014-06-11 2015-12-17 Electronics And Telecommunications Research Institute Transparent electrode and solar cell including the same
CN105097860B (zh) * 2015-06-18 2018-06-29 京东方科技集团股份有限公司 探测基板及其制造方法、探测器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030010922A1 (en) * 2001-07-12 2003-01-16 Jung-Kee Yoon Switching device of an X-ray sensor and method for manufacturing the same
CN1748314A (zh) * 2003-02-14 2006-03-15 佳能株式会社 固态图像拾取设备和辐射图像拾取设备
CN105720063A (zh) * 2016-04-13 2016-06-29 京东方科技集团股份有限公司 阵列基板及其制备方法、传感器和探测设备
CN205488128U (zh) * 2016-04-13 2016-08-17 京东方科技集团股份有限公司 阵列基板、传感器和探测设备
CN105789324A (zh) * 2016-04-15 2016-07-20 京东方科技集团股份有限公司 传感器及其制造方法、电子设备
CN205508828U (zh) * 2016-04-15 2016-08-24 京东方科技集团股份有限公司 传感器及电子设备

Also Published As

Publication number Publication date
JP2019514193A (ja) 2019-05-30
US10622388B2 (en) 2020-04-14
KR102002444B1 (ko) 2019-07-23
US10224353B2 (en) 2019-03-05
US20180114802A1 (en) 2018-04-26
EP3444842B1 (en) 2021-12-15
CN105720063B (zh) 2019-02-15
EP3444842A1 (en) 2019-02-20
JP6924698B2 (ja) 2021-08-25
CN105720063A (zh) 2016-06-29
US20190165007A1 (en) 2019-05-30
KR20170129761A (ko) 2017-11-27
EP3444842A4 (en) 2020-02-12

Similar Documents

Publication Publication Date Title
WO2017177735A1 (zh) 阵列基板及其制备方法、传感器和探测设备
US10297635B2 (en) TFT and manufacturing method thereof, array substrate and manufacturing method thereof, X-ray detector and display device
US9128341B2 (en) Visible sensing transistor, display panel and manufacturing method thereof
EP3444847B1 (en) Sensor and manufacturing method therefor, and electronic device
US9786711B2 (en) Array substrate of X-ray sensor and method for manufacturing the same
US10991750B2 (en) Active matrix substrate and imaging panel with same
US9214562B2 (en) Method of manufacturing field-effect transistor, field-effect display device and electromagnetic wave detector
KR20100126214A (ko) 전계 효과형 트랜지스터의 제조 방법, 전계 효과형 트랜지스터, 및 표시 장치의 제조 방법
CN109494231B (zh) 薄膜晶体管阵列基板及其制作方法、以及液晶显示面板
KR101674207B1 (ko) 엑스레이 검출기
JP6108941B2 (ja) 導電積層膜及びタッチパネル
KR100683526B1 (ko) 엑스-선 검출소자 및 그의 제조방법
JP2009182134A (ja) 電磁波検出素子の製造方法
KR920005635B1 (ko) 차광성 박막의 에칭방법.
JP2019145594A (ja) アクティブマトリクス基板及びそれを備えた撮像パネルと製造方法
US20130037903A1 (en) Display device
KR20080032983A (ko) 박막트랜지스터 기판 및 이의 제조 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15544704

Country of ref document: US

ENP Entry into the national phase

Ref document number: 2017538380

Country of ref document: JP

Kind code of ref document: A

REEP Request for entry into the european phase

Ref document number: 2017737456

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20177026551

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17737456

Country of ref document: EP

Kind code of ref document: A1