WO2017166463A1 - 转换电路、心跳电流信号转换装置及方法、心跳检测系统 - Google Patents

转换电路、心跳电流信号转换装置及方法、心跳检测系统 Download PDF

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WO2017166463A1
WO2017166463A1 PCT/CN2016/087620 CN2016087620W WO2017166463A1 WO 2017166463 A1 WO2017166463 A1 WO 2017166463A1 CN 2016087620 W CN2016087620 W CN 2016087620W WO 2017166463 A1 WO2017166463 A1 WO 2017166463A1
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Prior art keywords
switch
mos transistor
current signal
signal
heartbeat
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English (en)
French (fr)
Inventor
张孟文
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/02—Detecting, measuring or recording for evaluating the cardiovascular system, e.g. pulse, heart rate, blood pressure or blood flow
    • A61B5/024—Measuring pulse rate or heart rate

Definitions

  • the invention belongs to the technical field of integrated circuits, and in particular relates to a conversion circuit, a heartbeat current signal conversion device, a conversion method and a heartbeat detection system.
  • the conversion circuit is one of the core parts. Its function is to downconvert the heartbeat current signal modulated at the clock frequency to zero frequency, and then convert the heartbeat current signal into a voltage signal through the transimpedance amplifier. Then, it is sent to the subsequent circuit for processing. Therefore, the performance of the conversion circuit such as power consumption, noise, linearity, and output dynamic range seriously restricts the performance of the entire heartbeat detection system.
  • Current conversion circuits generally have two forms of single-ended and first-time mixing and re-integration.
  • a single-ended conversion circuit structure it is usually necessary to convert the heartbeat current signal modulated at the clock frequency into a voltage signal, and then down-convert the voltage signal to zero frequency. Since the heartbeat current signal is very small, a transimpedance amplifier is required to provide a very large transimpedance in order to obtain a suitable voltage signal, thereby increasing the noise of the conversion circuit. Moreover, using a single-ended form, common mode noise interference will affect the output of the transimpedance amplifier, which further increases the noise of the converted electrical.
  • the conversion circuit structure of the first mixing and re-integration is adopted, although the noise and common mode noise interference caused by the large-span resistance are solved, the working dynamic range is small due to the circuit bias voltage, especially in the deep sub-micron process. Next, this problem will be more obvious. Moreover, the bandwidth of the conversion circuit varies with the signal, and the influence of the parasitic capacitance is low, so the linearity is low.
  • the existing heartbeat current signal conversion circuit has many problems such as noise caused by large-span resistance, common mode noise interference, small working dynamic range, and poor linearity.
  • the technical problem to be solved by the present invention is to provide a conversion circuit and a heartbeat
  • the flow signal conversion device, the conversion method and the heartbeat detection system are used for solving the problem that the existing heartbeat current signal conversion circuit has noise caused by large-span resistance, common mode noise interference, small working dynamic range, and poor linearity.
  • a first aspect of the present invention provides a conversion circuit including a fully differential integrator and a mixer
  • the mixer is configured to frequency convert the input current signal, and then output the obtained variable frequency current signal to the fully differential integrator;
  • the fully differential integrator is configured to integrate the input variable frequency current signal, convert the integrated variable frequency current signal, and output a voltage signal.
  • a second aspect of the present invention provides a heartbeat current signal conversion apparatus including the conversion circuit and the converter as described above;
  • the converter is configured to convert a modulated optical signal into a current signal and then transmit the signal to the mixer; the modulated optical signal includes a modulated heartbeat optical signal;
  • the mixer is configured to frequency convert the heartbeat current signal in the current signal to zero frequency, convert the background photocurrent signal in the current signal to a clock frequency, and then convert the modulated photocurrent signal in the current signal to the converted heartbeat Transmitting a current signal and the converted background photocurrent signal to the fully differential integrator;
  • the fully differential integrator is configured to alternately perform positive integration and inverse integration on the input modulated photocurrent signal, the converted heartbeat current signal, and the converted background photocurrent signal, and then perform conversion and output Modulate the photovoltage signal and the heartbeat voltage signal.
  • a third aspect of the present invention provides a method for converting a heartbeat current signal, including:
  • the modulated optical signal includes a modulated heartbeat optical signal
  • the current signal includes a modulated optical current signal, a heartbeat current signal, and a background optical current signal
  • the modulated photocurrent signal, the converted heartbeat current signal and the converted background photocurrent signal are alternately positively integrated and inversely integrated, and then converted to output a modulated photovoltage signal and a heartbeat voltage signal.
  • a fourth aspect of the present invention provides a heartbeat detecting system including the above-described heartbeat current signal converting apparatus.
  • the fully differential integrator provided by the embodiment of the present invention can improve
  • the heartbeat current signal conversion device suppresses common mode noise, linearity, and output dynamic range.
  • the heartbeat current signal conversion device loop always forms a closed loop, so it can be directly output to the lower stage circuit, eliminating the output buffer circuit, thereby reducing power consumption.
  • the load capacitance is connected across the output of the fully differential integrator, the equivalent load capacitance can be doubled, resulting in a double the capacitance required to achieve the same noise bandwidth.
  • the heartbeat current signal conversion device provided by the embodiment of the present invention provides a standard differential output interface, which is easy to link the latter circuit.
  • the heartbeat detection system provided by the invention can suppress common mode noise, improve linearity, increase output swing, reduce power consumption, and save circuit cost.
  • FIG. 1 is a schematic structural diagram of a conversion circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a fully differential integrator according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of an operational amplifier according to Embodiment 1 of the present invention.
  • Embodiment 4 is a flow chart of a conversion method provided by Embodiment 2 of the present invention.
  • FIG. 5 is a schematic structural diagram of a heartbeat current signal conversion apparatus according to Embodiment 3 of the present invention.
  • FIG. 6 is a detailed structural diagram of a heartbeat current signal conversion apparatus according to Embodiment 3 of the present invention.
  • FIG. 7 is a timing diagram of a junction of a heartbeat current signal conversion apparatus according to Embodiment 3 of the present invention.
  • FIG. 8 is a schematic structural diagram of a heartbeat current signal conversion apparatus according to Embodiment 4 of the present invention.
  • FIG. 9 is a schematic structural diagram of a bootstrap circuit according to Embodiment 4 of the present invention.
  • FIG. 10 is a schematic structural diagram of a common mode negative feedback circuit according to Embodiment 5 of the present invention.
  • FIG. 11 is a flowchart of a method for converting a heartbeat current signal according to Embodiment 6 of the present invention.
  • Embodiment 1 shows a conversion circuit according to Embodiment 1 of the present invention, including a fully differential integrator and a mixer;
  • the mixer is configured to frequency convert the input current signal, and then output the obtained variable frequency current signal to the fully differential integrator;
  • the fully differential integrator is configured to integrate the input variable frequency current signal, convert the integrated variable frequency current signal, and output a voltage signal.
  • the input circuit signal can be converted, integrated, and converted to output a voltage signal.
  • This embodiment can efficiently filter out other interference signals to obtain an actual required voltage signal.
  • FIG. 2 shows a fully differential integrator according to Embodiment 1 of the present invention, including an operational amplifier 201, a first feedback capacitor C F1 , a second feedback capacitor C F2 , a first reset switch S F1 , and a second reset switch S F2 ;
  • the first feedback capacitor C F1 is connected between the inverting input terminal V IN of the operational amplifier 201 and the positive output terminal V OP ; the second feedback capacitor C F2 is connected to the non-inverting input terminal V IP and the negative output terminal V ON of the operational amplifier 201
  • the first end of the first reset switch S F1 is connected to the inverting input terminal V IN of the operational amplifier 201 , and the second end of the first reset switch S F1 is connected to the positive output terminal V OP of the operational amplifier 201 ;
  • the first end of S F2 is connected to the non-inverting input terminal V IP of the operational amplifier 201, and the second end of the second reset switch S F2 is connected to the negative output terminal V ON of the operational amplifier 201.
  • the fully differential integrator further includes a load capacitance C L connected between the positive output terminal V OP and the negative output terminal V ON of the operational amplifier.
  • the load capacitance C L is a preferred solution, and the purpose is to limit the noise bandwidth of the operational amplifier 201, and the trade-off is performed according to actual needs, and is not limited herein.
  • the invention also provides a conversion method as shown in FIG. 4, comprising:
  • Integrating the variable frequency current signal Integrating the variable frequency current signal, converting the integrated variable frequency current signal, and outputting a voltage signal.
  • the fully differential integrator provided in the above embodiment is suitable for the field of integrated circuits, and can improve the common mode noise suppression, linearity, output dynamic range, and circuit of the conversion circuit in the heartbeat detection circuit.
  • the operational amplifier is an operational amplifier of a folded cascode structure as shown in FIG. 3, and a single-machine structure can be used to reduce power consumption and to easily control the output noise voltage.
  • a heartbeat current signal conversion device includes a conversion circuit and a converter
  • the converter is configured to convert the modulated optical signal into a current signal and then transmit the signal to the mixer; the modulated optical signal includes a modulated heartbeat optical signal.
  • the heartbeat light signal is the light signal radiated by the LED light on the human body.
  • the modulated light contains the modulated light signal and the optical signal related to the modulation of the optical heartbeat in the modulation.
  • the mixer is configured to frequency convert the heartbeat current signal in the current signal to zero frequency, convert the background photocurrent signal in the current signal to a clock frequency, and then convert the modulated photocurrent signal in the current signal to the converted heartbeat
  • the current signal and the converted background photocurrent signal are transmitted to the fully differential integrator. Because in practical applications, when the converter converts the modulated optical signal into a current signal, it is easy to convert the mixed background light signal at the same time. Therefore, the converter actually converts the modulated optical signal and modulation.
  • the light includes a modulated heartbeat optical signal and a background optical signal, so the current signal generated by the converter conversion includes a modulated photocurrent signal, a heartbeat current signal, and a background photocurrent signal.
  • the main function of the mixer is to perform frequency conversion processing on the mixed background light current signal to ensure the modulated photocurrent signal in the current signal, the converted heartbeat current signal, and the converted background photocurrent signal input.
  • the fully differential integrator filters the background light.
  • the fully differential integrator is configured to alternately perform positive integration and inverse integration on the input modulated photocurrent signal, the converted heartbeat current signal, and the converted background photocurrent signal, and then perform conversion and output Modulate the photovoltage signal and the heartbeat voltage signal.
  • the function of the fully differential integrator is to integrate the input current signals alternately (including positive integration and inverse integration) to amplify the low frequency heartbeat signal, filter out the high frequency background light signal, and then filter After the background light signal, the modulated photocurrent signal and the heartbeat current signal obtained after the positive integration and the inverse integration are respectively converted, and the current signal is converted into a voltage signal to obtain a modulated photovoltage signal and a heartbeat voltage signal, and then output.
  • a converter is added on the basis of the first embodiment, and the modulated light modulated with the heartbeat signal can be converted into a current signal and then input to the conversion circuit, and the conversion circuit converts the current.
  • the signal is first converted, then integrated and converted to output a modulated photovoltage signal.
  • the number and heartbeat voltage signals are used in subsequent heartbeat detection to effectively amplify the low frequency heartbeat signal and filter out the high frequency background light signal.
  • the converter includes a photodiode D; the anode of the photodiode D is grounded, and the cathode of the photodiode D is connected to the mixer.
  • the mixer includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;
  • the first end of the first switch S1 is connected to the external common mode power supply V CM , the second end of the first switch S1 is connected to the converter through the third switch S3; the first end of the second switch S2 is connected to the external common mode power supply V CM The second end of the second switch S2 is connected to the converter through a fourth switch S4; the inverting input terminal V IN of the fully differential integrator is connected between the first switch S1 and the third switch S3, the whole The non-inverting input terminal V IP of the differential integrator is connected between the second switch S2 and the fourth switch S4.
  • the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all FETs.
  • the capacitance C PD is the parasitic junction capacitance of the photodiode D
  • the switches S1 to S4 constitute a mixer
  • the operational amplifier 201 the feedback capacitance C F1 , the feedback capacitance C F2 , the reset switch S F1 , and
  • the reset switch S F2 constitutes a fully differential integrator.
  • ⁇ and I a two-phase non-overlapping clock signal
  • ⁇ represents a clock signal of the first clock output
  • a clock signal representing the output of the second clock, rst being the reset signal of the fully differential integrator.
  • the working process of the heartbeat current signal conversion device provided by the third embodiment of the present invention is divided into three parts: a reset phase, an integration phase, and a retention phase:
  • the positive and inverse integral phases alternate.
  • ⁇ is high
  • the fully differential integrator is in positive integration phase.
  • switches S2 and S3 are closed, S1 and S4 are open, and the positive input terminal of operational amplifier 201 is open.
  • the inverting input terminal V IN of the operational amplifier 201 is coupled to the cathode voltage V PD of the photodiode D.
  • the photocurrent I PD of the photodiode can only flow from the positive output terminal V OP of the operational amplifier 201.
  • the inverting input terminal V IN of the operational amplifier 201 increases the voltage of the positive output terminal V OP of the operational amplifier 201.
  • the common mode negative feedback keeps the output common mode constant, a mirror current of the same magnitude as the photocurrent I PD is generated from the positive phase input terminal V IP of the operational amplifier 201 to the negative output terminal V ON , so that The voltage at the negative output terminal V ON of the operational amplifier 201 is lowered.
  • the load capacitance C L is used to limit the noise bandwidth of the operational amplifier 201, assuming that the input transconductance of the operational amplifier 201 is gm, and the impedance magnitude R EQ output from the fully differential integrator is :
  • df the differential of the frequency
  • ⁇ the angular frequency
  • ⁇ 2 ⁇ f
  • the differential output voltage of the fully differential integrator is:
  • the mixer switches S1 to S4 are turned on without any other circuit controlling the gate voltage of the mixer.
  • the gate-source and gate-drain voltage difference of the switches S1 to S4 is V DD /2.
  • S1 to S4 will enter the subthreshold region, resulting in The on-resistance is very large.
  • the resistor and the parasitic capacitance C PD of the photodiode D form a pole (low-pass characteristic), which will output the high-frequency component of the current of the photodiode D (modulating the photocurrent signal and the heartbeat current signal modulated on the modulated light and its harmonic
  • the filter is filtered so that the amount of signal entering the fully differential integrator becomes smaller, thereby affecting the signal-to-noise ratio of the fully differential integrator output.
  • the present invention provides a fourth embodiment as described in FIG. 8.
  • a bootstrap circuit is included;
  • the bootstrap circuit is configured to output a gate voltage to a gate of the switch in the mixer such that a difference between a gate-source voltage of the switch and a gate-drain voltage of the switch in the mixer is equal to a power supply voltage value.
  • the specific bootstrap circuit is as shown in FIG. 9 , and includes a fifth switch S5 , a sixth switch S6 , a seventh switch S7 , an eighth switch S8 , a ninth switch S9 , a first capacitor C 1 , and a first MOS transistor M1 .
  • the first end of the fifth switch S5 is grounded, and the second end of the fifth switch S5 is connected to the first power source V1 through the sixth switch S6, the seventh switch S7 and the eighth switch S8; the sixth switch S6 and the seventh switch common mode S7 external power source V CM; source of the first MOS transistor M1 is connected to a first capacitor C 1 between the fifth switch S5 and the sixth switch S6 via electrode, a gate of the first MOS transistor M1 is connected to the seventh Between the switch S7 and the eighth switch S8, the drain of the first MOS transistor M1 is connected to the gate voltage output terminal V G ; the gate of the second MOS transistor M2 is connected to the gate of the first MOS transistor M1, and the second MOS transistor The source of M2 is grounded through the ninth switch S9, the drain of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1; the drain of the third MOS transistor M3 is connected to the source of the first MOS transistor M1, and the third MOS The gate of the tube M3 is
  • the source of the fifth MOS transistor M5 is connected to the source of the second MOS transistor M2, the drain of the fifth MOS transistor M5 is connected to the fourth power source V4, and the gate of the fifth MOS transistor M5 is connected to the signal output terminal of the second clock.
  • the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8, and the ninth switch S9 are all FETs.
  • connection point between the fifth switch S5, a sixth switch and a first capacitor C 1 to the point A the seventh switch S7, the eighth switch S8, the gate of the first MOS transistor and a second
  • the connection point between the gates of the MOS transistors is point B
  • the connection point between the second MOS tube and the ninth switch S9 is C point
  • the connection point between the drains is point D to further elaborate the working principle of the bootstrap circuit:
  • the operating voltage of the positive phase input terminal V IP and the inverting input terminal V IN of the fully differential integrator is generally one-half of the power supply voltage V DD , the on-resistance of the mixer is very high, which will result in the inflow of fully differential integration.
  • the current of the device is reduced, and the larger resistance contributes to larger noise. Therefore, in the present embodiment, a bootstrap circuit is employed to increase the gate voltage of the mixer switch, so that the signal-to-noise ratio of the entire conversion circuit can be increased.
  • the gate voltage output terminal of the bootstrap circuit is connected to the gates of the mixer switches S1 to S4, so that the difference between the gate source and the gate drain voltage of the mixer is about the power supply voltage V DD , thereby This reduces the on-resistance of the switches in the mixer, which increases the signal-to-noise ratio of the fully differential integrator output.
  • the operational amplifiers provided in the embodiments of the present invention are all operational amplifiers of the folded cascode structure as shown in FIG. 3.
  • the single-stage structure can reduce power consumption and easily control the output noise voltage.
  • the finite gain of the operational amplifier will cause the output signal to remain in the parasitic junction capacitance of the photodiode, this will cause the output amplitude to increase as the number of integration times decreases, so that the resulting signal amount is reduced, the signal-to-noise ratio reduce.
  • the fifth embodiment provided by the present invention is to add a common mode feedback circuit based on the fourth embodiment; the common mode negative feedback circuit is used for the positive output terminal and the negative output terminal of the fully differential integrator Obtaining a feedback common mode voltage, and generating a control voltage according to the feedback common mode voltage; the control voltage is used to control the common mode negative feedback circuit and the fully differential integrator to form a negative feedback loop.
  • the common mode negative feedback circuit includes a second capacitor C 2 , a third capacitor C 3 , a first resistor R1, a second resistor R2, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS tube M8, ninth MOS tube M9 and tenth MOS tube M10;
  • a first end of the second capacitor C 2 is connected to the positive output terminal V OP of the fully differential integrator, and a second end of the second capacitor C 2 is connected to the negative output terminal of the fully differential integrator via a third capacitor C 3 V ON ;
  • the first end of the first resistor R1 is connected to the positive output terminal V OP of the fully differential integrator, and the second end of the first resistor R1 is connected to the negative output terminal of the fully differential integrator through the second resistor R2 V ON ;
  • the second end of the second capacitor C 2 is connected to the second end of the first resistor R1;
  • the gate of the eighth MOS transistor M8 is connected between the first resistor R1 and the second resistor R2, and the eighth MOS transistor
  • the source of M8 is connected to the drain of the tenth MOS transistor M10, the drain of the eighth MOS transistor M8 is connected to the drain of the sixth MOS transistor M6, and the gate of the sixth MOS transistor M6 is connected to the drain of the eighth MOS transistor M
  • the source of the sixth MOS transistor M6 is grounded; the source of the seventh MOS transistor M7 is grounded, the drain of the seventh MOS transistor M7 is connected to the drain of the ninth MOS transistor M9, and the gate of the seventh MOS transistor M7 is connected to the control voltage output.
  • a drain of the ninth MOS transistor M9 is connected to the control voltage output terminal, a gate of the ninth MOS transistor M9 is connected to the common mode power supply V CM , and a source of the ninth MOS transistor M9 is connected to the tenth MOS transistor M
  • the drain of 10; the source of the tenth MOS transistor M10 is connected to the fifth power source V5, and the gate of the tenth MOS transistor M10 is connected to the sixth power source V BP .
  • FIG. 10 is a common mode feedback circuit of the operational amplifier shown in FIG. 3.
  • the resistor R1 and the resistor R2 obtain a feedback common mode voltage V CMO from the positive output terminal V OP and the negative output terminal V ON of the operational amplifier.
  • the eighth MOS transistor M8 and the ninth MOS transistor M9 generate a control voltage V CTRL to control the current mirror load tubes M14 and M15 of the operational amplifier of FIG.
  • the common mode negative feedback circuit forms a negative feedback with M14 ⁇ M17 in the operational amplifier.
  • the feedback common mode voltage V CMO is equal to the common mode voltage V CM .
  • the capacitor C1 and the capacitor C2 in FIG. 10 generate a zero point to cancel the pole formed by the resistor R1, the resistor R2, the eighth MOS transistor M8, and the ninth MOS transistor M9, so that the stability of the common mode negative feedback is improved.
  • the present invention also provides a fifth embodiment, as shown in FIG. 11, a method for converting a heartbeat current signal, comprising:
  • the modulated optical signal includes a modulated heartbeat optical signal
  • the current signal includes a modulated optical current signal, a heartbeat current signal, and a background optical current signal ;
  • the modulated photocurrent signal, the converted heartbeat current signal, and the converted background photocurrent signal are alternately positively integrated and inversely integrated, and then converted to output a modulated photovoltage signal and a heartbeat voltage signal.
  • the heartbeat current signal conversion device converts the received modulated optical signal into a current signal, and then modulates the background optical signal in the optical signal by means of frequency conversion, integration, and conversion. Filtering, amplifying the low frequency heartbeat signal, and then outputting the modulated photovoltage signal and the heartbeat voltage signal for subsequent heartbeat signal detection.
  • the present invention also provides a heartbeat detection system comprising the heartbeat current signal conversion device as described above.
  • the heartbeat current signal conversion device of the structure of FIG. 5 is used as a conversion circuit of the heartbeat detection system, which can suppress common mode noise, improve linearity, increase output swing, reduce power consumption, and save circuit cost.
  • the fully differential integrator provided by the embodiment of the invention can improve the suppression, linearity and output dynamic range of the common mode noise of the heartbeat current signal conversion device. Moreover, since the heartbeat current signal conversion device loop always forms a closed loop, it can be directly output to the lower stage circuit, eliminating the output buffer circuit, thereby reducing power consumption. At the same time, because the load capacitance is connected across the output of the fully differential integrator, the equivalent load capacitance can be doubled, resulting in a double the capacitance required to achieve the same noise bandwidth.
  • the embodiment of the present invention provides a heartbeat current signal conversion device mainly used in the field of heart rate monitoring application, and can also be used in other fields such as a touch screen, providing a standard ground differential output interface, and facilitating the link of the rear stage circuit.
  • the heartbeat current signal conversion device can eliminate BG, realize full differential output, achieve the purpose of suppressing noise, and has common mode suppression, has a large output dynamic range, and also provides full access to the rear circuit.
  • the disclosed systems and methods can be implemented in other ways.
  • the system embodiment described above is merely illustrative.
  • the division of the module is only a logical function division.
  • there may be another division manner for example, multiple modules or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module. It can be electrical, mechanical or other form.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules if implemented in the form of software functional modules and sold or used as separate products, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

一种心跳电流信号转换装置，包括转换器，用于将调制光信号转换为电流信号后传输出去；混频器，用于将电流信号中的心跳电流信号和背景光电流信号进行变频，然后将电流信号中的调制光电流信号、变频后的心跳电流信号和背景光电流信号传输出去；全差分积分器用于将输入的调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号分别进行正积分和反积分，然后输出电压信号。其中的全差分积分器能够提高心跳电流信号转换装置对共模噪声的抑制、线性度、输出动态范围。而且，由于心跳电流信号转换装置环路始终形成闭环，因此对下级电路可以直接输出，省去输出缓冲电路，从而降低功耗。

Description

转换电路、心跳电流信号转换装置及方法、心跳检测系统
本申请要求于2016年4月1日提交中国专利局、申请号为201610204252.5、发明名称为“转换电路、心跳电流信号转换装置及方法、心跳检测系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于集成电路技术领域，尤其涉及一种转换电路、心跳电流信号转换装置及转换方法、心跳检测系统。
背景技术
在光电式心跳检测系统中，转换电路是核心部分之一，它的作用是将调制在时钟频率上的心跳电流信号下变频到零频，然后再通过跨阻放大器将心跳电流信号转换成电压信号，之后送给后续电路进行处理。因此转换电路的功耗、噪声、线性度、输出动态范围等性能好坏严重制约了整个心跳检测系统的性能。目前的转换电路一般有单端和先混频再积分两种形式。
若采用单端形式的转换电路结构，通常需要先把调制在时钟频率上的心跳电流信号转换成电压信号，然后再将电压信号下变频至零频。由于心跳电流信号非常小，因此为了得到合适大小的电压信号需要跨阻放大器能提供一个非常大的跨阻，从而增加了转换电路的噪声。而且使用单端形式，共模噪声干扰将影响跨阻放大器的输出，也进一步增加了转换电的噪声。
若采用先混频再积分的转换电路结构，虽然解决了因为大跨阻带来的噪声和共模噪声干扰问题，但是由于电路偏置电压导致其工作动态范围较小，特别在深亚微米工艺下，这个问题将更明显。而且转换电路带宽随信号变化而变化，再加上寄生电容的影响，因此其线性度较低。
因此，现有的心跳电流信号转换电路存在大跨阻带来的噪声、共模噪声干扰、工作动态范围小、线性度差等诸多问题。
发明内容
有鉴于此，本发明所要解决的技术问题在于提供一种转换电路、心跳电 流信号转换装置及转换方法、心跳检测系统，用于解决现有心跳电流信号转换电路存在大跨阻带来的噪声、共模噪声干扰、工作动态范围小、线性度差的问题。
本发明第一方面提供一种转换电路，包括全差分积分器和混频器；
所述混频器，用于将输入的电流信号进行变频，然后将得到的变频电流信号输出至所述全差分积分器；
所述全差分积分器，用于对输入的所述变频电流信号进行积分，将积分后的所述变频电流信号进行转换后，输出电压信号。
本发明第二方面提供一种心跳电流信号转换装置，包括如上所述的转换电路和转换器；
所述转换器，用于将调制光信号转换为电流信号后传输至所述混频器；所述调制光信号包含有调制的心跳光信号；
所述混频器，用于将电流信号中的心跳电流信号变频至零频，将电流信号中的背景光电流信号变频至时钟频率，然后将电流信号中的调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号传输至所述全差分积分器；
所述全差分积分器，用于将输入的所述调制光电流信号、所述变频后的心跳电流信号和所述变频后的背景光电流信号交替进行正积分和反积分，然后进行转换后输出调制光电压信号和心跳电压信号。
本发明第三方面提供一种心跳电流信号转换方法，包括：
接收调制光信号，然后将所述调制光信号转换为电流信号；所述调制光信号包含有调制的心跳光信号；所述电流信号包括调制光电流信号、心跳电流信号和背景光电流信号；
将所述心跳电流信号变频至零频，将所述背景光电流信号变频至时钟频率；
将所述调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号交替进行正积分和反积分，然后进行转换后输出调制光电压信号和心跳电压信号。
本发明第四方面提供一种心跳检测系统，包括上述的心跳电流信号转换装置。
从上述本发明实施例可知，本发明实施例提供的全差分积分器能够提高 心跳电流信号转换装置对共模噪声的抑制、线性度、输出动态范围。另一方面，心跳电流信号转换装置环路始终形成闭环，因此对下级电路可以直接输出，省去输出缓冲电路，从而降低功耗。同时，因为负载电容接在了全差分积分器的输出两端，因此等效负载电容可以翻倍，从而获得相同噪声带宽所需要的电容面积小了一倍。此外，本发明实施例提供的心跳电流信号转换装置提供了标准的差分输出接口，易于后级电路的链接。同时本发明提供的心跳检测系统可以实现抑制共模噪声、提高线性、增加输出摆幅、降低功耗、节约电路成本等。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例一提供的一种转换电路的结构示意图。
图2是本发明实施例一提供的一种全差分积分器的结构示意图。
图3是本发明实施例一提供的运算放大器的结构示意图。
图4是本发明实施例二提供的一种转换方法的流程图。
图5是本发明实施例三提供的一种心跳电流信号转换装置的结构示意图。
图6是本发明实施例三提供的一种心跳电流信号转换装置的详细结构示意图。
图7是本发明实施例三提供的一种心跳电流信号转换装置的结时序示意图。
图8是本发明实施例四提供的一种心跳电流信号转换装置的结构示意图。
图9是本发明实施例四提供的自举电路的结构示意图。
图10是本发明实施例五提供的共模负反馈电路的结构示意图。
图11是本发明实施例六提供的一种心跳电流信号转换方法的流程图。
具体实施方式
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整 地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而非全部实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1示出了本发明实施例一提供的一种转换电路，包括全差分积分器和混频器；
所述混频器，用于将输入的电流信号进行变频，然后将得到的变频电流信号输出至所述全差分积分器；
所述全差分积分器，用于对输入的所述变频电流信号进行积分，将积分后的所述变频电流信号进行转换后，输出电压信号。
在本实施例提供的转换电路中，能够将输入的电路信号进行变频、积分和转换后输出电压信号，本实施例能够有效率滤除其他干扰信号，得到实际所需要的电压信号。
图2示出了本发明实施例一提供的一种全差分积分器，包括运算放大器201、第一反馈电容CF1、第二反馈电容CF2、、第一复位开关SF1和第二复位开关SF2；
第一反馈电容CF1连接于运算放大器201的反相输入端VIN和正输出端VOP之间；第二反馈电容CF2连接于运算放大器201的正相输入端VIP和负输出端VON之间；第一复位开关SF1的第一端连接运算放大器201的反相输入端VIN，第一复位开关SF1的第二端连接运算放大器201的正输出端VOP；第二复位开关SF2的第一端连接运算放大器201的正相输入端VIP，第二复位开关SF2的第二端连接运算放大器201的负输出端VON。
进一步地，所述全差分积分器还包括连接于运算放大器的正输出端VOP和负输出端VON之间的负载电容CL。在本实施例中，负载电容CL为优选方案，目的是为了限制运算放大器201的噪声带宽，根据实际需要进行取舍，在此不做限制。
本发明还提供了如图4所示的一种转换方法，包括：
接收电流信号，然后将所述电流信号进行变频得到变频电流信号；
对所述变频电流信号进行积分，将积分后的所述变频电流信号进行转换，输出电压信号。
上述实施例提供的全差分积分器适用于集成电路领域，能够提高心跳检测电路中转换电路对共模噪声抑制、线性度、输出动态范围，并降低了电路 的功耗、成本及与后级电路级联的难度。在本实施例中，运算放大器为如图3所示的折叠共源共栅结构的运算放大器，使用单机结构可以降低功耗，并且易于控制输出噪声电压。
基于上述实施例提供的转换电路，如图5所示，为本发明实施例三提供的一种心跳电流信号转换装置，包括转换电路和转换器；
所述转换器，用于将调制光信号转换为电流信号后传输至所述混频器；所述调制光信号包含有调制的心跳光信号。心跳光信号就是LED的光照射在人体上放射回来的光信号，调制光中包含了调制光信号和调制在调制中光心跳相关的光信号。
所述混频器，用于将电流信号中的心跳电流信号变频至零频，将电流信号中的背景光电流信号变频至时钟频率，然后将电流信号中的调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号传输至所述全差分积分器。因为在实际应用中，当转换器在将调制光信号转换为电流信号的过程中，容易将混杂进入的背景光信号也同时进行了转换，因此，转换器实际上是转换了调制光信号、调制光中包含有的调制的心跳光信号及背景光信号，所以转换器转换生成的电流信号中包含了调制光电流信号、心跳电流信号及背景光电流信号。在本实施例中混频器的主要作用就是将混杂进入的背景光电流信号进行变频处理，以保证电流信号中的调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号输入全差分积分器后，全差分积分器能够将背景光滤除。
所述全差分积分器，用于将输入的所述调制光电流信号、所述变频后的心跳电流信号和所述变频后的背景光电流信号交替进行正积分和反积分，然后进行转换后输出调制光电压信号和心跳电压信号。在本实施例中，全差分积分器的作用是将输入的电流信号交替进行积分(包括正积分和反积分)，用以放大低频的心跳信号，滤除高频的背景光信号，然后在滤除背景光信号后，将经过正积分和反积分后获得的调制光电流信号和心跳电流信号分别进行转换，将电流信号转换为电压信号，得到调制光电压信号和心跳电压信号后输出。
在本发明提供的第三实施例中，在实施例一的基础上加入转换器，能够将调制了心跳信号的调制光转换成电流信号后输入所述转换电路，所述转换电路将所述电流信号先进行变频，然后进行积分和转换后输出调制光电压信 号和心跳电压信号用于后续的心跳检测中，有效的放大了低频的心跳信号，滤除了高频的背景光信号。
如图6所示，所述转换器包括光敏二极管D；光敏二极管D的阳极接地，光敏二极管D的阴极连接所述混频器。
所述混频器包括第一开关S1、第二开关S2、第三开关S3和第四开关S4；
第一开关S1的第一端连接外接共模电源VCM，第一开关S1的第二端通过第三开关S3连接所述转换器；第二开关S2的第一端连接外接共模电源VCM，第二开关S2的第二端通过第四开关S4连接所述转换器；所述全差分积分器的反相输入端VIN连接于第一开关S1和第三开关S3之间，所述全差分积分器的正相输入端VIP连接于第二开关S2和第四开关S4之间。第一开关S1、第二开关S2、第三开关S3和第四开关S4均为场效应管。
在图6所示的电路中，电容CPD为光敏二极管D的寄生结电容，开关S1～S4构成了混频器，运算放大器201、反馈电容CF1、反馈电容CF2、复位开关SF1和复位开关SF2构成了全差分积分器。其中，φ和
Figure PCTCN2016087620-appb-000001
是两相非交叠时钟信号，以φ表示第一时钟输出的时钟信号，以
Figure PCTCN2016087620-appb-000002
表示第二时钟输出的时钟信号，rst为全差分积分器的复位信号。φ、
Figure PCTCN2016087620-appb-000003
和rst都是由单独的数字控制电路生成，因为数字控电路不是本发明实施例所要保护的重点，此处略去不表。以下，本发明提供的实施例三的工作原理通过结合图7来进行进一步地分析：
本发明实施例三提供的心跳电流信号转换装置的工作过程分：复位阶段、积分阶段和保持阶段三部分：
在复位阶段，φ、
Figure PCTCN2016087620-appb-000004
和rst都为高电平，因此开关S1～S4、SF1、SF2都闭合，使得光敏二极管D的阴极电压VPD、运算放大器201的反相输入端VIN、正相输入端VIP和负输出端VON、正输出端VOP的电压均为共模电压VCM。
在积分阶段，正积分和反积分两个相位交替进行，当φ为高时，全差分积分器处于正积分相位，此时开关S2和S3闭合，S1和S4打开，运算放大器201正相输入端接至共模电压VCM，为运算放大器的正相输入端提供共模电压；运算放大器201反相输入端VIN接至光敏二极管D的阴极电压VPD。此时由于运算放大器的正反相输入端虚短，光敏二极管D的阴极与共模电压VCM的电压值相等，因此光敏二极管的光敏电流IPD只能从运算放大器201的正输出端VOP流向运算放大器201的反相输入端VIN，从而使运算放大器201的正输出端VOP 的电压上升。与此同时，由于共模负反馈的作用令输出共模保持恒定，因此从运算放大器201正相输入端VIP到负输出端VON产生了一个大小和光敏电流IPD相等的镜像电流，使得运算放大器201的负输出端VON的电压降低。当
Figure PCTCN2016087620-appb-000005
为高电平时，全差分积分器处于反积分相位，开关S1和S4闭合，S2和S3打开，情况正好与φ相反，因此运算放大器201负输出端VON变高、正输出端VOP变低。
在保持阶段，φ、
Figure PCTCN2016087620-appb-000006
为低电平，开关S1～S4均打开，此时光敏二极管D的光敏电流IPD不流过全差分积分器，因此全差分积分器的输出保持不变。
从图7中可见，若背景光恒定不变，那么经过φ、
Figure PCTCN2016087620-appb-000007
两个相位后，背景光的影响将完全被消除。从VOP和VON可以看出背景光被消除了，在正积分相位，全差分积分器正向积分了变频后的背景光电流信号、调制光电流信号和变频后的心跳电流信号。在反积分相位，全差分积分器只反向积分了变频后的背景光电流信号。因此在反积分相位结束时，全差分积分器将电流信号转换为电压信号，全差分积分器输出只剩下调制光电压信号和调制在调制光上的心跳电压信号。
在图6所示的心跳电流信号转换装置中，负载电容CL用以限制运算放大器201的噪声带宽，假设运算放大器201的输入跨导为gm，从全差分积分器输出的阻抗大小REQ为：
Figure PCTCN2016087620-appb-000008
Figure PCTCN2016087620-appb-000009
若输出电流噪声功率谱密度为：
Figure PCTCN2016087620-appb-000010
其中k为玻尔兹曼常数，T为绝对温度，γ为工艺常数：
那么输出噪声的积分噪声电压为：
Figure PCTCN2016087620-appb-000011
其中，上述积分噪声电压公式中，df表示频率的微分，ω表示角频率，ω＝2πf；
设时钟周期为TS，除背景光电流信号外的电流信号大小为ISIG，经过一 个时钟周期后，全差分积分器的差分输出电压为：
Figure PCTCN2016087620-appb-000012
由上可见，同单端结构相比，由于噪声不变，但是经本实施例提供的转换电路后信号变大了一倍，因此全差分积分器的噪声较单端得到一倍的改善。
因为在电路的使用中，通常共模电压VCM取值为电源电压VDD的一半，因此在无其他电路对混频器的栅压进行控制的情况下，混频器开关S1～S4导通时栅极会被拉到VDD，那么开关S1～S4的栅源、栅漏电压差为VDD/2，在一些高阈值电压的工艺下，S1～S4会进入到亚阈值区，导致其导通电阻非常大。该电阻和光敏二极管D的寄生电容CPD形成了一个极点(低通特性)，会把光敏二极管D输出电流的高频成分(调制光电流信号和调制在调制光上的心跳电流信号及其谐波)滤除，使得进入到全差分积分器的信号量变小，从而影响了全差分积分器输出的信噪比。
基于上述的原因，本发明提供了如图8所述的第四实施例，在第四实施例中，除了第三实施例提供的电路外，还包括了自举电路；
所述自举电路，用于输出栅压至所述混频器中开关的栅极，使得混频器中开关的栅源电压的差值和栅漏电压的差值与电源电压值相等。
具体的自举电路如图9所示，包括第五开关S5、第六开关S6、第七开关S7、第八开关S8、第九开关S9、第一电容C1、第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4和第五MOS管M5；
第五开关S5的第一端接地，第五开关S5的第二端通过依次通过第六开关S6、第七开关S7和第八开关S8连接至第一电源V1；第六开关S6和第七开关S7之间外接共模电源VCM；第一MOS管M1的源极通过第一电容C1连接至第五开关S5和第六开关S6之间，第一MOS管M1的栅极连接至第七开关S7和第八开关S8之间，第一MOS管M1的漏极连接至栅压输出端VG；第二MOS管M2的栅极连接至第一MOS管M1的栅极，第二MOS管M2的源极通过第九开关S9接地，第二MOS管M2的漏极连接第一MOS管M1的漏极；第三MOS管M3的漏极连接第一MOS管M1的源极，第三MOS管M3的栅极连接第一MOS管M1的漏极，第三MOS管M3的源极连接第二电源V2；第四MOS管M4的源极连接第一MOS管M1的漏极，第四MOS管M4的漏极连接第三电源V3，第四MOS管M4的栅极连接第二时钟的信号输出端
Figure PCTCN2016087620-appb-000013
第五MOS管M5的源极连 接第二MOS管M2的源极，第五MOS管M5的漏极连接第四电源V4，第五MOS管M5的栅极连接第二时钟的信号输出端
Figure PCTCN2016087620-appb-000014
第五开关S5、第六开关S6、第七开关S7、第八开关S8和第九开关S9均为场效应管。
在图9中，以第五开关S5、第六开关和第一电容C1之间的连接点为A点，以第七开关S7、第八开关S8、第一MOS管的栅极和第二MOS管的栅极之间的连接点为B点，以第二MOS管与第九开关S9之间的连接点为C点，以第一电容C1、第一MOS管源极和第三MOS管漏极之间的连接点为D点来对自举电路的工作原理进行进一步地的阐述：
当第一时钟输出的φ为高电平时，开关S5、S8和S9导通，B点接电源V1、C点接地，导致第二MOS管M2将栅压输出端VG下拉到地，于是第三MOS管M3导通将D点充至电源电压，此刻第一电容C1两端的电压差为电源电压VDD。
当第二时钟输出的
Figure PCTCN2016087620-appb-000015
为高电平时，第四MOS管M4、第五MOS管M5导通，C点被拉高令第二MOS管M2关断，栅压输出端VG被拉高令第三MOS管M3关断。之后开关S2、S3导通，A、B两点接到共模电压VCM上，此时D点电压变为VDD+VCM，因此D、B两点电压差为VDD，因此第一MOS管M1导通，将D点电压充至VG。
由于全差分积分器的正相输入端VIP、反相输入端VIN的工作电压一般为二分之一电源电压VDD，所以混频器的导通阻抗非常高，将导致流入全差分积分器的电流减小，并且较大的电阻贡献较大的噪声。因此，在本实施例中采用自举电路以提高混频器开关的栅压，从而可以增加整个转换电路的信噪比。因为采用自举电路后，自举电路的栅压输出端连到混频器开关S1～S4中的栅极，使得混频器的栅源、栅漏电压差值约为电源电压VDD，从而使得混频器中开关的导通电阻大大降低，从而提高了全差分积分器输出的信噪比。
在本发明实施例提供的运算放大器均为如图3所示的折叠共源共栅结构的运算放大器，使用单级结构可以降低功耗，并且易于控制输出噪声电压。此外，由于运算放大器的有限增益将导致输出信号残留在光敏二极管的寄生结电容中，这会导致输出幅度增长速度随积分次数变多而下降，从而一起最终获得的信号量减小，信噪比降低。
本发明提供的第五实施例是在第四实施例的基础上增加一共模反馈电路；所述共模负反馈电路，用于从所述全差分积分器的正输出端和负输出端 获取反馈共模电压，根据所述反馈共模电压产生控制电压；所述控制电压用以控制所述共模负反馈电路与所述全差分积分器形成负反馈回路。
如图10所示，所述共模负反馈电路包括第二电容C2、第三电容C3、第一电阻R1、第二电阻R2、第六MOS管M6、第七MOS管M7、第八MOS管M8、第九MOS管M9和第十MOS管M10；
第二电容C2的第一端连接所述全差分积分器的正输出端VOP，第二电容C2的第二端通过第三电容C3连接至所述全差分积分器的负输出端VON；第一电阻R1的第一端连接所述全差分积分器的正输出端VOP，第一电阻R1的第二端通过第二电阻R2连接至所述全差分积分器的负输出端VON；第二电容C2的第二端与第一电阻R1的第二端相连接；第八MOS管M8的栅极连接与第一电阻R1和第二电阻R2之间，第八MOS管M8的源极连接第十MOS管M10的漏极，第八MOS管M8的漏极连接第六MOS管M6的漏极；第六MOS管M6的栅极连接第八MOS管M8的漏极，第六MOS管M6的源极接地；第七MOS管M7的源极接地，第七MOS管M7的漏极连接第九MOS管M9的漏极，第七MOS管M7的栅极连接控制电压输出端VCTRL；第九MOS管M9的漏极连接所述控制电压输出端，第九MOS管M9的栅极连接共模电源VCM，第九MOS管M9的源极连接第十MOS管M10的漏极；第十MOS管M10的源极连接第五电源V5，第十MOS管M10的栅极连接第六电源VBP。
在本实施例中，图10为图3所示运算放大器的共模反馈电路，电阻R1、电阻R2从运算放大器的正输出端VOP、负输出端VON获得反馈共模电压VCMO，通过第八MOS管M8、第九MOS管M9比较产生控制电压VCTRL来控制图3中运算放大器的电流镜负载管M14、M15。共模负反馈电路与运算放大器中的M14～M17形成负反馈，根据运放虚短可知反馈共模电压VCMO与共模电压VCM相等。图10中的电容C1、电容C2产生零点以抵消电阻R1、电阻R2和第八MOS管M8、第九MOS管M9形成的极点，使得共模负反馈的稳定性得到提升。
本发明还提供了如图11所示的第五实施例，一种心跳电流信号转换方法，包括：
S1，接收调制光信号，然后将所述调制光信号转换为电流信号；所述调制光信号包含有调制的心跳光信号；所述电流信号包括调制光电流信号、心跳电流信号和背景光电流信号；
S2，将所述心跳电流信号变频至零频，将所述背景光电流信号变频至时 钟频率；
S3，将所述调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号交替进行正积分和反积分，然后进行转换后输出调制光电压信号和心跳电压信号。
在本发明提供的第五实施例中，所述心跳电流信号转换装置将接收的所述调制光信号转换成电流信号后，通过变频、积分和转换的方式，将调制光信号中的背景光信号滤除，放大低频的心跳信号，然后输出调制光电压信号和心跳电压信号用于后续的心跳信号检测。
本发明还提供了一种心跳检测系统，包括如上述所述的心跳电流信号转换装置。在本实施例中，使用图5结构的心跳电流信号转换装置来做心跳检测系统的转换电路，能够抑制共模噪声、提高线性、增加输出摆幅、降低功耗、节约电路成本等。
综上所述，本发明实施例提供的全差分积分器能够提高心跳电流信号转换装置对共模噪声的抑制、线性度、输出动态范围。而且，由于心跳电流信号转换装置环路始终形成闭环，因此对下级电路可以直接输出，省去输出缓冲电路，从而降低功耗。同时，因为负载电容接在了全差分积分器的输出两端，因此等效负载电容可以翻倍，从而获得相同噪声带宽所需要的电容面积小了一倍。此外，本发明实施例提供心跳电流信号转换装置主要应用于心率监测应用领域，也可以用于如触摸屏等其他领域、提供标准地差分输出接口，易于后级电路的链接。
同时，本发明提供的心跳电流信号转换装置能够消除BG，实现全差分输出，达到抑制噪声的目的，而且以共模抑制，具备较大输出动态范围，而且还提供了容易后面电路接入的全差分电路接口；具有Hold的功能减少一级SH,节约输出限制带宽的电容，进一步地，使用自举电路来降低混频器由于开关电阻过大导致运放噪声变大的问题。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统和方法，可以通过其它的方式实现。例如，以上所描述的系统实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连 接，可以是电性，机械或其它的形式。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
需要说明的是，对于前述的各方法实施例，为了简便描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以采用其它顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定都是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其它实施例的相关描述。
以上为对本发明所提供的转换电路、心跳电流信号转换装置及转换方法、心跳检测系统的描述，对于本领域的技术人员，依据本发明实施例的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本发明的限制。

Claims (14)

  1. 一种转换电路，其特征在于，所述转换电路包括全差分积分器和混频器；
    所述混频器，用于将输入的电流信号进行变频，然后将得到的变频电流信号输出至所述全差分积分器；
    所述全差分积分器，用于对输入的所述变频电流信号进行积分，将积分后的所述变频电流信号进行转换后，输出电压信号。
  2. 如权利要求1所述的转换电路，其特征在于，所述全差分积分器包括运算放大器、第一反馈电容、第二反馈电容、第一复位开关和第二复位开关；
    所述第一反馈电容连接于所述运算放大器的反相输入端和正输出端之间；所述第二反馈电容连接于所述运算放大器的正相输入端和负输出端之间；所述第一复位开关的第一端连接所述运算放大器的反相输入端，所述第一复位开关的第二端连接所述运算放大器的正输出端；所述第二复位开关的第一端连接所述运算放大器的正相输入端，所述第二复位开关的第二端连接所述运算放大器的负输出端。
  3. 如权利要求2所述的转换电路，其特征在于，所述全差分积分器还包括连接于所述运算放大器的正输出端和负输出端之间的负载电容。
  4. 如权利要求1所述的转换电路，其特征在于，所述混频器包括第一开关、第二开关、第三开关和第四开关；
    所述第一开关的第一端连接外接共模电源，所述第一开关的第二端通过所述第三开关连接所述转换器；所述第二开关的第一端连接外接共模电源，所述第二开关的第二端通过所述第四开关连接所述转换器；
    所述全差分积分器的反相输入端连接于所述第一开关和所述第三开关之间，所述全差分积分器的正相输入端连接于所述第二开关和所述第四开关之间。
  5. 如权利要求4所述的转换电路，其特征在于，所述第一开关、所述第二开关、所述第三开关和所述第四开关均为场效应管。
  6. 一种心跳电流信号转换装置，其特征在于，所述心跳电流信号转换装置包括权利要求1至5任一所述的转换电路和转换器；
    所述转换器，用于将调制光信号转换为电流信号后传输至所述混频器； 所述调制光信号包含有调制的心跳光信号；
    所述混频器，用于将电流信号中的心跳电流信号变频至零频，将电流信号中的背景光电流信号变频至时钟频率，然后将电流信号中的调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号传输至所述全差分积分器；
    所述全差分积分器，用于将输入的所述调制光电流信号、所述变频后的心跳电流信号和所述变频后的背景光电流信号交替进行正积分和反积分，然后进行转换后输出调制光电压信号和心跳电压信号。
  7. 如权利要求6所述的心跳电流信号转换装置，其特征在于，所述转换器包括光敏二极管；
    所述光敏二极管的阳极接地，所述光敏二极管的阴极连接所述混频器。
  8. 如权利要求6所述的心跳电流信号转换装置，其特征在于，所述心跳电流信号转换装置还包括与所述混频器相连接的自举电路；
    所述自举电路，用于输出栅压至所述混频器中开关的栅极，使得混频器中开关的栅源电压的差值和栅漏电压的差值与电源电压值相等。
  9. 如权利要求8所述的心跳电流信号转换装置，其特征在于，所述自举电路包括第五开关、第六开关、第七开关、第八开关、第九开关、第一电容、第一MOS管、第二MOS管、第三MOS管、第四MOS管和第五MOS管；
    所述第五开关的第一端接地，所述第五开关的第二端通过依次通过所述第六开关、所述第七开关和所述第八开关连接至第一电源；所述第六开关和所述第七开关之间外接共模电源；所述第一MOS管的源极通过所述第一电容连接至所述第五开关和第六开关之间，所述第一MOS管的栅极连接至所述第七开关和第八开关之间，所述第一MOS管的漏极连接至栅压输出端；所述第二MOS管的栅极连接至所述第一MOS管的栅极，所述第二MOS管的源极通过所述第九开关接地，所述第二MOS管的漏极连接所述第一MOS管的漏极；所述第三MOS管的漏极连接所述第一MOS管的源极，所述第三MOS管的栅极连接所述第一MOS管的漏极，所述第三MOS管的源极连接第二电源；所述第四MOS管的源极连接所述第一MOS管的漏极，所述第四MOS管的漏极连接第三电源，所述第四MOS管的栅极连接第二时钟的信号输出端；所述第五MOS管的源极连接所述第二MOS管的源极，所 述第五MOS管的漏极连接第四电源，所述第五MOS管的栅极连接第二时钟的信号输出端。
  10. 如权利要求9所述的心跳电流信号转换装置，其特征在于，所述第五开关、所述第六开关、所述第七开关、所述第八开关和所述第九开关均为场效应管。
  11. 如权利要求6所述的心跳电流信号转换装置，其特征在于，所述心跳电流信号转换装置还包括与所述全差分积分器相连接的共模负反馈电路；
    所述共模负反馈电路，用于从所述全差分积分器的正输出端和负输出端获取反馈共模电压，根据所述反馈共模电压产生控制电压；所述控制电压用以控制所述共模负反馈电路与所述全差分积分器形成负反馈回路。
  12. 如权利要求11所述的心跳电流信号转换装置，其特征在于，所述共模负反馈电路包括第二电容、第三电容、第一电阻、第二电阻、第六MOS管、第七MOS管、第八MOS管、第九MOS管和第十MOS管；
    所述第二电容的第一端连接所述全差分积分器的正输出端，所述第二电容的第二端通过所述第三电容连接至所述全差分积分器的负输出端；所述第一电阻的第一端连接所述全差分积分器的正输出端，所述第一电阻的第二端通过所述第二电阻连接至所述全差分积分器的负输出端；所述第二电容的第二端与所述第一电阻的第二端相连接；所述第八MOS管的栅极连接与所述第一电阻和所述第二电阻之间，所述第八MOS管的源极连接所述第十MOS管的漏极，所述第八MOS管的漏极连接所述第六MOS管的漏极；所述第六MOS管的栅极连接所述第八MOS管的漏极，所述第六MOS管的源极接地；所述第七MOS管的源极接地，所述第七MOS管的漏极连接所述第九MOS管的漏极，所述第七MOS管的栅极连接控制电压输出端；所述第九MOS管的漏极连接所述控制电压输出端，所述第九MOS管的栅极连接共模电源，所述第九MOS管的源极连接所述第十MOS管的漏极；所述第十MOS管的源极连接第五电源，所述第十MOS管的栅极连接第六电源。
  13. 一种心跳电流信号转换方法，其特征在于，包括：
    接收调制光信号，然后将所述调制光信号转换为电流信号；所述调制光信号包含有调制的心跳光信号；所述电流信号包括调制光电流信号、心跳电流信号和背景光电流信号；
    将所述心跳电流信号变频至零频，将所述背景光电流信号变频至时钟频 率；
    将所述调制光电流信号、变频后的心跳电流信号和变频后的背景光电流信号交替进行正积分和反积分，然后进行转换后输出调制光电压信号和心跳电压信号。
  14. 一种心跳检测系统，其特征在于，所述心跳检测系统包括权利要求6至12任一所述的心跳电流信号转换装置。
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