WO2017161625A1 - Tft基板的制作方法及制得的tft基板 - Google Patents

Tft基板的制作方法及制得的tft基板 Download PDF

Info

Publication number
WO2017161625A1
WO2017161625A1 PCT/CN2016/080189 CN2016080189W WO2017161625A1 WO 2017161625 A1 WO2017161625 A1 WO 2017161625A1 CN 2016080189 W CN2016080189 W CN 2016080189W WO 2017161625 A1 WO2017161625 A1 WO 2017161625A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
source
drain
contact
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/080189
Other languages
English (en)
French (fr)
Inventor
迟世鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/105,572 priority Critical patent/US10038074B2/en
Publication of WO2017161625A1 publication Critical patent/WO2017161625A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a TFT substrate produced.
  • OLED is a promising flat panel display technology, which has excellent display performance, especially self-illumination, simple structure, ultra-thin, fast response, wide viewing angle, low power consumption and flexible display.
  • OLED has been on the eve of mass production. With the further development of research and the emergence of new technologies, OLED display devices will have a breakthrough development.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • AMOLED is gradually maturing. In AMOLED, it is required to drive with current.
  • Low temperature Poly-Silicon (LTPS) has a large mobility, and a thin film transistor (Thin Film Transistor) is used as an active layer. , TFT) can meet the current drive mode of AMOLED.
  • Low-temperature polysilicon thin film transistors (LTPS TFTs) have higher mobility and can obtain higher on-state currents.
  • LTPS TFTs will have a high off state when they are off.
  • Current In order to reduce the off-state current of the LTPS TFT, a Lightly Doped Offset structure can be employed. The Offset structure has been studied more, but the offset structure forming a high-resistance region will reduce the on-state current of the LTPS TFT. In order to obtain a higher on-state current, the offset structure can be improved.
  • an overlap structure may be added in the TFT, that is, the source electrode or the drain electrode and the gate electrode have overlapping regions, which may reduce the channel. The length and the area of the high resistance are reduced, which in turn increases the on-state current.
  • the source or drain electrodes are in an offset and overlap configuration, respectively, which can achieve a smaller off-state current, while the on-state current is less affected.
  • the asymmetry of the TFT structure is caused. In the actual operation of the TFT, when the source or drain electrodes are interchanged, the asymmetry of the device may affect the flow. The current of the device.
  • An object of the present invention is to provide a method for fabricating a TFT substrate by designing a gate, a source or a drain as a U-shaped structure such that a current in the TFT is from a drain to a source or from a source to a drain.
  • the path needs to pass two offset structures and two overlap structures, which can not only reduce the off-state current, but also improve the on-state current, and the current path also has symmetry, which avoids the influence of device structure asymmetry on the current path in the LTPS TFT.
  • the on-state current is increased, and the current path is also symmetrical, which avoids the influence of device structure asymmetry on the current path in the LTPS TFT and improves the electrical performance of the TFT device.
  • the present invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, forming a gate on the substrate, the gate being a U-shaped structure, including a first vertical portion, a second vertical portion, and a corresponding end portion connecting the first and second vertical portions Horizontal connection
  • Step 2 depositing a gate insulating layer on the gate and the substrate, depositing amorphous silicon on the gate insulating layer, obtaining an amorphous silicon film, and converting the amorphous silicon film into polysilicon by a low temperature crystallization process a film, the polysilicon film is patterned by using a mask to obtain an active layer;
  • Step 3 performing ion light doping on the entire active layer; performing ion heavy doping on a portion of the active layer, forming a drain contact region corresponding to the partial region, and two respectively located in the drain contact region a first source contact region and a second source contact region at a distance from the side;
  • the left side of the drain contact region overlaps with a right portion of the first vertical portion of the gate; the left side of the second source contact region and the second vertical portion of the gate The right side of the overlap;
  • a region of the active layer between a right edge of the first source contact region and a left edge of the first vertical portion of the gate forms a first lightly doped compensation region
  • a region between a left edge of the first vertical portion of the gate and a left edge of the drain contact region forms a first channel region
  • a right edge of the drain contact region and the gate a region between the left edge of the second vertical portion forms a second lightly doped compensation region on the left side of the second vertical portion of the gate a region between the edge and a left edge of the second source contact region forms a second channel region;
  • Step 4 forming a first source, a second source, and a drain on the active layer corresponding to the positions of the first source contact region, the second source contact region, and the drain contact region, respectively.
  • a first overlap region is formed between a left side of the drain and a right side of the first vertical portion of the gate, and a left side of the second source and a right side of the second vertical portion of the gate Forming a second overlap region between the sides;
  • Step 5 depositing a passivation protective layer on the first source, the second source, the drain, the active layer, and the gate insulating layer, and patterning the passivation protective layer by using a photomask Forming a first through hole, a second through hole, and a third through hole respectively corresponding to the first source, the second source, and the drain;
  • Step 6 depositing a conductive layer on the passivation protective layer, and patterning the conductive layer by using a photomask to obtain a first contact electrode, a second contact electrode, a third contact electrode, and a connecting wire.
  • the first and second contact electrodes are respectively in contact with the first and second sources via the first and second via holes, and the third contact electrode is in contact with the drain via the third via hole;
  • the connecting wire connects the first and second contact electrodes together, since the first and second contact electrodes are respectively connected to the first and second source, thereby the first and second The sources are connected together to form a U-shaped source, thereby producing a TFT substrate.
  • the first channel region and the second channel region have the same width
  • the first lightly doped compensation region and the second lightly doped compensation region have the same width
  • the first overlap region and the second overlap region The width is equal.
  • the entire active layer is lightly doped with N-type ions, and the active layer is performed corresponding to the positions of the first source contact region, the second source contact region, and the drain contact region.
  • P-type ions are heavily doped; or, the entire active layer is lightly doped with P-type ions, corresponding to the positions of the first source contact region, the second source contact region, and the drain contact region
  • the source layer is heavily doped with N-type ions.
  • the gate is prepared by depositing a metal layer on a substrate, patterning the metal layer with a photomask to obtain a gate electrode, or: forming a polysilicon layer on the substrate, and performing the polysilicon layer on the substrate After the N-type doping, the N-type doped polysilicon layer is patterned by using a photomask to obtain a gate;
  • the first source, the second source, and the drain are prepared by depositing a metal layer on the active layer and the gate insulating layer, and patterning the metal layer by using a photomask to obtain a first a source, a second source, and a drain; or: forming a polysilicon layer on the active layer and the gate insulating layer, performing N-type doping on the polysilicon layer, using a mask to N-type doping
  • the heteropolysilicon layer is patterned to obtain a first source, a second source, and a drain.
  • the materials of the first, second, and third contact electrodes and the connecting wires are all transparent conductive metal oxides.
  • the present invention also provides a TFT substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active device disposed on the gate insulating layer a first source, a second source, and a drain disposed on the active layer, and the first source, the second source, the drain, the active layer, and the gate insulating layer a passivation protective layer on the layer, and first contact electrodes, second contact electrodes, third contact electrodes, and connecting wires disposed on the passivation protective layer;
  • the gate is a U-shaped structure, including a first vertical portion, a second vertical portion, and a lateral connecting portion connecting the corresponding ends of the first and second vertical portions;
  • the active layer is provided with a drain contact region and a first source contact region and a second source contact region respectively spaced apart from and spaced apart from the drain contact region;
  • a region of the active layer between a right edge of the first source contact region and a left edge of the first vertical portion of the gate forms a first lightly doped compensation region
  • a region between a left edge of the first vertical portion of the gate and a left edge of the drain contact region forms a first channel region
  • a right edge of the drain contact region and the gate a region between the left edge of the second vertical portion forms a second lightly doped compensation region
  • a left side edge of the second vertical portion of the gate and a left side of the second source contact region a region between the edges forms a second channel region
  • the first source, the second source, and the drain respectively are disposed on the active layer corresponding to the first source contact region, the second source contact region, and the drain contact region; and the drain Forming a first overlap region between the left side and the right side of the first vertical portion of the gate, and forming a left overlap between the left side of the second source and the right side of the second vertical portion of the gate Second overlapping area;
  • the passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the first source, the second source, and the drain, and the first and the
  • the two contact electrodes are respectively in contact with the first and second sources via the first and second via holes, and the third contact electrode is in contact with the drain via the third via hole; the first contact electrode and the second contact
  • the electrodes are connected together by connecting wires to connect the first and second sources together to form a U-shaped source.
  • the first channel region and the second channel region have the same width
  • the first lightly doped compensation region and the second lightly doped compensation region have the same width
  • the first overlap region and the second overlap region The width is equal.
  • the first source contact region, the second source contact region, and the drain contact region are N-type heavily doped regions, the first lightly doped compensation region, the second lightly doped compensation region, and the first channel The region and the second channel region are P-type lightly doped regions; or the first source contact region, the second source contact region, and the drain contact region are P-type heavily doped regions, the first The lightly doped compensation region, the second lightly doped compensation region, the first channel region, and the second channel region are N-type lightly doped regions.
  • the gate, the first source, the second source, and the drain are a metal layer or an N-type doped polysilicon layer.
  • the materials of the first, second, and third contact electrodes and the connecting wires are all transparent conductive metal oxides.
  • the present invention also provides a TFT substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active device disposed on the gate insulating layer a first source, a second source, and a drain disposed on the active layer, and the first source, the second source, the drain, the active layer, and the gate insulating layer a passivation protective layer on the layer, and first contact electrodes, second contact electrodes, third contact electrodes, and connecting wires disposed on the passivation protective layer;
  • the gate is a U-shaped structure, including a first vertical portion, a second vertical portion, and a lateral connecting portion connecting the corresponding ends of the first and second vertical portions;
  • the active layer is provided with a drain contact region and a first source contact region and a second source contact region respectively spaced apart from and spaced apart from the drain contact region;
  • a region of the active layer between a right edge of the first source contact region and a left edge of the first vertical portion of the gate forms a first lightly doped compensation region
  • a region between a left edge of the first vertical portion of the gate and a left edge of the drain contact region forms a first channel region
  • a right edge of the drain contact region and the gate a region between the left edge of the second vertical portion forms a second lightly doped compensation region
  • a left side edge of the second vertical portion of the gate and a left side of the second source contact region a region between the edges forms a second channel region
  • the first source, the second source, and the drain respectively are disposed on the active layer corresponding to the first source contact region, the second source contact region, and the drain contact region; and the drain Forming a first overlap region between the left side and the right side of the first vertical portion of the gate, and forming a left overlap between the left side of the second source and the right side of the second vertical portion of the gate Second overlapping area;
  • the passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the first source, the second source, and the drain, and the first and the
  • the two contact electrodes are respectively in contact with the first and second sources via the first and second via holes, and the third contact electrode is in contact with the drain via the third via hole;
  • the first contact electrode and the second contact The electrodes are connected together by connecting wires, thereby connecting the first and second sources together to form a U-shaped source;
  • first channel region and the second channel region have the same width
  • first lightly doped compensation region and the second lightly doped compensation region have the same width
  • first overlap region and the second overlap The width of the area is equal
  • the first source contact region, the second source contact region, and the drain contact region are N-type heavily doped regions, the first lightly doped compensation region, the second lightly doped compensation region, and the first The channel region and the second channel region are P-type lightly doped regions; or the first source contact region, the second source contact region, and the drain contact region are P-type heavily doped regions, a first lightly doped compensation zone, a second lightly doped compensation zone, The first channel region and the second channel region are N-type lightly doped regions.
  • the present invention provides a method of fabricating a TFT substrate by disposing a first channel region and a first lightly doped compensation region between a first source and a drain, and at a second source A second channel region and a second lightly doped compensation region are disposed between the drains, and the drain and the second source respectively form a first overlap region and a second overlap region with the gate, thereby
  • the current flowing from the first source and the second source to the drain is the same as the path through which the current flows from the drain to the first and second sources, that is, the current path from the source to the drain and from the drain to the source.
  • the current from the drain to the source or from the source to the drain of the TFT needs to pass through two offset structures and two overlap structures, which can not only reduce the off-state current but also improve the on-state.
  • the current and the current path have symmetry, which avoids the influence of device structure asymmetry on the current path in the LTPS TFT and improves the electrical performance of the TFT device.
  • FIG. 1 is a flow chart showing a method of fabricating a TFT substrate of the present invention
  • 2-3 is a schematic view showing the first step of the method for fabricating the TFT substrate of the present invention.
  • 4-5 is a schematic view showing the step 3 of the method for fabricating the TFT substrate of the present invention.
  • 6-7 is a schematic view showing a step 4 of a method of fabricating a TFT substrate of the present invention.
  • FIG 8-9 are schematic views showing the step 6 of the method of fabricating the TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a current direction when a source is extremely high in a TFT substrate produced by the present invention
  • FIG. 11 is a schematic view showing the current direction when the drain of the TFT substrate produced by the present invention is at a high voltage.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 as shown in FIG. 2-3, a substrate 10 is provided, and a gate electrode 20 is formed on the substrate 10.
  • the gate 20 is a U-shaped structure including a first vertical portion 21, a second vertical portion 22, and a lateral connecting portion 23 connecting the corresponding ends of the first and second vertical portions 21, 22.
  • the method for preparing the gate electrode 20 may be: by depositing a metal layer on the substrate 10, and patterning the metal layer by using a photomask to obtain the gate electrode 20.
  • the material of the metal layer is a metal material such as aluminum (Al), molybdenum (Mo), copper (Cu), or silver (Ag).
  • the method for preparing the gate electrode 20 may be: forming a polysilicon layer on the substrate 10, performing N-type doping on the polysilicon layer, and then patterning the N-type doped polysilicon layer by using a mask. , the gate 20 is obtained.
  • Step 2 referring to FIG. 4, a gate insulating layer 30 is deposited on the gate electrode 20 and the substrate 10, and amorphous silicon is deposited on the gate insulating layer 30 to obtain an amorphous silicon film, which is processed by a low temperature crystallization process.
  • the amorphous silicon film is converted into a polysilicon film, and the polysilicon film is patterned by using a photomask to obtain an active layer 40.
  • the gate insulating layer 30 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the low temperature crystallization process is preferably a solid phase crystallization (SPC) method.
  • SPC solid phase crystallization
  • Step 3 as shown in FIG. 4-5, the entire active layer 40 is ionically lightly doped; a portion of the active layer 40 is ion heavily doped, and a portion of the region is formed with a drain contact region 47. And a first source contact region 45 and a second source contact region 46 respectively located on opposite sides of the drain contact region 47 and spaced apart therefrom;
  • the left side of the drain contact region 47 overlaps with the right side portion of the first vertical portion 21 of the gate 20; the left side of the second source contact region 46 and the gate 20 The right side portions of the second vertical portion 22 overlap;
  • a region on the active layer 40 between a right edge of the first source contact region 45 and a left edge of the first vertical portion 21 of the gate 20 forms a first light doping compensation (a lightly doped offset region 43 in which a region between a left edge of the first vertical portion 21 of the gate 20 and a left edge of the drain contact region 47 forms a first channel region 41, located at A region between the right edge of the drain contact region 47 and the left edge of the second vertical portion 22 of the gate 20 forms a second lightly doped compensation region 44 at the second of the gate 20 A region between the left edge of the vertical portion 22 and the left edge of the second source contact region 46 forms a second channel region 42.
  • a first light doping compensation a lightly doped offset region 43 in which a region between a left edge of the first vertical portion 21 of the gate 20 and a left edge of the drain contact region 47 forms a first channel region 41, located at A region between the right edge of the drain contact region 47 and the left edge of the second vertical portion 22 of the gate 20 forms a second lightly do
  • first channel region 41 and the second channel region 42 have the same width
  • first lightly doped compensation region 43 and the second lightly doped compensation region 44 have the same width
  • the N-type ion is lightly doped to the entire active layer 40, corresponding to The positions of the first source contact region 45, the second source contact region 46, and the drain contact region 47 are P-type ion heavily doped to the active layer 40; or, the entire active layer 40 is performed.
  • the P-type ions are lightly doped, and the active layer 40 is heavily doped with N-type ions corresponding to the positions of the first source contact region 45, the second source contact region 46, and the drain contact region 47;
  • the N-type ions are phosphorus ions or arsenic ions; and the P-type ions are boron ions or gallium ions.
  • Step 4 as shown in FIG. 6-7, forming a first source on the active layer 40 corresponding to the positions of the first source contact region 45, the second source contact region 46, and the drain contact region 47, respectively.
  • 51, a second source 52, and a drain 53, and a first overlap region 510 is formed between a left side of the drain 53 and a right side of the first vertical portion 21 of the gate 20.
  • a second overlap region 520 is formed between the left side of the second source 52 and the right side of the second vertical portion 21 of the gate 20.
  • the widths of the first overlap region 510 and the second overlap region 520 are equal.
  • the first source 51, the second source 52, and the drain 53 may be prepared by depositing a metal layer on the active layer 40 and the gate insulating layer 30 by using a mask.
  • the metal layer is patterned to obtain a first source 51, a second source 52, and a drain 53.
  • the material of the metal layer is a metal material such as aluminum (Al), molybdenum (Mo), copper (Cu), or silver (Ag).
  • the first source 51, the second source 52, and the drain 53 may be prepared by forming a polysilicon layer on the active layer 40 and the gate insulating layer 30. After the N-type doping, the N-type doped polysilicon layer is patterned by using a photomask to obtain a first source 51, a second source 52, and a drain 53.
  • the first lightly doped compensation region 43 and the second lightly doped compensation region 44 form a high resistance region, which can reduce the off current of the LTPS TFT.
  • the first overlap region 510 and the second overlap region 520 can reduce the channel length of the LTPS TFT and reduce the high resistance region, thereby increasing the on-state current.
  • Step 5 referring to FIG. 8, depositing a passivation protective layer 60 on the first source 51, the second source 52, the drain 53, the active layer 40, and the gate insulating layer 30, using a mask
  • the passivation protection layer 60 is patterned to form a first via hole 61, a second via hole 62, and a third portion corresponding to the first source 51, the second source 52, and the drain 53 respectively.
  • Through hole 63 Through hole 63.
  • the passivation protective layer 60 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • Step 6 as shown in FIG. 8, a conductive layer is deposited on the passivation protective layer 60, and the conductive layer is patterned by using a photomask to obtain a first contact electrode 71, a second contact electrode 72, and a third contact electrode 73 and a connecting wire 80, wherein the first and second contact electrodes 71 and 72 are in contact with the first and second source electrodes 51 and 52 via the first and second through holes 61 and 62, respectively.
  • the third contact electrode 73 is in contact with the drain electrode 53 via the third via hole 63;
  • the connecting wire 80 connects the first and second contact electrodes 71, 72 together, since the first and second contact electrodes 71, 72 are respectively associated with the first and second
  • the sources 51, 52 are connected to connect the first and second sources 51, 52 together to form a U-shaped source 90, thereby producing a TFT substrate.
  • the materials of the first, second, and third contact electrodes 71, 72, and 73 and the connecting wires 80 are all transparent conductive metal oxides, preferably ITO (indium tin oxide).
  • one of the uses of the first, second, and third contact electrodes 71, 72, and 73 is to connect the first and second source electrodes 51, 52, and the drain electrode 53 to the data line as a lead.
  • the second purpose is to test the voltage signals of the first source 51, the second source 52, and the drain 53 as test sites.
  • the current flowing from the source 90 to the drain 53 includes two branch currents, which are respectively flowing from the first source 51 to the drain 53. a branch current and a second branch current flowing from the second source 52 to the drain 53, wherein the first branch current flows through the first lightly doped compensation region 43, the first channel region 41, and the first overlap a region 510, the second branch current flows through the second overlap region 520, the second channel region 42, and the second lightly doped compensation region 44;
  • the current flowing from the drain 53 to the source 90 includes two branch currents, respectively flowing from the drain 53 to the first source. a third branch current of the pole 51 and a fourth branch current flowing from the drain 53 to the second source 52, wherein the third branch current flows through the first overlap region 510, the first channel region 41, and the first Lightly doping compensation region 43, the second branch current flows through the second lightly doped compensation region 44, the second channel region 42, and the second overlap region 520;
  • the widths of the first channel region 41 and the second channel region 42 are equal, the first lightly doped compensation region 43 and the second lightly doped compensation region 44 have the same width, and the first overlap region 510 The width of the second overlap region 520 is equal, so the path of the two branch currents flowing from the source 90 to the drain 53 is substantially the same as the path of the two branch currents flowing from the drain 53 to the source 90, thereby ensuring the TFT device.
  • the symmetry of the drain 53 and the source 90 in practical operation does not affect the current flowing through the TFT device.
  • a first channel region 41 and a first lightly doped compensation region 43 are disposed between the first source 51 and the drain 53 to be disposed between the second source 52 and the drain 53.
  • a second channel region 42 and a second lightly doped compensation region 44, and the drain region 53 and the second source electrode 52 respectively form a first overlap region 510 and a second overlap region 520 with the gate electrode 20, Therefore, the current flowing from the first and second sources 51, 52 to the drain 53 flows from the drain 53 to the first and second sources 51,
  • the path of the current of 52 is the same, that is, the current path from the source 90 to the drain 53 and the drain 53 to the source 90 are the same, thereby realizing the symmetry of the TFT structure, and in actual operation, the drain 53 is
  • the use of the source 90 interchangeably does not affect the current flowing through the TFT device, improving the electrical performance of the TFT device.
  • the present invention further provides a TFT substrate, including a substrate 10, a gate electrode 20 disposed on the substrate 10, and the gate electrode 20 and the substrate 10.
  • the gate 20 is a U-shaped structure, including a first vertical portion 21, a second vertical portion 22, and a lateral connecting portion 23 connecting the corresponding ends of the first and second vertical portions 21, 22;
  • the active layer 40 is provided with a drain contact region 47 and a first source contact region 45 and a second source contact region 46 respectively located at two sides of the drain contact region 47 and spaced apart therefrom;
  • a region on the active layer 40 between a right edge of the first source contact region 45 and a left edge of the first vertical portion 21 of the gate 20 forms a first light doping compensation (a lightly doped offset region 43 in which a region between a left edge of the first vertical portion 21 of the gate 20 and a left edge of the drain contact region 47 forms a first channel region 41, located at A region between the right edge of the drain contact region 47 and the left edge of the second vertical portion 22 of the gate 20 forms a second lightly doped compensation region 44 at the second of the gate 20 A region between the left edge of the vertical portion 22 and the left edge of the second source contact region 46 forms a second channel region 42.
  • a first light doping compensation a lightly doped offset region 43 in which a region between a left edge of the first vertical portion 21 of the gate 20 and a left edge of the drain contact region 47 forms a first channel region 41, located at A region between the right edge of the drain contact region 47 and the left edge of the second vertical portion 22 of the gate 20 forms a second lightly do
  • the first source 51, the second source 52, and the drain 53 are respectively disposed on the active layer 40 corresponding to the first source contact region 45, the second source contact region 46, and the drain contact region 47. And forming a first overlap region 510 between the left side of the drain 53 and the right side of the first vertical portion 21 of the gate 20, the left side of the second source 52 a second overlap region 520 is formed between the right side of the second vertical portion 21 of the gate 20;
  • the passivation protective layer 60 is provided with a first through hole 61, a second through hole 62, and a third through hole 63 respectively corresponding to the first source 51, the second source 52, and the drain 53.
  • the first and second contact electrodes 71, 72 are in contact with the first and second sources 51, 52 via the first and second through holes 61, 62, respectively, and the third contact electrode 73 is connected to the third through
  • the hole 63 is in contact with the drain electrode 53; the first contact electrode 71 and the second contact electrode 72 are connected together by a connecting wire 80, thereby connecting the first and second source electrodes 51, 52 together to form a hole U-shaped source 90.
  • the first lightly doped compensation region 43 and the second lightly doped compensation region 44 form a high resistance. Zone, which can reduce the off-state current of the LTPS TFT.
  • the first overlap region 510 and the second overlap region 520 can reduce the channel length of the LTPS TFT and reduce the high resistance region, thereby increasing the on-state current.
  • the first channel region 41 and the second channel region 42 have the same width, and the first lightly doped compensation region 43 and the second lightly doped compensation region 44 have the same width, the first overlap.
  • the width of the region 510 and the second overlap region 520 are equal.
  • the gate 20, the first source 51, the second source 52, and the drain 53 may be a metal layer or an N-type doped polysilicon layer.
  • the material of the metal layer is a metal material such as aluminum (Al), molybdenum (Mo), copper (Cu), or silver (Ag).
  • the first source contact region 45, the second source contact region 46, and the drain contact region 47 are N-type heavily doped regions, the first lightly doped compensation region 43, and the second lightly doped region.
  • the compensation region 44, the first channel region 41, and the second channel region 42 are P-type lightly doped regions; or, the first source contact region 45, the second source contact region 46, and the drain contact region 47 is a P-type heavily doped region, and the first lightly doped compensation region 43, the second lightly doped compensation region 44, the first channel region 41, and the second channel region 42 are N-type lightly doped regions.
  • the ions doped in the N-type doping region are phosphorus ions or arsenic ions; and the ions doped in the P-type doping region are boron ions or gallium ions.
  • the gate insulating layer 30 and the passivation protective layer 60 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer. .
  • the materials of the first, second, and third contact electrodes 71, 72, and 73 and the connecting wires 80 are all transparent conductive metal oxides, preferably ITO (indium tin oxide).
  • one of the uses of the first, second, and third contact electrodes 71, 72, and 73 is to connect the first and second source electrodes 51, 52, and the drain electrode 53 to the data line as a lead.
  • the second purpose is to test the voltage signals of the first source 51, the second source 52, and the drain 53 as test sites.
  • a first channel region 41 and a first lightly doped compensation region 43 are disposed between the first source 51 and the drain 53, and a second channel is disposed between the second source 52 and the drain 53.
  • a region 42 and a second lightly doped compensation region 44, and the drain region 53 and the second source electrode 52 respectively form a first overlap region 510 and a second overlap region 520 with the gate electrode 20, thereby enabling 1.
  • the current flowing from the second source 51, 52 to the drain 53 is the same as the path through which the current flowing from the drain 53 to the first and second sources 51, 52 passes, that is, from the source 90 to the drain 53 and from
  • the current paths of the drain 53 to the source 90 are the same, thereby realizing the symmetry of the TFT structure. In practical operation, the use of the drain 53 and the source 90 is not affected, and the current flowing through the TFT device is not affected, and the TFT is improved.
  • the electrical properties of the device are not affected, and the current flowing through the TFT device is not affected, and the TFT
  • the present invention provides a method for fabricating a TFT substrate by disposing a first channel region and a first lightly doped compensation region between the first source and the drain, and at the second source and drain. Between the poles Providing a second channel region and a second lightly doped compensation region, and the drain and the second source respectively form a first overlap region and a second overlap region with the gate, thereby The current flowing from the second source to the drain is the same as the path through which the current flows from the drain to the first and second sources, that is, the current path from the source to the drain and the drain to the source are the same, thereby realizing The symmetry of the TFT structure, in the actual work of the use of the drain and source interchange does not affect the current flowing through the TFT device, improving the electrical performance of the TFT device.
  • the current from the drain to the source or from the source to the drain of the TFT needs to pass through two offset structures and two overlap structures, which can not only reduce the off-state current but also improve the on-state.
  • the current and the current path have symmetry, which avoids the influence of device structure asymmetry on the current path in the LTPS TFT and improves the electrical performance of the TFT device.

Landscapes

  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一种TFT基板的制作方法及制得的TFT基板，通过在第一源极(51)与漏极(53)之间设置第一沟道区(41)与第一轻掺杂补偿区(43)，在第二源极(52)与漏极(53)之间设置第二沟道区(42)与第二轻掺杂补偿区(44)，且该漏极(53)和第二源极(52)分别与栅极(20)之间形成第一重叠区(510)和第二重叠区(520)，从而使得从第一、第二源极(51、52)流向漏极(53)的电流与从漏极(53)流向第一、第二源极(51、52)的电流所经过的路径相同，即从源极(90)到漏极(53)与从漏极(53)到源极(90)的电流路径相同，从而实现了TFT结构的对称性，在实际工作中将漏极(53)与源极(90)互换使用也不会影响流过TFT器件的电流，提升了TFT器件的电学性能。

Description

TFT基板的制作方法及制得的TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及制得的TFT基板。
背景技术
OLED是一种极具发展前景的平板显示技术，它具有十分优异的显示性能，特别是自发光、结构简单、超轻薄、响应速度快、宽视角、低功耗及可实现柔性显示等特性，被誉为“梦幻显示器”，再加上其生产设备投资远小于TFT-LCD，得到了各大显示器厂家的青睐，已成为显示技术领域中第三代显示器件的主力军。目前OLED已处于大规模量产的前夜，随着研究的进一步深入，新技术的不断涌现，OLED显示器件必将有一个突破性的发展。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
目前，AMOLED正在逐步走向成熟，在AMOLED中，需要以电流作为驱动，低温多晶硅(Low Temperature Poly-Silicon，LTPS)具有较大的迁移率，以其为有源层制作的薄膜晶体管(Thin Film Transistor，TFT)可以满足AMOLED的电流驱动模式。低温多晶硅薄膜晶体管(LTPS TFT)具有较高的迁移率，可以得到比较高的开态电流，但是由于LTPS中晶粒存在造成的缺陷，会导致LTPS TFT在关态时会出现较高的关态电流。为了减小LTPS TFT的关态电流，可以采用轻掺杂补偿(Lightly Doped Offset)结构。Offset结构目前已被研究的较多，但是offset结构形成高阻区会降低LTPS TFT的开态电流，为了获得较高的开态电流，可以对offset结构进行改进。
在具有offset结构的LTPS TFT中，为了减小高阻区对开态电流的影响，可以在TFT中增加重叠(overlap)结构，即源电极或漏电极与栅电极存在重叠区域，可以降低沟道长度和减小高阻区域，进而会提高开态电流。在LTPS TFT中，源电极或者漏电极分别采用offset和overlap结构，可以实现较小的关态电流，同时开态电流受到影响较小。但是，在一个LTPS TFT 中，在源电极和漏电极分别采用offset和overlap结构时，会导致TFT结构出现不对称性，TFT在实际工作中，源电极或者漏电极互换时会因器件的不对称性而影响流过器件的电流。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，通过将栅极、以及源极或漏极设计为U形结构，使得TFT中的电流从漏极到源极或者从源极到漏极的通路均需通过两个offset结构与两个overlap结构，不仅可以降低关态电流，提高开态电流，而且电流通路还具有对称性，避免了器件结构不对称对LTPS TFT中电流通路的影响，提升了TFT器件的电学性能。
本发明的目的还在于提供一种TFT基板，TFT中的电流从漏极到源极或者从源极到漏极的通路均需通过两个offset结构与两个overlap结构，不仅可以降低关态电流，提高开态电流，而且电流通路还具有对称性，避免了器件结构不对称对LTPS TFT中电流通路的影响，提升了TFT器件的电学性能。
为实现上述目的，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上形成栅极，所述栅极为U形结构，包括第一竖直部、第二竖直部、以及连接第一与第二竖直部对应端部的横向连接部；
步骤2、在所述栅极及基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅，得到非晶硅薄膜，采用低温结晶工艺将所述非晶硅薄膜转化为多晶硅薄膜，采用一道光罩对所述多晶硅薄膜进行图形化处理，得到有源层；
步骤3、对整个有源层进行离子轻掺杂；对所述有源层上的部分区域进行离子重掺杂，对应该部分区域形成漏极接触区以及分别位于所述漏极接触区的两侧且与其间隔一定距离的第一源极接触区与第二源极接触区；
其中，所述漏极接触区的左侧与所述栅极的第一竖直部的右侧部分重叠；所述第二源极接触区的左侧与所述栅极的第二竖直部的右侧部分重叠；
所述有源层上位于所述第一源极接触区的右侧边缘与所述栅极的第一竖直部的左侧边缘之间的区域形成第一轻掺杂补偿区，位于所述栅极的第一竖直部的左侧边缘与所述漏极接触区的左侧边缘之间的区域形成第一沟道区，位于所述漏极接触区的右侧边缘与所述栅极的第二竖直部的左侧边缘之间的区域形成第二轻掺杂补偿区，位于所述栅极的第二竖直部的左侧 边缘与所述第二源极接触区的左侧边缘之间的区域形成第二沟道区；
步骤4、在所述有源层上分别对应第一源极接触区、第二源极接触区、及漏极接触区的位置形成第一源极、第二源极、及漏极，且所述漏极的左侧与所述栅极的第一竖直部的右侧之间形成第一重叠区，所述第二源极的左侧与所述栅极的第二竖直部的右侧之间形成第二重叠区；
步骤5、在所述第一源极、第二源极、漏极、有源层、及栅极绝缘层上沉积钝化保护层，采用一道光罩对所述钝化保护层进行图形化处理，分别对应于所述第一源极、第二源极、漏极上方形成第一通孔、第二通孔、及第三通孔；
步骤6、在所述钝化保护层上沉积导电层，采用一道光罩对所述导电层进行图形化处理，得到第一接触电极、第二接触电极、第三接触电极、及连接导线，所述第一、第二接触电极分别经由第一、第二通孔与第一、第二源极相接触，所述第三接触电极经由第三通孔与漏极相接触；
所述连接导线将所述第一与第二接触电极连接在一起，由于所述第一、第二接触电极分别与所述第一、第二源极相连，从而将所述第一、第二源极连接在一起，形成一U形的源极，从而制得一TFT基板。
所述第一沟道区与第二沟道区的宽度相等，所述第一轻掺杂补偿区与第二轻掺杂补偿区的宽度相等，所述第一重叠区和第二重叠区的宽度相等。
所述步骤3中，对整个有源层进行N型离子轻掺杂，对应所述第一源极接触区、第二源极接触区、及漏极接触区的位置对所述有源层进行P型离子重掺杂；或者，对整个有源层进行P型离子轻掺杂，对应所述第一源极接触区、第二源极接触区、及漏极接触区的位置对所述有源层进行N型离子重掺杂。
所述栅极的制备方法为：通过在基板上沉积金属层，采用一道光罩对该金属层进行图形化处理，得到栅极；或者为：通过在基板上形成多晶硅层，对该多晶硅层进行N型掺杂后，采用一道光罩对N型掺杂多晶硅层进行图形化处理，得到栅极；
所述第一源极、第二源极、及漏极的制备方法为：通过在有源层及栅极绝缘层上沉积金属层，采用一道光罩对该金属层进行图形化处理，得到第一源极、第二源极、及漏极；或者为：通过在有源层及栅极绝缘层上形成多晶硅层，对该多晶硅层进行N型掺杂后，采用一道光罩对N型掺杂多晶硅层进行图形化处理，得到第一源极、第二源极、及漏极。
所述第一、第二、第三接触电极、及连接导线的材料均为透明导电金属氧化物。
本发明还提供一种TFT基板，包括一基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上的第一源极、第二源极、及漏极、设于所述第一源极、第二源极、漏极、有源层、及栅极绝缘层上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、第三接触电极、及连接导线；
所述栅极为U形结构，包括第一竖直部、第二竖直部、以及连接第一与第二竖直部对应端部的横向连接部；
所述有源层上设有漏极接触区以及分别位于所述漏极接触区两侧且与其间隔一定距离的第一源极接触区与第二源极接触区；
所述有源层上位于所述第一源极接触区的右侧边缘与所述栅极的第一竖直部的左侧边缘之间的区域形成第一轻掺杂补偿区，位于所述栅极的第一竖直部的左侧边缘与所述漏极接触区的左侧边缘之间的区域形成第一沟道区，位于所述漏极接触区的右侧边缘与所述栅极的第二竖直部的左侧边缘之间的区域形成第二轻掺杂补偿区，位于所述栅极的第二竖直部的左侧边缘与所述第二源极接触区的左侧边缘之间的区域形成第二沟道区；
所述第一源极、第二源极、及漏极分别对应第一源极接触区、第二源极接触区、漏极接触区设于所述有源层上；且所述漏极的左侧与所述栅极的第一竖直部的右侧之间形成第一重叠区，所述第二源极的左侧与所述栅极的第二竖直部的右侧之间形成第二重叠区；
所述钝化保护层上设有分别对应于所述第一源极、第二源极、漏极上方的第一通孔、第二通孔、及第三通孔，所述第一、第二接触电极分别经由第一、第二通孔与第一、第二源极相接触，所述第三接触电极经由第三通孔与漏极相接触；所述第一接触电极、第二接触电极通过连接导线连接在一起，从而将所述第一、第二源极连接在一起，形成一U形的源极。
所述第一沟道区与第二沟道区的宽度相等，所述第一轻掺杂补偿区与第二轻掺杂补偿区的宽度相等，所述第一重叠区和第二重叠区的宽度相等。
所述第一源极接触区、第二源极接触区、漏极接触区为N型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、第一沟道区、及第二沟道区为P型轻掺杂区；或者，所述第一源极接触区、第二源极接触区、漏极接触区为P型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、第一沟道区、及第二沟道区为N型轻掺杂区。
所述栅极、第一源极、第二源极、及漏极为金属层或者N型掺杂多晶硅层。
所述第一、第二、第三接触电极、及连接导线的材料均为透明导电金属氧化物。
本发明还提供一种TFT基板，包括一基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上的第一源极、第二源极、及漏极、设于所述第一源极、第二源极、漏极、有源层、及栅极绝缘层上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、第三接触电极、及连接导线；
所述栅极为U形结构，包括第一竖直部、第二竖直部、以及连接第一与第二竖直部对应端部的横向连接部；
所述有源层上设有漏极接触区以及分别位于所述漏极接触区两侧且与其间隔一定距离的第一源极接触区与第二源极接触区；
所述有源层上位于所述第一源极接触区的右侧边缘与所述栅极的第一竖直部的左侧边缘之间的区域形成第一轻掺杂补偿区，位于所述栅极的第一竖直部的左侧边缘与所述漏极接触区的左侧边缘之间的区域形成第一沟道区，位于所述漏极接触区的右侧边缘与所述栅极的第二竖直部的左侧边缘之间的区域形成第二轻掺杂补偿区，位于所述栅极的第二竖直部的左侧边缘与所述第二源极接触区的左侧边缘之间的区域形成第二沟道区；
所述第一源极、第二源极、及漏极分别对应第一源极接触区、第二源极接触区、漏极接触区设于所述有源层上；且所述漏极的左侧与所述栅极的第一竖直部的右侧之间形成第一重叠区，所述第二源极的左侧与所述栅极的第二竖直部的右侧之间形成第二重叠区；
所述钝化保护层上设有分别对应于所述第一源极、第二源极、漏极上方的第一通孔、第二通孔、及第三通孔，所述第一、第二接触电极分别经由第一、第二通孔与第一、第二源极相接触，所述第三接触电极经由第三通孔与漏极相接触；所述第一接触电极、第二接触电极通过连接导线连接在一起，从而将所述第一、第二源极连接在一起，形成一U形的源极；
其中，所述第一沟道区与第二沟道区的宽度相等，所述第一轻掺杂补偿区与第二轻掺杂补偿区的宽度相等，所述第一重叠区和第二重叠区的宽度相等；
其中，所述第一源极接触区、第二源极接触区、漏极接触区为N型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、第一沟道区、及第二沟道区为P型轻掺杂区；或者，所述第一源极接触区、第二源极接触区、漏极接触区为P型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、 第一沟道区、及第二沟道区为N型轻掺杂区。
本发明的有益效果：本发明提供的一种TFT基板的制作方法，通过在第一源极与漏极之间设置第一沟道区与第一轻掺杂补偿区，在第二源极与漏极之间设置第二沟道区与第二轻掺杂补偿区，且所述漏极和第二源极分别与所述栅极之间形成第一重叠区和第二重叠区，从而使得从第一、第二源极流向漏极的电流与从漏极流向第一、第二源极的电流所经过的路径相同，即从源极到漏极与从漏极到源极的电流路径相同，从而实现了TFT结构的对称性，在实际工作中将漏极与源极互换使用也不会影响流过TFT器件的电流，提升了TFT器件的电学性能。本发明制得的TFT基板，TFT中的电流从漏极到源极或者从源极到漏极的通路均需通过两个offset结构与两个overlap结构，不仅可以降低关态电流，提高开态电流，而且电流通路具有对称性，避免了器件结构不对称对LTPS TFT中电流通路的影响，提升了TFT器件的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的TFT基板的制作方法的流程图；
图2-3为本发明的TFT基板的制作方法的步骤1的示意图；
图4-5为本发明的TFT基板的制作方法的步骤3的示意图；
图6-7为本发明的TFT基板的制作方法的步骤4的示意图；
图8-9为本发明的TFT基板的制作方法的步骤6的示意图。
图10为本发明制得的TFT基板中源极为高电压时的电流方向示意图；
图11为本发明制得的TFT基板中漏极为高电压时的电流方向示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图2-3所示，提供一基板10，在所述基板10上形成栅极20， 所述栅极20为U形结构，包括第一竖直部21、第二竖直部22、以及连接第一与第二竖直部21、22对应端部的横向连接部23。
具体的，所述栅极20的制备方法可以为：通过在基板10上沉积金属层，采用一道光罩对该金属层进行图形化处理，得到栅极20。
具体的，所述金属层的材料为铝(Al)、钼(Mo)、铜(Cu)、银(Ag)等金属材料。
具体的，所述栅极20的制备方法还可以为：通过在基板10上形成多晶硅层，对该多晶硅层进行N型掺杂后，采用一道光罩对N型掺杂多晶硅层进行图形化处理，得到栅极20。
步骤2、请参阅图4，在所述栅极20及基板10上沉积栅极绝缘层30，在所述栅极绝缘层30上沉积非晶硅，得到非晶硅薄膜，采用低温结晶工艺将所述非晶硅薄膜转化为多晶硅薄膜，采用一道光罩对所述多晶硅薄膜进行图形化处理，得到有源层40。
具体的，所述栅极绝缘层30可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述低温结晶工艺优选为固相结晶法(SPC，Solid Phase Crystallization)。
步骤3、如图4-5所示，对整个有源层40进行离子轻掺杂；对所述有源层40上的部分区域进行离子重掺杂，对应该部分区域形成漏极接触区47以及分别位于所述漏极接触区47的两侧且与其间隔一定距离的第一源极接触区45与第二源极接触区46；
其中，所述漏极接触区47的左侧与所述栅极20的第一竖直部21的右侧部分重叠；所述第二源极接触区46的左侧与所述栅极20的第二竖直部22的右侧部分重叠；
所述有源层40上位于所述第一源极接触区45的右侧边缘与所述栅极20的第一竖直部21的左侧边缘之间的区域形成第一轻掺杂补偿(Lightly Doped Offset)区43，位于所述栅极20的第一竖直部21的左侧边缘与所述漏极接触区47的左侧边缘之间的区域形成第一沟道区41，位于所述漏极接触区47的右侧边缘与所述栅极20的第二竖直部22的左侧边缘之间的区域形成第二轻掺杂补偿区44，位于所述栅极20的第二竖直部22的左侧边缘与所述第二源极接触区46的左侧边缘之间的区域形成第二沟道区42。
具体的，所述第一沟道区41与第二沟道区42的宽度相等，所述第一轻掺杂补偿区43与第二轻掺杂补偿区44的宽度相等。
具体的，所述步骤3中，对整个有源层40进行N型离子轻掺杂，对应 所述第一源极接触区45、第二源极接触区46、及漏极接触区47的位置对所述有源层40进行P型离子重掺杂；或者，对整个有源层40进行P型离子轻掺杂，对应所述第一源极接触区45、第二源极接触区46、及漏极接触区47的位置对所述有源层40进行N型离子重掺杂；
优选的，所述N型离子为磷离子或砷离子；所述P型离子为硼离子或镓离子。
步骤4、如图6-7所示，在所述有源层40上分别对应第一源极接触区45、第二源极接触区46、及漏极接触区47的位置形成第一源极51、第二源极52、及漏极53，且所述漏极53的左侧与所述栅极20的第一竖直部21的右侧之间形成第一重叠(overlap)区510，所述第二源极52的左侧与所述栅极20的第二竖直部21的右侧之间形成第二重叠区520。
具体的，所述第一重叠区510和第二重叠区520的宽度相等。
具体的，所述第一源极51、第二源极52、及漏极53的制备方法可以为：通过在有源层40及栅极绝缘层30上沉积金属层，采用一道光罩对该金属层进行图形化处理，得到第一源极51、第二源极52、及漏极53。
具体的，所述金属层的材料为铝(Al)、钼(Mo)、铜(Cu)、银(Ag)等金属材料。
具体的，所述第一源极51、第二源极52、及漏极53的制备方法还可以为：通过在有源层40及栅极绝缘层30上形成多晶硅层，对该多晶硅层进行N型掺杂后，采用一道光罩对N型掺杂多晶硅层进行图形化处理，得到第一源极51、第二源极52、及漏极53。
具体的，所述第一轻掺杂补偿区43与第二轻掺杂补偿区44形成高阻区，可降低LTPS TFT的关态电流。所述第一重叠区510与第二重叠区520可以降低LTPS TFT的沟道长度和减小高阻区域，进而提高开态电流。
步骤5、请参阅图8，在所述第一源极51、第二源极52、漏极53、有源层40、及栅极绝缘层30上沉积钝化保护层60，采用一道光罩对所述钝化保护层60进行图形化处理，分别对应于所述第一源极51、第二源极52、漏极53上方形成第一通孔61、第二通孔62、及第三通孔63。
具体的，所述钝化保护层60可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
步骤6、如图8所示，在所述钝化保护层60上沉积导电层，采用一道光罩对所述导电层进行图形化处理，得到第一接触电极71、第二接触电极72、及第三接触电极73、及连接导线80，所述第一、第二接触电极71、72分别经由第一、第二通孔61、62与第一、第二源极51、52相接触，所述 第三接触电极73经由第三通孔63与漏极53相接触；
如图9所示，所述连接导线80将所述第一与第二接触电极71、72连接在一起，由于所述第一、第二接触电极71、72分别与所述第一、第二源极51、52相连，从而将所述第一、第二源极51、52连接在一起，形成一U形的源极90，从而制得一TFT基板。
具体的，所述第一、第二、第三接触电极71、72、73、及连接导线80的材料均为透明导电金属氧化物，优选为ITO(氧化铟锡)。
具体的，所述第一、第二、第三接触电极71、72、73的用途之一为作为引线将所述第一、第二源极51、52、及漏极53接至数据线，用途之二为作为测试位点，来测试所述第一源极51、第二源极52、及漏极53的电压信号。
如图10所示，当所述TFT基板中源极90为高电压时，从源极90流向漏极53的电流包括两个分支电流，分别为从第一源极51流向漏极53的第一分支电流与从第二源极52流向漏极53的第二分支电流，其中，所述第一分支电流流经第一轻掺杂补偿区43、第一沟道区41、及第一重叠区510，所述第二分支电流流经第二重叠区520、第二沟道区42、及第二轻掺杂补偿区44；
如图11所示，当所述TFT基板中漏极53为高电压时，从所述漏极53流向所述源极90的电流包括两个分支电流，分别为从漏极53流向第一源极51的第三分支电流与从漏极53流向第二源极52的第四分支电流，其中，所述第三分支电流流经第一重叠区510、第一沟道区41、及第一轻掺杂补偿区43，所述第二分支电流流经第二轻掺杂补偿区44、第二沟道区42、及第二重叠区520；
由于所述第一沟道区41与第二沟道区42的宽度相等，所述第一轻掺杂补偿区43与第二轻掺杂补偿区44的宽度相等，所述第一重叠区510和第二重叠区520的宽度相等，因此从源极90流向漏极53的两个分支电流的路径与从漏极53流向源极90的两个分支电流的路径实质相同，从而保证了TFT器件的对称性，在实际工作中将漏极53与源极90互换使用也不会影响流过TFT器件的电流。
上述TFT基板的制作方法，通过在第一源极51与漏极53之间设置第一沟道区41与第一轻掺杂补偿区43，在第二源极52与漏极53之间设置第二沟道区42与第二轻掺杂补偿区44，且所述漏极53和第二源极52分别与所述栅极20之间形成第一重叠区510和第二重叠区520，从而使得从第一、第二源极51、52流向漏极53的电流与从漏极53流向第一、第二源极51、 52的电流所经过的路径相同，即从源极90到漏极53与从漏极53到源极90的电流路径相同，从而实现了TFT结构的对称性，在实际工作中将漏极53与源极90互换使用也不会影响流过TFT器件的电流，提升了TFT器件的电学性能。
请参阅图8-9，同时参阅图4-7，本发明还提供一种TFT基板，包括一基板10、设于所述基板10上的栅极20、设于所述栅极20及基板10上的栅极绝缘层30、设于所述栅极绝缘层30上的有源层40、设于所述有源层40上的第一源极51、第二源极52、及漏极53、设于所述第一源极51、第二源极52、漏极53、有源层40、及栅极绝缘层30上的钝化保护层60、以及设于所述钝化保护层60上的第一接触电极71、第二接触电极72、第三接触电极73、及连接导线80；
所述栅极20为U形结构，包括第一竖直部21、第二竖直部22、以及连接第一与第二竖直部21、22对应端部的横向连接部23；
所述有源层40上设有漏极接触区47以及分别位于所述漏极接触区47的两侧且与其间隔一定距离的第一源极接触区45与第二源极接触区46；
所述有源层40上位于所述第一源极接触区45的右侧边缘与所述栅极20的第一竖直部21的左侧边缘之间的区域形成第一轻掺杂补偿(Lightly Doped Offset)区43，位于所述栅极20的第一竖直部21的左侧边缘与所述漏极接触区47的左侧边缘之间的区域形成第一沟道区41，位于所述漏极接触区47的右侧边缘与所述栅极20的第二竖直部22的左侧边缘之间的区域形成第二轻掺杂补偿区44，位于所述栅极20的第二竖直部22的左侧边缘与所述第二源极接触区46的左侧边缘之间的区域形成第二沟道区42。
所述第一源极51、第二源极52、及漏极53分别对应第一源极接触区45、第二源极接触区46、漏极接触区47设于所述有源层40上；且所述漏极53的左侧与所述栅极20的第一竖直部21的右侧之间形成第一重叠(overlap)区510，所述第二源极52的左侧与所述栅极20的第二竖直部21的右侧之间形成第二重叠区520；
所述钝化保护层60上设有分别对应于所述第一源极51、第二源极52、漏极53上方的第一通孔61、第二通孔62、及第三通孔63，所述第一、第二接触电极71、72分别经由第一、第二通孔61、62与第一、第二源极51、52相接触，所述第三接触电极73经由第三通孔63与漏极53相接触；所述第一接触电极71、第二接触电极72通过连接导线80连接在一起，从而将所述第一、第二源极51、52连接在一起，形成一U形的源极90。
具体的，所述第一轻掺杂补偿区43与第二轻掺杂补偿区44形成高阻 区，可降低LTPS TFT的关态电流。所述第一重叠区510与第二重叠区520可以降低LTPS TFT的沟道长度和减小高阻区域，进而提高开态电流。
具体的，所述第一沟道区41与第二沟道区42的宽度相等，所述第一轻掺杂补偿区43与第二轻掺杂补偿区44的宽度相等，所述第一重叠区510和第二重叠区520的宽度相等。
具体的，所述栅极20、第一源极51、第二源极52、及漏极53可以为金属层，也可以为N型掺杂多晶硅层。具体的，所述金属层的材料为铝(Al)、钼(Mo)、铜(Cu)、银(Ag)等金属材料。
具体的，所述第一源极接触区45、第二源极接触区46、漏极接触区47为N型重掺杂区，所述第一轻掺杂补偿区43、第二轻掺杂补偿区44、第一沟道区41、及第二沟道区42为P型轻掺杂区；或者，所述第一源极接触区45、第二源极接触区46、漏极接触区47为P型重掺杂区，所述第一轻掺杂补偿区43、第二轻掺杂补偿区44、第一沟道区41、及第二沟道区42为N型轻掺杂区。
优选的，所述N型掺杂区中掺杂的离子为磷离子或砷离子；所述P型掺杂区中掺杂的离子为硼离子或镓离子。
具体的，所述栅极绝缘层30、钝化保护层60可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述第一、第二、第三接触电极71、72、73、及连接导线80的材料均为透明导电金属氧化物，优选为ITO(氧化铟锡)。
具体的，所述第一、第二、第三接触电极71、72、73的用途之一为作为引线将所述第一、第二源极51、52、及漏极53接至数据线，用途之二为作为测试位点，来测试所述第一源极51、第二源极52、及漏极53的电压信号。
上述TFT基板，通过在第一源极51与漏极53之间设置第一沟道区41与第一轻掺杂补偿区43，第二源极52与漏极53之间设置第二沟道区42与第二轻掺杂补偿区44，且所述漏极53和第二源极52分别与所述栅极20之间形成第一重叠区510和第二重叠区520，从而使得从第一、第二源极51、52流向漏极53的电流与从漏极53流向第一、第二源极51、52的电流所经过的路径相同，即从源极90到漏极53与从漏极53到源极90的电流路径相同，从而实现了TFT结构的对称性，在实际工作中将漏极53与源极90互换使用也不会影响流过TFT器件的电流，提升了TFT器件的电学性能。
综上所述，本发明提供的一种TFT基板的制作方法，通过在第一源极与漏极之间设置第一沟道区与第一轻掺杂补偿区，在第二源极与漏极之间 设置第二沟道区与第二轻掺杂补偿区，且所述漏极和第二源极分别与所述栅极之间形成第一重叠区和第二重叠区，从而使得从第一、第二源极流向漏极的电流与从漏极流向第一、第二源极的电流所经过的路径相同，即从源极到漏极与从漏极到源极的电流路径相同，从而实现了TFT结构的对称性，在实际工作中将漏极与源极互换使用也不会影响流过TFT器件的电流，提升了TFT器件的电学性能。本发明制得的TFT基板，TFT中的电流从漏极到源极或者从源极到漏极的通路均需通过两个offset结构与两个overlap结构，不仅可以降低关态电流，提高开态电流，而且电流通路具有对称性，避免了器件结构不对称对LTPS TFT中电流通路的影响，提升了TFT器件的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上形成栅极，所述栅极为U形结构，包括第一竖直部、第二竖直部、以及连接第一与第二竖直部对应端部的横向连接部；
    步骤2、在所述栅极及基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅，得到非晶硅薄膜，采用低温结晶工艺将所述非晶硅薄膜转化为多晶硅薄膜，采用一道光罩对所述多晶硅薄膜进行图形化处理，得到有源层；
    步骤3、对整个有源层进行离子轻掺杂；对所述有源层上的部分区域进行离子重掺杂，对应该部分区域形成漏极接触区以及分别位于所述漏极接触区的两侧且与其间隔一定距离的第一源极接触区与第二源极接触区；
    其中，所述漏极接触区的左侧与所述栅极的第一竖直部的右侧部分重叠；所述第二源极接触区的左侧与所述栅极的第二竖直部的右侧部分重叠；
    所述有源层上位于所述第一源极接触区的右侧边缘与所述栅极的第一竖直部的左侧边缘之间的区域形成第一轻掺杂补偿区，位于所述栅极的第一竖直部的左侧边缘与所述漏极接触区的左侧边缘之间的区域形成第一沟道区，位于所述漏极接触区的右侧边缘与所述栅极的第二竖直部的左侧边缘之间的区域形成第二轻掺杂补偿区，位于所述栅极的第二竖直部的左侧边缘与所述第二源极接触区的左侧边缘之间的区域形成第二沟道区；
    步骤4、在所述有源层上分别对应第一源极接触区、第二源极接触区、及漏极接触区的位置形成第一源极、第二源极、及漏极，且所述漏极的左侧与所述栅极的第一竖直部的右侧之间形成第一重叠区，所述第二源极的左侧与所述栅极的第二竖直部的右侧之间形成第二重叠区；
    步骤5、在所述第一源极、第二源极、漏极、有源层、及栅极绝缘层上沉积钝化保护层，采用一道光罩对所述钝化保护层进行图形化处理，分别对应于所述第一源极、第二源极、漏极上方形成第一通孔、第二通孔、及第三通孔；
    步骤6、在所述钝化保护层上沉积导电层，采用一道光罩对所述导电层进行图形化处理，得到第一接触电极、第二接触电极、第三接触电极、及连接导线，所述第一、第二接触电极分别经由第一、第二通孔与第一、第二源极相接触，所述第三接触电极经由第三通孔与漏极相接触；
    所述连接导线将所述第一与第二接触电极连接在一起，由于所述第一、第二接触电极分别与所述第一、第二源极相连，从而将所述第一、第二源极连接在一起，形成一U形的源极，从而制得一TFT基板。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述第一沟道区与第二沟道区的宽度相等，所述第一轻掺杂补偿区与第二轻掺杂补偿区的宽度相等，所述第一重叠区和第二重叠区的宽度相等。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3中，对整个有源层进行N型离子轻掺杂，对应所述第一源极接触区、第二源极接触区、及漏极接触区的位置对所述有源层进行P型离子重掺杂；或者，对整个有源层进行P型离子轻掺杂，对应所述第一源极接触区、第二源极接触区、及漏极接触区的位置对所述有源层进行N型离子重掺杂。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述栅极的制备方法为：通过在基板上沉积金属层，采用一道光罩对该金属层进行图形化处理，得到栅极；或者为：通过在基板上形成多晶硅层，对该多晶硅层进行N型掺杂后，采用一道光罩对N型掺杂多晶硅层进行图形化处理，得到栅极；
    所述第一源极、第二源极、及漏极的制备方法为：通过在有源层及栅极绝缘层上沉积金属层，采用一道光罩对该金属层进行图形化处理，得到第一源极、第二源极、及漏极；或者为：通过在有源层及栅极绝缘层上形成多晶硅层，对该多晶硅层进行N型掺杂后，采用一道光罩对N型掺杂多晶硅层进行图形化处理，得到第一源极、第二源极、及漏极。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述第一、第二、第三接触电极、及连接导线的材料均为透明导电金属氧化物。
  6. 一种TFT基板，包括一基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上的第一源极、第二源极、及漏极、设于所述第一源极、第二源极、漏极、有源层、及栅极绝缘层上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、第三接触电极、及连接导线；
    所述栅极为U形结构，包括第一竖直部、第二竖直部、以及连接第一与第二竖直部对应端部的横向连接部；
    所述有源层上设有漏极接触区以及分别位于所述漏极接触区两侧且与其间隔一定距离的第一源极接触区与第二源极接触区；
    所述有源层上位于所述第一源极接触区的右侧边缘与所述栅极的第一竖直部的左侧边缘之间的区域形成第一轻掺杂补偿区，位于所述栅极的第 一竖直部的左侧边缘与所述漏极接触区的左侧边缘之间的区域形成第一沟道区，位于所述漏极接触区的右侧边缘与所述栅极的第二竖直部的左侧边缘之间的区域形成第二轻掺杂补偿区，位于所述栅极的第二竖直部的左侧边缘与所述第二源极接触区的左侧边缘之间的区域形成第二沟道区；
    所述第一源极、第二源极、及漏极分别对应第一源极接触区、第二源极接触区、漏极接触区设于所述有源层上；且所述漏极的左侧与所述栅极的第一竖直部的右侧之间形成第一重叠区，所述第二源极的左侧与所述栅极的第二竖直部的右侧之间形成第二重叠区；
    所述钝化保护层上设有分别对应于所述第一源极、第二源极、漏极上方的第一通孔、第二通孔、及第三通孔，所述第一、第二接触电极分别经由第一、第二通孔与第一、第二源极相接触，所述第三接触电极经由第三通孔与漏极相接触；所述第一接触电极、第二接触电极通过连接导线连接在一起，从而将所述第一、第二源极连接在一起，形成一U形的源极。
  7. 如权利要求6所述的TFT基板，其中，所述第一沟道区与第二沟道区的宽度相等，所述第一轻掺杂补偿区与第二轻掺杂补偿区的宽度相等，所述第一重叠区和第二重叠区的宽度相等。
  8. 如权利要求6所述的TFT基板，其中，所述第一源极接触区、第二源极接触区、漏极接触区为N型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、第一沟道区、及第二沟道区为P型轻掺杂区；或者，所述第一源极接触区、第二源极接触区、漏极接触区为P型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、第一沟道区、及第二沟道区为N型轻掺杂区。
  9. 如权利要求6所述的TFT基板，其中，所述栅极、第一源极、第二源极、及漏极为金属层或者N型掺杂多晶硅层。
  10. 如权利要求6所述的TFT基板，其中，所述第一、第二、第三接触电极、及连接导线的材料均为透明导电金属氧化物。
  11. 一种TFT基板，包括一基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上的第一源极、第二源极、及漏极、设于所述第一源极、第二源极、漏极、有源层、及栅极绝缘层上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、第三接触电极、及连接导线；
    所述栅极为U形结构，包括第一竖直部、第二竖直部、以及连接第一与第二竖直部对应端部的横向连接部；
    所述有源层上设有漏极接触区以及分别位于所述漏极接触区两侧且与 其间隔一定距离的第一源极接触区与第二源极接触区；
    所述有源层上位于所述第一源极接触区的右侧边缘与所述栅极的第一竖直部的左侧边缘之间的区域形成第一轻掺杂补偿区，位于所述栅极的第一竖直部的左侧边缘与所述漏极接触区的左侧边缘之间的区域形成第一沟道区，位于所述漏极接触区的右侧边缘与所述栅极的第二竖直部的左侧边缘之间的区域形成第二轻掺杂补偿区，位于所述栅极的第二竖直部的左侧边缘与所述第二源极接触区的左侧边缘之间的区域形成第二沟道区；
    所述第一源极、第二源极、及漏极分别对应第一源极接触区、第二源极接触区、漏极接触区设于所述有源层上；且所述漏极的左侧与所述栅极的第一竖直部的右侧之间形成第一重叠区，所述第二源极的左侧与所述栅极的第二竖直部的右侧之间形成第二重叠区；
    所述钝化保护层上设有分别对应于所述第一源极、第二源极、漏极上方的第一通孔、第二通孔、及第三通孔，所述第一、第二接触电极分别经由第一、第二通孔与第一、第二源极相接触，所述第三接触电极经由第三通孔与漏极相接触；所述第一接触电极、第二接触电极通过连接导线连接在一起，从而将所述第一、第二源极连接在一起，形成一U形的源极；
    其中，所述第一沟道区与第二沟道区的宽度相等，所述第一轻掺杂补偿区与第二轻掺杂补偿区的宽度相等，所述第一重叠区和第二重叠区的宽度相等；
    其中，所述第一源极接触区、第二源极接触区、漏极接触区为N型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、第一沟道区、及第二沟道区为P型轻掺杂区；或者，所述第一源极接触区、第二源极接触区、漏极接触区为P型重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区、第一沟道区、及第二沟道区为N型轻掺杂区。
  12. 如权利要求11所述的TFT基板，其中，所述栅极、第一源极、第二源极、及漏极为金属层或者N型掺杂多晶硅层。
  13. 如权利要求11所述的TFT基板，其中，所述第一、第二、第三接触电极、及连接导线的材料均为透明导电金属氧化物。
PCT/CN2016/080189 2016-03-23 2016-04-26 Tft基板的制作方法及制得的tft基板 Ceased WO2017161625A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/105,572 US10038074B2 (en) 2016-03-23 2016-04-26 Manufacture method of TFT substrate and manufactured TFT substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610169540.1 2016-03-23
CN201610169540.1A CN105742294B (zh) 2016-03-23 2016-03-23 Tft基板的制作方法及制得的tft基板

Publications (1)

Publication Number Publication Date
WO2017161625A1 true WO2017161625A1 (zh) 2017-09-28

Family

ID=56251079

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/080189 Ceased WO2017161625A1 (zh) 2016-03-23 2016-04-26 Tft基板的制作方法及制得的tft基板

Country Status (3)

Country Link
US (1) US10038074B2 (zh)
CN (1) CN105742294B (zh)
WO (1) WO2017161625A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742294B (zh) * 2016-03-23 2019-01-15 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板
CN107482055B (zh) * 2017-08-28 2023-12-01 京东方科技集团股份有限公司 薄膜晶体管、薄膜晶体管制备方法和阵列基板
CN119993007A (zh) 2019-08-21 2025-05-13 群创光电股份有限公司 电子装置
CN110649101B (zh) * 2019-10-18 2022-04-15 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN113785352B (zh) 2020-04-10 2023-04-11 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
US11875749B2 (en) 2020-04-10 2024-01-16 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and manufacturing method thereof, display device
CN116564231B (zh) 2020-04-10 2025-07-25 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN117812946A (zh) * 2024-02-07 2024-04-02 京东方科技集团股份有限公司 一种显示基板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010004537A1 (en) * 1999-12-18 2001-06-21 Lee Sung Kwon Method for fabricating thin film transistors
CN1549349A (zh) * 2003-05-19 2004-11-24 友达光电股份有限公司 低温多晶硅薄膜电晶体的结构
CN1638564A (zh) * 2003-12-27 2005-07-13 Lg.菲利浦Lcd株式会社 有源矩阵有机电致发光显示器件及其制造方法
CN101866918A (zh) * 2010-06-28 2010-10-20 信利半导体有限公司 一种薄膜晶体管阵列基板、显示器及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198379A (en) * 1990-04-27 1993-03-30 Sharp Kabushiki Kaisha Method of making a MOS thin film transistor with self-aligned asymmetrical structure
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
US5808317A (en) * 1996-07-24 1998-09-15 International Business Machines Corporation Split-gate, horizontally redundant, and self-aligned thin film transistors
US6680223B1 (en) * 1997-09-23 2004-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6218219B1 (en) * 1997-09-29 2001-04-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US7022556B1 (en) * 1998-11-11 2006-04-04 Semiconductor Energy Laboratory Co., Ltd. Exposure device, exposure method and method of manufacturing semiconductor device
US6891236B1 (en) * 1999-01-14 2005-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
JP2000277738A (ja) * 1999-03-19 2000-10-06 Fujitsu Ltd 薄膜トランジスタおよびその製造方法
KR100611743B1 (ko) * 2001-12-19 2006-08-10 삼성에스디아이 주식회사 멀티플 게이트 박막 트랜지스터
KR100477102B1 (ko) * 2001-12-19 2005-03-17 삼성에스디아이 주식회사 금속유도화 측면결정화방법을 이용한 멀티플 게이트씨모스 박막 트랜지스터 및 그의 제조방법
KR100635048B1 (ko) * 2003-11-25 2006-10-17 삼성에스디아이 주식회사 박막 트랜지스터, 이의 제조 방법 및 이를 사용하는 평판표시 장치
TWI420670B (zh) * 2008-10-30 2013-12-21 Hitachi Displays Ltd 顯示裝置
JP5575455B2 (ja) * 2009-10-29 2014-08-20 株式会社ジャパンディスプレイ 表示装置の製造方法
KR20140054465A (ko) * 2010-09-15 2014-05-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 표시 장치
CN105742294B (zh) * 2016-03-23 2019-01-15 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010004537A1 (en) * 1999-12-18 2001-06-21 Lee Sung Kwon Method for fabricating thin film transistors
CN1549349A (zh) * 2003-05-19 2004-11-24 友达光电股份有限公司 低温多晶硅薄膜电晶体的结构
CN1638564A (zh) * 2003-12-27 2005-07-13 Lg.菲利浦Lcd株式会社 有源矩阵有机电致发光显示器件及其制造方法
CN101866918A (zh) * 2010-06-28 2010-10-20 信利半导体有限公司 一种薄膜晶体管阵列基板、显示器及其制造方法

Also Published As

Publication number Publication date
CN105742294A (zh) 2016-07-06
US20180102417A1 (en) 2018-04-12
CN105742294B (zh) 2019-01-15
US10038074B2 (en) 2018-07-31

Similar Documents

Publication Publication Date Title
WO2017161625A1 (zh) Tft基板的制作方法及制得的tft基板
CN104465702B (zh) Amoled背板的制作方法
CN106558593B (zh) 阵列基板、显示面板、显示装置及阵列基板的制备方法
CN104752343B (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2017161626A1 (zh) Tft基板的制作方法及制得的tft基板
WO2014183422A1 (zh) 薄膜晶体管及其制备方法、阵列基板
CN110649101A (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
CN105097841B (zh) Tft基板的制作方法及tft基板
WO2016101392A1 (zh) Amoled背板的制作方法及其结构
CN106057735A (zh) Tft背板的制作方法及tft背板
WO2016165187A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2020215603A1 (zh) Oled显示面板及其制备方法
WO2016165185A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
KR101456405B1 (ko) 박막 트랜지스터, 어레이 기판, 및 그 제조방법
CN103762244A (zh) 薄膜晶体管及其制造方法、薄膜晶体管阵列基板及液晶面板
CN107482055B (zh) 薄膜晶体管、薄膜晶体管制备方法和阵列基板
WO2017219412A1 (zh) 顶栅型薄膜晶体管的制作方法
CN104752426A (zh) 共栅极立体式cmos器件、oled器件及其制造方法
CN102709283B (zh) 低温多晶硅薄膜晶体管阵列基板及其制作方法
US10424672B2 (en) Oxide semiconductor transistor
CN114203726A (zh) 显示面板及其制备方法
TWI578521B (zh) A thin film transistor and its preparation method
CN104934444B (zh) 共平面型氧化物半导体tft基板结构及其制作方法
CN107946244B (zh) 一种阵列基板及其制备方法
WO2022001468A1 (zh) 薄膜晶体管、显示基板及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15105572

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16894978

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16894978

Country of ref document: EP

Kind code of ref document: A1