WO2017156817A1 - 可调节削角波形的削角电路及削角波形的调节方法 - Google Patents

可调节削角波形的削角电路及削角波形的调节方法 Download PDF

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WO2017156817A1
WO2017156817A1 PCT/CN2016/079230 CN2016079230W WO2017156817A1 WO 2017156817 A1 WO2017156817 A1 WO 2017156817A1 CN 2016079230 W CN2016079230 W CN 2016079230W WO 2017156817 A1 WO2017156817 A1 WO 2017156817A1
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Prior art keywords
triode
resistor
voltage
chamfering
output terminal
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PCT/CN2016/079230
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English (en)
French (fr)
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扶伟
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深圳市华星光电技术有限公司
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Priority to US15/122,636 priority Critical patent/US10074337B2/en
Publication of WO2017156817A1 publication Critical patent/WO2017156817A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a chamfering circuit capable of adjusting a chamfering waveform and a method for adjusting a chamfering waveform.
  • LCD Liquid Crystal Display
  • advantages such as thin body, power saving, no radiation, etc., such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or Laptop screens, etc., dominate the field of flat panel display.
  • PDA personal digital assistant
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the TFT array substrate includes a plurality of gate lines and data lines, a plurality of gate lines and a plurality of data lines perpendicular to each other form a plurality of pixel units, and each of the pixel units is provided with a thin film transistor (Thin Film Transistor, TFT) ), pixel electrodes, storage capacitors, etc.
  • TFT Thin Film Transistor
  • the TFT includes a gate connected to the gate line, a source connected to the data line, and a drain connected to the pixel electrode.
  • the TFT When the gate line is driven, the TFT is in an on state, and the corresponding data line is fed with a gray scale voltage signal and loaded to the pixel electrode, thereby generating a corresponding electric field between the pixel electrode and the common electrode, in the liquid crystal layer
  • the liquid crystal molecules undergo an orientation change under the action of an electric field, so that different image display can be realized.
  • the TFT turn-on voltage VGH needs to be chamfered to The voltage difference between the TFT turn-on voltage VGH and the TFT turn-off voltage VGL when the TFT is turned off is reduced to reduce the influence on the data signal voltage.
  • a method of resistance grounding discharge is generally used to achieve the purpose of chamfering. As shown in FIG.
  • the existing chamfering circuit includes: an integrated circuit (IC) 10 (Integrated Circuit, IC) And a chamfering resistor 20; one end of the chamfering resistor 20 is connected to the power supply integrated circuit 10, and the other end is grounded; referring to FIG. 2, the TFT turn-on voltage VGH generated by the power supply integrated circuit 10 is discharged through the chamfering resistor 20.
  • IC integrated circuit
  • IC integrated Circuit
  • VGH chamfering resistor 20
  • the chamfering waveform formed by the TFT turn-on voltage VGH is also the same. Since the chamfering waveform affects the pixel charging time and causes the H-block phenomenon (horizontal block), it is necessary to control the chamfering of the TFT turn-on voltage VGH.
  • the waveform is used to reduce the influence on the charging time of the pixel and avoid the H-block phenomenon. This requires constant replacement of the chamfering resistor 20 to find the optimum resistance that has the least influence on the charging time of the pixel. This method is cumbersome and has low work efficiency.
  • the object of the present invention is to provide a chamfering circuit capable of adjusting a chamfering waveform, which can conveniently and quickly adjust a chamfering waveform, improve work efficiency, and improve picture quality.
  • Another object of the present invention is to provide a method for adjusting a chamfering waveform, which can conveniently and quickly adjust a chamfering waveform, improve work efficiency, and improve picture quality.
  • the present invention provides a chamfering circuit capable of adjusting a chamfering waveform, comprising: a digital power IC, a first resistor, a second resistor, and a triode;
  • the digital power IC includes: a TFT turn-on voltage output terminal, and a triode base voltage output terminal;
  • One end of the first resistor is electrically connected to the TFT open voltage output terminal of the digital power IC, and the other end is electrically connected to the emitter of the triode;
  • the base of the triode is electrically connected to the base voltage output terminal of the triode of the digital power IC, the emitter is electrically connected to one end of the second resistor, and the collector is grounded;
  • One end of the second resistor is electrically connected to the other end of the first resistor, and the other end is grounded;
  • the TFT turn-on voltage output terminal outputs a TFT turn-on voltage
  • the triode base voltage output terminal outputs a triode base voltage
  • the triode base voltage is an adjustable voltage
  • the chamfering waveform of the TFT turn-on voltage is adjusted by adjusting the magnitude of the base voltage of the triode.
  • the triode emitter when the voltage of the triode emitter is less than the base voltage of the three-stage tube, the triode is turned on, and the resistance of the chamfering resistor is the resistance of the first resistor.
  • the triode emitter when the voltage of the triode emitter is greater than the tertiary tube base voltage, the triode is turned off, and the resistance of the chamfering resistor is the sum of the resistances of the first resistor and the second resistor.
  • the digital power IC is provided with an I2C interface, and the base voltage of the triode output from the base voltage output terminal of the triode is adjusted through the I2C interface.
  • the invention also provides a method for adjusting a chamfering waveform, comprising the following steps:
  • Step 1 Providing a chamfering circuit, comprising: a digital power IC, a first resistor, a second resistor, and a triode;
  • the digital power IC includes: a TFT turn-on voltage output terminal and a triode base voltage output terminal; one end of the first resistor is electrically connected to the TFT turn-on voltage output terminal of the digital power IC, and the other end is connected to the emitter of the triode Electrically connecting; a base of the triode is electrically connected to a base voltage output terminal of the triode of the digital power IC, an emitter is electrically connected to one end of the second resistor, and a collector is grounded; one end of the second resistor Electrically connected to the other end of the first resistor and grounded at the other end;
  • Step 2 Adjust the magnitude of the base voltage of the triode at the base voltage output terminal of the triode of the digital power IC, control the on-time of the triode, and change the chamfering waveform of the TFT turn-on voltage.
  • the chamfering circuit provided in the step 1 is in the process of turning on the voltage of the TFT, and when the voltage of the emitter of the triode is less than the voltage of the base of the three-stage tube, the triode is turned on, and the resistance of the chamfering resistor is the first resistor. Resistance.
  • the chamfering circuit provided in the step 1 is in the process of turning on the voltage of the TFT, and when the voltage of the emitter of the triode is greater than the base voltage of the triode, the resistance of the chamfering resistor is the first resistor and the second resistor. The sum of the resistance values.
  • the base voltage of the triode output of the triode base voltage output terminal of the digital power IC is adjusted through the I2C interface.
  • the invention also provides a chamfering circuit capable of adjusting a chamfering waveform, comprising: a digital power IC, a first resistor, a second resistor, and a triode;
  • the digital power IC includes: a TFT turn-on voltage output terminal, and a triode base voltage output terminal;
  • One end of the first resistor is electrically connected to the TFT open voltage output terminal of the digital power IC, and the other end is electrically connected to the emitter of the triode;
  • the base of the triode is electrically connected to the base voltage output terminal of the triode of the digital power IC, the emitter is electrically connected to one end of the second resistor, and the collector is grounded;
  • One end of the second resistor is electrically connected to the other end of the first resistor, and the other end is grounded;
  • the TFT turn-on voltage output terminal outputs a TFT turn-on voltage
  • the triode base voltage output terminal outputs a triode base voltage
  • the triode base voltage is an adjustable voltage
  • the chamfering waveform of the TFT turn-on voltage is adjusted by adjusting the magnitude of the base voltage of the triode;
  • the digital power IC is provided with an I2C interface, and the base voltage of the triode output from the base voltage output terminal of the triode is adjusted through the I2C interface.
  • the present invention provides a chamfering circuit capable of adjusting a chamfering waveform, including a digital power IC, a first resistor, a second resistor, and a triode; and a triode base voltage that can be output by adjusting a digital power IC
  • a chamfering circuit capable of adjusting a chamfering waveform, including a digital power IC, a first resistor, a second resistor, and a triode; and a triode base voltage that can be output by adjusting a digital power IC
  • the invention also provides a method for adjusting the chamfering waveform, which can conveniently and quickly adjust the chamfering waveform, improve working efficiency and improve picture quality.
  • 1 is a circuit diagram of a conventional chamfering circuit
  • Figure 2 is a chamfering waveform diagram of the circuit shown in Figure 1;
  • FIG. 3 is a circuit diagram of a chamfering circuit of an adjustable chamfering waveform of the present invention.
  • FIG. 4 is a waveform diagram of a chamfer when the base voltage of the triode is VB1 in the chamfering circuit of the adjustable chamfering waveform of the present invention
  • FIG. 5 is a waveform diagram of a chamfer when the base voltage of the triode is VB2 in the chamfering circuit of the adjustable chamfering waveform of the present invention
  • Fig. 6 is a flow chart showing a method of adjusting a chamfering waveform of the present invention.
  • the present invention provides a chamfering circuit capable of adjusting a chamfering waveform, comprising: a digital power IC1, a first resistor R1, a second resistor R2, and a triode Tr1;
  • the digital power IC1 includes: a TFT turn-on voltage output terminal 11 and a triode base voltage output terminal 12;
  • One end of the first resistor R1 is electrically connected to the TFT open voltage output terminal 11 of the digital power IC1, and the other end is electrically connected to the emitter e of the transistor Tr1;
  • the base b of the triode Tr1 is electrically connected to the triode base voltage output terminal 12 of the digital power IC1, the emitter e is electrically connected to one end of the second resistor R2, and the collector c is grounded;
  • One end of the second resistor R2 is electrically connected to the other end of the first resistor R1, and the other end is grounded;
  • the TFT turn-on voltage output terminal 11 outputs a TFT turn-on voltage VGH
  • the transistor base voltage output terminal 12 outputs a triode base voltage VB
  • the triode base voltage VB is Adjust the voltage.
  • the voltage of the triode emitter is smaller than the third-stage tube base voltage VB.
  • the transistor Tr1 is turned on, and the chamfering resistor is turned on.
  • the resistance value is the resistance value of the first resistor R1
  • the TFT turn-on voltage VGH is grounded and discharged via the first resistor R1 and the transistor Tr1, the discharge speed is faster, the chamfering waveform is steep, and the voltage discharged to the emitter of the triode is equal to the third-order tube.
  • the transistor Tr1 When the base voltage is VB, the transistor Tr1 is turned off, and the resistance of the chamfering resistance is the sum of the resistances of the first resistor R1 and the second resistor R2, the discharge speed is slow, and the chamfering waveform is relatively gentle.
  • the TFT turn-on voltage VGH is discharged to 10V at a faster speed with the path of the first resistor R1 and the transistor Tr1, and then the first resistor R1 and the second resistor R2 from 10V.
  • the path continues to discharge at a slower speed, that is, the smaller the base voltage VB of the transistor, the longer the conduction time of the transistor Tr1, the steeper the chamfering waveform of the TFT turn-on voltage VGH, and the faster the discharge speed, so that
  • the I2C interface adjusts the triode base voltage VB outputted from the triode base voltage output terminal 12 of the digital power IC1, controls the conduction time of the triode Tr1, and then changes the chamfering waveform to control the discharge speed of the TFT turn-on voltage VGH, for example, 4 and FIG. 5, the chamfering waveforms of the base voltages of two different triodes, wherein VB1 is greater than VB2, and the discharge speed of the TFT turn-on voltage VGH in FIG.
  • the discharge amount in the same time T is lower than that in FIG. 5, and the lowest point after the TFT turn-on voltage VGH is discharged is higher than the lowest point after the TFT turn-on voltage VGH is discharged in FIG.
  • the present invention further provides a method for adjusting a chamfering waveform, including the following steps:
  • Step 1 please refer to FIG. 3, providing a chamfering circuit, comprising: a digital power IC1, a first resistor R1, a second resistor R2, and a triode Tr1;
  • the digital power IC1 includes: a TFT turn-on voltage output terminal 11 and a triode base voltage output terminal 12;
  • One end of the first resistor R1 is electrically connected to the TFT open voltage output terminal 11 of the digital power IC1, and the other end is electrically connected to the emitter e of the transistor Tr1;
  • the base b of the triode Tr1 is electrically connected to the triode base voltage output terminal 12 of the digital power IC1, the emitter e is electrically connected to one end of the second resistor R2, and the collector c is grounded;
  • One end of the second resistor R2 is electrically connected to the other end of the first resistor R1, and the other end is grounded;
  • Step 2 Adjust the magnitude of the triode base voltage VB outputted from the triode base voltage output terminal 12 of the digital power IC1, control the conduction time of the triode Tr1, and change the chamfering waveform of the TFT turn-on voltage VGH.
  • the chamfering circuit provided in the step 1 is in the process of turning off the voltage of the TFT,
  • the triode Tr1 When the voltage of the emitter of the triode is less than the base voltage VB of the tertiary tube, the triode Tr1 is turned on, and the resistance of the chamfering resistor is the resistance of the first resistor R1; when the voltage of the emitter of the triode is greater than the triode At the base voltage VB, the transistor Tr1 is turned off, and the resistance of the chamfer resistor is the sum of the resistances of the first resistor R1 and the second resistor R2.
  • the discharge speed of the TFT turn-on voltage VGH in FIG. 4 is higher than the discharge voltage of the TFT turn-on voltage VGH in FIG.
  • the speed is slow, and the discharge amount in the same time T is lower than that in FIG. 5, and the lowest point after the TFT turn-on voltage VGH is discharged is higher than the lowest point after the TFT turn-on voltage VGH is discharged in FIG.
  • the triode base voltage VB outputted from the triode base voltage output terminal 12 of the digital power IC1 is adjusted through the I2C interface, and the operation is simple and convenient.
  • the present invention provides a chamfering circuit capable of adjusting a chamfering waveform, including a digital power IC, a first resistor, a second resistor, and a triode; and adjusting a base voltage of a triode by a digital power IC
  • the size is used to adjust the chamfering waveform to improve the picture quality.
  • the chamfering waveform can be adjusted without welding resistance, and the operation is simple and the working efficiency is high.
  • the invention also provides a method for adjusting the chamfering waveform, which can conveniently and quickly adjust the chamfering waveform, improve working efficiency and improve picture quality.

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  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种可调节削角波形的削角电路及削角波形的调节方法。可调节削角波形的削角电路，包括数字电源IC（1）、第一电阻（R1）、第二电阻（R2）及三极管（Tr1），通过调节数字电源IC（1）输出的三极管基极电压（VB）的大小来调节削角波形，以提升画面品质，相比于现有技术，不需要通过焊接电阻即可完成削角波形的调整，操作简单，工作效率高。

Description

可调节削角波形的削角电路及削角波形的调节方法 技术领域
本发明涉及显示技术领域，尤其涉及一种可调节削角波形的削角电路及削角波形的调节方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
TFT阵列基板包括多条栅极线和数据线，相互垂直的多条栅极线和多条数据线形成了多个像素单元，且每个像素单元内均设置有薄膜晶体管(Thin Film Transistor，TFT)、像素电极及存储电容等。TFT包括一栅极连接至栅极线，源极连接至数据线，漏极连接至像素电极。当栅极线被驱动时，TFT处于导通状态，对应的数据线送入灰阶电压信号并将其加载至像素电极，从而使得像素电极与公共电极之间产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，因此可以实现不同的图像显示。
现有技术的液晶显示装置中，由于电容耦合效应的影响，在TFT打开与关闭时，会影响到数据信号电压的稳定，进而影响画面品质，因此需要对TFT开启电压VGH进行削角处理，以降低TFT关闭时TFT开启电压VGH与TFT关闭电压VGL之间的电压差，减小对数据信号电压的影响。具体地，请参阅图1，现有技术中通常采用电阻接地放电的方法来达到削角的目的，如图1所示，现有的削角电路包括：电源集成电路10(Integrated Circuit，IC)、以及削角电阻20；所述削角电阻20的一端与电源集成电路10相连，另一端接地；请参阅图2，所述电源集成电路10产生的TFT开启电压VGH经由削角电阻20放电形成削角。对于阻值相同的削角电阻20， 所述TFT开启电压VGH形成的削角波形也相同，由于削角波形会影响像素充电时间，造成H-block现象(Horizontal Block，水平区块不良)，因此需要控制对TFT开启电压VGH的削角波形，以降低对像素充电时间的影响，避免H-block现象，这就需要不断更换削角电阻20来找到对像素充电时间影响最小的最佳电阻，这种方法操作繁琐，工作效率低。
发明内容
本发明的目的在于提供一种可调节削角波形的削角电路，能够方便快捷的调节削角波形，提升工作效率，改善画面品质。
本发明的目的还在于提供一种削角波形的调节方法，能够方便快捷的调节削角波形，提升工作效率，改善画面品质。
为实现上述目的，本发明提供了一种可调节削角波形的削角电路，包括：数字电源IC、第一电阻、第二电阻、及三极管；
所述数字电源IC包括：TFT开启电压输出端子、以及三极管基极电压输出端子；
所述第一电阻一端与所述数字电源IC的TFT开启电压输出端子电性连接，另一端与三极管的发射极电性连接；
所述三极管的基极与所述数字电源IC的三极管基极电压输出端子电性连接，发射极与第二电阻的一端电性连接，集电极接地；
所述第二电阻的一端与第一电阻的另一端电性连接，另一端接地；
所述TFT开启电压输出端子输出TFT开启电压，三极管基极电压输出端子输出三极管基极电压，所述三极管基极电压为可调电压。
通过调节所述三极管基极电压的大小，来调节TFT开启电压的削角波形。
对TFT开启电压削角过程中，当三极管发射极的电压小于所述三级管基极电压时，三极管导通，削角电阻的阻值为第一电阻的阻值。
对TFT开启电压削角过程中，当三极管发射极的电压大于所述三级管基极电压时，三极管关闭，削角电阻的阻值为第一电阻和第二电阻的阻值之和。
所述数字电源IC上设有I2C接口，三极管基极电压输出端子输出的三极管基极电压通过I2C接口来调节。
本发明还提供一种削角波形的调节方法，包括如下步骤：
步骤1、提供一削角电路，包括：数字电源IC、第一电阻、第二电阻、及三极管；
所述数字电源IC包括：TFT开启电压输出端子、以及三极管基极电压输出端子；所述第一电阻一端与所述数字电源IC的TFT开启电压输出端子电性连接，另一端与三极管的发射极电性连接；所述三极管的基极与所述数字电源IC的三极管基极电压输出端子电性连接，发射极与第二电阻的一端电性连接，集电极接地；所述第二电阻的一端与第一电阻的另一端电性连接，另一端接地；
步骤2、调节数字电源IC的三极管基极电压输出端子输出的三极管基极电压的大小，控制三极管的导通时间，改变TFT开启电压的削角波形。
所述步骤1中提供的削角电路对TFT开启电压削角过程中，当三极管发射极的电压小于所述三级管基极电压时，三极管导通，削角电阻的阻值为第一电阻的阻值。
所述步骤1中提供的削角电路对TFT开启电压削角过程中，当三极管发射极的电压大于所述三级管基极电压时，削角电阻的阻值为第一电阻和第二电阻的阻值之和。
所述步骤2中通过I2C接口来调节数字电源IC的三极管基极电压输出端子输出的三极管基极电压。
本发明还提供一种可调节削角波形的削角电路，包括：数字电源IC、第一电阻、第二电阻、及三极管；
所述数字电源IC包括：TFT开启电压输出端子、以及三极管基极电压输出端子；
所述第一电阻一端与所述数字电源IC的TFT开启电压输出端子电性连接，另一端与三极管的发射极电性连接；
所述三极管的基极与所述数字电源IC的三极管基极电压输出端子电性连接，发射极与第二电阻的一端电性连接，集电极接地；
所述第二电阻的一端与第一电阻的另一端电性连接，另一端接地；
所述TFT开启电压输出端子输出TFT开启电压，三极管基极电压输出端子输出三极管基极电压，所述三极管基极电压为可调电压；
其中，通过调节所述三极管基极电压的大小，来调节TFT开启电压的削角波形；
其中，所述数字电源IC上设有I2C接口，三极管基极电压输出端子输出的三极管基极电压通过I2C接口来调节。
本发明的有益效果：本发明提供了一种可调节削角波形的削角电路，包括数字电源IC、第一电阻、第二电阻、及三极管；可通过调节数字电源IC输出的三极管基极电压的大小来调节削角波形，以提升画面品质，相比 于现有技术，不需要通过焊接电阻即可完成削角波形的调整，操作简单，工作效率高。本发明还提供一种削角波形的调节方法，能够方便快捷的调节削角波形，提升工作效率，改善画面品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的削角电路的电路图；
图2为图1所示电路的削角波形图；
图3为本发明的可调节削角波形的削角电路的电路图；
图4为本发明的可调节削角波形的削角电路中三极管基极电压为VB1时的削角波形图；
图5为本发明的可调节削角波形的削角电路中三极管基极电压为VB2时的削角波形图；
图6为本发明的削角波形的调节方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明提供一种可调节削角波形的削角电路，包括：数字电源IC1、第一电阻R1、第二电阻R2、及三极管Tr1；
所述数字电源IC1包括：TFT开启电压输出端子11、以及三极管基极电压输出端子12；
所述第一电阻R1一端与所述数字电源IC1的TFT开启电压输出端子11电性连接，另一端与三极管Tr1的发射极e电性连接；
所述三极管Tr1的基极b与所述数字电源IC1的三极管基极电压输出端子12电性连接，发射极e与第二电阻R2的一端电性连接，集电极c接地；
所述第二电阻R2的一端与第一电阻R1的另一端电性连接，另一端接地；
所述TFT开启电压输出端子11输出TFT开启电压VGH，三极管基极电压输出端子12输出三极管基极电压VB，所述三极管基极电压VB为可 调电压。
具体地，请参阅图4和图5，当开始对TFT开启电压VGH进行削角时，三极管发射极的电压小于所述三级管基极电压VB，此时，三极管Tr1导通，削角电阻的阻值为第一电阻R1的阻值，TFT开启电压VGH经由第一电阻R1和三极管Tr1接地放电，放电速度较快，削角波形较陡，当放电至三极管发射极的电压等于三级管基极电压VB时，三极管Tr1关闭，削角电阻的阻值为第一电阻R1和第二电阻R2的阻值之和，放电速度较慢，削角波形较平缓。例如，确定三极管基极电压VB为10V时，TFT开启电压VGH会以第一电阻R1和三极管Tr1的路径以较快的速度放电至10V，随后再从10V以第一电阻R1和第二电阻R2的路径以较慢的速度继续放电，也即所述三极管基极电压VB越小，三极管Tr1的导通时间越长，TFT开启电压VGH的削角波形越陡，放电速度越快，从而可以通过I2C接口来调节数字电源IC1的三极管基极电压输出端子12输出的三极管基极电压VB，控制三级管Tr1的导通时间，进而改变削角波形，控制TFT开启电压VGH的放电速度，例如图4和图5所示，两种不同的三极管基极电压下的削角波形，其中VB1大于VB2，图4中的TFT开启电压VGH的放电速度比图5中TFT开启电压VGH的放电速度慢，相同时间T内的放电量比图5低，TFT开启电压VGH放电后的最低点高于图5中TFT开启电压VGH放电后的最低点。
请参阅图6，本发明还提供一种削角波形的调节方法，包括如下步骤：
步骤1、请参阅图3，提供一削角电路，包括：数字电源IC1、第一电阻R1、第二电阻R2、及三极管Tr1；
所述数字电源IC1包括：TFT开启电压输出端子11、以及三极管基极电压输出端子12；
所述第一电阻R1一端与所述数字电源IC1的TFT开启电压输出端子11电性连接，另一端与三极管Tr1的发射极e电性连接；
所述三极管Tr1的基极b与所述数字电源IC1的三极管基极电压输出端子12电性连接，发射极e与第二电阻R2的一端电性连接，集电极c接地；
所述第二电阻R2的一端与第一电阻R1的另一端电性连接，另一端接地；
步骤2、调节数字电源IC1的三极管基极电压输出端子12输出的三极管基极电压VB的大小，控制三极管Tr1的导通时间，改变TFT开启电压VGH的削角波形。
具体的，所述步骤1中提供的削角电路对TFT开启电压削角过程中， 当三极管发射极的电压小于所述三级管基极电压VB时，三极管Tr1导通，削角电阻的阻值为第一电阻R1的阻值；当三极管发射极的电压大于所述三级管基极电压VB时，三极管Tr1关闭，削角电阻的阻值为第一电阻R1和第二电阻R2的阻值之和。例如图4和图5所示，两种不同的三极管基极电压下的削角波形，其中VB1大于VB2，则图4中的TFT开启电压VGH的放电速度比图5中TFT开启电压VGH的放电速度慢，相同时间T内的放电量比图5低，TFT开启电压VGH放电后的最低点高于图5中TFT开启电压VGH放电后的最低点。
进一步地，所述步骤2中通过I2C接口来调节数字电源IC1的三极管基极电压输出端子12输出的三极管基极电压VB，操作简单方便。
综上所述，本发明提供了一种可调节削角波形的削角电路，包括数字电源IC、第一电阻、第二电阻、及三极管；可通过调节数字电源IC输出的三极管基极电压的大小来调节削角波形，以提升画面品质，相比于现有技术，不需要通过焊接电阻即可完成削角波形的调整，操作简单，工作效率高。本发明还提供一种削角波形的调节方法，能够方便快捷的调节削角波形，提升工作效率，改善画面品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种可调节削角波形的削角电路，包括：数字电源IC、第一电阻、第二电阻、及三极管；
    所述数字电源IC包括：TFT开启电压输出端子、以及三极管基极电压输出端子；
    所述第一电阻一端与所述数字电源IC的TFT开启电压输出端子电性连接，另一端与三极管的发射极电性连接；
    所述三极管的基极与所述数字电源IC的三极管基极电压输出端子电性连接，发射极与第二电阻的一端电性连接，集电极接地；
    所述第二电阻的一端与第一电阻的另一端电性连接，另一端接地；
    所述TFT开启电压输出端子输出TFT开启电压，三极管基极电压输出端子输出三极管基极电压，所述三极管基极电压为可调电压。
  2. 如权利要求1所述的可调节削角波形的削角电路，其中，通过调节所述三极管基极电压的大小，来调节TFT开启电压的削角波形。
  3. 如权利要求2所述的可调节削角波形的削角电路，其中，对TFT开启电压削角过程中，当三极管发射极的电压小于所述三级管基极电压时，三极管导通，削角电阻的阻值为第一电阻的阻值。
  4. 如权利要求2所述的可调节削角波形的削角电路，其中，对TFT开启电压削角过程中，当三极管发射极的电压大于所述三级管基极电压时，三极管关闭，削角电阻的阻值为第一电阻和第二电阻的阻值之和。
  5. 如权利要求1所述的可调节削角波形的削角电路，其中，所述数字电源IC上设有I2C接口，三极管基极电压输出端子输出的三极管基极电压通过I2C接口来调节。
  6. 一种削角波形的调节方法，包括如下步骤：
    步骤1、提供一削角电路，包括：数字电源IC、第一电阻、第二电阻、及三极管；
    所述数字电源IC包括：TFT开启电压输出端子、以及三极管基极电压输出端子；所述第一电阻一端与所述数字电源IC的TFT开启电压输出端子电性连接，另一端与三极管的发射极电性连接；所述三极管的基极与所述数字电源IC的三极管基极电压输出端子电性连接，发射极与第二电阻的一端电性连接，集电极接地；所述第二电阻的一端与第一电阻的另一端电性连接，另一端接地；
    步骤2、调节数字电源IC的三极管基极电压输出端子输出的三极管基极电压的大小，控制三极管的导通时间，改变TFT开启电压的削角波形。
  7. 如权利要求6所述的削角波形的调节方法，其中，所述步骤1中提供的削角电路对TFT开启电压削角过程中，当三极管发射极的电压小于所述三级管基极电压时，三极管导通，削角电阻的阻值为第一电阻的阻值。
  8. 如权利要求6所述的削角波形的调节方法，其中，所述步骤1中提供的削角电路对TFT开启电压削角过程中，当三极管发射极的电压大于所述三级管基极电压时，三极管关闭，削角电阻的阻值为第一电阻和第二电阻的阻值之和。
  9. 如权利要求6所述的削角波形的调节方法，其中，所述步骤2中通过I2C接口来调节数字电源IC的三极管基极电压输出端子输出的三极管基极电压。
  10. 一种可调节削角波形的削角电路，包括：数字电源IC、第一电阻、第二电阻、及三极管；
    所述数字电源IC包括：TFT开启电压输出端子、以及三极管基极电压输出端子；
    所述第一电阻一端与所述数字电源IC的TFT开启电压输出端子电性连接，另一端与三极管的发射极电性连接；
    所述三极管的基极与所述数字电源IC的三极管基极电压输出端子电性连接，发射极与第二电阻的一端电性连接，集电极接地；
    所述第二电阻的一端与第一电阻的另一端电性连接，另一端接地；
    所述TFT开启电压输出端子输出TFT开启电压，三极管基极电压输出端子输出三极管基极电压，所述三极管基极电压为可调电压；
    其中，通过调节所述三极管基极电压的大小，来调节TFT开启电压的削角波形；
    其中，所述数字电源IC上设有I2C接口，三极管基极电压输出端子输出的三极管基极电压通过I2C接口来调节。
  11. 如权利要求10所述的可调节削角波形的削角电路，其中，对TFT开启电压削角过程中，当三极管发射极的电压小于所述三级管基极电压时，三极管导通，削角电阻的阻值为第一电阻的阻值。
  12. 如权利要求10所述的可调节削角波形的削角电路，其中，对TFT开启电压削角过程中，当三极管发射极的电压大于所述三级管基极电压时，三极管关闭，削角电阻的阻值为第一电阻和第二电阻的阻值之和。
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