Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
  • H03K3/03—Astable circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
  • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
  • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
  • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
  • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
  • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
  • H03B5/26—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator frequency-determining element being part of bridge circuit in closed ring around which signal is transmitted; frequency-determining element being connected via a bridge circuit to such a closed ring, e.g. Wien-Bridge oscillator, parallel-T oscillator
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
  • H03K3/03—Astable circuits
  • H03K3/0315—Ring oscillators
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/01—Shaping pulses
  • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
  • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
  • H03K5/065—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements using dispersive delay lines
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/125—Discriminating pulses
  • H03K5/1252—Suppression or limitation of noise or interference
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Definitions

• the present disclosure relates generally to oscillators, and more particularly to an RC oscillator having a variable frequency.
• RC oscillator circuits In the design of digital logic circuits, large scale integration techniques have brought about the construction of large numbers of components being fabricated on a single chip of silicon. Digital circuitry typically require various clock signals to provide a time base for their operation. Such clock signals are generated by oscillator circuits, which come in a variety of designs. One such design is based on a resistor/capacitor (RC) network, referred to as an RC oscillator.
• RC resistor/capacitor
• Conventional RC oscillators can provide a low-cost timing source. Furthermore, conventional RC oscillators avoid the use of inductors (see, for example, FIG. 5), which can be difficult to fabricate on integrated circuits. RC oscillators may allow for generation of variable frequencies by changing the resistance R, or capacitance C to increase their utility.
• an oscillator circuit having a programmable output frequency may comprise a first delay section having an input end and an output end.
• the first delay section may have a negative gain between the input end and the output end and a variable delay that is set by a control signal provided to the first delay section.
• the oscillator may further comprise a second delay section electrically connected in series with the first delay section.
• the second delay section may have an input end and an output end and a negative gain between the input end and the output end.
• the second delay section may have a fixed delay.
• the oscillator may further comprise a circuit output for an output signal having a frequency that is a function of the delay due to the first delay section and the second delay section.
• the circuit output may comprise the output end of the second delay section.
• the first delay section may include a first RC network comprising a resistor and a variable capacitor, and a second RC network connected in series with the first RC network and also comprising a resistor and a variable capacitor.
• a delay of the first delay section may be determined based on capacitances of the variable capacitors of the first and second RC networks.
• the control signal may set the capacitance of the variable capacitor of the first RC network, and an additional control signal may set the capacitance of the variable capacitor of the second RC network.
• the first delay section may include an RC network comprising a resistor and a variable capacitor.
• the control signal provided to the first delay section may set a capacitance of the variable capacitor of the first RC network.
• a delay of the first delay section may be based on the capacitance of the variable capacitor.
• the first delay section may include a plurality of switched capacitors, wherein the control signal selectively sets each of the plurality of switched capacitors to an ON state or an OFF state.
• the control signal when a switched capacitor is in the ON state, the switched capacitor has a node electrically connected to a DC voltage. In other embodiments, when a switched capacitor is in the ON state, the switched capacitor has a node electrically connected to ground potential.
• the control signal may be an n-bit word.
• the second delay section may include an RC network comprising a fixed value resistive component and a fixed value capacitive component. At least one node of the fixed value capacitive component may swing above supply voltage of the oscillator circuit. In some embodiments, the at least one node of the fixed value capacitive component may swing below ground potential.
• the first delay section may be electrically connected to the circuit output via the second delay section in a feedback loop.
• an oscillator circuit may comprise a first delay section having an input end and an output end.
• the first delay section may have a negative gain between the input end and the output end.
• the first delay section may include a first RC network comprising a resistor and a variable capacitor and a second RC network connected in series with the first RC network and comprising a resistor and a variable capacitor.
• the oscillator circuit may include at least one control signal provided to at least the variable capacitor of the first RC network to set a delay of the first delay section.
• the oscillator circuit may include a second delay section electrically connected in series with the first delay section.
• the second delay section may have an input end and an output end, and a negative gain between the input end and the output end.
• the second delay section may have a fixed delay.
• the oscillator circuit may include a circuit output for an output signal having a frequency that is a function of the delay due to the first delay section and the second delay section.
• the circuit output may comprise the output end of the second delay section.
• each of the variable capacitors in the first and second RC networks in the first delay section may comprise a plurality of switched capacitors, wherein the control signal provided to the programmable delay stage selectively sets each of the plurality of switched capacitors to an ON state or an OFF state.
• the control signal provided to the programmable delay stage selectively sets each of the plurality of switched capacitors to an ON state or an OFF state.
• a node of the switched capacitor when a switched capacitor is in the ON state, a node of the switched capacitor is electrically connected to a DC voltage. In other embodiments, when a switched capacitor is in the ON state, a node of the switched capacitor is electrically connected to ground potential.
• control signal may be provided to the variable capacitor in the first RC network.
• the oscillator circuit may further include an additional control signal provided to the variable capacitor in the second RC network.
• the first delay section may further comprise at least a third RC network connected in series with the second RC network and comprising a resistor and a variable capacitor.
• the second delay section may comprise an RC network comprising a fixed value resistive component and a fixed value capacitive component,. At least one node of the capacitive component may swings above supply voltage of the oscillator circuit. The at least one node of the capacitive component may further swing below ground potential.
• an oscillator circuit may comprise a first inverter stage and a second inverter stage having an input electrically connected to an output of the first inverter stage. The second inverter stage may have an output for an output signal of the oscillator circuit.
• the oscillator circuit may comprise an RC circuit comprising a resistor element connected to a capacitive element.
• the RC circuit may be electrically connected between the input and output of the second inverter stage.
• the oscillator circuit may comprise at least one variable delay stage having a delay that is set by a control signal provided to the at least one variable delay stage.
• the at least one variable delay stage may be electrically connected between a node in the RC circuit that connects the resistor element and the capacitor element and an input of the first inverter stage.
• a frequency of the output signal may be dependent on a delay of the at least one variable delay stage.
• the oscillator circuit may further comprise at least one additional variable delay stage connected in series with the at least one variable delay stage, and having a delay that is dependent on a control signal provided to the at least one additional variable delay stage.
• a voltage level at the node that connects the resistor element and the capacitor element may swings above and below a supply voltage of the oscillator circuit and above and below a ground potential during operation of the oscillator circuit.
• the at least one variable delay stage may comprise a resistor and a variable capacitor, wherein the control signal provided to the at least one variable delay stage sets a capacitance of the variable capacitor.
• the delay of the at least one variable delay stage may be dependent on the capacitance of the variable capacitor.
• the at least one variable delay stage may comprise a plurality of switched capacitors, wherein the control signal sets each of the plurality of switched capacitors to an ON state or an OFF state.
• the control signal sets each of the plurality of switched capacitors to an ON state or an OFF state.
• a node of the switched capacitor is electrically connected to a DC voltage or to ground potential.
• At least one node of the capacitive element of the RC circuit swings above supply voltage of the oscillator circuit and below ground potential.
• FIGs. 1 A and IB show oscillator circuits in accordance with the present disclosure.
• FIG. 2 shows an oscillator circuit in accordance with the present disclosure.
• FIG. 2A shows details of a variable capacitor in accordance with the present disclosure.
• FIG. 3 shows an oscillator circuit in accordance with the present disclosure.
• FIG. 3 A shows details of a variable capacitor in accordance with the present disclosure.
• FIGs. 4A and 4B illustrate alternate embodiments in accordance with the present disclosure.
• FIG. 5 shows an example of a conventional RC oscillator.
• FIG. 1A shows an electronic circuit 10 in accordance with an embodiment of the present disclosure.
• the electronic circuit 10 may include an oscillator circuit 102 and electronic circuitry 12.
• the oscillator circuit 102 may have an output 1 14 for an output signal (e.g., a clock signal 132), which for example, may be used by the electronic circuitry 12.
• the electronic circuit 10 may be a component in an electronic device (not shown).
• the oscillator circuit 102 may be powered by a source VDD and the electronic circuitry 12 may be powered by a source VDDL
• VDD may be the same as VDDI, and in other embodiments VDD may be different from VDDL
• the oscillator 102 may comprise a first delay section 104 and a second delay section 106 electrically connected in series with the first delay section 104.
• the first delay section 104 may be characterized by a negative gain between the input end of the first delay section 104 and the output end of the first delay section 104.
• the first delay section 104 may include a delay stage 126 connected in series with an inversion stage 122.
• the first delay section 104 may be further characterized by having a variable delay.
• negative gain we mean that a given positive change (say of the voltage) at the input end produces a negative change (of the voltage) at the output end.
• the input end of the first delay section 104 may be defined by the input side of delay stage 126.
• the output end of the first delay section 104 may be defined by the output of the inversion stage 122. It will be clear from the discussion below that the gain of delay stage 126 is positive.
• the inversion stage 122 has a negative gain, and so the first delay section 104 has a negative gain.
• the inversion stage 122 may comprise a single inverter as shown in FIG. 1 A. In other embodiments, the inversion stage 122 may comprise any odd number of inverters, and in general any suitable circuitry that can provide a negative gain.
• the second delay section 106 may likewise be characterized by a negative gain between its input end and its output end.
• the second delay section 106 may include an inversion stage 124 connected across (in parallel with) a delay stage 128; for example, at terminals a and ⁇ of delay stage 128.
• the input and output ends of the second delay section 106 may be the input and output, respectively, of the inversion stage 124.
• the inversion stage 124 has a negative gain, and so the second delay section 106 has a negative gain.
• the inversion stage 124 may comprise a single inverter as shown in FIG. 1 A. In other embodiments, the inversion stage 124 may comprise any odd number of inverters, and in general any suitable circuitry that can provide a negative gain.
• the first delay section 104 may be connected to the output 114 via the second delay section 106 to define a feedback loop around which oscillations can propagate to produce the clock signal 132.
• the frequency fci_0CK of the clock signal 132 is generally a function of the delay ⁇ of the delay stage 128 and the delay ⁇ of the delay stage 126.
• the clock signal 132 may be tapped out or otherwise produced at the output of the second inversion stage 124, as depicted in FIG. 1 A. However, it is understood that the clock signal 132 may be obtained at other points 114' within the loop.
• the delay stage 128 may comprise an RC network comprising a resistor R and a capacitor C. Terminal a of the delay stage 128 may be connected to the resistor R and capacitor C may be connected to terminal ⁇ . Terminal ⁇ of the delay stage 128 may be connected to a node Vx to which resistor R and capacitor C are connected.
• the delay n of the RC network is generally a function of a time constant (sometimes referred to as the RC time constant) defined as R x C , which represent respective element values of resistor R and capacitor C.
• resistor R and capacitor C may be fixed-value elements. Accordingly, the delay stage 128 may provide a fixed delay.
• node Vx is not connected to ground potential, as compared to other elements in the oscillator circuit 102 (e.g., inversion stages 122, 124, delay stage 126). Rather, node Vx is a "floating" node, which means that the potential at node Vx may vary as the voltage across capacitor C varies during operation of the oscillator circuit 102. For example, during operation the voltage at node Vx may swing above and below the supply voltage in one half of a cycle of the clock signal 132 at the output 114, and may swing above and below ground potential in the other half of the cycle. This aspect of the present disclosure is discussed below.
• the delay stage 126 may have a variable (tunable, programmable) delay.
• the delay stage 126 may receive a selector input signal 112 to select or otherwise set the delay X2 of the delay stage 126.
• the selector input 112 may be a digital code.
• the selector input 112 may change in order to select a different delay X2 for the delay stage 126 during operation of the electronic circuit 10.
• the selector input 112 may provide different digital codes to the delay stage 126, thus allowing for on-the-fly selection of a delay X2.
• the frequency of oscillation in oscillator circuit 102 may be controlled according to the delays xi and X2.
• the delay xi may be determined, for example, during the design phase by selecting appropriate element values for resistor R and capacitor C in the delay stage 128.
• the delay of X2 may be set by providing a suitable selector input 112 to the delay stage 126. Since the delay X2 of the delay stage 126 may be set on-the-fly, the frequency of clock signal 132 produced by oscillator circuit 102 may likewise be set on-the-fly, namely by providing a suitable selector input 112 to the delay stage 126.
• FIG. 2 shows additional details for delay stage 126 of the first delay section 104 in accordance with some embodiments of the present disclosure.
• the delay stage 126 may comprise a high input impedance non-inverting input buffer 202 and a variable RC network 204.
• the supply (not shown) for input buffer 202 may be the VDD supply provided to the delay stage 126, as illustrated in FIG. 1 A for example.
• the variable RC network 204 may comprise a resistor Ri and a variable capacitor Ci.
• the selector input 112 may be an n-bit signal bus that can be provided to the variable capacitor Ci to select or otherwise set a capacitance for the variable capacitor Ci.
• the delay X2 of delay stage 126 may be determined based on a time constant defined as R x C , which are respective values of resistor Ri and variable capacitor Ci. The delay X2 may therefore be set depending on the capacitance setting of variable capacitor Ci.
• the delay stage 126 may employ a tunable current source to charge a fixed capacitor.
• the delay stage 126 may use a current starved inverter with a tunable current source and/or a tunable capacitor, and so on.
• FIG. 2A shows additional details of the variable capacitor Ci .
• the variable capacitor Ci may include a set of n fixed value switched capacitive elements C x .
• the capacitive elements C x may be connected in parallel with each other.
• each capacitive element C x may have a connection between resistor Ri and a ground potential connection via a corresponding switch Mo - M n -i . It will be appreciated that in other embodiments, the capacitive elements C x may be arranged in connection topologies other than in parallel.
• the capacitive elements C x may be realized using any semiconductor technology suitable for a given application of the oscillator circuit 102.
• capacitive elements C x may be PN junction capacitors, MOSFET gate capacitors, metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and so on.
• the capacitive elements C x may be based on the same semiconductor technology, or they may be based on different technologies.
• each of the capacitive elements C x may have the same capacitance. In other embodiments, the capacitive elements C x may have different capacitances.
• the capacitive elements C x may be selectively switched to ground potential via a set of corresponding switches Mo - M n -i .
• the switches Mo - M n -1 may be any suitable switching device.
• the switches Mo - M n -i may be semiconductor switches such as MOS transistors shown in FIG. 2A, for instance; although in other embodiments other transistor technologies or designs may be used, such as FETs for example.
• MOS transistors shown in FIG. 2A, for instance; although in other embodiments other transistor technologies or designs may be used, such as FETs for example.
• all the switches Mo - M n -i may be based on the same technology, or they may be based on several different technologies.
• Each of the n signal lines that comprise the selector input 1 12 may be connected to a respective one of the switches Mo - M n -i .
• each signal line of the selector input 1 12 is connected to a respective gate terminal of the switches Mo - M n -i .
• the input to selector input 1 12 may be generated by digital logic or other suitable circuitry associated with the oscillator circuit 102 or with electronic circuit 10 (FIG. 1 A).
• the nodes of capacitive elements C x in FIG. 2A are not floating nodes as explained above in connection with node Vx. Rather, in some embodiments, the nodes of capacitive elements C x may be electrically connected to or otherwise referenced to ground potential. In other embodiments, the capacitive elements C x may be electrically connected to or otherwise referenced to a DC voltage; e.g., a supply voltage such as VDD. More generally, one of skill in the art will appreciate that the capacitive elements C x may be electrically connected to any suitable low impedance node.
• any one or more of the n signal lines in the selector input 112 may be asserted to turn ON their corresponding switches Mo - M n -i , and hence the corresponding capacitive element C x .
• a switch e.g., Mo
• Mo that is in the ON state connects its corresponding capacitive element C x to the RC network 204 (switched on), and conversely a switch that is in the OFF state disconnects its corresponding capacitive element C x from the RC network 204
• the capacitance of variable capacitor Ci may be computed as the sum of the switched- on capacitive elements.
• the delay X2 of the delay stage 126 may be set depending on which capacitive elements are switched on or switched off in the RC network 204.
• resistor Ri may be a fixed value element such as shown in FIG. 2A. In other embodiments (not shown), resistor Ri may be a variable resistor and capacitor Ci may be a fixed value element. In still other embodiments, resistor Ri may be a variable resistor and capacitor Ci may be a variable capacitor.
• the first delay section 104 may comprise an additional delay stage 326 connected in series with the delay stage 126.
• An input inverter 322 may be provided to couple the oscillations produced at the output of delay stage 126 to the input of the additional delay stage 326; in other words, the inverter 322 keeps the oscillations going.
• An output inverter 324 may be provided to maintain a net negative gain between the input end and the output end of the first delay section 104.
• the supply (not shown) for input inverter 322 and output inverter 324 may be the same VDD supply provided to the delay stage 126, as illustrated in FIG. 1 A for example.
• the additional delay stage 326 can improve the noise performance of oscillator circuit 102.
• the additional delay stage 326 may include a variable RC network 304 comprising a resistor R2 and a variable capacitor C2.
• a selector input 312 may comprise an m-bit signal bus that can be provided to the variable capacitor C2 to select or otherwise set a capacitance for the variable capacitor C2.
• the additional delay stage 326 may provide a delay 13 that may be determined based on a time constant defined as R x C , which are respective values of resistor f3 ⁇ 4 and variable capacitor C2. The delay 13 provided by additional delay stage 326 may therefore be set depending on the capacitance setting of variable capacitor C2.
• variable capacitor C2 may comprise a set ofm fixed value switched capacitive elements C y .
• the capacitive elements C y may be connected in parallel with each other.
• each capacitive element C y may have a connection between resistor R2 and a ground potential connection via a corresponding switch Mo - M m -1. It will be appreciated that in other embodiments, the capacitive elements C y may be connected in connection topologies other than in parallel.
• the capacitive elements C y may be realized using any semiconductor technology suitable for a given application of the oscillator circuit 102.
• capacitive elements C y may be PN junction capacitors, MOSFET gate capacitors, metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and so on.
• the capacitive elements C y may be based on the same semiconductor technology, or they may be based on different technologies.
• each of the capacitive elements C y may have the same capacitance. In other embodiments, the capacitive elements C y may different capacitances.
• the capacitive elements C y may be selectively switched to ground potential via a set of corresponding switches Mo - M m -1.
• the switches Mo - M m -1 may be any suitable switching device.
• the switches Mo - M m -1 may be semiconductor switches such as P P transistors shown in FIG. 3 A, for example.
• all the switches Mo - Mm-1 may be based on the same technology, or may they may be based on different technologies.
• Each of the m signal lines that comprise the selector input 312 may be connected to a respective one of the switches Mo - M m -1.
• the input to selector input 312 may be generated by digital logic or other suitable circuitry associated with the oscillator circuit 102 or with electronic circuit 10 (FIG. 1A).
• the nodes of capacitive elements C y in FIG. 3 A are not floating. Rather, the nodes of capacitive elements C y may be electrically connected to ground potential.
• the capacitive elements C Y may be electrically connected to a DC voltage; (e.g., supply VDD). More generally, the capacitive elements C y may be electrically connected to any suitable low impedance node.
• any one or more of the m signal lines in the selector input 312 may be asserted to turn ON their corresponding switches Mo - M M -1 .
• a switch e.g., Mo
• Mo that is in the ON state connects its corresponding capacitive element (switched on) to the RC network 304, and conversely a switch that is in the OFF state disconnects its corresponding capacitive element (switched off) from the RC network 304.
• the capacitive elements C y are connected in parallel, as shown in FIG. 3 A for example, the capacitance of variable capacitor C2 may be computed as the sum of the switched-on capacitive elements.
• the delay 13 of the additional delay stage 326 may be set depending on which capacitive elements C y are switched on or switched off in the RC network 304.
• resistor R2 may be a fixed value element such as shown in FIG. 3 A. In other embodiments (not shown), resistor R2 may be a variable resistor and capacitor C2 may be a fixed value element. In still other embodiments (not shown), resistor R2 may be a variable resistor and capacitor C2 may be a variable capacitor.
• the selector inputs 112, 312 of respective delay stages 126, 326 may receive the same selection input; e.g., the same n-bit code may be provided to each selector input 112, 312. In other embodiments, each selector input 112, 312 may receive different selection inputs.
• the frequency of oscillation in oscillator circuit 102 may be controlled according to the delays ⁇ , X2, and 13.
• the delay ⁇ in delay stage 128 may be fixed for resistor R and capacitor C.
• the delay 12 of the delay stage 126 may be set by asserting appropriate bit lines that comprise selector input 112 for the delay stage 126.
• the delay T3 in delay stage 326 may be set by asserting appropriate bit lines that comprise selector signal 312. Accordingly, the frequency of the clock signal 132 may be selected as a function of the variable delays 12 and 13.
• the first delay section 104 may comprise several additional delay stages connected in series. FIG.
• the first delay section 104 may comprise delay stage 126 and two additional delay stages 426a, 426b.
• Inverters 422a, 422b may be provided to couple the signal between delay stages.
• inverter 422a may couple the signal between delay stage 126 and delay stage 422a
• inverter 422b may couple the signal between delay stage 422a and delay stage 422b. Note that inverters 422a, 422b, 122 that comprise the first delay section 104 provide a net negative gain.
• FIG. 4B is a schematic representation of an oscillator circuit 102b comprising a first delay section 102 that has three additional delay stages 426a, 426b, 426c and inverters 422a, 422b, 422c, 422d.
• the inverters 422a - 422c couple the signal among delay stages 126 and 426 - 426c. It can be seen that the inverter 424 provides the first delay section 104 with a net negative gain.
• a conventional RC oscillator design such as shown in FIG. 5, has many desirable properties. Such designs are generally insensitive to variations in supply voltage. The design is relatively simple, having few components. As a results these RC oscillators can achieve low noise performance. Some designs, for example, may achieve noise levels only 3dB above the theoretical low limit. Because of their relatively simple designs, RC oscillators have smaller footprints on the IC chip.
• a basic RC oscillator design comprises two inverters (e.g., inversion stages 122, 124) and an RC network comprising a resistor R and a capacitor C.
• the RC network provides a delay that sets an operating frequency of the RC oscillator. Accordingly, varying the elements values of either R or C can serve to provide programmability in the operating frequency of the RC oscillator.
• the method of making R or C may not be practical. Programmable resistors can be difficult to provide. High programmability requires the ability to modify the total R in small increments.
• Programmable capacitors can be difficult, since the capacitor C is a "floating" capacitor because of the behavior at node Vx.
• the node Vx is a floating node because the voltage at node Vx may swing above and below the supply voltage in one half of a cycle of the output and above and below ground potential in the other half of the cycle.
• Programmable capacitors typically comprise a bank of switched capacitor elements. When the source (or drain) of a switch is connected at the node Vx, the state of the switch can become forward biased during portions of the cycle and conduct when it is supposed to be in an OFF (non-conducting) state.
• a delay stage 126 can be provided separately from the RC network 128.
• the delay stage 126 may be grounded so that operation of the delay stage 126 is significantly less affected by voltage swings in the circuit.

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• Physics & Mathematics (AREA)
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• Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
• Pulse Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)

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