WO2017149957A1 - 信号出力回路 - Google Patents

信号出力回路 Download PDF

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Publication number
WO2017149957A1
WO2017149957A1 PCT/JP2017/001216 JP2017001216W WO2017149957A1 WO 2017149957 A1 WO2017149957 A1 WO 2017149957A1 JP 2017001216 W JP2017001216 W JP 2017001216W WO 2017149957 A1 WO2017149957 A1 WO 2017149957A1
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WIPO (PCT)
Prior art keywords
output
circuit
slope
signal
output circuit
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PCT/JP2017/001216
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English (en)
French (fr)
Japanese (ja)
Inventor
典正 岡
博史 川合
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株式会社デンソー
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/94—Generating pulses having essentially a finite slope or stepped portions having trapezoidal shape
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

  • This disclosure relates to a signal output circuit that outputs a signal corresponding to the level of a control signal.
  • slope control is performed to control the rising and falling slopes (hereinafter referred to as slope) of an output signal for the purpose of suppressing radiation noise.
  • the slope control is generally performed by charging / discharging a capacitor and obtaining a desired slope waveform using the terminal voltage of the capacitor.
  • the capacitor is connected between the drain and gate of the output transistor whose drain is connected to the signal output terminal, the apparent capacitance when viewed from the input side (hereinafter simply referred to as capacitance) due to the Miller effect. Also called). Therefore, a desired slope waveform can be obtained using a capacitor having a relatively small capacity. However, in this configuration, when noise is superimposed on the output terminal, the noise propagates to the internal circuit through the capacitor and may cause malfunction.
  • Patent Document 1 discloses a technique for preventing the above-described malfunction.
  • the internal node voltage and the internal node where the slope-controlled signal is generated and the output terminal for outputting the signal are connected without adding the current mirror circuit or the like. Make the output terminal voltage equal. With such a configuration, the occurrence of malfunction when noise is superimposed on the output terminal can be prevented while realizing slope control of the output signal.
  • the minimum operating voltage is increased by the threshold voltage Vt of the transistors configuring the current mirror circuit.
  • a communication driver for in-vehicle communication such as LIN (Local Interconnect Network)
  • LIN Local Interconnect Network
  • An object of the present disclosure is to provide a signal output circuit that can prevent malfunction due to noise superimposed on an output terminal while suppressing an increase in circuit scale and an increase in minimum operating voltage.
  • the signal output circuit controls the level of the control signal from the output terminal connected to one main terminal of the output transistor by controlling the driving of the output transistor based on the control signal input from the outside.
  • the output signal of the level according to is output.
  • the signal output circuit includes an output transistor and outputs an output signal, a pseudo output circuit whose configuration is at least partially similar to the output circuit, and an input node and an output node of the pseudo output circuit And a slope control circuit for controlling the slope of the output signal.
  • the pseudo output circuit includes a pseudo output transistor having a conduction control terminal connected to the input node and one main terminal connected to the output node.
  • the slope control circuit indirectly controls the slope of the output signal using the pseudo output circuit as follows. That is, the slope control circuit charges and discharges the feedback capacitor according to the level of the control signal. As a result, the output of the pseudo output circuit is slope-controlled.
  • the slope control circuit drives the output transistor using the voltage of the input node of the pseudo output circuit in which the output slope control is performed. Therefore, the signal of the output terminal connected to one main terminal of the output transistor, that is, the slope of the output signal is also controlled.
  • the output circuit and the pseudo output circuit are at least partially similar in configuration. Therefore, according to the above configuration, it is possible to obtain a slope waveform close to a slope waveform obtained by conventional control for charging / discharging the feedback capacitor provided between the input and output of the output circuit.
  • the pseudo output circuit since the pseudo output circuit is not connected to the output terminal, it can be composed of elements that operate with the same power supply as other internal circuits. Therefore, according to the above configuration, it is not necessary to use a high breakdown voltage element even when the output side voltage is higher than the operating voltage of the internal circuit. Furthermore, since the feedback capacitor is connected between the input / output nodes of the pseudo output circuit, a desired slope waveform can be obtained using a relatively small feedback capacitor due to the mirror effect. For this reason, according to the above configuration, an increase in circuit scale can be suppressed. Further, the above configuration does not require a current mirror circuit for determining the voltage of the output terminal, so that there is no restriction that the minimum operating voltage becomes high.
  • the pseudo output circuit has the same circuit format as the output circuit, and thus is substantially equivalent to a slope waveform obtained by conventional control for charging / discharging a feedback capacitor provided between the input and output of the output circuit. Slope waveform can be obtained.
  • FIG. 1 is a diagram showing a schematic configuration of a signal output circuit according to the first embodiment.
  • FIG. 2 is a diagram showing operation waveforms of each part of the signal output circuit
  • FIG. 3 is a diagram illustrating a schematic configuration of the signal output circuit according to the second embodiment.
  • FIG. 4 is a diagram illustrating a specific configuration example of the output monitor circuit.
  • FIG. 5 is a diagram illustrating a specific first configuration example of the slope adjusting unit
  • FIG. 6 is a diagram illustrating a specific second configuration example of the slope adjustment unit
  • FIG. 7 is a diagram illustrating a specific third configuration example of the slope adjustment unit
  • FIG. 1 is a diagram showing a schematic configuration of a signal output circuit according to the first embodiment.
  • FIG. 2 is a diagram showing operation waveforms of each part of the signal output circuit
  • FIG. 3 is a diagram illustrating a schematic configuration of the signal output circuit according to the second embodiment.
  • FIG. 4 is a diagram illustrating a specific configuration example of the output
  • FIG. 8 is a diagram showing a schematic configuration of a signal output circuit according to the third embodiment.
  • FIG. 9 is a diagram illustrating a schematic configuration of the signal output circuit according to the fourth embodiment.
  • FIG. 10 is a diagram showing the relationship between the input voltage Vc and the output voltage Vd of the pseudo output circuit.
  • FIG. 11 is a diagram illustrating a modification of the specific configuration of the output monitor circuit.
  • FIG. 12 is a diagram schematically showing the configuration of a signal output circuit in which the configuration of the output stage is changed
  • FIG. 13 is a diagram schematically showing the configuration of a signal output circuit without a buffer.
  • the signal output circuit 1 controls the drive of the N-channel type MOS transistor 3 based on the control signal IN inputted from the outside through the input terminal 2, thereby controlling the control signal IN from the output terminal 4.
  • the output signal OUT of a level corresponding to the level of is output.
  • the control signal IN and the output signal OUT are both digital signals that represent a binary value at two voltage levels: a high level (hereinafter referred to as H level) and a low level (hereinafter referred to as L level). Therefore, the level described above corresponds to a voltage level.
  • the transistor 3 corresponds to an output transistor, and its source is connected to the ground GND as a reference potential of the circuit, and its drain is connected to the output terminal 4 and to the power source VB via the resistor 5. .
  • the transistor 3 and the resistor 5 constitute an output circuit 6 having a circuit format of a common source amplifier circuit.
  • the power source VB is supplied from, for example, a battery (not shown), and the steady value of the voltage is about + 12V.
  • the driving of the transistor 3 is controlled by a slope control circuit 7. Therefore, the gate of the transistor 3 is connected via the buffer 8 to the node N1 to which the output of the slope control circuit 7 is given.
  • the drain of the transistor 3 corresponds to one main terminal, and the gate corresponds to a conduction control terminal.
  • the pseudo output circuit 9 is a common source amplifier circuit including a resistor 10 and an N channel type MOS transistor 11 connected in series between a power supply VDD and a ground GND. That is, the pseudo output circuit 9 has the same circuit format as the output circuit 6.
  • the power supply VDD is a power supply for operation of the signal output circuit 1, and the steady value of the voltage is about + 5V.
  • the transistor 11 corresponds to a pseudo output transistor, and has a gate connected to a node N1 that is an input node of the pseudo output circuit 9, and a drain connected to a node N2 that is an output node of the pseudo output circuit 9. .
  • the drain of the transistor 11 corresponds to one main terminal, and the gate corresponds to a conduction control terminal.
  • a capacitor 12 corresponding to a feedback capacitor is connected between the input and output of the pseudo output circuit 9, that is, between the nodes N1 and N2.
  • the signal output circuit 1 is configured as an integrated circuit.
  • the following measures are taken so that the pairing between corresponding elements is good. Has been made. That is, the resistors 5 and 10 and the transistors 3 and 11 are made of the same material and have the same structure, and are arranged close to each other.
  • the resistors 5 and 10 and the transistors 3 and 11 have substantially the same characteristics such as temperature characteristics. Further, the resistance values of the resistors 5 and 10 and the sizes of the transistors 3 and 11 are set so as to obtain a desired gradient with respect to the output signal OUT and the voltage Vd, as will be described later.
  • each element constituting the output circuit 6 and the structure and characteristics of each element constituting the pseudo output circuit 9 corresponding to each element are approximated. It should be noted that the output circuit 6 and the pseudo output circuit 9 only need to have the same circuit format in the main portion, and the structure, characteristics, circuit constants, and the like of each element constituting them may not necessarily be approximated.
  • the slope control circuit 7 includes a current source 13, a P-channel type MOS transistor 14, an N-channel type MOS transistor 15 and a current source 16 connected in series between the power supply VDD and the ground GND.
  • the drains of the transistors 14 and 15 are connected to the node N 1, and the gates are connected to the input terminal 2.
  • the input terminal 2 is supplied with a control signal IN from a control circuit (not shown) that controls the operation of the signal output circuit 1.
  • the slope control circuit 7 charges the capacitor 12 when the control signal IN is at the L level, and discharges the capacitor 12 when the control signal IN is at the H level.
  • the voltage Vd at the node N2 that is the output of the pseudo output circuit 9 is slope-controlled.
  • the slope control circuit 7 drives the transistor 3 using the voltage Vc of the node N1, which is an input node of the pseudo output circuit 9 in which the output slope control is performed. Therefore, the signal of the output terminal 4 connected to the drain of the transistor 3, that is, the slope of the output signal OUT is also controlled.
  • the slope waveform obtained by the conventional control for charging / discharging the feedback capacitor provided between the input and output of the output circuit 6 is substantially the same.
  • a slope waveform can be obtained.
  • the values of the currents I1 and I2 output from the current sources 13 and 16 are appropriately set according to a desired slope control amount, that is, a desired slope of the output signal OUT.
  • the output signal OUT becomes constant at the minimum value after the time t4 when the output signal OUT decreases and reaches the minimum value.
  • the voltage Vd becomes constant at the minimum value. Note that the minimum value of the output signal OUT and the minimum value of the voltage Vd are both approximately the GND potential. Since the voltage Vd becomes constant at the minimum value after the time point t5, the slope of the increase in the voltage Vc is as steep as the slope from the time point t1 to the time point t2.
  • the size of the transistors 3 and 11 and the resistance values of the resistors 5 and 10 are set so that the falling period Tb of the output signal OUT falls within this period Ta. Circuit constants have been determined. Specifically, since it is necessary to make the slope of the voltage Vd gentler than the slope of the output signal OUT, the size of the transistor 11 is made relatively small, and the resistance value of the resistor 10 is set relatively large. Yes.
  • the output signal OUT becomes constant at the maximum value.
  • the voltage Vd becomes constant at the maximum value. Note that the maximum value of the output signal OUT is approximately the voltage VB, and the maximum value of the voltage Vd is approximately the voltage VDD. Further, since the voltage Vd becomes constant at the maximum value after the time point t10, the slope of the voltage Vc becomes as steep as the slope from the time t6 to the time t7.
  • the signal output circuit 1 of the present embodiment described above the following effects can be obtained.
  • no intentionally provided element such as a capacitor 12 is connected between the output terminal 4 and the slope control circuit 7. Therefore, according to the present embodiment, even if noise is superimposed on the output terminal 4, there is no main path through which the noise is transmitted to the slope control circuit 7, so that noise affects the operation of the slope control circuit 7. A malfunction that the output signal OUT becomes an unintended level does not occur.
  • the pseudo output circuit 9 is not connected to the output terminal 4, the pseudo output circuit 9 is composed of a low withstand voltage element that operates with the same power supply VDD as the other circuits constituting the signal output circuit 1. Further, since the capacitor 12 is not connected to the output terminal 4, a capacitor having a lower withstand voltage can be used as compared with a conventional configuration in which a feedback capacitor is connected to the output terminal. Therefore, according to the signal output circuit 1, even when the output side voltage is higher than the operation voltage of the circuit as in this embodiment, it is not necessary to use a high breakdown voltage element. Furthermore, since the capacitor 12 is connected between the input and output of the pseudo output circuit 9, a desired slope waveform can be obtained by using the capacitor 12 having a relatively small capacity due to the mirror effect.
  • the configuration of the output stage is the same as the conventional basic configuration, and it is not necessary to add a current mirror circuit for determining the voltage of the output terminal 4, so that the minimum operating voltage is increased. There is no restriction such as.
  • the integrated circuit is designed so that the structure and characteristics of each element constituting the output circuit 6 and the structure and characteristics of each element constituting the pseudo output circuit 9 are approximated.
  • the pair property between the elements is good. For this reason, it is possible to reliably obtain the desired slope waveform of the output signal OUT despite the configuration in which the pseudo output circuit 9 is used to indirectly control the slope of the output signal OUT as in the present embodiment. It becomes possible.
  • the signal output circuit 1 has a configuration in which a buffer 8 is interposed between the node N1 and the gate of the transistor 3.
  • a buffer 8 is interposed between the node N1 and the gate of the transistor 3.
  • a parasitic capacitance exists between the drain and gate of the transistor 3. Since the transistor 3 is provided in the output stage, the transistor 3 has a large size for ensuring driving capability, and the parasitic capacitance is relatively large. Therefore, the noise superimposed on the output terminal 4 may propagate to an internal circuit such as the slope control circuit 7 through the parasitic capacitance.
  • the buffer 8 By providing the buffer 8 as described above, the noise propagation path through the parasitic capacitance is cut off, so that the transistor 3 malfunctions due to the noise and the output signal OUT becomes an unintended level. Can be prevented. In addition, by providing the buffer 8, the impedance of the gate node of the transistor 3 is lowered, and the noise amplitude can be suppressed.
  • the signal output circuit 21 includes an output monitor circuit 22 that detects the slope of the output signal OUT.
  • the output monitor circuit 22 can be configured by a comparison circuit 23 and a logic circuit 24, as shown in FIG.
  • the comparison circuit 23 composed of a comparator or the like compares the voltage value of the output signal OUT with a predetermined threshold value Vth, and outputs a comparison signal Sa indicating the comparison result.
  • the threshold value Vth is set to an intermediate voltage of the voltage VB, that is, VB / 2, for example.
  • the logic circuit 24 includes a counter circuit that operates according to the clock signal CLK. Using the counter circuit, the logic circuit 24 counts the time from when the control signal IN is inverted to when the comparison signal Sa is inverted. That is, the logic circuit 24 counts the time until the voltage value of the output signal OUT reaches the threshold value Vth from the minimum value or the maximum value. The logic circuit 24 detects the slope of the output signal OUT, that is, the slope from the counted time and the threshold value Vth, and outputs a detection signal Sb indicating the detection result.
  • the signal output circuit 21 includes a slope adjustment unit 26 that adjusts the slope of the output signal OUT to a desired value based on the slope detection result by the output monitor circuit 22.
  • a slope adjustment unit 26 that adjusts the slope of the output signal OUT to a desired value based on the slope detection result by the output monitor circuit 22.
  • a variable resistor 27 is connected between the source which is the other main terminal of the transistor 11 and GND.
  • the resistor 10, the transistor 11, and the variable resistor 27 constitute a pseudo output circuit 28 having a circuit format of a common source amplifier circuit.
  • the control unit 29 including a logic circuit adjusts the slope of the output signal OUT by changing the resistance value of the variable resistor 27.
  • the slope control circuit 30 includes variable current sources 31, 32 that output variable currents Ia, Ib instead of the current sources 13, 16 that output constant currents I1, I2. It has.
  • the control unit 33 composed of a logic circuit or the like adjusts the falling slope of the output signal OUT by changing the current value of the variable current Ia, and changes the rising value of the output signal OUT by changing the current value of the variable current Ib. Adjust the slope. When only one slope of the rising and falling edges of the output signal OUT needs to be adjusted, only one of the two current sources 13 and 16 that needs to be adjusted needs to be a variable current source.
  • a capacitor 34 which is a variable capacitor whose capacitance value is variable, is connected between the nodes N1 and N2.
  • the control unit 35 including a logic circuit adjusts the slope of the output signal OUT by changing the capacitance value of the capacitor 34.
  • the signal output circuit 21 of the present embodiment is configured so that the output monitor circuit 22 detects the slope of the output signal OUT, and the slope of the output signal OUT becomes a desired value based on the slope detection result by the output monitor circuit 22.
  • a slope adjusting unit 26 is provided for adjustment. That is, the signal output circuit 21 of the present embodiment has a function of feedback controlling the slope of the output signal OUT. Therefore, according to the present embodiment, it is possible to improve the accuracy of the slope control of the output signal OUT.
  • the output monitor circuit 22 is a simple circuit composed of a comparator, a counter circuit, etc., and does not have a complicated circuit configuration. Therefore, an increase in the circuit scale of the output monitor circuit 22 and consequently the circuit scale of the signal output circuit 21 can be suppressed.
  • the slope adjusting unit 26 it is possible to adjust the slope of the output signal OUT only by adding the variable resistor 27 to the source side of the transistor 11 of the pseudo output circuit 28. That is, according to the first configuration example, the slope adjustment function can be added while suppressing an increase in the circuit scale of the signal output circuit 21 to a low level.
  • the charge / discharge current for the capacitor 12 is variable, and the slope of the output signal OUT is adjusted by changing them, so that the accuracy of the slope adjustment can be improved. it can.
  • the charging current and discharging current for the capacitor 12 can be changed independently, so that the rising and falling slopes can be individually adjusted.
  • the configurations of the output circuit 6 and the pseudo output circuit 9 are the same as those in the first embodiment, are not changed, and have the same circuit configuration. Therefore, although the configuration is such that the pseudo output circuit 9 is used to indirectly control the slope of the output signal OUT, it is possible to reliably obtain the desired slope waveform of the output signal OUT.
  • the slope can be adjusted by making the capacitance of the capacitor 34 as the feedback capacitance variable. Therefore, the configurations of the output circuit 6 and the pseudo output circuit 9 are the same as those of the first embodiment, are not changed, and have the same circuit configuration. Therefore, according to the third configuration example, it is possible to reliably obtain the desired slope waveform of the output signal OUT, as in the second configuration example.
  • the signal output circuit 41 includes a pseudo output monitor circuit 42 that detects the slope of the voltage Vd at the node N ⁇ b> 2 that is the output node of the pseudo output circuit 9.
  • the pseudo output monitor circuit 42 can employ the same configuration as the output monitor circuit 22.
  • the threshold value Vth for comparison with the voltage value of the voltage Vd may be set to, for example, an intermediate voltage of the voltage VDD, that is, VDD / 2.
  • the signal output circuit 41 includes a slope adjusting unit 43 that adjusts the slope of the output signal OUT to a desired value based on the detection result of the slope by the output monitor circuit 22 and the pseudo output monitor circuit 42.
  • a specific configuration example for realizing the function as the slope adjustment unit 43 can employ the same configuration as the slope adjustment unit 26.
  • the slope of the output signal OUT becomes a desired value based on the detection result of the slope of the voltage Vd that is the output of the pseudo output circuit 9 in addition to the detection result of the slope of the output signal OUT. It comes to adjust. Therefore, according to the present embodiment, it is possible to adjust the slope so that the rising and falling periods of the output signal OUT are reliably within the period in which the voltage Vd changes, that is, the period in which the voltage Vc changes gradually. As a result, it is possible to obtain the advantages of the mirror effect more reliably.
  • the pseudo output monitor circuit 42 is a simple circuit composed of a comparator, a counter circuit, and the like, similar to the output monitor circuit 22, and does not have a complicated circuit configuration. Accordingly, it is possible to suppress an increase in the circuit scale of the pseudo output monitor circuit 42 and, consequently, the circuit scale of the signal output circuit 41.
  • the signal output circuit 51 illustrated in FIG. 9 corresponds to a configuration in which the slope adjustment unit 43 of the first configuration example is employed in the signal output circuit 41 of the third embodiment.
  • the signal output circuit 51 is used as an in-vehicle communication driver, for example, a LIN communication driver. Therefore, in this case, the input terminal 2 is a terminal to which transmission data TX corresponding to the control signal IN is given from the internal communication control circuit.
  • the output terminal 4 outputs a communication signal LIN corresponding to the output signal OUT, and is a terminal connected to a bus used for LIN communication.
  • bus-type communication such as LIN
  • the circuit connected to the bus and the length of the bus vary depending on the application. Therefore, when applied to the communication driver as in the signal output circuit 51, the magnitude of the load connected to the output terminal 4 is assumed to change to various values depending on the application. If the size of the load connected to the output terminal 4 changes, the slope of the output signal OUT may change accordingly as intended.
  • the relationship between the voltage Vd and the voltage Vc changes according to the resistance value Rv of the variable resistor 27. Specifically, as the resistance value Rv decreases, the slope of the voltage Vd becomes steeper and the timing at which the voltage Vd reaches the intermediate voltage is earlier. As the resistance value Rv increases, the slope of the voltage Vd becomes gentler and the timing at which the voltage Vd reaches the intermediate voltage is delayed.
  • the slope adjusting unit 43 changes the timing at which the voltage Vd reaches the intermediate voltage in consideration of such a relationship, so that the timing at which the voltage value of the output signal OUT reaches the intermediate voltage and the timing at which the voltage Vd reaches the intermediate voltage. Match.
  • the signal output circuit 51 of the present embodiment even when the output terminal 4, that is, the size of the load connected to the bus fluctuates, feedback control is performed so that the slope of the output signal OUT is desired. Is possible. Therefore, according to the signal output circuit 51 of the present embodiment, when applied to a communication driver for bus type communication such as LIN, regardless of the size of the load connected to the output terminal 4 or the length of the bus, It is possible to maintain a state where the slope of the output signal OUT satisfies a specified slope standard.
  • the output monitor circuit 22 is connected to the output terminal 4, and this portion may be a noise transmission path. Therefore, as a specific configuration of the output monitor circuit 22, the configuration shown in FIG. 11 may be adopted instead of the configuration shown in FIG.
  • the output monitor circuit 52 shown in FIG. 11 includes a low-pass filter circuit 53 (hereinafter referred to as an LPF circuit 53) interposed between the output terminal of the comparison circuit 23 and the logic circuit 24. Therefore, the noise superimposed on the output terminal 4 is attenuated by the LPF circuit 53. Therefore, when noise is superimposed on the output terminal 4, the noise does not reach the internal circuit such as the logic circuit 24 and the slope adjustment unit 43 at the level as it is, and the occurrence of malfunction due to the noise is prevented. Can do.
  • LPF circuit 53 low-pass filter circuit 53
  • the N-channel MOS transistor 3 is used as the output transistor and the drain thereof is pulled up by the resistor 5, that is, the signal output circuit having the low-side drive configuration.
  • the output circuit 64 is configured by the transistor 62 and the resistor 63.
  • the pseudo output circuit 65 may be configured to use a P-channel MOS transistor 66 as the pseudo output transistor and pull down its drain by a resistor 67 so as to have the same circuit format as the output circuit 64.
  • a configuration in which the buffer 8 is omitted may be employed as in the signal output circuit 71 shown in FIG.
  • the gate of the transistor 3 may be directly connected to the node N1.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
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PCT/JP2017/001216 2016-03-01 2017-01-16 信号出力回路 WO2017149957A1 (ja)

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JP2016038954A JP2017158011A (ja) 2016-03-01 2016-03-01 信号出力回路
JP2016-038954 2016-03-01

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Publication number Priority date Publication date Assignee Title
CN109714040A (zh) * 2018-12-21 2019-05-03 北京时代民芯科技有限公司 一种带反馈控制的cmos输出驱动电路
US20220239460A1 (en) * 2019-08-30 2022-07-28 Denso Corporation Communication apparatus
CN118112310A (zh) * 2024-04-30 2024-05-31 江苏帝奥微电子股份有限公司 一种电压正负斜率检测电路及其检测方法

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JPH07273631A (ja) * 1994-03-29 1995-10-20 Oki Micro Design Miyazaki:Kk 半導体集積回路
JPH09186568A (ja) * 1995-07-28 1997-07-15 Texas Instr Deutschland Gmbh 電気的負荷の電源供給回路に配置されたｍｏｓ電界効果トランジスタを駆動するための回路構造
JPH11346147A (ja) * 1998-06-02 1999-12-14 Nec Corp スルーレート出力回路
JP2011091888A (ja) * 2009-10-20 2011-05-06 Sharp Corp スイッチング制御回路及びこれを用いたスイッチング電源装置
JP2012114793A (ja) * 2010-11-26 2012-06-14 Denso Corp 通信ドライバ回路

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JPH07273631A (ja) * 1994-03-29 1995-10-20 Oki Micro Design Miyazaki:Kk 半導体集積回路
JPH09186568A (ja) * 1995-07-28 1997-07-15 Texas Instr Deutschland Gmbh 電気的負荷の電源供給回路に配置されたｍｏｓ電界効果トランジスタを駆動するための回路構造
JPH11346147A (ja) * 1998-06-02 1999-12-14 Nec Corp スルーレート出力回路
JP2011091888A (ja) * 2009-10-20 2011-05-06 Sharp Corp スイッチング制御回路及びこれを用いたスイッチング電源装置
JP2012114793A (ja) * 2010-11-26 2012-06-14 Denso Corp 通信ドライバ回路

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109714040A (zh) * 2018-12-21 2019-05-03 北京时代民芯科技有限公司 一种带反馈控制的cmos输出驱动电路
CN109714040B (zh) * 2018-12-21 2023-04-18 北京时代民芯科技有限公司 一种带反馈控制的cmos输出驱动电路
US20220239460A1 (en) * 2019-08-30 2022-07-28 Denso Corporation Communication apparatus
US12212647B2 (en) * 2019-08-30 2025-01-28 Denso Corporation Communication apparatus
CN118112310A (zh) * 2024-04-30 2024-05-31 江苏帝奥微电子股份有限公司 一种电压正负斜率检测电路及其检测方法

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