WO2017143636A1 - 一种薄膜晶体管及其制备方法 - Google Patents

一种薄膜晶体管及其制备方法 Download PDF

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WO2017143636A1
WO2017143636A1 PCT/CN2016/076514 CN2016076514W WO2017143636A1 WO 2017143636 A1 WO2017143636 A1 WO 2017143636A1 CN 2016076514 W CN2016076514 W CN 2016076514W WO 2017143636 A1 WO2017143636 A1 WO 2017143636A1
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layer
barrier layer
source
gate
thin film
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French (fr)
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王质武
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69391—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing aluminium, e.g. Al2O3

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a thin film transistor and a method of fabricating the same.
  • TFTs thin film transistors
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • TFT technology using metal oxide (Oxide) as a channel layer material is currently a hot spot in the field of display.
  • IGZO indium gallium zinc oxide
  • the IGZO TFT can make the display power consumption close to the OLED, but the cost is lower, and the thickness is only higher than the OLED. 25%, and the resolution can reach full HD (full HD, 1920 * 1080P) or even Ultra HD (Ultra Definition, resolution 4k * 2k) level.
  • ESL Etch Stop Layer
  • the etch barrier layer is a silicon dioxide (SiO2) film prepared by a plasma enhanced chemical vapor deposition (PECVD) method, and the reaction gases used for preparing the SiO2 film are SiH4 and N2O, or TEOS and O2. It is SiOx:H, and therefore, the SiO2 film layer contains hydrogen.
  • SiO2 film layer is formed at a high temperature, the diffusion of H causes IGZO to be reduced, resulting in deterioration of the electrical properties of the TFT device; and the high temperature is liable to cause IGZO damage; when the SiO2 film layer is formed at a low temperature, the H content is The relative increase and the occurrence of pin holes are also likely to cause deterioration of the electrical properties of the TFT device.
  • Al2O3 is a new type III-VI wide bandgap semiconductor material with good physicochemical properties.
  • Al2O3 is used instead of SiO2 as an etch barrier, but Al2O3 has a slow film formation rate, complicated equipment, high fabrication cost, and is not economical.
  • the present invention proposes a thin film transistor and a method for fabricating the same, which can avoid damage to the device by high temperature, reduce film formation time, and increase productivity.
  • the specific technical solution proposed by the present invention is to provide a thin film transistor, including:
  • a gate insulating layer on the substrate and completely covering the gate
  • the semiconductor layer on the gate insulating layer, the semiconductor layer further including a channel region corresponding to the gate;
  • An etch barrier layer on the semiconductor layer includes a first barrier layer disposed on a side of the channel region away from the gate, and a first layer on the first barrier layer Two barrier layers;
  • the source and drain layers including a source and a drain respectively connected to the etch barrier layer;
  • the etch stop layer is configured to protect the semiconductor layer when the source and drain layers are etched to form the source and the drain; the projected area of the semiconductor layer on the substrate is smaller than A projected area of the gate insulating layer on the substrate.
  • first barrier layer is an aluminum oxide film
  • second barrier layer is a silicon dioxide film
  • the thickness of the first barrier layer is The thickness of the second barrier layer is
  • the semiconductor layer is made of a metal oxide semiconductor material.
  • a protective layer is disposed on the gate insulating layer and completely covering the semiconductor layer, the source and drain layers, and the etch barrier layer.
  • the gate is copper or a copper alloy.
  • the present invention also provides a method of fabricating a thin film transistor as described above, comprising:
  • the source and drain layers are etched to form the source and the drain such that the source and the drain are separated from each other and are located on both sides of the first barrier layer and the second barrier layer.
  • the first barrier layer is an aluminum oxide film; the second barrier layer is a silicon dioxide film; the thickness of the first barrier layer is The thickness of the second barrier layer is
  • the temperature required to form the second barrier layer is from 100 ° C to 250 ° C.
  • the thin film transistor further includes a protective layer on the gate insulating layer and completely covering the semiconductor layer, the source and drain layers, and the etch barrier layer, the method further comprising:
  • the thin film transistor and the preparation method thereof provided by the invention adopts a two-layer thin film structure of SiO 2 /Al 2 O 3 instead of the SiO 2 single-layer thin film structure as an etch barrier layer, wherein the Al 2 O 3 thin film layer is relatively thin, SiO 2 The film layer is relatively thick.
  • the Al 2 O 3 film layer does not contain hydrogen to avoid the reduction reaction of the metal oxide;
  • Al 2 O 3 can be prepared at a low temperature to avoid damage to the device at a high temperature;
  • the relatively thin Al 2 O 3 can reduce the film formation time and increase the productivity;
  • SiO2 can be prepared at lower temperatures to avoid damage to the device at high temperatures.
  • FIG. 1 is a schematic structural view of a thin film transistor of the present invention
  • FIG. 2 is another schematic structural view of a thin film transistor of the present invention.
  • FIG. 3 is a schematic flow chart of a method for preparing a thin film transistor of the present invention.
  • the present embodiment provides a bottom gate type thin film transistor including a substrate 1, a gate 2, a gate insulating layer 3, a semiconductor layer 4, an etch barrier layer 5, and a source and drain layer 6. .
  • the substrate 1 is a transparent glass substrate or a PET substrate, and the gate 2 is patterned on the substrate 1.
  • the gate 2 is made of a metal conductive material, for example, aluminum, copper, One of the simple substances such as molybdenum is made of or made of an aluminum alloy.
  • the gate insulating layer 3 is located on the substrate 1 and completely covers the gate 2.
  • the material of the gate insulating layer 3 is one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Or a composite structure of the above three films.
  • the semiconductor layer 4 is patterned on the gate insulating layer 3, and the semiconductor layer is made of a metal oxide, for example, indium gallium zinc oxide (IGZO), germanium indium zinc oxide (HIZO), Indium zinc oxide (IZO), a-InZnO, etc., preferably, the semiconductor layer is made of IGZO.
  • the etch stop layer 5 and the source and drain layers 6 are formed on the semiconductor layer 4, wherein a region corresponding to the gate 2 in the semiconductor layer 4 is a channel region of the semiconductor layer 4. , the etch stop layer 5 bits On a side of the channel region away from the gate 2;
  • the source and drain layer 6 includes a source 6a and a drain 6b.
  • the source 6a and the drain 6b are respectively located at two sides of the etch barrier layer 5.
  • the source and the drain are connected to each other (not shown).
  • the source 6a and the drain 6b are made of a metal conductive material, for example, made of one of elemental materials such as aluminum, copper, molybdenum or the like or made of an aluminum alloy.
  • the performance of the thin film transistor is lowered, and the semiconductor layer 4 and the source and drain layer 6 are respectively in the
  • the projected area on the substrate 1 is smaller than the projected area of the gate insulating layer 3 on the substrate 1.
  • the etch barrier layer 5 is located away from the channel region. a first barrier layer 5a on one side of the gate 2 and a second barrier layer 5b on the first barrier layer 5a.
  • the first barrier layer 5a is an aluminum oxide film
  • the second barrier layer 5b is a silicon dioxide film.
  • the thin film transistor in order to improve the stability of the thin film transistor, it further includes a protective layer 7 on the gate insulating layer 3 and the semiconductor layer 4, the etch stop layer 5, and the source.
  • the drain layer 6 is completely covered.
  • the protective layer may be an oxide, a nitride or an oxynitride.
  • the embodiment further provides a method for fabricating the thin film transistor, wherein the patterning process involved in the following method includes a process for forming a predetermined pattern by photolithography, etching, printing, inkjet, or the like;
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, etc., which are well known to those skilled in the art and will not be described herein.
  • the method includes the following steps:
  • Step S1 depositing a first conductive film on the substrate 1 by using a method of magnetron sputtering (PVD) and patterning the first conductive film to form the gate electrode 2.
  • PVD magnetron sputtering
  • Step S2 depositing a first insulating film on the substrate 1 on which the gate electrode 2 is formed by using a plasma enhanced chemical vapor deposition (PECVD) method to form the gate insulating layer 3, so that the gate insulating layer 3 is completely Covering the gate 2.
  • PECVD plasma enhanced chemical vapor deposition
  • Step S3 depositing a metal oxide film on the gate insulating layer 3 by using a method of magnetron sputtering (PVD) and patterning the metal oxide film to form the semiconductor layer 4, so that the semiconductor The channel region of layer 4 corresponds to the gate 2.
  • PVD magnetron sputtering
  • Step S4 depositing a second insulating film and a third insulating film on the side of the channel region away from the gate 2, and sequentially patterning the third insulating film and forming a second insulating film to form the second blocking film.
  • forming the first barrier layer 5a in step S4 may adopt a magnetron sputtering (PVD) method, an atomic layer deposition (ALD) method or a metal organic chemical vapor deposition (MOCVD) method, and preferably, atomic layer deposition ( The ALD) method forms the first barrier layer 5a; forming the second barrier layer 5b on the first barrier layer 5a is a plasma enhanced chemical vapor deposition (PECVD) method.
  • PVD magnetron sputtering
  • ALD atomic layer deposition
  • MOCVD metal organic chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the first barrier layer 5a is an aluminum oxide film having a thickness of
  • the second barrier layer 5b is a silicon dioxide film having a thickness of
  • the temperature required for preparing the second barrier layer 5b is from 100 ° C to 250 ° C.
  • the first barrier layer 5a is provided between the second barrier layer 5b and the semiconductor 4, at a high temperature, by using the reaction gases SiH 4 and N 2 O, or TEOS and O 2
  • the reaction gases SiH 4 and N 2 O, or TEOS and O 2 When the second barrier layer 5b is described, hydrogen contained in the second barrier layer 5b does not diffuse into the semiconductor layer 4 and the first barrier layer 5a does not contain hydrogen, so that the semiconductor layer 4 does not A reduction reaction occurs to cause deterioration of electrical properties of the thin film transistor.
  • the thickness of the first barrier layer 5a is an aluminum oxide film
  • the film formation rate of the aluminum oxide film is slow, the device is complicated, and the manufacturing cost is high, which is disadvantageous for industrialization. Therefore, in order to reduce the film formation time and increase the productivity, it is preferable that the thickness of the first barrier layer 5a is The thickness of the second barrier layer 5b is The aluminum oxide film can be prepared at a low temperature, and the first barrier layer 5a can also prevent damage to the thin film transistor when the first barrier layer 5b is produced at a high temperature.
  • Step S5 depositing a second conductive film on the semiconductor layer 4 by using a method of magnetron sputtering (PVD) to form the source and drain layers 6, such that the source and drain layers 6 completely cover the first barrier Layer 5a and second barrier layer 5b.
  • PVD magnetron sputtering
  • Step S6 etching the source and drain layers 6 to form the source 6a and the drain 6b, so that the source 6a and the drain 6b are separated from each other and respectively located in the first barrier layer 5a. And two sides of the second barrier layer 5b.
  • Step S7 using a plasma enhanced chemical vapor deposition (PECVD) method on the gate insulating layer A passivation film is deposited on the third layer to form the protective layer 7, such that the protective layer 7 completely covers the semiconductor layer 4, the etch stop layer 5, and the source and drain layers 6.
  • PECVD plasma enhanced chemical vapor deposition
  • the method for preparing the gate electrode 2, the gate insulating layer 3, the semiconductor layer 4, the etch barrier layer 5, and the source/drain layer 6 in the thin film transistor listed in this embodiment is merely shown as an example, and is not used in the present invention.
  • the method for preparing the gate electrode 2, the gate insulating layer 3, the semiconductor layer 4, the etch barrier layer 5, and the source/drain layer 6 may also adopt other methods well known to those skilled in the art, and details are not described herein. .
  • the thin film transistor and the preparation method thereof of the present invention adopt a two-layer thin film structure of SiO 2 /Al 2 O 3 instead of the SiO 2 single-layer thin film structure as an etch barrier layer, wherein the Al 2 O 3 thin film layer is relatively relatively
  • the thin, SiO 2 film layer is relatively thick.
  • the Al 2 O 3 film layer does not contain hydrogen to avoid the reduction reaction of the metal oxide;
  • Al 2 O 3 can be prepared at a low temperature to avoid damage to the device at a high temperature;
  • the relatively thin Al 2 O 3 can reduce the film formation time and increase the productivity;
  • SiO2 can be prepared at lower temperatures to avoid damage to the device at high temperatures.

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Abstract

一种薄膜晶体管及其制备方法。薄膜晶体管包括基板（1）；位于基板上的栅极（2）；位于基板上并完全覆盖栅极的栅极绝缘层（3）；位于栅极绝缘层上的半导体层（4）以及位于半导体层上的刻蚀阻挡层以及源漏极层（6）；刻蚀阻挡层（5）包括设置于沟道区远离栅极一面上的第一阻挡层（5a）以及位于第一阻挡层上的第二阻挡层（5b）；位于半导体层上的源漏极层（6），源漏极层包括分别与刻蚀阻挡层连接的源极和漏极；刻蚀阻挡层用于在对源漏极层进行刻蚀形成源极、漏极时保护半导体层；半导体层在基板上的投影面积小于栅极绝缘层在基板上的投影面积。薄膜晶体管及其制备方法，采用SiO2/Al2O3的双层薄膜结构替代SiO2单层薄膜结构作为刻蚀阻挡层，Al2O3薄膜层相对较薄，SiO2薄膜层相对较厚，避免高温对器件的损伤，Al2O3相对较薄可以减少成膜时间，提高产能；而且以Al2O3作为基础，SiO2可以在更低的温度下制备，避免高温对器件的损伤。

Description

一种薄膜晶体管及其制备方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种薄膜晶体管及其制备方法。
背景技术
目前，薄膜晶体管(TFT，Thin Film Transistor)主要应用于控制和驱动液晶显示器(LCD，Liquid Crystal Display)、有机发光二极管(OLED，Organic Light-Emitting Diode)显示器的子像素，是平板显示领域中最重要的电子器件。其中，采用金属氧化物(Oxide)作为沟道层材料的TFT技术是目前显示器领域研究的热点。
现有技术中大多数将铟镓锌氧化物(indium gallium zinc oxide，IGZO)作为沟道层材料，采用IGZO的TFT可以使显示屏功耗接近OLED，但成本更低，厚度也只比OLED高出25％，且分辨率可以达到全高清(full HD，1920*1080P)甚至超高清(Ultra Definition，分辨率4k*2k)级别。为了避免在形成源漏金属电极时保护金属氧化物层不被破坏，提高金属氧化物TFT的性能，常常采用刻蚀阻挡型(Etch Stop Layer，简称ESL)金属氧化物TFT。其中，刻蚀阻挡层为采用等离子体增强化学气相沉积(PECVD)方法制备而成的二氧化硅(SiO2)薄膜，制备SiO2薄膜所使用的反应气体为SiH4和N2O，或者TEOS和O2，生成物为SiOx:H，因此，该SiO2薄膜层中含有氢。当在高温下形成该SiO2薄膜层时，由于H的扩散会导致IGZO的还原，造成TFT器件电性的恶化；而且高温容易造成IGZO损坏；当在低温下形成该SiO2薄膜层时，H含量会相对提高，且容易出现孔洞(Pin hole)，也会造成TFT器件电性的恶化。综上所述，为了保持IGZO TFT器件的稳定性，必须减少刻蚀阻挡层的氢含量，同时要避免Pin hole的出现。
氧化铝(Al2O3)是一种新型的Ⅲ-Ⅵ族宽禁带半导体材料，具有良好的物理化学性质。现有技术中也有采用Al2O3来代替SiO2作为刻蚀阻挡层，但是Al2O3成膜速率慢，设备复杂，制作成本高，不利于产业化。
发明内容
为了解决现有技术的不足，本发明提出了一种薄膜晶体管及其制备方法，能够避免高温对器件的损伤、减少成膜时间、提高产能。
本发明提出的具体技术方案为：提供一种薄膜晶体管，包括：
基板；
位于所述基板上的栅极；
位于所述基板上并完全覆盖所述栅极的栅极绝缘层；
位于所述栅极绝缘层上的半导体层，所述半导体层还包括与所述栅极对应的沟道区；
位于所述半导体层上的刻蚀阻挡层，所述刻蚀阻挡层包括设置于所述沟道区远离所述栅极一面上的第一阻挡层，以及位于所述第一阻挡层上的第二阻挡层；以及
位于所述半导体层上的源漏极层，所述源漏极层包括分别与所述刻蚀阻挡层连接的源极和漏极；
其中，所述刻蚀阻挡层用于在对所述源漏极层进行刻蚀形成所述源极、漏极时保护所述半导体层；所述半导体层在所述基板上的投影面积小于所述栅极绝缘层在所述基板上的投影面积。
进一步地，所述第一阻挡层为氧化铝薄膜；所述第二阻挡层为二氧化硅薄膜。
进一步地，所述第一阻挡层的厚度为
Figure PCTCN2016076514-appb-000001
所述第二阻挡层的厚度为
Figure PCTCN2016076514-appb-000002
进一步地，所述半导体层由金属氧化物半导材料制作而成。
进一步地，还包括位于所述栅极绝缘层上并将所述半导体层、所述源漏极层以及所述刻蚀阻挡层完全覆盖的保护层。
进一步地，所述栅极为铜或铜合金。
本发明还提供了一种如上所述的薄膜晶体管的制备方法，包括：
在所述基板上沉积第一导电薄膜并图案化所述第一导电薄膜形成为所述栅极；
在形成有所述栅极的基板上沉积第一绝缘薄膜形成为所述栅极绝缘层，使得所述栅极绝缘层完全覆盖所述栅极；
在所述栅极绝缘层上沉积一层金属氧化物薄膜并图案化所述金属氧化物薄膜形成为所述半导体层，使得所述半导体层的沟道区与所述栅极对应；
在所述沟道区远离所述栅极一面上依次沉积第二绝缘薄膜、第三绝缘薄膜并依次图案化所述第三绝缘薄膜、第二绝缘薄膜形成为所述第二阻挡层、第一阻挡层；
在所述半导体层上沉积第二导电薄膜形成为所述源漏极层，使得所述源漏极层完全覆盖所述第一阻挡层以及第二阻挡层；
刻蚀所述源漏极层形成为所述源极、所述漏极，使得所述源极、所述漏极相互分离并位于所述第一阻挡层和第二阻挡层两侧。
进一步地，所述第一阻挡层为氧化铝薄膜；所述第二阻挡层为二氧化硅薄膜；所述第一阻挡层的厚度为
Figure PCTCN2016076514-appb-000003
所述第二阻挡层的厚度为
Figure PCTCN2016076514-appb-000004
进一步地，形成所述第二阻挡层所需的温度为100℃～250℃。
进一步地，所述薄膜晶体管还包括位于所述栅极绝缘层上并将所述半导体层、源漏极层以及刻蚀阻挡层完全覆盖的保护层，所述方法还包括：
在所述栅极绝缘层上沉积一层钝化薄膜形成为所述保护层，使得所述保护层完全覆盖所述半导体层、源漏极层以及刻蚀阻挡层。
本发明提出的薄膜晶体管及其制备方法，采用SiO2/Al2O3的双层薄膜结构替代SiO2单层薄膜结构作为刻蚀阻挡层，其中Al2O3薄膜层相对较薄，SiO2薄膜层相对较厚。这样，Al2O3薄膜层不含氢可避免金属氧化物的还原反应； Al2O3可以在低温下制备避免高温对器件的损伤；Al2O3相对较薄可以减少成膜时间，提高产能；而且以Al2O3作为基础，SiO2可以在更低的温度下制备，避免高温对器件的损伤。
附图说明
图1为本发明薄膜晶体管的结构示意图；
图2为本发明薄膜晶体管的另一结构示意图；
图3为本发明薄膜晶体管制备方法流程示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，相同的标号将始终被用于表示相同的元件。
实施例1
参照图1，本实施例提供了一种底栅型薄膜晶体管，所述薄膜晶体管包括基板1、栅极2、栅极绝缘层3、半导体层4、刻蚀阻挡层5以及源漏极层6。
所述基板1为透明的玻璃基板或PET基板，所述的栅极2被图案化的形成于所述基板1上，所述栅极2由金属导电材料制成，例如，由铝、铜、钼等其中一种单质制成或由铝合金制成。所述栅极绝缘层3位于所述基板1上并完全覆盖所述栅极2，所述栅极绝缘层3的材料为氧化硅薄膜、氮化硅薄膜和氮氧化硅薄膜的其中一种，或是上述三种薄膜的复合结构。
所述半导体层4图案化形成于所述栅极绝缘层3上，所述半导体层由金属氧化物制成，例如，为铟镓锌氧化物(IGZO)、铪铟锌氧化物(HIZO)、铟锌氧化物(IZO)、a-InZnO等，优选的，所述半导体层由IGZO制成。所述刻蚀阻挡层5以及源漏极层6形成于所述半导体层4上，其中，在所述半导体层4中与所述栅极2对应的区域为所述半导体层4的沟道区，所述刻蚀阻挡层5位 于所述沟道区远离所述栅极2的一面上；
所述源漏极层6包括源极6a、漏极6b。所述源极6a、漏极6b分别位于所述刻蚀阻挡层5的两侧，在该薄膜晶体管的俯视图中，所述源极、漏极是相互连接的(图中未示出)。所述源极6a、漏极6b由金属导电材料制成，例如，由铝、铜、钼等其中一种单质制成或由铝合金制成。为了避免所述栅极2与所述半导体层4、源漏极层6之间产生影响，导致所述薄膜晶体管的性能下降，所述半导体层4、所述源漏极层6分别在所述基板1上的投影面积小于所述栅极绝缘层3在所述基板1上的投影面积。
为了在对所述源漏极层6进行刻蚀形成所述源极6a、漏极6b时保护所述半导体层4不被破坏，所述刻蚀阻挡层5包括位于所述沟道区远离所述栅极2一面上的第一阻挡层5a以及位于所述第一阻挡层5a上的第二阻挡层5b，优选的，所述第一阻挡层5a为氧化铝薄膜，所述第二阻挡层5b为二氧化硅薄膜。
参照图2，为了提升所述薄膜晶体管的稳定性，其还包括保护层7，所述保护层7位于所述栅极绝缘层3上并将所述半导体层4、刻蚀阻挡层5以及源漏极层6完全覆盖。其中，所述保护层可以为氧化物、氮化物或者氧氮化合物。
参照图3，本实施例还提供了所述薄膜晶体管的制备方法，其中，下面方法中所涉及的图案化工艺包括光刻、刻蚀、打印、喷墨等用于形成预定图形的工艺；而光刻工艺是指利用光刻胶、掩膜版、曝光机等形成图形的工艺，这些工艺为本领域技术人员所熟知，这里不再赘述。所述方法包括以下步骤：
步骤S1、采用磁控溅射(PVD)的方法在所述基板1上沉积第一导电薄膜并图案化所述第一导电薄膜形成为所述栅极2。
步骤S2、采用等离子体增强化学气相沉积(PECVD)方法在形成有所述栅极2的基板1上沉积第一绝缘薄膜形成为所述栅极绝缘层3，使得所述栅极绝缘层3完全覆盖所述栅极2。
步骤S3、采用磁控溅射(PVD)的方法在所述栅极绝缘层3上沉积一层金属氧化物薄膜并图案化所述金属氧化物薄膜形成为所述半导体层4，使得所述半导体层4的沟道区与所述栅极2对应。
步骤S4、在所述沟道区远离所述栅极2一面上依次沉积第二绝缘薄膜、第三绝缘薄膜并依次图案化所述第三绝缘薄膜、第二绝缘薄膜形成为所述第二阻挡层5b、第一阻挡层5a。
其中，步骤S4中形成所述第一阻挡层5a可以采用磁控溅射(PVD)方法、原子层沉积(ALD)方法或者金属有机物化学气相沉积(MOCVD)方法，优选的，采用原子层沉积(ALD)方法形成所述第一阻挡层5a；在所述第一阻挡层5a上形成所述第二阻挡层5b采用的是等离子体增强化学气相沉积(PECVD)方法。
优选的，所述第一阻挡层5a为氧化铝薄膜，其厚度为
Figure PCTCN2016076514-appb-000005
所述第二阻挡层5b为二氧化硅薄膜，其厚度为
Figure PCTCN2016076514-appb-000006
其中，制备所述第二阻挡层5b所需的温度为100℃～250℃。
由于在所述第二阻挡层5b与所述半导体4之间设有所述第一阻挡层5a，所以，在高温下，通过使用反应气体SiH4和N2O，或者TEOS和O2制备所述第二阻挡层5b时，所述第二阻挡层5b中含有的氢不会扩散到所述半导体层4中且所述第一阻挡层5a不含氢，从而，所述半导体层4不会发生还原反应而导致所述薄膜晶体管电性的恶化。
由于所述第一阻挡层5a为氧化铝薄膜，而氧化铝薄膜成膜速率慢，设备复杂，制作成本高，不利于产业化。所以，为了减少成膜时间，提高产能，优选的，所述第一阻挡层5a的厚度为
Figure PCTCN2016076514-appb-000007
所述第二阻挡层5b的厚度为
Figure PCTCN2016076514-appb-000008
氧化铝薄膜可以在低温下制备，所述第一阻挡层5a还可以避免高温生产所述第一阻挡层5b时损坏所述薄膜晶体管。
步骤S5、采用磁控溅射(PVD)的方法在所述半导体层4上沉积第二导电薄膜形成为所述源漏极层6，使得所述源漏极层6完全覆盖所述第一阻挡层5a以及第二阻挡层5b。
步骤S6、刻蚀所述源漏极层6形成为所述源极6a、所述漏极6b，使得所述源极6a、所述漏极6b相互分离并分别位于所述第一阻挡层5a和第二阻挡层5b两侧。
步骤S7、采用等离子体增强化学气相沉积(PECVD)方法在所述栅极绝缘层 3上沉积一层钝化薄膜形成为所述保护层7，使得所述保护层7完全覆盖所述半导体层4、刻蚀阻挡层5以及源漏极层6。
本实施例中列举出的薄膜晶体管中栅极2、栅极绝缘层3、半导体层4、刻蚀阻挡层5、源漏极层6的制备方法仅仅是作为示例示出，并不用于对本发明进行限定，所述栅极2、栅极绝缘层3、半导体层4、刻蚀阻挡层5、源漏极层6的制备方法也可以采用其他本领域技术人员所熟知的方法，这里不再赘述。
从上可知，本发明提出的薄膜晶体管及其制备方法，采用SiO2/Al2O3的双层薄膜结构替代SiO2单层薄膜结构作为刻蚀阻挡层，其中Al2O3薄膜层相对较薄，SiO2薄膜层相对较厚。这样，Al2O3薄膜层不含氢可避免金属氧化物的还原反应；Al2O3可以在低温下制备避免高温对器件的损伤；Al2O3相对较薄可以减少成膜时间，提高产能；而且以Al2O3作为基础，SiO2可以在更低的温度下制备，避免高温对器件的损伤。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (12)

  1. 一种薄膜晶体管，其中，包括：
    基板；
    位于所述基板上的栅极；
    位于所述基板上并完全覆盖所述栅极的栅极绝缘层；
    位于所述栅极绝缘层上的半导体层，所述半导体层还包括与所述栅极对应的沟道区；
    位于所述半导体层上的刻蚀阻挡层，所述刻蚀阻挡层包括设置于所述沟道区远离所述栅极一面上的第一阻挡层，以及位于所述第一阻挡层上的第二阻挡层；以及
    位于所述半导体层上的源漏极层，所述源漏极层包括分别与所述刻蚀阻挡层连接的源极和漏极；
    其中，所述刻蚀阻挡层用于在对所述源漏极层进行刻蚀形成所述源极、漏极时保护所述半导体层；所述半导体层在所述基板上的投影面积小于所述栅极绝缘层在所述基板上的投影面积。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一阻挡层为氧化铝薄膜；所述第二阻挡层为二氧化硅薄膜。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第一阻挡层的厚度为
    Figure PCTCN2016076514-appb-100001
    所述第二阻挡层的厚度为
    Figure PCTCN2016076514-appb-100002
  4. 根据权利要求2所述的薄膜晶体管，其中，所述第一阻挡层的厚度为
    Figure PCTCN2016076514-appb-100003
    所述第二阻挡层的厚度为
    Figure PCTCN2016076514-appb-100004
  5. 根据权利要求1所述的薄膜晶体管，其中，所述半导体层由金属氧化物半导材料制作而成。
  6. 根据权利要求1所述的薄膜晶体管，其中，还包括位于所述栅极绝缘层上并将所述半导体层、所述源漏极层以及所述刻蚀阻挡层完全覆盖的保护层。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述栅极为铜或铜合金。
  8. 根据权利要求6所述的薄膜晶体管，其中，所述栅极为铜或铜合金。
  9. 一种如权利要求1所述的薄膜晶体管的制备方法，其中，包括：
    在所述基板上沉积第一导电薄膜并图案化所述第一导电薄膜形成为所述栅极；
    在形成有所述栅极的基板上沉积第一绝缘薄膜形成为所述栅极绝缘层，使得所述栅极绝缘层完全覆盖所述栅极；
    在所述栅极绝缘层上沉积一层金属氧化物薄膜并图案化所述金属氧化物薄膜形成为所述半导体层，使得所述半导体层的沟道区与所述栅极对应；
    在所述沟道区远离所述栅极一面上依次沉积第二绝缘薄膜、第三绝缘薄膜并依次图案化所述第三绝缘薄膜、第二绝缘薄膜形成为所述第二阻挡层、第一阻挡层；
    在所述半导体层上沉积第二导电薄膜形成为所述源漏极层，使得所述源漏极层完全覆盖所述第一阻挡层以及第二阻挡层；
    刻蚀所述源漏极层形成为所述源极、所述漏极，使得所述源极、所述漏极相互分离并位于所述第一阻挡层和第二阻挡层两侧。
  10. 根据权利要求9所述的制备方法，其中，所述第一阻挡层为氧化铝薄膜；所述第二阻挡层为二氧化硅薄膜；所述第一阻挡层的厚度为
    Figure PCTCN2016076514-appb-100005
    所述第二阻挡层的厚度为
    Figure PCTCN2016076514-appb-100006
  11. 根据权利要求9所述的制备方法，其中，形成所述第二阻挡层所需的温度为100℃～250℃。
  12. 根据权利要求9所述的制备方法，其中，所述薄膜晶体管还包括位于所述栅极绝缘层上并将所述半导体层、源漏极层以及刻蚀阻挡层完全覆盖的保护层，所述方法还包括：
    在所述栅极绝缘层上沉积一层钝化薄膜形成为所述保护层，使得所述保护层完全覆盖所述半导体层、源漏极层以及刻蚀阻挡层。
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