WO2017121117A1 - 制作光电二极管的方法、光电二极管及光感应器 - Google Patents

制作光电二极管的方法、光电二极管及光感应器 Download PDF

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WO2017121117A1
WO2017121117A1 PCT/CN2016/096044 CN2016096044W WO2017121117A1 WO 2017121117 A1 WO2017121117 A1 WO 2017121117A1 CN 2016096044 W CN2016096044 W CN 2016096044W WO 2017121117 A1 WO2017121117 A1 WO 2017121117A1
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layer
photodiode
conductivity type
semiconductor substrate
window
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PCT/CN2016/096044
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English (en)
French (fr)
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宋华
杨欢
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无锡华润上华半导体有限公司
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Publication of WO2017121117A1 publication Critical patent/WO2017121117A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table

Definitions

  • the present invention relates to semiconductor technology, and more particularly to a method of fabricating a photodiode, a photodiode, and a photosensor.
  • LED Light Emitting in English
  • Diode is a type of semiconductor diode that converts electrical energy into light energy, emitting visible light of various colors such as yellow, green, and blue, and infrared and ultraviolet invisible light. Compared with small incandescent bulbs and xenon lamps, it has the advantages of low operating voltage and current, high reliability, long life and easy adjustment of luminous brightness.
  • the components in the analog circuit can be bipolar junction transistors (Bipolar Junction Transistor, BJT), metal oxide semiconductor field effect transistor (metal oxid Semiconductor, MOS), laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide) Semiconductor, LDMOS) or other active devices.
  • BJT Bipolar Junction Transistor
  • MOS metal oxide semiconductor field effect transistor
  • LDMOS laterally diffused metal oxide semiconductor
  • a method of making a photodiode comprising:
  • Photodiode PN junction Forming a photodiode PN junction in a semiconductor substrate, the photodiode PN junction being formed synchronously with active devices in an analog circuit;
  • Silicon nitride and/or silicon dioxide is deposited on the surface of the window region to form a reflective layer.
  • a photodiode comprising:
  • first conductivity type epitaxial layer on an upper surface of the semiconductor substrate, a first conductivity type well region and a second conductivity type well region disposed in the first conductivity type epitaxial layer, wherein the first conductivity type a buried layer and the second conductivity type well region constitute a photodiode PN junction;
  • An anode and a cathode of the photodiode are formed by different source/drain implantation of the first conductivity type and the second conductivity type in different regions of the first conductivity type epitaxial layer;
  • the reflective layer located in the window region, the reflective layer being at least one of a silicon dioxide layer and a silicon nitride layer.
  • a light sensor includes an analog circuit, and further includes the above photodiode, the photodiode being integrated with the analog circuit.
  • the photodiode PN junction is formed in the semiconductor substrate while maintaining the original device performance in the existing semiconductor process, and the photodiode PN junction is formed synchronously with the active device in the analog circuit, and can be realized on any process platform.
  • the photodiode is integrated with the single chip of the active device in the analog circuit, and simultaneously changes the etching process of the photodiode window, and a reflective layer is added in the window region, and the reflective layer is at least one of a silicon dioxide layer and a silicon nitride layer.
  • FIG. 1 is a flow chart of a method of integrally fabricating a photodiode in an analog circuit, in accordance with an embodiment
  • 2 to 6 are cross-sectional views showing different stages of a photodiode in a photodiode manufacturing method
  • Figure 7 is a topographical view of the window region under the scanning electron microscope
  • Figure 8 is a cross-sectional view of a photodiode of an embodiment
  • Figure 9 is a cross-sectional view showing a photodiode of another embodiment
  • Figure 10 is a topographical view of a silicon nitride deposition in a window region under a scanning electron microscope
  • Figure 11 is a spectral diagram showing the relationship between the thickness of the reflective layer of different materials and the reflectance
  • Figure 12 is a block diagram showing the structure of a light sensor.
  • a flow chart of a method of integrating a photodiode in an analog circuit is shown in FIG.
  • a method of fabricating a photodiode according to an embodiment includes:
  • Step S10 forming a photodiode PN junction in the semiconductor substrate, the photodiode PN junction being formed synchronously with the active device in the analog circuit.
  • a semiconductor substrate 100 is provided, which is a P-type silicon substrate 100. Ion implantation forms a first conductivity type buried layer 110 and a second conductivity type buried layer 120 on the semiconductor substrate, and thermally grows the first conductivity type epitaxial layer 130 in the semiconductor substrate.
  • a first conductivity type buried layer 110 is formed by photolithographic implantation on the P-type silicon substrate 100, and then a second conductivity type buried layer 120 is implanted by self-alignment.
  • the conductivity of the first conductivity type buried layer 110 is different from that of the second conductivity type buried layer 120.
  • the first conductivity type buried layer 110 is an N type buried layer
  • the second conductivity type buried layer 120 is a P type buried layer. .
  • the N-type buried layer 110 can be used as an N-type isolated terminal of a bipolar junction transistor BJT or an isolated lateral diffusion metal oxide semiconductor LDMOS used in an analog circuit.
  • the first type epitaxial layer 130 is formed by thermal growth over the P-type buried layer 120 and the N-type buried layer 110 in the P-type substrate 100.
  • the first type of epitaxial layer 130 is an N-type epitaxial layer.
  • the P-type buried layer 120 connects the N well 140 and the P-type semiconductor substrate 100.
  • a first conductivity type impurity and a second conductivity type impurity are implanted in the N-type epitaxial layer 130, respectively, to form a first conductivity type well region 140 and a second conductivity type well region 150.
  • the conductivity of the first conductivity type impurity and the second conductivity type impurity are opposite.
  • the first conductivity type impurity is an N type impurity (P or As)
  • the second conductivity type impurity is a P type ion (B or Ga) ).
  • the corresponding first conductivity type well region is an N-type well region 140
  • the second conductivity type well region is a P-type well region 150.
  • a photodiode PN junction in the second conductivity type buried layer 120 and the first conductivity type well region 140.
  • a PN junction of a photodiode is formed in the P-type buried layer 120 and the N-type well region 140.
  • the process conditions formed by the N-type well region 140 and the P-type well region 150 are compared with BCD (Bipolar).
  • DMOS Diffused Metal-Oxide
  • CMOS DMOS Bipolar-Complementary Metal Oxide Semiconductor-Double-Diffused Metal Oxide Semiconductor Process
  • the P-type well region and the N-type well region of the semiconductor, double-diffused metal oxide semiconductor device have the same process conditions.
  • BCD is a monolithic integrated process technology, which can produce bipolar bipolar, complementary metal oxide semiconductor CMOS on the same chip.
  • Metal Oxide Semiconductor (CMOS) and double-diffused metal oxide semiconductor DMOS resulting in N-type well region, P-well region and BCD of photodiode N of the DMOS device in the process
  • the well region and the P-well region can be integrated.
  • the N-type well region and the P-type well region in the analog circuit can be used as a substrate of a MOS transistor or a laterally diffused metal oxide semiconductor (Laterally Diffused).
  • the channel region of Metal Oxide Semiconductor, LDMOS is a monolithic integrated process technology, which can produce bipolar bipolar, complementary metal oxide semiconductor CMOS on the same chip.
  • CMOS Metal Oxide Semiconductor
  • DMOS double-diffused metal oxide semiconductor
  • LDMOS laterally diffused metal oxide semiconductor
  • the formation of the photodiode PN junction can also be performed by performing N+ on the predetermined region of the semiconductor substrate 100 at the P+ particles. Or a P+ heavily doped region is formed by diffusion, that is, a photodiode PN junction is formed at the P-type substrate 100 in the N+ or P+ heavily doped region.
  • P+ in the N-well on the P-type silicon substrate 100 The heavily doped region forms a photodiode PN junction, or the N+ heavily doped region in the P well on the P-type silicon substrate forms a photodiode PN junction.
  • deposition and local oxidation are performed on the first conductivity type epitaxial layer 130 in accordance with the COMS process to form a plurality of active regions and field oxide isolation regions 200 of active devices or circuit portions.
  • deposition and local oxidation are performed on the N-type epitaxial layer 130 using an existing standard complementary metal oxide semiconductor COMS process to form a plurality of active regions and field oxide isolation of active devices or circuit portions.
  • District 200 The active region and the field oxide isolation region 200 achieve isolation between active devices.
  • the first conductivity type and the second conductivity type ion source/drain implant are performed in different regions of the first conductivity type epitaxial layer 130, respectively.
  • CMOS complementary metal-oxide-semiconductor
  • LDMOS active device
  • an N-type ion or a P-type ion implantation is then performed on the active device (CMOS, LDMOS), including: a first conductivity type ion (N-type ion 210) source/drain injection COMS process, using BCD
  • the N-type source/drain implant of the CMOS device in the process, the impurity is arsenic.
  • P+ doping and N+ doping are performed by ion implantation to form the anode 220 and the cathode 210 of the photodiode, respectively.
  • the photodiode's anode 220 and cathode 210 are formed separately from BCD
  • the P-type source/drain implant region and the N-type source/drain implant region of the CMOS device in the process are formed together.
  • Step S20 depositing a semiconductor substrate to form a multilayer structure.
  • a silicide and a metal are sequentially deposited in the anode 220 and cathode 210 regions of the photodiode to form alternating dielectric layers (310, 320, 330) and metal layers (314, 324, 334) to form a multilayer structure, and Via holes (312, 322, 332) are provided in the dielectric layer (310, 320, 330) to form conductive lines of the analog circuit and lead wires of the anode and cathode of the photodiode.
  • the areas 340, 350 marked by the dashed box in the figure may form analog circuit conductive lines, and may also be used for the photodiode anode and cathode lead lines.
  • the dielectric layer (310, 320, 330) is a silicon dioxide layer; the metal layer (314, 324, 334) may be an aluminum layer.
  • Step S30 forming a window in the multi-layer structure, the window being located above the PN junction of the photodiode.
  • a nitride is deposited on the metal layer to form a passivation layer 400, which is a silicon dioxide layer or/and a silicon nitride layer.
  • the passivation layer 400 includes a silicon nitride layer and a silicon dioxide layer which are sequentially stacked.
  • a window 410 is formed for the dielectric layers 310, 320, 330 and their passivation layer 400 by photolithography and etching processes. Wherein, the window 410 is opened over at least a portion of the photodiode PN junction, and the window 410 extends toward the semiconductor substrate 100 to the field oxide isolation layer 200 (refer to FIG. 5) or the semiconductor substrate 100 (refer to FIG. 6).
  • the etching process includes dry etching and wet etching, and the ratio of the amount of dry etching to the amount of wet etching depends on the number of layers of the dielectric layer (310, 320, 330) and the metal layers (314, 324, 334).
  • Wet etching is an etching method that peels off an object to be etched by a chemical reaction between a chemical etching solution and an object to be etched; dry etching refers to reacting a high-energy beam with a surface film to form a volatile substance, or directly The process of bombarding the surface of a film to corrode it.
  • the number of layers of the dielectric layer (310, 320, 330) and the metal layer (314, 324, 334) is three, and the ratio of the dry etching amount to the wet etching amount is 10:1.
  • the number of layers of the dielectric layer and the metal layer may be determined according to the requirements of the specific device, and thus the ratio of the amount of dry etching to the amount of wet etching is also changed.
  • the dry etching method steps include:
  • the silicon nitride layer in the passivation layer 400 is removed by a dry etching process
  • the silicon dioxide layer in the passivation layer 400 and the silicon dioxide layer of the partial dielectric layer are removed by a dry etching process;
  • the ratio of dry etching and wet etching is selected according to the thickness of the remaining portion of the dielectric layer (for example, the amount of dry etching in the present embodiment: wet etching amount is 10:1, and in other examples, dry etching amount:
  • the amount of wet etching can be, for example, 6:1), forming a window by combining dry etching and wet etching.
  • the ratio of dry etching and wet etching is related to the metal level in the analog circuit. The more metal layers, the thicker the medium, the more dry etching is required.
  • Figure 7 is a topographical view of the window region under the scanning electron microscope.
  • Step S40 depositing silicon nitride and/or silicon dioxide on the surface of the window region to form a reflective layer.
  • Silicon nitride and/or silicon dioxide are deposited on the upper surface of the window region 410 and the passivation layer 400 to form a reflective layer 500.
  • the reflective layer 500 is a silicon nitride layer.
  • the thickness of the reflective layer 500 is the thickness corresponding to the minimum reflectivity of the silicon dioxide layer and/or the silicon nitride layer under different light wave conditions. In view of the fact that the photodiode needs to absorb the optical signal, and the optical signal with reflection loss is as small as possible, and the trough position corresponds to the lowest emissivity of the thickness and the optical loss is the least, referring to FIG. 8 and FIG.
  • the reflective layer 500 is a silicon nitride layer having a thickness of 110 nm.
  • Figure 10 is a topographical view of the deposition of silicon nitride in the window region under the scanning electron microscope.
  • the photodiode is integrated, and the photodiode can also be integrated with a single chip of the analog circuit.
  • FIG 8 is a cross-sectional view of an embodiment of a photodiode that can be used for monolithic integration with analog circuitry.
  • the photodiode 10a comprises:
  • the semiconductor substrate 100 is sequentially formed with a first conductive type buried layer 110 and a second conductive type buried layer 120 in the semiconductor substrate 100.
  • the semiconductor substrate 100 is a P-type silicon substrate
  • the first conductive type buried layer 110 is an N-type buried layer
  • the second conductive type buried layer 120 is a P-type buried layer.
  • the first conductive type epitaxial layer 130 on the upper surface of the semiconductor substrate 100 is disposed on the first conductive type well region 140 and the second conductive type well region 150 of the first conductive type epitaxial layer 130, wherein the second conductive type is buried Layer 120 and first conductivity type well region 140 form the PN junction of the photodiode.
  • the first conductive type epitaxial layer 130 is an N-type epitaxial layer
  • the first conductive type well region 140 is an N-type well region
  • the second conductive type well region 150 is a P-type well region, and is in an N-type well region.
  • a PN junction of a photodiode is formed at 140 and P-type buried layer 120.
  • a plurality of active regions and field oxide isolation regions 200 are disposed on the first conductivity type epitaxial layer 130.
  • a plurality of active regions and field oxide isolation regions 200 of the device or analog circuit portion are fabricated on the N-type epitaxial layer 130.
  • the anode 220 and cathode 210 of the photodiode are formed in different regions of the first conductivity type epitaxial layer 130 by N-type ions and P-type ion source/drain implants.
  • the anode 220 and the cathode 210 of the photodiode are formed in different regions of the N-type epitaxial layer.
  • a dielectric layer (310, 320, 330), a metal layer (314, 324, 334) and a passivation layer 400 are disposed over the semiconductor substrate.
  • the first dielectric layer 310, the first contact hole 312, the first metal layer 314, the second dielectric layer 320, and the first layer are formed by performing processes such as interlayer dielectric, metal, contact, via, and passivation.
  • the regions 340, 350 marked in the figure may form analog circuit conductive lines, and may also be used for the photodiode anode and cathode lead wires.
  • the dielectric layer (310, 320, 330), typically an oxide layer (SiO 2 layer), may be partially removed by using an etch etch; the metal layer (314, 324, 334) is an aluminum layer.
  • a window 410 is formed above the photodiode PN junction.
  • the window 410 extends toward the semiconductor substrate 100 to the field oxide isolation region 200.
  • a nitride is deposited on the metal layer 314 to form a passivation layer 400 including a silicon oxide (SiO 2 ) layer and a silicon nitride (Si 3 N 4 ) layer which are sequentially stacked, and A window 410 is formed in the dielectric layer (310, 320, 330) and the passivation layer 400.
  • the window 410 is located above the photodiode PN junction, and the window 410 extends toward the semiconductor substrate 100 to the field oxide isolation region 200.
  • the passivation layer 400 and a portion of the dielectric layer are photolithographically removed so that the window 410 extends toward the semiconductor substrate 100 to the field oxide isolation region 200.
  • a reflective layer 500 located in the region of the window 410, the reflective layer 500 being at least one of a silicon dioxide layer and a silicon nitride layer.
  • the reflective layer 500 is located above the passivation layer 400 and the window region 410.
  • the reflective layer 500 is at least one of a silicon dioxide layer and a silicon nitride layer.
  • the reflective layer 500 is a silicon nitride layer.
  • the thickness of the reflective layer 500 is the thickness corresponding to the minimum reflectivity of the silicon dioxide layer and/or the silicon nitride layer under different wavelength conditions. In view of the fact that the photodiode needs to absorb the optical signal, the optical signal with reflection loss is as small as possible.
  • the trough position corresponds to the lowest emissivity and the lowest optical loss.
  • the relationship between the thickness of the reflective layer and the reflectance of different materials is shown in the figure.
  • the (valley) film thickness is 150 nm or 460 nm; the silicon nitride corresponding to the lowest reflectance (valley) film thickness is 110 nm or 330 nm.
  • the reflective layer 500 is a silicon nitride layer having a thickness of 110 nm.
  • the photodiode is integrated, and the photodiode can also be integrated with a single chip of the analog circuit.
  • Figure 10 is a cross-sectional view of an embodiment of a photodiode that can be used for monolithic integration with analog circuitry.
  • the structure of the photodiode 10b and the photodiode of FIG. 8 are different except that the extending position of the window 410 is the same, and the window 410 extends toward the semiconductor substrate 100 to the semiconductor substrate 100. More specifically, the passivation layer 400 and a portion of the dielectric layer are photolithographically removed so that the window 410 extends toward the semiconductor substrate 100 to the semiconductor substrate 100.
  • This embodiment can be based on common semiconductor processes (eg CMOS process)
  • CMOS process common semiconductor processes
  • the photodiode is manufactured to reduce the production cost, and since it can be fabricated by a common semiconductor process, the photodiode of the present embodiment can be fabricated integrally with other circuit components.
  • a light sensor with reference to FIG. 12, includes an analog circuit 20, and further includes the above-described photodiode 10, which is integrated with the analog circuit 20.
  • the input of the voltage of the analog circuit 20 and the output of the current are realized by the light intensity control of the photodiode 10.

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Abstract

一种制作光电二极管的方法，包括：在半导体衬底中形成光电二极管PN结，光电二极管PN结与模拟电路中的有源器件是同步形成的；在半导体衬底上沉积形成多层结构；在多层结构中形成窗口，窗口位于光电二极的PN结上方；及，在窗口区域表面沉积氮化硅和/或二氧化硅形成反射层。

Description

制作光电二极管的方法、光电二极管及光感应器
【技术领域】
本发明涉及半导体技术，特别是涉及制作光电二极管的方法、光电二极管及光感应器。
【背景技术】
发光二极管（英文为Light Emitting Diode，简称LED）是半导体二极管的一种，它能将电能转化为光能，发出黄、绿、蓝等各种颜色的可见光及红外和紫外不可见光。与小白炽灯泡及氖灯相比，它具有工作电压和电流低、可靠性高、寿命长且可方便调节发光亮度等优点。
现如今，随着半导体工艺技术的发展，光电二极管与模拟电路中元器件的集成也成为人们所关注的焦点之一。模拟电路中的元器件可以为双极结型晶体管（Bipolar Junction Transistor，BJT）、金属氧化物半导体场效应晶体管（metal oxid semiconductor，MOS）、横向扩散金属氧化物半导体（Laterally Diffused Metal Oxide Semiconductor，LDMOS）或其他有源器件。在保持现有半导体工艺中原有器件性能不变的情况下，想要在任意工艺平台上集成光电二极管，大多采用和集成电路不兼容的特殊工艺，和模拟电路无法集成在同一个芯片上，成本较高，工艺过程复杂。
【发明内容】
基于此，有必要提供一种在保持原有工艺中元件性能不变的情况下，与模拟电路同时制作光电二极管的方法、光电二极管及光感应器。
一种制作光电二极管的方法，包括：
在半导体衬底中形成光电二极管PN结，所述光电二极管PN结与模拟电路中的有源器件是同步形成的；
在所述半导体衬底上沉积形成多层结构；
在所述多层结构中形成窗口，所述窗口位于所述光电二极管的PN结上方；
在所述窗口区域表面沉积氮化硅和/或二氧化硅，形成反射层。
一种光电二极管，包括：
半导体衬底；
形成在所述半导体衬底中的第一导电类型埋层和第二导电类型埋层；
位于所述半导体衬底的上表面的第一导电类型外延层，设于所述第一导电类型外延层中的第一导电类型阱区和第二导电类型阱区，其中所述第一导电类型埋层与所述第二导电类型阱区构成光电二极管PN结；
位于所述第一导电类型外延层上的多个有源区和场氧化隔离区；
光电二极管的阳极和阴极，在所述第一导电类型外延层的不同区域通过第一导电类型和第二导电类型离子源/漏注入而形成；
位于所述半导体衬底上方的介质层、金属层和钝化层；
开设在所述光电二极管PN结上方的窗口，所述窗口向所述半导体衬底方向延伸至所述场氧化隔离区或所述半导体衬底；以及
位于所述窗口区域的反射层，所述反射层为二氧化硅层和氮化硅层中的至少一种。
一种光感应器，包括模拟电路，还包括上述光电二极管，所述光电二极管与所述模拟电路集成为一体。
在保持现有半导体工艺中原有器件性能不变的情况下，在半导体衬底中形成光电二极管PN结，光电二极管PN结与模拟电路中的有源器件同步形成，就能实现在任意工艺平台上光电二极管与模拟电路中有源器件的单芯片集成，同时改变光电二极管窗口的腐蚀工艺，在窗口区域增加了反射层，其反射层为二氧化硅层和氮化硅层中的至少一种。光电二极管与模拟电路集成在同一个芯片的工艺过程简单、成本低。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据一实施例的在模拟电路中集成制作光电二极管的方法流程图；
图2-图6为光电二极管制作方法中光电二极管不同阶段的剖面图；
图7为扫描电子显微镜下窗口区域腐蚀后的的形貌图；
图8为一实施例的光电二极管的剖面图；
图9为另一实施例的光电二极管的剖面图；
图10为扫描电子显微镜下窗口区域氮化硅淀积后的形貌图；
图11为不同材质反射层膜层厚度与反射率的关系谱线图；
图12为一光感应器的结构简图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和／或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示的为在模拟电路中集成光电二极管的方法流程图。根据一实施例的光电二极管的制作方法，包括：
步骤S10：在半导体衬底中形成光电二极管PN结，光电二极管PN结与模拟电路中的有源器件是同步形成的。
参考图2，提供半导体衬底100，半导体衬底100为P型硅衬底100。离子注入，在半导体衬底上形成第一导电类型埋层110和第二导电类型埋层120，在半导体衬底中热生长第一导电类型外延层130。
在P型硅衬底100上通过光刻注入形成了第一导电类型埋层110，然后通过自对准注入第二导电类型埋层120。第一导电类型埋层110与第二导电类型埋层120的导电性不同，在本实施例中第一导电类型埋层110为N型埋层，第二导电类型埋层120为P型埋层。
N型埋层110可以作为模拟电路中使用到的双极结型晶体管BJT或者隔离型横向扩散金属氧化物半导体LDMOS的N型隔离端。
在P型衬底100中的P型埋层120和N型埋层110上方通过热生长形成第一类型外延层130，在本实施例中，第一类型外延层130为N型外延层。
在第一导电类型外延层130分别注入第一导电类型杂质和第二导电类型杂质，形成第一导电类型阱区140和第二导电类型阱区150，在第二导电类型埋层120与第一导电类型阱区140，形成光电二极管PN结。 P型埋层120连接N阱140与P型半导体衬底100。
在N型外延层130分别注入第一导电类型杂质和第二导电类型杂质，形成第一导电类型阱区140和第二导电类型阱区150。第一导电类型杂质和第二导电类型杂质的导电性相反，在本实施例中，第一导电类型杂质为N型杂质（P或As），第二导电类型杂质为P型离子（B或Ga）。对应的第一导电类型阱区为N型阱区140，第二导电类型阱区为P型阱区150。并在第二导电类型埋层120与第一导电类型阱区140形成光电二极管PN结。在本实施中，在P型埋层120和N型阱区140形成光电二极管的PN结。在本实施例中N型阱区140和P型阱区150形成的工艺条件与BCD（Bipolar CMOS DMOS，双极-互补金属氧化物半导体-双重扩散金属氧化物半导体）工艺中的DMOS（Diffused Metal-Oxide Semiconductor，双重扩散金属氧化物半导体）器件的P型阱区和N型阱区形成的工艺条件相同。其中，BCD是一种单片集成工艺技术，该技术能够在同一芯片上制作双极管bipolar，互补金属氧化物半导体CMOS（Complementary Metal Oxide Semiconductor，CMOS）和双重扩散金属氧化物半导体DMOS，从而使得光电二极管的N 型阱区、P型阱区与BCD 工艺中的DMOS 器件的N 型阱区、P型阱区能够集成在一起。模拟电路中N型阱区、P型阱区的可以作为MOS管的衬底或者横向扩散金属氧化物半导体（Laterally Diffused Metal Oxide Semiconductor，LDMOS）的沟道区。
在其他实施例中，光电二极管PN结的形成还可以通过在P+粒子在半导体衬底100的预定区域进行N+ 或P+重掺杂区扩散而形成，即在N+ 或P+重掺杂区于P型衬底100处形成光电二极管PN结。
在其他实施例中，在P型硅衬底100上的N阱中的P+ 重掺杂区形成光电二极管PN结，或在P型硅衬底上的P阱中的N+ 重掺杂区形成光电二极管PN结。
参考图3，依照COMS工艺，在第一导电类型外延层130上进行淀积和局部氧化，制作有源器件或电路部分的多个有源区和场氧化隔离区200。
在本实施例中，利用现有的标准互补金属氧化物半导体COMS工艺，在N型外延层130上进行淀积和局部氧化，形成有源器件或者电路部分的多个有源区和场氧化隔离区200。其中，有源区、场氧化隔离区200实现对有源器件之间的隔离。
在第一导电类型外延层130的不同区域分别进行第一导电类型和第二导电类型离子源/漏注入。
在本实施例中，在有源区和场氧化隔离区200的上面继续沉积多晶硅，形成多晶硅层（图中未示），经过光刻、腐蚀工艺形成有源器件（CMOS、LDMOS）的栅极。参考图3，然后对有源器件（CMOS、LDMOS）进行N型离子或P型离子注入，其中包括：第一导电类型离子（N型离子210）源/漏注入COMS工艺，采用BCD 工艺中的CMOS 器件的N 型源/漏注入，注入杂质为砷。第二导电类型离子（P型离子）源/漏注入COMS工艺，采用BCD 工艺中的CMOS 器件的P 型源/漏注入，注入杂质为硼。光电二极管与BCD工艺集成时，通过离子注入作P+掺杂和N+掺杂，分别形成光电二极管的阳极220和阴极210。光电二极管的阳极220和阴极210的形成分别与BCD 工艺中的CMOS 器件的P 型源/漏注入区、N 型源/漏注入区一起形成。
基于常用半导体工艺( 例如BCD 工艺) 制造光电二极管，降低了生产成本。由于可以采用常用的半导体工艺制造，本实施例的光电二极管可以与其它的电路元件集成制造。
步骤S20：在半导体衬底上沉积形成多层结构。
参考图4，在光电二极管的阳极220和阴极210区域依次沉积硅化物和金属形成交替的介质层（310、320、330）和金属层（314、324、334），形成多层结构，并在介质层（310、320、330）上设有通孔（312、322、332），形成模拟电路的导电线和光电二极管的阳极和阴极的引出线。
形成第一介质层310、第一接触孔312、第一金属层314、第二介质层320、第一通孔322、第二金属层324、第三介质层330、第二通孔332、第三金属层334。其中图中虚线框标记的区域340、350可以形成模拟电路导电线，也可以用于光电二极管阳极和阴极的引出线。
其中，介质层（310、320、330）为二氧化硅层；金属层（314、324、334）可以为铝层。
步骤S30：在多层结构中形成窗口，窗口位于光电二极的PN结上方。
在金属层上沉积氮化物，形成钝化层400，钝化层400为二氧化硅层或/和氮化硅层。在本实施例中，钝化层400包括依次层叠的氮化硅层和二氧化硅层。
对介质层310、320、330及其钝化层400通过光刻、腐蚀工艺形成窗口410。其中，窗口410开设在光电二极管PN结至少一部分的上方，窗口410向半导体衬底100方向延伸至场氧化隔离层200（参考图5）或者半导体衬底100（参考图6）。
进一步地，腐蚀工艺包括干法腐蚀和湿法腐蚀，干法腐蚀量和湿法腐蚀量的比例根据介质层（310、320、330）和金属层（314、324、334）的层数而定。湿法腐蚀是通过化学蚀刻液和被刻蚀物质之间的化学反应将被刻蚀物质剥离下来的刻蚀方法；干法腐蚀是指利用高能束与表面薄膜反应，形成挥发性物质，或直接轰击薄膜表面使之被腐蚀的工艺。传统的一般只采用干法腐蚀，这样就会造成光电二极管的表面不平整，从而导致光反射率变大，影响光电二极管的发光效率。在本实施例中，介质层（310、320、330）和金属层（314、324、334）的层数均为3层，干法腐蚀量与湿法腐蚀量的比例为10:1。在其他实施例中，其介质层和金属层的层数可以根据具体器件的要求而定，从而，其干法腐蚀量和湿法腐蚀量的比例也随之改变。
为了满足光电二极管需求的表面状态，干法腐蚀方法步骤，包括：
首先用干法腐蚀的工艺去除钝化层400中的氮化硅层；
然后用干法腐蚀的工艺去除钝化层的400中的二氧化硅层和部分介质层的二氧化硅层；
根据剩余的部分介质层的厚度，选择干法腐蚀和湿法腐蚀的比例（例如：本实施例中干法腐蚀量：湿法腐蚀量为10:1，在其他实施例中干法腐蚀量：湿法腐蚀量可以为，例如6:1），通过结合干法腐蚀和湿法腐蚀形成窗口。一般干法腐蚀和湿法腐蚀量的比例与模拟电路中相关的金属层次相关，金属层次越多，介质越厚，则所需要的干法腐蚀量就越多。图7为扫描电子显微镜下窗口区域腐蚀后的形貌图。
步骤S40：在窗口区域表面沉积氮化硅和/或二氧化硅形成反射层。
在窗口区域410和钝化层400的上表面沉积氮化硅和/或二氧化硅，形成反射层500。其中，在本实施例中，反射层500为氮化硅层。而反射层500的厚度为不同光波条件下二氧化硅层和/或所述氮化硅层最小反射率对应的厚度。鉴于光电二极管需要吸收光信号，且反射损耗掉的光信号尽量小，而波谷位置对应厚度的发射率最低，光损耗最少，参考图8和图9，根据工艺的难易度，在本实施例中，反射层500为氮化硅层，其反射层的厚度为110nm。如图10所示的为扫描电子显微镜下窗口区域氮化硅淀积后的形貌图。当然可以根据不同模拟电路和对应光电二极管的需求，以及使用的光波波段，可以通过调整工艺流程，在窗口区域410选择合适厚度的二氧化硅和/或氮化硅，进而实现在任意工艺平台上集成光电二极管，同时光电二极管还能与模拟电路的单芯片集成。
还可以根据需要，定义钝化打开的区域，进行干法腐蚀，腐蚀至金属层。
如图8所示的为一实施例光电二极管的剖面图，图中光电二极管可用于与模拟电路的单片集成。其中，光电二极管10a包括：
半导体衬底100，依次形成在半导体衬底100中的第一导电类型埋层110和第二导电类型埋层120。在本实施例中，半导体衬底100为P型硅衬底，第一导电类型埋层110为N型埋层；第二导电类型埋层120为P型埋层。
位于半导体衬底100的上表面的第一导电类型外延层130，设于第一导电类型外延层130的第一导电类型阱区140和第二导电类型阱区150，其中，第二导电类型埋层120与第一导电类型阱区140构成光电二极管的PN结。在本实施例中第一导电类型外延层130为N型外延层，第一导电类型阱区140为N型阱区；第二导电类型阱区150为P型阱区，并在N型阱区140和P型埋层120处形成光电二极管的PN结。
位于第一导电类型外延层130上的多个有源区和场氧化隔离区200。在本实施例中，在N型外延层130上制作器件或模拟电路部分的多个有源区和场氧化隔离区200。
光电二极管的阳极220和阴极210，通过N型离子和P型离子源/漏注入形成在第一导电类型外延层130的不同区域。在本实施例中，在N型外延层的不同区域形成光电二极管的阳极220和阴极210。
位于半导体衬底上方的介质层（310、320、330）、金属层（314、324、334）和钝化层400。
在本实施例中，通过进行层间介质、金属、接触、通孔和钝化等工艺来形成第一介质层310、第一接触孔312、第一金属层314、第二介质层320、第一通孔322、第二金属层324、第三介质层330、第二通孔332、第三金属层334。其中图中标记的区域340、350可以形成模拟电路导电线，也可以用于光电二极管阳极和阴极的引出线。其中，介质层（310、320、330），典型地，是氧化物层（SiO2层），其部分可以通过使用氧化蚀刻来去除；金属层（314、324、334）为铝层。
开设在光电二极管PN结上方的窗口410。
窗口410向半导体衬底100方向延伸至场氧化隔离区200。在本实施例中，在金属层314上沉积氮化物，形成钝化层400，钝化层400包括依次层叠的二氧化硅（SiO2）层和氮化硅（Si3N4）层，并在介质层（310、320、330）和钝化层400中形成窗口410，窗口410位于光电二极管PN结的上方，窗口410向半导体衬底100方向延伸至场氧化隔离区200。在本实施例中，钝化层400、介质层一部分被光刻去除，以便窗口410向半导体衬底100方向延伸至场氧化隔离区200。
以及位于窗口410区域的反射层500，反射层500为二氧化硅层和氮化硅层中的至少一种。
反射层500，位于钝化层400和窗口区域410的上方。反射层500为二氧化硅层和氮化硅层中的至少一种。在本实施例中，反射层500为氮化硅层。而反射层500的厚度为不同波长条件下所述二氧化硅层和/或所述氮化硅层最小反射率对应的厚度，鉴于光电二极管需要吸收光信号，且反射损耗掉的光信号尽量小，而波谷位置对应厚度的发射率最低，光损耗最少。
如图11所示的为不同材质反射层膜层厚度与反射率的关系谱线图，从图中可以看出，光波长度λ=900nm的红外光的照射下，二氧化硅对应的反射率最低（波谷）的膜层厚度为150nm或者460nm；氮化硅对应的反射率最低（波谷）的膜层厚度为110nm或者330nm。鉴于工艺的难易度，在本实施例中，反射层500为氮化硅层，其反射层的厚度为110nm。当然可以根据不同模拟电路和对应光电二极管的需求，以及使用的光波波段，可以通过调整工艺流程，在窗口区域410选择合适厚度的二氧化硅和/或氮化硅，进而实现在任意工艺平台上集成光电二极管，同时光电二极管还能与模拟电路的单芯片集成。
如图10所示的为一实施例光电二极管的剖面图，图中光电二极管可用于与模拟电路的单片集成。其中，光电二极管10b与图8中光电二极管的结构除了窗口410的延伸位置不同，其他的结构均相同，其中，窗口410向半导体衬底100方向延伸至半导体衬底100。更具体的说，钝化层400、介质层一部分被光刻去除，以便窗口410向半导体衬底100方向延伸至半导体衬底100。
本实施例可以基于常用半导体工艺( 例如CMOS 工艺) 制造该光电二极管，降低了生产成本，并且，由于可以采用常用的半导体工艺制造，本实施例的光电二极管可以与其它的电路元件集成制造。
一种光感应器，参考图12，包括模拟电路20，还包括上述光电二极管10，光电二极管10与模拟电路20集成为一体。通过对光电二极管10的光强控制，实现模拟电路20的电压的输入和电流的输出。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种制作光电二极管的方法，包括：
    在半导体衬底中形成光电二极管PN结，其中，所述光电二极管PN结与模拟电路中的有源器件是同步形成的；
    在所述半导体衬底上沉积形成多层结构；
    在所述多层结构中形成窗口，所述窗口位于所述光电二极管PN结上方；及
    在所述窗口区域表面沉积氮化硅和/或二氧化硅，形成反射层。
  2. 根据权利要求1所述的制作光电二极管的方法，其特征在于，在所述半导体衬底中形成所述光电二极管PN结包括：
    在半导体衬底上进行离子注入，形成第一导电类型埋层和第二导电类型埋层，在所述半导体衬底上热生长第一导电类型外延层；
    在所述第一导电类型外延层分别注入第一导电类型杂质和第二导电类型杂质，形成第一导电类型阱区和第二导电类型阱区，在所述第一导电类型埋层与所述第二导电类型阱区形成光电二极管PN结；
    依照COMS工艺，在所述第一导电类型外延层上进行淀积和局部氧化，制作所述有源器件或所述模拟电路的多个有源区和场氧化隔离区；
    在所述第一导电类型外延层的不同区域分别进行第一导电类型和第二导电类型离子源/漏注入，形成光电二极管的阳极和阴极。
  3. 根据权利要求2所述的方法，其特征在于，在所述半导体衬底上沉积形成多层结构包括：
    在所述光电二极管的阳极和阴极区域依次沉积硅化物和金属，形成交替的介质层和金属层，形成多层结构；及
    在所述介质层上设有通孔，形成光电二极管的阳极和阴极的引出线以及模拟电路的导电线。
  4. 根据权利要求3所述的方法，其特征在于，在所述多层结构中形成窗口包括：
    在所述金属层上沉积氮化物，形成钝化层;
    在所述介质层和钝化层中形成窗口，其中，所述窗口位于所述光电二极管PN结的上方，所述窗口向所述半导体衬底方向延伸至所述场氧化隔离层或所述半导体衬底。
  5. 根据权利要求2所述的方法，其特征在于，采用BCD工艺中DMOS器件中阱区的形成方法形成所述第一导电类型阱区和第二导电类型阱区。
  6. 根据权利要求2所述的方法，其特征在于，采用BCD工艺中的CMOS器件中的源/漏注入方法或者采用BCD工艺中双极结型晶体管的发射极注入方法对所述第一导电类型和第二导电类型离子进行源/漏注入。
  7. 根据权利要求2所述的方法，其特征在于，所述第一导电类型与所述第二导电类型的导电性相反。
  8. 根据权利要求7所述的制作光电二极管的方法，其特征在于，所述第一导电类型为N型，所述第一导电类型为P型。
  9. 根据权利要求4所述的方法，其特征在于，所述钝化层包括通过沉积形成的依次层叠的二氧化硅层和氮化硅层。
  10. 根据权利要求9所述的方法，其特征在于，在所述多层结构中形成窗口包括：
    干法腐蚀去除所述钝化层中的氮化硅层；
    干法腐蚀去除所述钝化层的二氧化硅层和部分介质层的二氧化硅层；
    根据剩余的部分介质层的厚度，选择干法腐蚀和湿法腐蚀量的比例，结合干法腐蚀和湿法腐蚀形成窗口。
  11. 一种光电二极管，包括：
    半导体衬底；
    形成在所述半导体衬底中的第一导电类型埋层和第二导电类型埋层；
    位于所述半导体衬底的上表面的第一导电类型外延层，设于所述第一导电类型外延层中的第一导电类型阱区和第二导电类型阱区，其中，所述第一导电类型埋层与所述第二导电类型阱区构成光电二极管PN结；
    位于所述第一导电类型外延层上的多个有源区和场氧化隔离区；
    光电二极管的阳极和阴极，通过第一导电类型和第二导电类型离子源/漏注入形成在所述第一导电类型外延层的不同区域；
    位于所述半导体衬底上方的介质层、金属层和钝化层；
    开设在所述光电二极管PN结上方的窗口；所述窗口向所述半导体衬底方向延伸至所述场氧化隔离区或所述半导体衬底；以及
    位于所述窗口区域的反射层，所述反射层为二氧化硅层和氮化硅层中的至少一种。
  12. 根据权利要求11所述的光电二极管，其特征在于，所述反射层的厚度为预设波长条件下所述反射层最小反射率对应的厚度。
  13. 根据权利要求12所述的光电二极管，其特征在于，所述反射层为厚度为110纳米的氮化硅层。
  14. 一种光感应器，包括模拟电路，还包括如权利要求11~13任一项所述的光电二极管，所述光电二极管与所述模拟电路集成为一体。
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