WO2017118105A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2017118105A1
WO2017118105A1 PCT/CN2016/099880 CN2016099880W WO2017118105A1 WO 2017118105 A1 WO2017118105 A1 WO 2017118105A1 CN 2016099880 W CN2016099880 W CN 2016099880W WO 2017118105 A1 WO2017118105 A1 WO 2017118105A1
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Prior art keywords
conductive structure
array substrate
layer
conductive
forming
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PCT/CN2016/099880
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English (en)
French (fr)
Inventor
江鹏
周茂秀
杨海鹏
戴珂
尹傛俊
王章涛
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/525,765 priority Critical patent/US10163938B2/en
Publication of WO2017118105A1 publication Critical patent/WO2017118105A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the array substrate of the display device includes a plurality of mutually parallel gate lines 1 and a plurality of parallel data lines 2, and the gate lines 1 and the data lines 2 enclose a plurality of pixel units 3 at the gate lines.
  • a thin film transistor 4 is disposed at an intersection of the first and the data lines 2. By controlling the on and off of the thin film transistor 4, the pixel unit 3 corresponding to the thin film transistor 4 can be controlled to display a screen, and the display screen of the display device can be controlled.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device, which can improve the problem that the display device cannot display the screen normally due to signal delay.
  • At least one embodiment of the present invention provides an array substrate including a plurality of mutually parallel gate lines, an insulating layer on a film layer on which the plurality of gate lines are located, and at least one first conductive layer on the insulating layer a structure, the insulating layer is provided with at least two first vias corresponding to the first conductive structure, and the first conductive structure is electrically connected to the gate line through the first via.
  • At least one embodiment of the present invention also provides a display device including the array substrate as described above.
  • At least one embodiment of the present invention further provides a method for fabricating an array substrate, the method comprising: forming a gate metal layer, forming a pattern including a gate line through a patterning process; and forming a gate line on the film layer Forming an insulating layer, forming at least two first via holes corresponding to the first conductive structure on the insulating layer through a patterning process; forming a first conductive layer on the insulating layer, forming a first process by a patterning process a pattern of a conductive structure, wherein the first conductive structure is electrically connected to the gate line through the first via.
  • 1 is a plan view showing the structure of an array substrate
  • FIG. 2 is a plan view of a planar structure of an array substrate according to an embodiment of the present invention.
  • Figure 3 is a cross-sectional view taken along line C-C' of Figure 2;
  • FIG. 4 is a plan view 2 of a planar structure of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a third structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a plan view 4 of a planar structure of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a fifth structural diagram of an array substrate according to an embodiment of the present invention.
  • Figure 8 is a cross-sectional view taken along line D-D' of Figure 7;
  • FIG. 9 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present invention.
  • 0-substrate substrate 1-gate line/signal line; 2-data line; 3-pixel unit; 4-thin film transistor; 5-insulating layer; 6-first conductive structure; 7-first via hole; Source; 9-drain; 10-active layer; 11-etch barrier layer; 12-second via; 13-third via; 14-passivation layer; 15-second conductive structure; Fourth via; 17-pixel electrode.
  • the process of displaying the picture by the pixel unit 3 at the A position is that the driving signal of the gate line 1 reaches the pixel unit 3 at the A position, and the thin film transistor 4 corresponding to the pixel unit 3 at the A position is turned on.
  • the drive signal (data signal) of the data line 2 also reaches the pixel unit 3 at the A position, the voltage is applied to the pixel electrode of the pixel unit 3 at the A position, and the pixel unit 3 that drives the A position displays the picture.
  • the inventor of the present application found in the actual research process that, as shown in FIG. 1, since the driving manner of the pixel unit 3 is generally scanning a single gate line 1 from left to right and scanning a single data line 2 from above to the left, The gate line 1 of the display device of the large-size display screen is relatively long, and a signal delay is generated.
  • the driving signal of the gate line 1 reaches the pixel unit 3 of the A position later than the driving signal of the data line 2, and thus the gate
  • the driving signal of the data line 2 has passed through the pixel unit 3 at the A position, so that the pixel unit 3 at the A position cannot display the picture normally, and thus the display screen of the display device is not displayed. Complete, the afterimage appears.
  • Embodiments of the present invention provide an array substrate, a method of manufacturing the same, and a display device.
  • the array substrate includes: a plurality of mutually parallel signal lines, an insulating layer on the film layer on which the plurality of signal lines are located, and at least one first conductive structure on the insulating layer. At least two first vias corresponding to the first conductive structure are disposed on the insulating layer, and the first conductive structure is electrically connected to the signal line through the at least two first vias.
  • the array substrate can be applied to a display device having a large-sized display panel, and can also help the display panel including the array substrate to be completely displayed, avoiding the occurrence of afterimages.
  • This embodiment provides an array substrate, as shown in FIG. 2 and FIG. 3, the array substrate includes multiple strips.
  • the gate lines 1 parallel to each other further include an insulating layer 5 on the film layer where the plurality of gate lines 1 are located, and at least one first conductive structure 6 on the insulating layer 5.
  • the insulating layer 5 is provided with a corresponding first conductive structure.
  • the at least two first vias 7 of the first conductive structure 6 are electrically connected to the gate line 1 through the at least two first vias 7.
  • the first conductive structure 6 is electrically connected to the gate line 1 through the at least two first via holes 7, the first conductive structure 6 is connected in parallel with the gate line 1, which is equivalent to the gate line. 1 a resistor is connected in parallel, thereby reducing the resistance value of the entire gate line 1 as a whole. Moreover, according to the relationship between the resistance value and the signal delay time, the resistance value is proportional to the signal delay time, and thus reducing the resistance value of the gate line 1 can reduce the signal delay time of the gate line 1. Compared with the position of the first pixel unit 3 that cannot be normally displayed in the normal array substrate in the row (for example, the pixel unit 3 at the A position in FIG.
  • the signal of the pixel unit 3 reaching the A position is obtained.
  • the resistance of the passed gate line 1 is reduced, thereby reducing the signal delay time, so that when the driving signal of the gate line 1 reaches the pixel unit 3 at the A position, the driving signal of the data line 2 can just reach the A position as set.
  • the pixel unit 3 is such that the pixel unit 3 at the A position can display the picture normally, and thus cannot be normally displayed in the embodiment of the present invention compared with the number of the pixel units 3 that cannot be normally displayed in the technical solution scheme shown in FIG.
  • the number of pixel units 3 can be significantly reduced, thereby improving the problem that the display device cannot display the screen normally. It is to be noted that the present embodiment is described in detail with the signal line as the gate line.
  • the embodiments of the present invention include but are not limited thereto, and the signal line may also be other signal lines such as data lines.
  • the signal line may be a data line.
  • the first conductive structure 6 is strip-shaped, and the extending direction of the first conductive structure 6 is the same as the extending direction of the gate line 1.
  • At least two first via holes 7 are disposed at least at both ends of the first conductive structure 6, so that the size of the first conductive structure 6 is not In the case of a change, the utilization efficiency of the first conductive structure 6 is improved, and the overall resistance value of the entire gate line 1 is reduced.
  • the “at least one first conductive structure” may be one first conductive structure 6 or multiple first conductive structures 6 .
  • the first conductive structure 6 when the array substrate includes a first conductive structure 6, "the first conductive structure 6 is electrically connected to the gate line 1 through at least two first via holes 7" may be the first conductive structure 6 through the first The via hole 7 is electrically connected to one of the plurality of gate lines 1.
  • the array substrate includes more When the first conductive structures 6 are, "the first conductive structures 6 are electrically connected to the gate lines 1 through the at least two first via holes 7", as shown in FIG.
  • each group includes a specific number of first conductive structures 6, each of which includes a first conductive structure 6 corresponding to a gate line 1, in the direction in which the gate lines 1 extend, each group includes A conductive structure 6 is electrically connected to a gate line 1 through a plurality of first via holes 7, respectively.
  • the first conductive structure 6 is electrically connected to the gate line 1 through the at least two first via holes 7" may also be other cases, which are not enumerated here.
  • each of the first conductive structures 6 included in each group corresponds to one gate line 1.
  • each of the first conductive structures 6 included in each group passes through the first vias, respectively. 7 is electrically connected to a gate line 1.
  • the resistance of each gate line 1 can be reduced, so that the signal delay time of each gate line 1 can be reduced, so that the number of pixel units 3 that cannot be normally displayed is further reduced. Further, the problem that the display device cannot display the screen normally can be improved.
  • the insulating layer 5 may be a gate insulating layer or another insulating layer, which is not specifically limited.
  • the projection of the first conductive structure 6 on the array substrate (eg, the substrate substrate 0) and the projection of the gate lines 1 on the array substrate may at least partially overlap, disposed on the insulating layer 5.
  • the first via 7 is at least partially located in the overlapping region, and the first conductive structure 6 is electrically connected to the gate line 1 through at least two first vias 7; further, the projection and gate of the first conductive structure 6 on the array substrate
  • the projection of the line 1 on the array substrate may also not overlap.
  • the projection of the first conductive structure 6 on the array substrate is just in contact with the projection of the gate line 1 on the array substrate, and the first via hole 7 is located at the first conductive layer.
  • the first via hole 7 may be filled with a conductive material, and the first conductive structure 6 is in contact with the edge of the gate line 1 through the conductive material in the first via hole 7, thereby achieving electrical connection.
  • the projection of the first conductive structure 6 on the array substrate and the projection of the gate line 1 on the array substrate at least partially overlap, and the first via 7 disposed on the insulating layer 5 is at least partially located.
  • the first conductive structure 6 has a larger contact area with the gate line 1 than the projection of the first conductive structure 6 on the array substrate and the projection of the gate line 1 on the array substrate. The connection of the first conductive structure 6 and the gate line 1 is made more stable.
  • the projection of the first conductive structure 6 on the array substrate can be within the projection of the gate line 1 on the array substrate. Since the gate line 1 is located in a light-shielding region of the array substrate (for example, covered by a black matrix), The first conductive structure 6 is also located in the light-shielding region and does not affect the aperture ratio of the display device.
  • the array substrate further includes a thin film transistor including a source 8 and a drain 9, and the source 8 and the drain 9 are both in the same layer as the first conductive structure 6. They are disposed and are not in contact with the first conductive structure 6.
  • the array substrate further includes a data line 2 that intersects the gate lines to define pixel units arranged in sequence, and the first conductive structure 6 is also disposed in the same layer as the data lines 2, and thus can be formed in the same preparation process, thereby simplifying The fabrication process of the array substrate.
  • the first conductive structure 6 needs to be disposed along the direction of the gate line 1 between the adjacent two drains 9, that is, the first conductive structure 6 is disposed between the adjacent two pixel units in the direction of the gate line 1.
  • the thin film transistor may further include an active layer 10 and an etch stop layer 11 between the insulating layer 5 and the film layer where the source 8 and the drain 9 are located, and the etch barrier
  • the layer 11 is provided with a second via 12 corresponding to the source 8 and a third via 13 corresponding to the drain, and the source 8 and the drain 9 are respectively activated through the second via 12 and the third via 13 Layer 10 is connected. Since the etch stop layer 11 is provided on the active layer 10, when the source 8 and the drain 9 are etched on the active layer 10, the active layer 10 is not etched, so that the active layer 10 is not affected. Performance.
  • the array substrate can include a passivation layer 14 on the film layer on which the first conductive structure 6 is located, and at least one second conductive layer on the passivation layer 14.
  • the passivation layer 14 is provided with at least two fourth via holes 16 corresponding to the second conductive structure 15, and the second conductive structure 15 is electrically connected to the first conductive structure 6 through at least two fourth via holes 16.
  • the second conductive structure 15 is electrically connected to the first conductive structure 6 through the at least two fourth vias 16, the second conductive structure 15 and the gate line 1 and the first conductive structure 6 are The constituent structures are connected in parallel, which is equivalent to a resistor in parallel with the structure composed of the gate line 1 and the first conductive structure 6, so that the resistance value of the entire gate line 1 as a whole can be further reduced.
  • the addition of the second conductive structure 15 can further improve the problem that the display device cannot display the screen normally.
  • the "at least one second conductive structure 15" may be a second conductive structure 15 or a plurality of second conductive structures 15.
  • the second conductive structure 15 is electrically connected to the first conductive structure 6 through the at least two fourth vias 16
  • the structure 6 is electrically connected;
  • a second conductive structure 15 may also be electrically connected to the plurality of first conductive structures 6 through at least two fourth vias 16.
  • a second conductive structure 15 is electrically connected to the two first conductive structures 6 through the two fourth via holes 16, respectively.
  • the array substrate includes a plurality of second conductive structures 15, "the second conductive structures 15 are electrically connected to the first conductive structures through the at least two fourth vias 16" may be in the extending direction of the gate lines 1, each of the first The two conductive structures 15 are respectively electrically connected to a first conductive structure 6; or, as shown in FIG. 6, in the extending direction of the at least one gate line 1, a plurality of first conductive structures 6 are sequentially disposed, and the second conductive structures 15 are located.
  • the second conductive structure 15 is electrically connected to the two first conductive structures 6 adjacent to the second conductive structure 15 through the two fourth via holes 16, respectively. That is, in the extending direction of the gate line 1, the second conductive structure 15 connects the first conductive structures 6 together through the fourth via holes 16; further, “the second conductive structure 15 passes through at least two fourth via holes 16 Electrically connected to the first conductive structure 6" may also be other structures, which are not enumerated here.
  • each gate line 1 a plurality of first conductive structures 6 are sequentially spaced apart, and a second conductive structure 15 is located between any adjacent two first conductive structures 6, and the second conductive structure 15 passes
  • the fourth via holes 16 are electrically connected to the two first conductive structures 6 adjacent to the second conductive structure 15 respectively.
  • the first conductive structures 6 and the second conductive structures 15 may cover the entire gate lines, which is equivalent to
  • Each of the gate lines 1 is connected in parallel with a plurality of resistors, so that the overall resistance of the gate lines is further reduced, and the signal delay time of each of the gate lines 1 can be further reduced, so that the display device can normally display the picture.
  • the array substrate further includes a plurality of parallel data lines 2, and the data lines 2 can be disposed in the same layer as the source 8 and the drain 9.
  • the data line 2 and the source 8 The drain electrode 9 and the drain electrode 9 can be formed simultaneously, thereby simplifying the fabrication process of the array substrate.
  • the gate line 1 and the data line 2 may enclose a plurality of pixel units 3, and a thin film transistor is disposed in the pixel unit 3.
  • the thin film transistor includes a source 8 and a drain 9 disposed in the pixel unit 3 Inside.
  • the first conductive structure 6 is also disposed in the pixel unit 3, the first conductive structure 6 is in one-to-one correspondence with the pixel unit 3, and the second conductive structure 15 is disposed in any adjacent two pixel units 3. between.
  • the first conductive structure 6 is in one-to-one correspondence with the pixel unit 3, which can reduce the process complexity; moreover, the second conductive structure 15 is disposed between any adjacent two pixel units 3, and can be not in the gate line 1
  • the second conductive structure 15 is connected in parallel at a position covered by the conductive structure 6, so that the entire gate line 1 is connected in parallel with a conductive structure, thereby reducing the resistance of the gate line 1. Therefore, such a design can reduce the process complexity and reduce the resistance of the gate line 1 to cause the display device to display the picture normally.
  • the projection of the second conductive structure 15 on the array substrate and the projection of the first conductive structure 6 on the array substrate may at least partially overlap, and the fourth via 16 disposed on the passivation layer 14 Located in the overlapping region, the second conductive structure 15 is electrically connected to the first conductive structure 6 through the fourth via 16; further, the projection of the second conductive structure 15 on the array substrate and the first conductive structure 6 on the array substrate The projections of the second conductive structure 15 on the array substrate and the projection of the first conductive structure 6 on the array substrate are just in contact, and the fourth via 16 is located at the contact of the second conductive structure 15 .
  • the fourth via 16 may be filled with a conductive material, and the second conductive structure 15 is in contact with the edge of the first conductive structure 6 through the conductive material in the fourth via 16, thereby achieving electrical connection.
  • the projection of the second conductive structure 15 on the array substrate and the projection of the first conductive structure 6 on the array substrate at least partially overlap with the projection of the second conductive structure 15 on the array substrate.
  • the contact area of the second conductive structure 15 with the first conductive structure 6 is larger than the projection of the conductive structure 6 on the array substrate, so that the connection between the second conductive structure 15 and the first conductive structure 6 can be made more. stable.
  • the array substrate further includes a gate disposed in the same layer as the gate line 1, and the projection of the second conductive structure 15 on the array substrate and the projection of the gate on the array substrate may at least partially overlap.
  • the above gate is also included in the thin film transistor.
  • the second conductive structure 15 is electrically connected to the first conductive structure 6, the first conductive structure 6 is electrically connected to the gate line 1, and thus the second conductive structure 15 is electrically connected to the gate line 1, and further, since the gate line 1 is connected to the gate line , for example, formed integrally, so that the signal loaded on the second conductive structure 15 is the same as the gate signal loaded on the gate; in addition, due to the projection of the second conductive structure 15 on the array substrate and the gate on the array substrate The projections at least partially overlap, and in the thin film transistor, the projection of the gate on the array substrate overlaps with the projection of the active layer 10 on the array substrate, and thus, the second conductive structure 15 at least partially overlaps the active layer 10. This causes the second conductive structure 15 and the gate to collectively drive the active layer 10 when the gate signal is applied to the second conductive structure 15 and the gate, thereby increasing the carrier mobility in the active layer 10, Improve the display performance of the display device.
  • the array substrate may further include a pixel electrode 17 disposed on the passivation layer 14, and the second conductive structure 15 is disposed in the same material as the pixel electrode 17.
  • the second conductive structure 15 can be formed simultaneously with the pixel electrode 17, thereby simplifying the fabrication process of the array substrate.
  • the gate line 1 since the gate line 1 has the first conductive structure 6 and the second conductive structure 15 connected in parallel thereto, the resistance of the gate line 1 is small, and slightly increasing the resistance of the gate line 1 does not affect the display effect of the display screen.
  • the width of the gate line 1 can be reduced such that the width of the gate line 1 ranges from 2 ⁇ m to 10 ⁇ m, and the width of the gate line 1 can be reduced as compared with the width of the gate line of the prior art of 20 ⁇ m or more. Increase the aperture ratio of the display device.
  • the width of the gate line 1 at the position of the first via hole 7 is made to make the first conductive structure 6 and the gate line 1 electrically connected more stably.
  • the width of the first via hole 7 formed at this time is larger than the width at other positions of the gate line 1, and thus the connection between the first conductive structure 6 and the gate line 1 can be made more stable.
  • the gate line 1 is wider at the position of the second via 16 than at other positions of the gate line 1.
  • the embodiment further provides a display device, including the array substrate provided by the above technical solution. Since the display device includes the array substrate in the above technical solution, the display device has the same beneficial effects as the array substrate in the above technical solution, and details are not described herein again.
  • the display device may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator, and the like.
  • This embodiment further provides a method for fabricating an array substrate. As shown in FIG. 9, the method includes the following steps S801-S803.
  • S801 forming a metal layer, and forming a pattern including signal lines through a patterning process.
  • S802 forming an insulating layer on the film layer where the signal line is located, and forming at least two first via holes corresponding to the first conductive structure to be formed on the insulating layer through a patterning process.
  • S803 forming a first conductive layer on the insulating layer, and forming a pattern including the first conductive structure through a patterning process, wherein the first conductive structure is electrically connected to the signal line through the at least two first via holes.
  • This embodiment provides a method for fabricating an array substrate. As shown in FIG. 10, the method includes the following steps S901 to S903:
  • a gate metal layer is formed by plasma enhanced chemical vapor deposition, sputtering, or thermal evaporation, a photoresist is coated on the gate metal layer, and a mask mask having a pattern of gate lines is used to cover the photolithography. After the step of exposing, developing, etching, etc., the gate metal layer of the glue forms a pattern including the gate lines.
  • an insulating layer on the film layer where the gate line is located, and forming at least two first via holes corresponding to the first conductive structure (the first conductive structure to be formed) on the insulating layer through a patterning process.
  • an insulating layer is formed on the film layer where the gate line is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, and then at least two corresponding to the first conductive structure are formed on the insulating layer by a patterning process.
  • the first via is formed on the film layer where the gate line is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, and then at least two corresponding to the first conductive structure are formed on the insulating layer by a patterning process.
  • a first conductive layer is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, a photoresist is coated on the first conductive layer, and a mask is coated with a pattern having a first conductive structure.
  • the gate layer coated with the photoresist is subjected to exposure, development, etching, etc. to form a pattern including the first conductive structure.
  • the first conductive structure Since the first conductive structure is electrically connected to the gate line through the at least two first via holes, the first conductive structure is connected in parallel with the gate line, which is equivalent to connecting a resistor in parallel with the gate line, thereby reducing the overall gate line as a whole.
  • the resistance value and, according to the relationship between the resistance value and the signal delay time, the resistance value is proportional to the signal delay time, so reducing the resistance value of the gate line can reduce the signal delay time of the gate line, so that Some of the pixel units that may not be normally displayed in the illustrated technical solution become normal display, and the number of pixel units that cannot be normally displayed in the present invention is compared with the number of pixel units that cannot be normally displayed in the technical solution shown in FIG.
  • the present embodiment is described in detail with the signal line as the gate line.
  • the embodiments of the present invention include but are not limited thereto, and the signal line may also be other signal lines such as data lines.
  • the signal line can be a data line.
  • the method for fabricating the array substrate may further include: forming an active layer film layer on the insulating layer, forming a pattern including the active layer by a patterning process; and forming a layer on the active layer Forming an etch barrier layer, forming a second via hole corresponding to the source (source to be formed) and a third via corresponding to the drain (drain to be formed) on the etch barrier layer through a patterning process
  • the pattern of the first conductive structure and the pattern of the source and drain are simultaneously formed by one patterning process.
  • the source and the drain are electrically connected to the active layer through the second via and the third via, respectively.
  • Forming at least two second vias of the structure Forming at least two second vias of the structure; forming a second conductive layer on the passivation layer, forming a pattern including the second conductive structure through a patterning process, the second conductive structure being electrically connected to the first conductive structure through the second via hole,
  • a second conductive layer is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, a photoresist is coated on the second conductive layer, and a mask is coated with a pattern having a second conductive structure.
  • the gate layer coated with the photoresist is subjected to exposure, development, etching, etc. to form a pattern including the second conductive structure.
  • the method of fabricating the array substrate further includes: forming a gate electrode, the projection of the second conductive structure on the array substrate and the projection of the gate on the array substrate at least partially overlapping.
  • the design allows the second conductive structure and the gate to drive the active layer together, thereby increasing the carrier mobility in the active layer and improving the display performance of the display device.

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Abstract

一种阵列基板及其制作方法、显示装置。该阵列基板包括：多条相互平行的信号线（1）、位于多条信号线（1）所在膜层上的绝缘层（5）以及位于绝缘层（5）上的至少一个第一导电结构（6），绝缘层（5）上设置有对应于第一导电结构（6）的至少两个第一过孔（7），第一导电结构（6）通过至少两个第一过孔（7）与信号线（1）电连接。该阵列基板可应用于具有大尺寸显示屏幕的显示装置中，并可改善因信号延迟导致的显示装置不能正常显示画面的问题。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
通常，如图1所示，显示装置的阵列基板包括多条相互平行的栅线1和多条相互平行的数据线2，栅线1和数据线2围成多个像素单元3，在栅线1和数据线2的交叉处设置有薄膜晶体管4，通过控制薄膜晶体管4的导通与断开，可以控制该薄膜晶体管4对应的像素单元3显示画面，进而可控制显示装置显示画面。
发明内容
本发明的实施例提供了一种阵列基板及其制作方法、显示装置，可以改善因信号延迟而导致的显示装置不能正常显示画面的问题。
本发明的至少一个实施例提供了一种阵列基板，包括多条相互平行的栅线、位于所述多条栅线所在膜层上的绝缘层以及位于所述绝缘层上的至少一个第一导电结构，所述绝缘层上设置有对应于所述第一导电结构的至少两个第一过孔，所述第一导电结构通过所述第一过孔与所述栅线电连接。
此外，本发明的至少一个实施例还提供了一种显示装置，该显示装置包括如上所述的阵列基板。
此外，本发明的至少一个实施例还提供了一种阵列基板的制作方法，所述制作方法包括：形成栅金属层，经过构图工艺形成包括栅线的图形；在所述栅线所在膜层上形成绝缘层，经过构图工艺在所述绝缘层上形成对应于第一导电结构的至少两个第一过孔；在所述绝缘层上形成第一导电层，经过构图工艺形成包括所述第一导电结构的图形，其中，所述第一导电结构通过所述第一过孔与所述栅线电连接。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种阵列基板的平面结构图；
图2为本发明一实施例提供的阵列基板的平面结构图一；
图3为图2中沿C-C’方向的剖面图；
图4为本发明实施例提供的阵列基板的平面结构图二；
图5为本发明实施例提供的阵列基板的平面结构图三；
图6为本发明实施例提供的阵列基板的平面结构图四；
图7为本发明实施例提供的阵列基板的平面结构图五；
图8为图7中沿D-D’方向的剖面图；
图9为本发明实施例提供的一种阵列基板的制作方法流程图；以及
图10为本发明实施例提供的另一种阵列基板的制作方法流程图。
附图标记说明：
0-衬底基板；1-栅线/信号线；2-数据线；3-像素单元；4-薄膜晶体管；5-绝缘层；6-第一导电结构；7-第一过孔；8-源极；9-漏极；10-有源层；11-刻蚀阻挡层；12-第二过孔；13-第三过孔；14-钝化层；15-第二导电结构；16-第四过孔；17-像素电极。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。另外，附图中各膜层的厚度和形状不反映真实比例，目的只是示意说明本发明内容。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的”第一”、”第二” 以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。”包括”或者”包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。”连接”或者”相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常，如图1所示，使A位置的像素单元3显示画面的过程为：栅线1的驱动信号到达A位置的像素单元3，使A位置的像素单元3对应的薄膜晶体管4导通，与此同时，数据线2的驱动信号(数据信号)也到达A位置的像素单元3，为A位置的像素单元3的像素电极加载电压，驱动A位置的像素单元3显示画面。
然而，本申请发明人在实际研究过程中发现，如图1所示，由于像素单元3的驱动方式通常为从左向右扫描单条栅线1以及从上向下扫描单条数据线2，而具有大尺寸显示屏幕的显示装置的栅线1比较长，会产生信号延迟。例如：当需要驱动A位置的像素单元3时，由于栅线1的驱动信号的信号延迟，会使栅线1的驱动信号比数据线2的驱动信号晚到达A位置的像素单元3，因而栅线1的驱动信号到达A位置的像素单元3时，数据线2的驱动信号已经经过A位置的像素单元3，导致A位置的像素单元3不能正常显示画面，因而会导致显示装置的显示画面不完整，出现残像。
本发明实施例提供一种阵列基板及其制造方法以及显示装置。该阵列基板包括：多条相互平行的信号线、位于多条信号线所在膜层上的绝缘层以及位于绝缘层上的至少一个第一导电结构。绝缘层上设置有对应于第一导电结构的至少两个第一过孔，第一导电结构通过该至少两个第一过孔与信号线电连接。该阵列基板可应用于具有大尺寸显示面板的显示装置中，并且还可帮助包括该阵列基板的显示面板显示画面完整，避免出现残像。
下面结合附图对本发明实施例提供的阵列基板及其制造方法以及显示装置进行说明。
实施例一
本实施例提供了一种阵列基板，如图2和图3所示，该阵列基板包括多条 相互平行的栅线1，还包括位于多条栅线1所在膜层上的绝缘层5以及位于绝缘层5上的至少一个第一导电结构6，绝缘层5上设置有对应于第一导电结构6的至少两个第一过孔7，第一导电结构6通过该至少两个第一过孔7与栅线1电连接。
在本实施例提供的阵列基板中，由于第一导电结构6通过至少两个第一过孔7与栅线1电连接，使得第一导电结构6与栅线1并联，这相当于为栅线1并联一个电阻，因而可减小整条栅线1整体上的电阻值。并且，根据电阻值和信号延时时间的关系式可知，电阻值与信号延迟时间呈正比，因而减小栅线1的电阻值可减小栅线1的信号延迟时间。与通常的阵列基板中首个无法正常显示的像素单元3在行中的位置(例如，图1中A位置的像素单元3)相比，本发明中，由于到达A位置的像素单元3的信号所经过的栅线1的电阻减小，从而减小信号延迟时间，使得当栅线1的驱动信号到达A位置的像素单元3时，数据线2的驱动信号能够如设定地恰好到达A位置的像素单元3，从而使得A位置的像素单元3可正常显示画面，因而与例如图1所示的技术放方案中无法正常显示的像素单元3的数量相比，本发明实施例中无法正常显示的像素单元3的数量可以明显减少，因而可改善显示装置不能正常显示画面的问题。值得注意的是，本实施例以信号线为栅线进行了详细的说明，然而，本发明实施例包括但不限于此，信号线还可为数据线等其他信号线。例如，当采用本实施例提供的阵列基板的显示面板的尺寸较大或显示面板的数据线比栅线长时，信号线可为数据线。
例如，在本实施例一示例提供的阵列基板中，如图2所述，第一导电结构6为条状，第一导电结构6的延伸方向与栅线1的延伸方向相同。
例如，在本实施例一示例提供的阵列基板中，如图2所述，至少两个第一过孔7至少设置在第一导电结构6的两端，从而可在第一导电结构6尺寸不变的情况下，提高第一导电结构6的利用效率，减小整条栅线1的整体电阻值。
需要说明的是，“至少一个第一导电结构”可为一个第一导电结构6或者多个第一导电结构6。如图4所示，当阵列基板包括一个第一导电结构6时，“第一导电结构6通过至少两个第一过孔7与栅线1电连接”可为第一导电结构6通过第一过孔7与多条栅线1中的一条栅线1电连接。当阵列基板包括多 个第一导电结构6时，“第一导电结构6通过至少两个第一过孔7与栅线1电连接”可如图5所示，在栅线1的延伸方向上，多个第一导电结构6分别通过多个第一过孔7与多条栅线1中的一条栅线1电连接；或者，可如图6所示，将多个第一导电结构6按照栅线1的数量分为多组，每组均包括特定数量的第一导电结构6，每组所包括的第一导电结构6对应于一条栅线1，在栅线1的延伸方向上，每组所包括的第一导电结构6分别通过多个第一过孔7与一条栅线1电连接。此外，“第一导电结构6通过至少两个第一过孔7与栅线1电连接”还可为其他情形，此处不再一一列举。例如，如图6所示，每组所包括的第一导电结构6对应于一条栅线1，在栅线1的延伸方向上，每组所包括的第一导电结构6分别通过第一过孔7与一条栅线1电连接，此时可使减小每条栅线1的电阻，从而可减小每条栅线1的信号延迟时间，使得无法正常显示的像素单元3的数量进一步减少，进而可改善显示装置不能正常显示画面的问题。
还需说明的是，绝缘层5可为栅绝缘层也可为其他绝缘层，对此不作具体限定。
例如，如图2所示，第一导电结构6在阵列基板(例如，衬底基板0)上的投影和栅线1在阵列基板上的投影可至少部分交叠，设置在绝缘层5上的第一过孔7至少部分位于该交叠区域内，第一导电结构6通过至少两个第一过孔7与栅线1电连接；此外，第一导电结构6在阵列基板上的投影和栅线1在阵列基板上的投影也可不交叠，此时，例如第一导电结构6在阵列基板上的投影与栅线1在阵列基板上的投影恰好接触，第一过孔7位于第一导电结构6的上述接触边缘，第一过孔7中可以填充有导电材料，进而第一导电结构6通过第一过孔7中的导电材料与栅线1的边缘接触，从而实现电连接。例如，如图2所示，第一导电结构6在阵列基板上的投影和栅线1在阵列基板上的投影至少部分交叠，且设置在绝缘层5上的第一过孔7至少部分位于该交叠区域内，与第一导电结构6在阵列基板上的投影和栅线1在阵列基板上的投影不交叠相比，第一导电结构6与栅线1接触面积较大，因而可使第一导电结构6和栅线1的连接更稳定。
例如，第一导电结构6在阵列基板上的投影可位于栅线1在阵列基板上的投影内。由于栅线1位于阵列基板的遮光区域(例如，被黑矩阵覆盖)，因而 第一导电结构6也位于遮光区域，不会影响显示装置的开口率。在上述实施例中，如图2和图3所示，阵列基板还包括薄膜晶体管，该薄膜晶体管包括源极8和漏极9，源极8和漏极9均与第一导电结构6同层设置，且均与第一导电结构6不接触。由于源极8和漏极9与第一导电结构6同层设置，因而可同时形成，从而可减化阵列基板的制作工艺。此外，阵列基板还包括数据线2，其与栅线彼此交叉以界定依次排列的像素单元，第一导电结构6与数据线2也同层设置，因而可在同一制备工艺中形成，从而可简化阵列基板的制作工艺。需要说明的是，由于源极8和漏极9均与第一导电结构6不接触，且第一导电结构6在阵列基板上的投影与栅线1在阵列基板上的投影至少部分交叠，因而第一导电结构6需设置在：沿栅线1方向，相邻的两个漏极9之间，也即第一导电结构6沿栅线1方向设置在相邻两个像素单元之间。
例如，如图3所示，在一个示例中，薄膜晶体管还可以包括位于绝缘层5和源极8和漏极9所在膜层之间的有源层10和刻蚀阻挡层11，刻蚀阻挡层11上设置有对应于源极8的第二过孔12和对应于漏极的第三过孔13，源极8和漏极9分别通过第二过孔12和第三孔13与有源层10连接。由于有源层10上设置有刻蚀阻挡层11，因而在有源层10上刻蚀形成源极8和漏极9时，不会刻蚀有源层10，从而不会影响有源层10的性能。
例如，如图7和图8所示，在另一个示例中，阵列基板可以包括位于第一导电结构6所在膜层上的钝化层14，以及位于钝化层14上的至少一个第二导电结构15，钝化层14上设置有对应于第二导电结构15的至少两个第四过孔16，第二导电结构15通过至少两个第四过孔16与第一导电结构6电连接。
在本实施例提供的阵列基板中，由于第二导电结构15通过至少两个第四过孔16与第一导电结构6电连接，使得第二导电结构15与栅线1和第一导电结构6组成的结构并联，这相当于为栅线1和第一导电结构6组成的结构并联一个电阻，因而可进一步减小整条栅线1整体上的电阻值。参见上述第一导电结构6的有益效果可知，增加第二导电结构15可进一步改善显示装置无法正常显示画面的问题。
例如，同第一导电结构6相类似，“至少一个第二导电结构15”可为一个第二导电结构15或者多个第二导电结构15。当阵列基板包括一个第二导电结 构15时，“第二导电结构15通过至少两个第四过孔16与第一导电结构6电连接”可为一个第二导电结构15通过至少两个第四过孔16与一个第一导电结构6电连接；还可为一个第二导电结构15通过至少两个第四过孔16与多个第一导电结构6电连接。
例如，如图7所示，在栅线1的延伸方向上，一个第二导电结构15分别通过两个第四过孔16与两个第一导电结构6电连接。当阵列基板包括多个第二导电结构15时，“第二导电结构15通过至少两个第四过孔16与第一导电结构电连接”可为在栅线1的延伸方向上，每个第二导电结构15分别与一个第一导电结构6电连接；或者，如图6所示，在至少一条栅线1的延伸方向上，多个第一导电结构6依次设置，第二导电结构15位于任意相邻的两个第一导电结构6之间，第二导电结构15通过两个第四过孔16分别和与该第二导电结构15相邻的两个第一导电结构6电连接，也即，在栅线1的延伸方向上，第二导电结构15通过第四过孔16将第一导电结构6串接在一起；此外，“第二导电结构15通过至少两个第四过孔16与第一导电结构6电连接”还可为其他结构，此处不再一一列举。例如，在每条栅线1的延伸方向上，多个第一导电结构6依次间隔设置，第二导电结构15位于任意相邻的两个第一导电结构6之间，第二导电结构15通过第四过孔16分别和与该第二导电结构15相邻的两个第一导电结构6电连接，此时，第一导电结构6和第二导电结构15可以覆盖整条栅线，相当于每条栅线1并联多个电阻，使得栅线的整体电阻进一步减小，可进一步减小每条栅线1的信号延迟时间，从而可使显示装置正常显示画面。
例如，如图2和图7所示，阵列基板还包括多条相互平行的数据线2，数据线2可与源极8和漏极9同层设置，此时，数据线2、源极8和漏极9可同时形成，从而可简化阵列基板的制作工艺。如图2所示，栅线1和数据线2可围成多个像素单元3，薄膜晶体管设置在像素单元3内，相应地，薄膜晶体管包括的源极8和漏极9设置在像素单元3内。
例如，如图7所示，第一导电结构6也设置在像素单元3内，第一导电结构6与像素单元3一一对应，第二导电结构15设置在任意相邻的两个像素单元3之间。如此设计，与一个像素单元3内设置有多个第一导电结构6相比， 第一导电结构6与像素单元3一一对应，可减少工艺复杂度；此外，第二导电结构15设置在任意相邻的两个像素单元3之间，可在栅线1的未被第一导电结构6覆盖的位置处并联第二导电结构15，从而使整条栅线1均并联有导电结构，进而可减小栅线1的电阻。因此，如此设计既可以减少工艺复杂度，又可以减小栅线1的电阻使显示装置正常显示画面。
例如，如图7所示，第二导电结构15在阵列基板上的投影与第一导电结构6在阵列基板上的投影可至少部分交叠，设置在钝化层14上的第四过孔16位于该交叠区域内，第二导电结构15通过第四过孔16与第一导电结构6电连接；此外，第二导电结构15在阵列基板上的投影和第一导电结构6在阵列基板上的投影也可不交叠，此时，第二导电结构15在阵列基板上的投影和第一导电结构6在阵列基板上的投影恰好接触，第四过孔16位于第二导电结构15的上述接触边缘，第四过孔16中可以填充导电材料，第二导电结构15通过第四过孔16中的导电材料与第一导电结构6的边缘接触，从而实现电连接。例如，如图7所示，第二导电结构15在阵列基板上的投影和第一导电结构6在阵列基板上的投影至少部分交叠，与第二导电结构15在阵列基板上的投和第一导电结构6在阵列基板上的投影不交叠相比，第二导电结构15与第一导电结构6的接触面积较大，因而可使第二导电结构15与第一导电结构6的连接更稳定。
例如，阵列基板还包括与栅线1同层设置的栅极，第二导电结构15在阵列基板上的投影和栅极在阵列基板上的投影可至少部分交叠。上述栅极也包含在薄膜晶体管中。由于第二导电结构15与第一导电结构6电连接，第一导电结构6与栅线1电连接，因而第二导电结构15与栅线1电连接，此外，由于栅线1与栅极连接，例如一体形成，因而第二导电结构15上所加载的信号与栅极上所加载的栅极信号相同；另外，由于第二导电结构15在阵列基板上的投影和栅极在阵列基板上的投影至少部分交叠，而在薄膜晶体管中，栅极在阵列基板上的投影与有源层10在阵列基板上的投影交叠，因而，第二导电结构15与有源层10至少部分交叠，这使得当在第二导电结构15和栅极上加载栅极信号时，第二导电结构15和栅极共同驱动有源层10，因而可增加有源层10中的载流子迁移率，提高显示装置的显示性能。
例如，阵列基板还可以包括设置在钝化层14上的像素电极17，第二导电结构15与像素电极17同层同材料设置。如此设计，可使第二导电结构15与像素电极17同时形成，因而可简化阵列基板的制作工艺。
例如，由于栅线1具有与其并联的第一导电结构6和第二导电结构15，使得栅线1的电阻较小，此时稍微增加栅线1的电阻不会影响显示画面的显示效果，因而可减小栅线1的宽度，使栅线1的宽度范围在2μm-10μm之间，由于与现有技术中栅线的宽度为20μm以上相比，可减小栅线1的宽度，因而可提高显示装置的开口率。
需要说明的是，如图2所示，当栅线1的宽度减小时，为使第一导电结构6与栅线1电连接更稳定，栅线1在第一过孔7的位置处的宽度比栅线1其他位置处的宽度宽，此时形成的第一过孔7的尺寸较大，因而可使第一导电结构6与栅线1的连接更稳定。同理可知，栅线1在第二过孔16的位置处比栅线1其他位置处的宽度宽。
实施例二
本实施例还提供了一种显示装置，包括上述技术方案所提供的阵列基板。由于该显示装置包括以上技术方案中的阵列基板，因此该显示装置与以上技术方案中的阵列基板具有相同的有益效果，在此不再赘述。
需要说明的是，本发明实施例所提供的显示装置可为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、导航仪等任何具有显示功能的产品或部件。
实施例三
本实施例还提供一种阵列基板的制作方法，如图9所示，该方法包括以下步骤S801-S803。
S801：形成金属层，经过构图工艺形成包括信号线的图形。
S802：在信号线所在膜层上形成绝缘层，经过构图工艺在绝缘层上形成对应于待形成的第一导电结构的至少两个第一过孔。
S803：以及在绝缘层上形成第一导电层，经过构图工艺形成包括第一导电结构的图形，其中，第一导电结构通过该至少两个第一过孔与信号线电连接。
下面以信号线为栅线为例对本发明实施例提供的阵列基板的制作方法进 行详细的说明。
实施例四
本实施例提供了一种阵列基板的制作方法，如图10所示，该方法包括如下的步骤S901～S903：
S901、形成栅金属层，经过构图工艺形成包括栅线的图形。例如，通过等离子增强化学气相沉积、溅射或者热蒸发等方法形成一层栅金属层，在栅金属层上涂覆光刻胶，使用具有栅线的图形的掩膜板遮盖涂覆有光刻胶的栅金属层，经过曝光、显影、刻蚀等步骤后，形成包括栅线的图形。
S902、在栅线所在膜层上形成绝缘层，经过构图工艺在绝缘层上形成对应于第一导电结构(待形成的第一导电结构)的至少两个第一过孔。例如，通过等离子增强化学气相沉积、溅射或者热蒸发等方法，在栅线所在膜层上，形成一层绝缘层，然后，通过构图工艺使绝缘层上形成对应于第一导电结构的至少两个第一过孔。
S903、在绝缘层上形成第一导电层，经过构图工艺形成包括第一导电结构的图形，其中，第一导电结构通过该至少两个第一过孔与栅线电连接。例如，通过等离子增强化学气相沉积、溅射或者热蒸发等方法形成一层第一导电层，在第一导电层上涂覆光刻胶，使用具有第一导电结构的图形的掩膜板遮盖涂覆有光刻胶的栅极层，经过曝光、显影、刻蚀等步骤后，形成包括第一导电结构的图形。
由于第一导电结构通过至少两个第一过孔与栅线电连接，使得第一导电结构与栅线并联，这相当于为栅线并联一个电阻，因而可减小整条栅线整体上的电阻值，并且，根据电阻值与信号延时时间的关系式可知，电阻值与信号延迟时间呈正比，因而减小栅线的电阻值可减小栅线的信号延迟时间，使如图1所示的技术方案中可能无法正常显示的部分像素单元变得正常显示，与如图1所示的技术方案中无法正常显示的像素单元的数量相比，本发明中无法正常显示的像素单元的数量明显减少，因而可改善显示装置不能正常显示画面的问题。值得注意的是，本实施例以信号线为栅线进行了详细的说明，然而，本发明实施例包括但不限于此，信号线还可为数据线等其他信号线。例如，当采用本实施例提供的阵列基板的显示面板的尺寸较大或显示面板的数据线比栅线长时， 信号线可为数据线。
在上述实施例中，在S903之前，阵列基板的制作方法还可以包括：在绝缘层上形成有源层膜层，经过构图工艺，形成包括有源层的图形；在有源层所在膜层上形成刻蚀阻挡层，经过构图工艺，在刻蚀阻挡层上形成对应于源极(待形成的源极)的第二过孔和对应于漏极(待形成的漏极)的第三过孔；通过一次构图工艺同时形成第一导电结构的图形和源极和漏极的图形。源极和漏极分别通过第二过孔和第三过孔与有源层电连接。
在上述实施例中，在S903之后，阵列基板的制作方法还包括：在第一导电结构所在膜层上，形成钝化层，经过构图工艺形成对应于第二导电结构(待形成的第二导电结构)的至少两个第二过孔。例如，通过等离子增强化学气相沉积、溅射或者热蒸发等方法，在第一导电结构所在膜层上，形成一层钝化层，然后，通过构图工艺使钝化层上形成对应于第二导电结构的至少两个第二过孔；在钝化层上形成第二导电层，经过构图工艺形成包括第二导电结构的图形，第二导电结构通过第二过孔与第一导电结构电连接，例如，通过等离子增强化学气相沉积、溅射或者热蒸发等方法形成一层第二导电层，在第二导电层上涂覆光刻胶，使用具有第二导电结构的图形的掩膜板遮盖涂覆有光刻胶的栅极层，经过曝光、显影、刻蚀等步骤后，形成包括第二导电结构的图形。
由于第二导电结构通过至少两个第二过孔与第一导电结构电连接，使得第二导电结构与栅线和第一导电结构组成的结构并联，这相当于为栅线和第一导电结构组成的结构并联一个电阻，因而可进一步减小整体栅线整体上的电阻值，并且参见第一导电结构的制作方法的有益效果可知，制作形成第二导电结构，可使显示装置正常显示画面。
在上述实施例中，在形成栅线的同时，阵列基板的制作方法还包括：形成栅极，第二导电结构在阵列基板上的投影与栅极在阵列基板上的投影至少部分交叠。如此设计，可使第二导电结构和栅极共同驱动有源层，因而可增加有源层中的载流子迁移率，提高显示装置的显示性能。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得 比较简单，相关之处参见产品实施例的部分说明即可。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。
本申请要求于2016年01月04日递交的中国专利申请第201610005961.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括：
    多条相互平行的信号线；
    位于所述多条信号线所在膜层上的绝缘层；以及
    位于所述绝缘层上的至少一个第一导电结构，
    其中，所述绝缘层上设置有对应于所述第一导电结构的至少两个第一过孔，所述第一导电结构通过所述至少两个第一过孔与所述信号线电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述信号线包括栅线。
  3. 根据权利要求2所述的阵列基板，其中，所述第一导电结构为条状，所述第一导电结构的延伸方向与所述栅线的延伸方向相同。
  4. 根据权利要求2所述的阵列基板，其中，所述至少两个第一过孔至少设置在所述第一导电结构的两端。
  5. 根据权利要求2-4中任一项所述的阵列基板，其中，所述第一导电结构在所述阵列基板上的投影与所述栅线在所述阵列基板上的投影至少部分交叠，所述第一过孔位于所述交叠区域内。
  6. 根据权利要求2-5中任一项所述的阵列基板，其中，所述阵列基板还包括薄膜晶体管，所述薄膜晶体管包括源极和漏极，所述源极和所述漏极均与所述第一导电结构同层设置，且均与所述第一导电结构不接触。
  7. 根据权利要求6所述的阵列基板，其中，所述薄膜晶体管还包括位于所述绝缘层和所述源极和漏极所在膜层之间的有源层和刻蚀阻挡层，所述刻蚀阻挡层上设置有对应于所述源极的第二过孔和对应于所述漏极的第三过孔，所述源极和所述漏极分别通过所述第二过孔和所述第三过孔与所述有源层电连接。
  8. 根据权利要求2-5中任一项所述的阵列基板，其中，所述阵列基板还包括位于所述第一导电结构所在膜层上的钝化层，以及位于所述钝化层上的至少一个第二导电结构，所述钝化层上设置有对应于所述第二导电结构的至少两个第四过孔，所述第二导电结构通过所述至少两个第四过孔与所述第一导电结构电连接。
  9. 根据权利要求8所述的阵列基板，其中，在每条所述栅线的延伸方向上，多个所述第一导电结构依次间隔设置，所述第二导电结构位于任意相邻的 两个第一导电结构之间，所述第二导电结构通过所述至少两个第四过孔分别和与所述第二导电结构相邻的两个所述第一导电结构电连接。
  10. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括多条相互平行的数据线，所述多条栅线和所述多条数据线围成多个像素单元，各所述第一导电结构分别设置在各所述像素单元内，且所述第一导电结构与所述像素单元一一对应，所述第二导电结构设置在任意相邻的两个所述像素单元之间。
  11. 根据权利要求8所述的阵列基板，其中，所述第二导电结构在所述阵列基板上的投影与所述栅线在所述阵列基板上的投影至少部分交叠，所述第四过孔位于所述交叠区域内。
  12. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括与所述栅线同层设置的栅极，所述第二导电结构在所述阵列基板上的投影与所述栅极在所述阵列基板上的投影至少部分交叠。
  13. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括设置在所述钝化层上的像素电极，所述第二导电结构与所述像素电极同层同材料设置。
  14. 根据权利要求8所述的阵列基板，其中，所述栅线的宽度范围为2μm-10μm。
  15. 一种显示装置，包括如权利要求1-14任一项所述的阵列基板。
  16. 一种阵列基板的制作方法，包括：
    形成金属层，经过构图工艺形成包括信号线的图形；
    在所述信号线所在膜层上形成绝缘层，经过构图工艺在所述绝缘层上形成对应于待形成的第一导电结构的至少两个第一过孔；以及
    在所述绝缘层上形成第一导电层，经过构图工艺形成包括所述第一导电结构的图形，其中，所述第一导电结构通过所述至少两个第一过孔与所述信号线电连接。
  17. 根据权利要求16所述的阵列基板的制作方法，其中，所述金属层为栅金属层，所述信号线为栅线。
  18. 根据权利要求17所述的阵列基板的制作方法，在形成所述第一导电层之前，还包括：
    在所述绝缘层上形成有源层膜层，经过构图工艺，形成包括有源层的图形；
    在所述有源层所在膜层上形成刻蚀阻挡层，经过构图工艺，在所述刻蚀阻 挡层上形成对应于待形成的源极的第二过孔和对应于待形成的漏极的第三过孔；以及
    通过一次构图工艺同时形成第一导电结构的图形和源极和漏极的图形，
    其中，所述源极和所述漏极分别通过所述第二过孔和所述第三过孔与所述有源层电连接。
  19. 根据权利要求17或18所述的阵列基板的制作方法，在形成第一导电结构之后，还包括：
    在所述第一导电结构所在膜层上，形成钝化层，经过构图工艺形成对应于待形成的第二导电结构的至少两个第四过孔；以及
    在所述钝化层上形成第二导电层，经过构图工艺形成包括第二导电结构的图形，所述第二导电结构通过所述至少两个第四过孔与所述第一导电结构电连接。
  20. 根据权利要求19所述的阵列基板的制作方法，在形成栅线的同时，还包括：
    形成栅极，所述第二导电结构在所述阵列基板上的投影与所述栅极在所述阵列基板上的投影至少部分交叠。
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