WO2017113442A1 - 液晶显示面板的像素构造及其制作方法 - Google Patents

液晶显示面板的像素构造及其制作方法 Download PDF

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Publication number
WO2017113442A1
WO2017113442A1 PCT/CN2016/070815 CN2016070815W WO2017113442A1 WO 2017113442 A1 WO2017113442 A1 WO 2017113442A1 CN 2016070815 W CN2016070815 W CN 2016070815W WO 2017113442 A1 WO2017113442 A1 WO 2017113442A1
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layer
capacitor
region
capacitor layer
line
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English (en)
French (fr)
Inventor
郝思坤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/907,826 priority Critical patent/US9791756B2/en
Publication of WO2017113442A1 publication Critical patent/WO2017113442A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to a pixel structure of a liquid crystal display panel and a method of fabricating the same, and more particularly to a pixel structure of a liquid crystal display panel having a large capacity storage capacitor and a method of fabricating the same.
  • Liquid crystal display is one of the most widely used flat panel displays, and has been widely used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens. Color screen display. With the development of liquid crystal display technology, people have put forward higher requirements on the display quality, design, low cost and high transmittance of liquid crystal displays.
  • IPS In-Plane Switching, plane control mode
  • the wide viewing angle technology of the liquid crystal display allows the observer to see only the short axis of the liquid crystal molecules at any time, so the pictures viewed at various angles are not much different, which is a perfect improvement.
  • the viewing angle of the liquid crystal display The first generation of IPS technology proposed a new liquid crystal arrangement for the drawbacks of the TN mode, achieving a better viewing angle.
  • the second-generation IPS technology (S-IPS or Super-IPS) uses a herringbone electrode to introduce a dual-domain mode to improve the gray-scale reversal of the IPS mode at certain angles.
  • Third generation IPS technology (AS-IPS or Advanced) Super-IPS) reduces the distance between liquid crystal molecules, increases the aperture ratio, and achieves higher brightness.
  • FIG. 1 discloses a schematic diagram of a pixel structure of a conventional IPS liquid crystal display panel.
  • a conventional IPS liquid crystal display panel defines a range of a pixel structure 100 by a plurality of scanning lines and data lines crossing the panel, the long direction of the pixel is set to a vertical direction, and the pixels adopt a chevron electrode, and the pixels
  • the structure 100 mainly includes a scan line 110, a data line 120, a thin film transistor 130, a common line 140, a pixel electrode 150, and a common electrode 160.
  • the pixel structure 100 further includes a storage capacitor 170.
  • the storage capacitor 170 is disposed on the common line 140, but a data line 120 used by the existing IPS liquid crystal display panel corresponds to one scan line 110. Therefore, the number of data driving chips cannot be reduced, and since the capacity of the storage capacitor 170 is too small, a punch-through effect is generated due to parasitic capacitance on the liquid crystal display panel (Feed Through), causing the panel to display a bad phenomenon.
  • the main object of the present invention is to provide a pixel structure of a liquid crystal display panel and a manufacturing method thereof, which adopt a tri-gate structure, and a thin film transistor and a storage capacitor can be simultaneously formed in the manufacturing process.
  • the present invention provides a pixel structure of a liquid crystal display panel formed on a substrate, which comprises:
  • a first metal layer is formed on the substrate and includes a scan line and a gate of a thin film transistor
  • a first insulating layer formed on the first metal layer and the active layer
  • a second metal layer is formed on the insulating layer, and includes a data line, a common line, a source of the thin film transistor, and a drain, wherein the data line is connected to the source, the film a transistor adjacent to the scan line and the data line, the common line being parallel to the data line;
  • a transparent conductive layer formed on the second metal layer comprising a pixel electrode and a common electrode
  • the pixel structure further includes a storage capacitor, which includes:
  • a second capacitor layer is formed over the first capacitor layer and includes a first region and a second region, a first region of the second capacitor layer is connected to the drain, and the second capacitor layer a second area connecting the common line to form a raised portion of the common line;
  • first via is at a junction of the first capacitor layer and the first region of the second capacitor layer, and a portion of the first via is connected a first capacitor layer, another portion of which penetrates and connects the first region of the second capacitor layer, such that the first capacitor layer is connected to the second capacitor layer; and the second via hole runs through a second region of the second capacitor layer connecting the first capacitor layer and the second capacitor layer;
  • a third capacitor layer includes a first region and a second region, a portion of the first region of the third capacitor layer is above the first via and connected to the first via, Another portion is located above the common line and connected to the pixel electrode; a second region of the third capacitor layer is above the second via and connected to the second via, and The common electrode is connected.
  • the storage capacitor is located between the data line and the common line.
  • the first region of the second capacitor layer is adjacent to the drain.
  • the pixel electrode is formed by a first region of the third capacitor layer along a positive direction of the scan line to form a plurality of comb branches; a portion of the common electrode overlaps Above the scan line, another portion is formed on the other side with respect to the storage capacitor, and a plurality of comb branches are formed along a reverse direction of the scan line, and a plurality of comb branches of the pixel electrode A plurality of comb-shaped branches of the common electrode are formed to interpenetrate each other.
  • the present invention further provides a pixel structure of a liquid crystal display panel formed on a substrate, which comprises:
  • a first metal layer is formed on the substrate and includes a scan line and a gate of a thin film transistor
  • a first insulating layer formed on the first metal layer and the active layer
  • a second metal layer is formed on the insulating layer, comprising a data line, a common line, a source of the thin film transistor and a drain, wherein the data line is connected to the source;
  • a transparent conductive layer formed on the second metal layer comprising a pixel electrode and a common electrode
  • the pixel structure further includes a storage capacitor, which includes:
  • a second capacitor layer is formed over the first capacitor layer and includes a first region and a second region, a first region of the second capacitor layer is connected to the drain, and the second capacitor layer a second area connecting the common line to form a raised portion of the common line;
  • first via is at a junction of the first capacitor layer and the first region of the second capacitor layer, and a portion of the first via is connected a first capacitor layer, another portion of which penetrates and connects the first region of the second capacitor layer, such that the first capacitor layer is connected to the second capacitor layer; and the second via hole runs through a second region of the second capacitor layer connecting the first capacitor layer and the second capacitor layer;
  • a third capacitor layer includes a first region and a second region, a portion of the first region of the third capacitor layer is above the first via and connected to the first via, Another portion is located above the common line and connected to the pixel electrode; a second region of the third capacitor layer is above the second via and connected to the second via, and The common electrode is connected.
  • the thin film transistor is adjacent to the scan line and the data line.
  • the common line is parallel to the data line.
  • the storage capacitor is located between the data line and the common line.
  • the first region of the second capacitor layer is adjacent to the drain.
  • the pixel electrode is formed by a first region of the third capacitor layer along a positive direction of the scan line to form a plurality of comb branches; a portion of the common electrode overlaps Above the scan line, another portion is formed on the other side with respect to the storage capacitor, and a plurality of comb branches are formed along a reverse direction of the scan line, and a plurality of comb branches of the pixel electrode A plurality of comb-shaped branches of the common electrode are formed to interpenetrate each other.
  • the present invention further provides a method for fabricating a pixel structure of a liquid crystal display panel, which comprises the following steps:
  • Forming a first metal layer on a substrate comprising forming a scan line, a gate of a thin film transistor, and a first capacitor layer of a storage capacitor;
  • Forming a second metal layer on the insulating layer the step of forming a data line, a common line, a source and a drain of the thin film transistor, and a second capacitor layer of the storage capacitor;
  • the data line is connected to the source;
  • the second capacitor layer is formed above the first capacitor layer and includes a first region and a second region, and the first region of the second capacitor layer is connected The drain, the second region of the second capacitor layer is connected to the common line to form a convex portion of the common line;
  • first via and a second via of the storage capacitor Forming a first via and a second via of the storage capacitor, where the first via is at a junction of the first capacitor layer and the first region of the second capacitor layer, the first a portion of the via is connected to the first capacitor layer, and another portion of the via is connected to and connected to the first region of the second capacitor layer, and the first capacitor layer is connected to the second capacitor layer;
  • the second via hole extends through the second region of the second capacitor layer to connect the first capacitor layer and the second capacitor layer;
  • the third capacitor layer includes a first region and a second region, a portion of the first region of the third capacitor layer is above the first via and connected to the first via, and another portion is above the common line And connecting the pixel electrode; the second region of the third capacitor layer is located above the second via hole and connected to the second via hole, and is connected to the common electrode.
  • the thin film transistor is adjacent to the scan line and the data line; the common line is parallel to the data line; and the storage capacitor is located in the data line and the common line between.
  • the first region of the second capacitor layer is adjacent to the drain.
  • the pixel electrode is formed by a first region of the third capacitor layer along a positive direction of the scan line to form a plurality of comb branches; a portion of the common electrode overlaps Above the scan line, another portion is formed on the other side with respect to the storage capacitor, and a plurality of comb branches are formed along a reverse direction of the scan line, and a plurality of comb branches of the pixel electrode A plurality of comb-shaped branches of the common electrode are formed to interpenetrate each other.
  • the invention provides a pixel structure of a liquid crystal display panel and a manufacturing method thereof, which adopts a tri-gate structure, and a thin film transistor and a storage capacitor can be simultaneously formed in the manufacturing process.
  • the portion of the storage capacitor whose main storage capacitor further includes a region below the common line, so that the capacity of the storage capacitor can be greatly increased, and the punch-through effect due to parasitic capacitance on the liquid crystal display panel can be reduced (Feed Through), the panel display quality is improved, and since the parasitic capacitance between the data line and the pixel electrode is reduced, the cross talk phenomenon of the panel can also be improved at the same time.
  • FIG. 1 is a schematic diagram of a pixel configuration of a conventional IPS liquid crystal display panel.
  • FIGS. 2A-2E are schematic diagrams showing a method of fabricating a pixel structure of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 3 is a schematic view showing a pixel structure of a liquid crystal display panel in accordance with a preferred embodiment of the present invention.
  • FIG. 2A-2E are schematic diagrams showing a method of fabricating a pixel structure of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • the liquid crystal display panel of the present invention adopts a tri-gate structure, that is, one data line can correspond to three scanning lines, so the long direction of the pixel is set to the horizontal direction, and the pixel adopts a chevron-shaped electrode to introduce a dual domain.
  • the pattern is described first.
  • the method for fabricating the pixel structure of the present invention comprises the following steps:
  • a first metal layer 210 is formed on a substrate, the step of forming a scan line 220, a gate 231 of a thin film transistor and a first capacitor layer 241 of a storage capacitor;
  • an active layer 232 of the thin film transistor is formed on the gate 231;
  • a second metal layer 250 is formed on the insulating layer.
  • the step includes forming a data line 260, a common line 270, a source 233 and a drain 234 of the thin film transistor, and the a second capacitor layer 242 of the storage capacitor; wherein the data line 260 is connected to the source 233; the second capacitor layer 242 is formed above the first capacitor layer 241 and includes a first region 242a and a a second region 242b, the first region 242a of the second capacitor layer is connected to the drain 234, and the second region 242b of the second capacitor layer is connected to the common line 270 to form a convex portion of the common line 270 Starting part
  • a first via 243 and a second via 244 of the storage capacitor are formed.
  • the first via 243 is at the first of the first capacitor layer 241 and the second capacitor layer. a portion of the first via 243 is connected to the first capacitor layer 241, and another portion of the first via 243 is connected to and connected to the first region 242a of the second capacitor layer, so that the first capacitor is
  • the layer 241 is connected to the second capacitor layer 242; and the second via 244 extends through the second region 242b of the second capacitor layer, such that the first capacitor layer 241 and the second capacitor are here.
  • Layer 242 is connected; and
  • a transparent conductive layer 280 is formed on the second metal layer 250.
  • the step includes forming a pixel electrode 280a, a common electrode 280b, and a third capacitor layer 245 of the storage capacitor.
  • the third capacitor layer 245 includes a first region 245a and a second region 245b. A portion of the first region 245a of the third capacitor layer is above the first via 243 and is connected to the first via. 243, another portion thereof is located above the common line 270, and is connected to the pixel electrode 280a; the second region 245b of the third capacitor layer is located above the second via 244 and is connected The second via 244 is described and connected to the common electrode 280b.
  • FIG. 3 is a schematic diagram of a pixel structure of a liquid crystal display panel according to a preferred embodiment of the present invention, wherein the lower surface covered by the transparent conductive layer 280 is clearly shown. Configuration, in contrast to FIG. 2E, FIG. 3 particularly expresses the transparent conductive layer 280 in a transparent manner, as previously described.
  • a pixel structure 200 of the liquid crystal display panel of the present invention can be formed by the above steps (a)-(g), in which a thin film transistor and a storage capacitor can be simultaneously formed.
  • the pixel structure 200 of the present invention is formed on a substrate, and the specific configuration thereof is as follows:
  • a first metal layer 210 formed on the substrate, comprising a scan line 220, and a gate 231 of a thin film transistor 230;
  • An active layer 232 is formed on the gate 231;
  • a first insulating layer (not shown) is formed on the first metal layer 210 and the active layer 232;
  • a second metal layer 250 is formed on the insulating layer, and includes a data line 260, a common line 270, a source 233 of the thin film transistor, and a drain 234, wherein the data line 260 is connected to the Source 233;
  • a second insulating layer (not shown) is formed on the second metal layer 250;
  • a transparent conductive layer 280 is formed on the second metal layer 250, and includes a pixel electrode 280a and a common electrode 280b;
  • a storage capacitor 240 comprising:
  • a first capacitor layer 241 is formed on one side of the pixel structure 200;
  • a second capacitor layer 242 is formed above the first capacitor layer 241 and includes a first region 242a and a second region 242b.
  • the first region 242a of the second capacitor layer is connected to the drain 234.
  • the second region 242b of the second capacitor layer is connected to the common line 270 to form a convex portion of the common line 270;
  • the first via 243 is located at a junction of the first capacitor layer 241 and the first region 242a of the second capacitor layer, the first pass A portion of the hole 243 is connected to the first capacitor layer 241, and another portion of the hole 243 is connected to and connected to the first region 242a of the second capacitor layer, so that the first capacitor layer 241 and the second capacitor layer 242 are here.
  • Connecting; and the second via 244 extends through the second region 242b of the second capacitor layer to connect the first capacitor layer 241 and the second capacitor layer 242 herein;
  • the thin film transistor 230 is adjacent to the scan line 210 and the data line 260.
  • the common line 270 is parallel to the data line 260.
  • the storage capacitor 240 is located between the data line 260 and the common line 270.
  • the first region 242a of the second capacitor layer is adjacent to the drain 234.
  • the pixel electrode 280a is formed by a first region 245a of the third capacitor layer along a positive direction of the scan line to form a plurality of comb branches; a portion of the common electrode 280b overlaps the scan line Above the 210, another portion thereof is formed on the other side of the storage capacitor, and a plurality of comb branches are formed along a reverse direction of the scan line, and the plurality of comb branches of the pixel electrode 280a are The plurality of comb-like branches of the common electrode 280b are formed to interpenetrate each other.
  • a pixel structure 200 of the liquid crystal display panel of the present invention can be formed by the above steps (a)-(g), and the thin film transistor 230 can be simultaneously formed in the fabrication process.
  • the storage capacitor 240 wherein a portion of the storage capacitor 240 that is mainly stored is a second region 245b of the third capacitor layer (a raised portion of the common line 270) and the common line
  • the area under the 270 can greatly increase the capacity of the storage capacitor 240, and can reduce the punch-through effect due to the parasitic capacitance on the liquid crystal display panel (Feed).
  • the panel display quality is improved, and since the parasitic capacitance between the data line 260 and the pixel electrode 280a is reduced, the crosstalk of the panel can also be improved at the same time (Cross) Talk) phenomenon.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种液晶显示面板的像素构造及其制作方法，其采用三栅极架构，在制作过程中同时形成一薄膜晶体管(230)及一储存电容(240)。所述储存电容(240)包含一第一过孔(243)及一第二过孔(244)，使所述储存电容(240)的一第一电容层(241)与一第二电容层(242)连接。所述储存电容(240)的主要储存电容的部分还包含一公共线(270)的下方的区域，因此可大幅度增加所述储存电容(240)的容量，减小因液晶显示面板上的寄生电容而产生穿通效应，改善面板显示质量。

Description

液晶显示面板的像素构造及其制作方法 技术领域
本发明涉及一种液晶显示面板的像素构造及其制作方法，特别是涉及一种具有大容量的储存电容的液晶显示面板的像素构造及其制作方法。
 背景技术
液晶显示器(LCD)是目前使用最广泛的一种平板显示器，已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用具有高分辨率彩色屏幕的显示器。随着液晶显示器技术的发展进步，人们对液晶显示器的显示品质、外观设计、低成本和高穿透率等提出了更高的要求。
IPS（In-Plane Switching，平面控制模式）广视角技术的液晶显示让观察者任何时候都只能看到液晶分子的短轴，因此在各个角度上观看的画面都不会有太大差别，这样就比较完美地改善了液晶显示器的视角。第一代IPS技术针对TN模式的弊病提出了全新的液晶排列方式，实现较好的可视角度。第二代IPS技术（S-IPS即Super-IPS）采用人字形电极，引入双畴模式，改善IPS模式在某些特定角度的灰阶逆转现象。第三代IPS技术（AS-IPS即Advanced Super-IPS）减小液晶分子间距离，提高开口率，获得更高亮度。
请参照图1所示，图1揭示一种现有的IPS液晶显示面板的像素构造的示意图。一种现有的IPS液晶显示面板由面板上的多条扫描线及数据线横直交叉定义出一像素构造100的范围，像素的长方向设为纵方向，并且像素采用人字形电极，所述像素构造100主要包含一扫描线110、一数据线120、一薄膜晶体管130、一公共线140、一像素电极150及一公共电极160。另外，所述像素构造100还包含一储存电容170，所述储存电容170设于所述公共线140上，但由于现有的IPS液晶显示面板采用的一条数据线120对应一条扫描线110的方式，因此数据驱动芯片的数量无法减少，并且由于所述储存电容170的容量过小，因液晶显示面板上的寄生电容而产生穿通效应(Feed through)，造成面板显示不良的现象。
因此，有必要提供一种液晶显示面板的像素构造及其制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的主要目的是提供一种液晶显示面板的像素构造及其制作方法，其采用三栅极(Tri-gate)架构，在制作过程中可以同时形成一薄膜晶体管及一储存电容。所述储存电容的主要储存电容的部分还包含一公共线的下方的区域，因此可大幅度增加所述储存电容的容量，可以减小因液晶显示面板上的寄生电容而产生穿通效应(Feed through)，改善面板显示质量，并且因为数据线与像素电极之间的寄生电容减小了，也能同时改善面板的串扰(Cross talk)现象。
 技术解决方案
为达上述目的，本发明提供一种液晶显示面板的像素构造，形成在一基板上，其包含：
一第一金属层，形成于所述基板上，包含一扫描线及一薄膜晶体管的一栅极；
一有源层，形成于所述栅极上；
一第一绝缘层，形成于所述第一金属层及所述有源层上；
一第二金属层，形成于所述绝缘层上，包含一数据线、一公共线、所述薄膜晶体管的一源极及一漏极，其中所述数据线连接所述源极，所述薄膜晶体管邻近所述扫描线及所述数据线，所述公共线与所述数据线平行；
一第二绝缘层，形成于所述第二金属层上；及
一透明导电层，形成于所述第二金属层上，包含一像素电极及一公共电极；
所述像素构造另包含一储存电容，其包含：
一第一电容层，形成于所述像素构造的一侧边；
一第二电容层，形成在所述第一电容层的上方并包含一第一区域及一第二区域，所述第二电容层的第一区域连接所述漏极，所述第二电容层的第二区域连接所述公共线，形成所述公共线的一凸起部；
一第一过孔及一第二过孔，所述第一过孔位在所述第一电容层与所述第二电容层的第一区域交接处，所述第一过孔的一部分连接所述第一电容层，其另一部分贯穿及连接所述第二电容层的第一区域，使此处的所述第一电容层与所述第二电容层连接；以及所述第二过孔贯穿所述第二电容层的第二区域，使此处的所述第一电容层与所述第二电容层连接；及
一第三电容层，包含一第一区域及一第二区域，所述第三电容层的第一区域的一部份位所述第一过孔的上方并连接所述第一过孔，其另一部份位在所述公共线的上方，并连接所述像素电极；所述第三电容层的第二区域位在所述第二过孔的上方并连接所述第二过孔，并连接所述公共电极。
在本发明的一实施例中，所述储存电容位于所述数据线及所述公共线之间。
在本发明的一实施例中，所述第二电容层的第一区域邻近所述漏极。
在本发明的一实施例中，所述像素电极由所述第三电容层的第一区域沿所述扫描线的一正方向形成多个梳状分支；所述公共电极的一部分重迭于所述扫描线的上方，其另一部分形成在相对于所述储存电容的另一侧边，并沿所述扫描线的一反方向形成多个梳状分支，所述像素电极的多个梳状分支与所述公共电极的多个梳状分支形成相互穿插对应。
为达上述目的，本发明还提供一种液晶显示面板的像素构造，形成在一基板上，其包含：
一第一金属层，形成于所述基板上，包含一扫描线及一薄膜晶体管的一栅极；
一有源层，形成于所述栅极上；
一第一绝缘层，形成于所述第一金属层及所述有源层上；
一第二金属层，形成于所述绝缘层上，包含一数据线、一公共线、所述薄膜晶体管的一源极及一漏极，其中所述数据线连接所述源极；
一第二绝缘层，形成于所述第二金属层上；及
一透明导电层，形成于所述第二金属层上，包含一像素电极及一公共电极；
所述像素构造另包含一储存电容，其包含：
一第一电容层，形成于所述像素构造的一侧边；
一第二电容层，形成在所述第一电容层的上方并包含一第一区域及一第二区域，所述第二电容层的第一区域连接所述漏极，所述第二电容层的第二区域连接所述公共线，形成所述公共线的一凸起部；
一第一过孔及一第二过孔，所述第一过孔位在所述第一电容层与所述第二电容层的第一区域交接处，所述第一过孔的一部分连接所述第一电容层，其另一部分贯穿及连接所述第二电容层的第一区域，使此处的所述第一电容层与所述第二电容层连接；以及所述第二过孔贯穿所述第二电容层的第二区域，使此处的所述第一电容层与所述第二电容层连接；及
一第三电容层，包含一第一区域及一第二区域，所述第三电容层的第一区域的一部份位所述第一过孔的上方并连接所述第一过孔，其另一部份位在所述公共线的上方，并连接所述像素电极；所述第三电容层的第二区域位在所述第二过孔的上方并连接所述第二过孔，并连接所述公共电极。
在本发明的一实施例中，所述薄膜晶体管邻近所述扫描线及所述数据线。
在本发明的一实施例中，所述公共线与所述数据线平行。
在本发明的一实施例中，所述储存电容位于所述数据线及所述公共线之间。
在本发明的一实施例中，所述第二电容层的第一区域邻近所述漏极。
在本发明的一实施例中，所述像素电极由所述第三电容层的第一区域沿所述扫描线的一正方向形成多个梳状分支；所述公共电极的一部分重迭于所述扫描线的上方，其另一部分形成在相对于所述储存电容的另一侧边，并沿所述扫描线的一反方向形成多个梳状分支，所述像素电极的多个梳状分支与所述公共电极的多个梳状分支形成相互穿插对应。
为达上述目的，本发明另提供一种液晶显示面板的像素构造的制作方法，其包含以下步骤：
形成一第一金属层于一基板上，此步骤包含形成一扫描线、一薄膜晶体管的一栅极及一储存电容的一第一电容层；
形成所述薄膜晶体管的一有源层于所述栅极上；
形成一第一绝缘层于所述第一金属层及所述有源层上；
形成一第二金属层于所述绝缘层上，此步骤包含形成一数据线、一公共线、所述薄膜晶体管的一源极及一漏极、及所述储存电容的一第二电容层；其中所述数据线连接所述源极；所述第二电容层形成在所述第一电容层的上方并包含一第一区域及一第二区域，所述第二电容层的第一区域连接所述漏极，所述第二电容层的第二区域连接所述公共线，形成所述公共线的一凸起部；
形成所述储存电容的一第一过孔及一第二过孔，所述第一过孔位在所述第一电容层与所述第二电容层的第一区域交接处，所述第一过孔的一部分连接所述第一电容层，其另一部分贯穿及连接所述第二电容层的第一区域，使此处的所述第一电容层与所述第二电容层连接；以及所述第二过孔贯穿所述第二电容层的第二区域，使此处的所述第一电容层与所述第二电容层连接；及
形成一第二绝缘层于所述第二金属层上；及
形成一透明导电层于所述第二金属层上，此步骤包含形成一像素电极、一公共电极及一所述储存电容的一第三电容层；所述第三电容层包含一第一区域及一第二区域，所述第三电容层的第一区域的一部份位所述第一过孔的上方并连接所述第一过孔，其另一部份位在所述公共线的上方，并连接所述像素电极；所述第三电容层的第二区域位在所述第二过孔的上方并连接所述第二过孔，并连接所述公共电极。
在本发明的一实施例中，所述薄膜晶体管邻近所述扫描线及所述数据线；所述公共线与所述数据线平行；所述储存电容位于所述数据线及所述公共线之间。
在本发明的一实施例中，所述第二电容层的第一区域邻近所述漏极。
在本发明的一实施例中，所述像素电极由所述第三电容层的第一区域沿所述扫描线的一正方向形成多个梳状分支；所述公共电极的一部分重迭于所述扫描线的上方，其另一部分形成在相对于所述储存电容的另一侧边，并沿所述扫描线的一反方向形成多个梳状分支，所述像素电极的多个梳状分支与所述公共电极的多个梳状分支形成相互穿插对应。
 有益效果
本发明提供一种液晶显示面板的像素构造及其制作方法，其采用三栅极(Tri-gate)架构，在制作过程中可以同时形成一薄膜晶体管及一储存电容。所述储存电容的主要储存电容的部分还包含一公共线的下方的区域，因此可大幅度增加所述储存电容的容量，可以减小因液晶显示面板上的寄生电容而产生穿通效应(Feed through)，改善面板显示质量，并且因为数据线与像素电极之间的寄生电容减小了，也能同时改善面板的串扰(Cross talk)现象。
附图说明
图1：一种现有的IPS液晶显示面板的像素构造的示意图。
图2A-2E：本发明较佳实施例的一种液晶显示面板的像素构造的制作方法示意图。
图3：本发明较佳实施例的一种液晶显示面板的像素构造的示意图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明。为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参照附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图2A-2E所示，图2A-2E是本发明较佳实施例的一种液晶显示面板的像素构造的制作方法示意图。本发明的液晶显示面板采用三栅极(Tri-gate)架构，也就是一条数据线可以对应三条扫描线的方式，因此像素的长方向设为横方向，并且像素采用人字形电极，引入双畴模式，合先叙明。本发明的像素构造的制作方法包含以下步骤：
(a) 参照图2A，形成一第一金属层210于一基板上，此步骤包含形成一扫描线220、一薄膜晶体管的一栅极231及一储存电容的一第一电容层241；
(b) 参照图2B，形成所述薄膜晶体管的一有源层232于所述栅极231上；
(c) 形成一第一绝缘层(未绘示)于所述第一金属层210及所述有源层232上；
(d) 参照图2C，形成一第二金属层250于所述绝缘层上，此步骤包含形成一数据线260、一公共线270、所述薄膜晶体管的一源极233及一漏极234、及所述储存电容的一第二电容层242；其中所述数据线260连接所述源极233；所述第二电容层242形成在所述第一电容层241的上方并包含一第一区域242a及一第二区域242b，所述第二电容层的第一区域242a连接所述漏极234，所述第二电容层的第二区域242b连接所述公共线270，形成所述公共线270的一凸起部；
(e) 参照图2D，形成所述储存电容的一第一过孔243及一第二过孔244，所述第一过孔位243在所述第一电容层241与所述第二电容层的第一区域242a交接处，所述第一过孔243的一部分连接所述第一电容层241，其另一部分贯穿及连接所述第二电容层的第一区域242a，使此处的所述第一电容层241与所述第二电容层242连接；以及所述第二过孔244贯穿所述第二电容层的第二区域242b，使此处的所述第一电容层241与所述第二电容层242连接；及
(f) 形成一第二绝缘层(未绘示)于所述第二金属层上250；及
(g) 参照图2E，形成一透明导电层280于所述第二金属层250上，此步骤包含形成一像素电极280a、一公共电极280b及一所述储存电容的一第三电容层245；所述第三电容层245包含一第一区域245a及一第二区域245b，所述第三电容层的第一区域245a的一部份位所述第一过孔243的上方并连接所述第一过孔243，其另一部份位在所述公共线270的上方，并连接所述像素电极280a；所述第三电容层的第二区域245b位在所述第二过孔244的上方并连接所述第二过孔244，并连接所述公共电极280b。
请同时参照图2A-2E及图3所示，图3是本发明较佳实施例的一种液晶显示面板的像素构造的示意图，其中为了清楚呈现被所述透明导电层280所遮盖的下方的构造，相较于图2E，图3特别以透明的方式来表现所述透明导电层280，合先叙明。在本发明中，通过上述步骤(a)-(g)可以形成本发明的液晶显示面板的一像素构造200，所述制作过程中可以同时形成一薄膜晶体管及一储存电容。本发明的所述像素构造200形成在一基板上，其具体构造详述如下：包含：
一第一金属层210，形成于所述基板上，包含一扫描线220、及一薄膜晶体管230的一栅极231；
一有源层232，形成于所述栅极231上；
一第一绝缘层(未绘示)，形成于所述第一金属层210及所述有源层232上；
一第二金属层250，形成于所述绝缘层上，包含一数据线260、一公共线270、所述薄膜晶体管的一源极233及一漏极234，其中所述数据线260连接所述源极233；
一第二绝缘层(未绘示)，形成于所述第二金属层250上；
一透明导电层280，形成于所述第二金属层250上，包含一像素电极280a及一公共电极280b；及
一储存电容240，其包含：
一第一电容层241，形成于所述像素构造200的一侧边；
一第二电容层242，形成在所述第一电容层241的上方并包含一第一区域242a及一第二区域242b，所述第二电容层的第一区域242a连接所述漏极234，所述第二电容层的第二区域242b连接所述公共线270，形成所述公共线270的一凸起部；
一第一过孔243及一第二过孔244，所述第一过孔243位在所述第一电容层241与所述第二电容层的第一区域242a交接处，所述第一过孔243的一部分连接所述第一电容层241，其另一部分贯穿及连接所述第二电容层的第一区域242a，使此处的所述第一电容层241与所述第二电容层242连接；以及所述第二过孔244贯穿所述第二电容层的第二区域242b，使此处的所述第一电容层241与所述第二电容层242连接；及
一第三电容层245，包含一第一区域245a及一第二区域245b，所述第三电容层的第一区域245a的一部份位所述第一过孔243的上方并连接所述第一过孔243，其另一部份位在所述公共线270的上方，并连接所述像素电极280a；所述第三电容层的第二区域245b位在所述第二过孔244的上方并连接所述第二过孔244，并连接所述公共电极280b。
优选的，所述薄膜晶体管230邻近所述扫描线210及所述数据线260。
优选的，所述公共线270与所述数据线260平行。
优选的，所述储存电容240位于所述数据线260及所述公共线270之间。
优选的，所述第二电容层的第一区域242a邻近所述漏极234。
优选的，所述像素电极280a由所述第三电容层的第一区域245a沿所述扫描线的一正方向形成多个梳状分支；所述公共电极280b的一部分重迭于所述扫描线210的上方，其另一部分形成在相对于所述储存电容的另一侧边，并沿所述扫描线的一反方向形成多个梳状分支，所述像素电极280a的多个梳状分支与所述公共电极280b的多个梳状分支形成相互穿插对应。
综上所述，在本发明中，通过上述步骤(a)-(g)可以形成本发明的液晶显示面板的一像素构造200，并且在所述制作过程中可以同时形成所述薄膜晶体管230及所述储存电容240，其中，所述储存电容240的主要储存电容的部分是位在所述第三电容层的第二区域245b(所述公共线270的一凸起部)与所述公共线270的下方的区域(图3中框线A所示区域)，因此可大幅度增加所述储存电容240的容量，可以减小因液晶显示面板上的寄生电容而产生穿通效应(Feed through)，改善面板显示质量，并且因为所述数据线260与所述像素电极280a之间的寄生电容减小了，也能同时改善面板的串扰(Cross talk)现象。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (16)

  1. 一种液晶显示面板的像素构造，形成在一基板上，其包含：
    一第一金属层，形成于所述基板上，包含一扫描线及一薄膜晶体管的一栅极；
    一有源层，形成于所述栅极上；
    一第一绝缘层，形成于所述第一金属层及所述有源层上；
    一第二金属层，形成于所述绝缘层上，包含一数据线、一公共线、所述薄膜晶体管的一源极及一漏极，其中所述数据线连接所述源极，所述薄膜晶体管邻近所述扫描线及所述数据线，所述公共线与所述数据线平行；
    一第二绝缘层，形成于所述第二金属层上；及
    一透明导电层，形成于所述第二金属层上，包含一像素电极及一公共电极；
    其中，所述像素构造另包含一储存电容，其包含：
    一第一电容层，形成于所述像素构造的一侧边；
    一第二电容层，形成在所述第一电容层的上方并包含一第一区域及一第二区域，所述第二电容层的第一区域连接所述漏极，所述第二电容层的第二区域连接所述公共线，形成所述公共线的一凸起部；
    一第一过孔及一第二过孔，所述第一过孔位在所述第一电容层与所述第二电容层的第一区域交接处，所述第一过孔的一部分连接所述第一电容层，其另一部分贯穿及连接所述第二电容层的第一区域，使此处的所述第一电容层与所述第二电容层连接；以及所述第二过孔贯穿所述第二电容层的第二区域，使此处的所述第一电容层与所述第二电容层连接；及
    一第三电容层，包含一第一区域及一第二区域，所述第三电容层的第一区域的一部份位所述第一过孔的上方并连接所述第一过孔，其另一部份位在所述公共线的上方，并连接所述像素电极；所述第三电容层的第二区域位在所述第二过孔的上方并连接所述第二过孔，并连接所述公共电极。
  2. 如权利要求1所述的像素构造，其中所述储存电容位于所述数据线及所述公共线之间。
  3. 如权利要求1所述的像素构造，其中所述第二电容层的第一区域邻近所述漏极。
  4. 如权利要求1所述的像素构造，其中所述像素电极由所述第三电容层的第一区域沿所述扫描线的一正方向形成多个梳状分支；所述公共电极的一部分重迭于所述扫描线的上方，其另一部分形成在相对于所述储存电容的另一侧边，并沿所述扫描线的一反方向形成多个梳状分支，所述像素电极的多个梳状分支与所述公共电极的多个梳状分支形成相互穿插对应。
  5. 一种液晶显示面板的像素构造，形成在一基板上，其包含：
    一第一金属层，形成于所述基板上，包含一扫描线及一薄膜晶体管的一栅极；
    一有源层，形成于所述栅极上；
    一第一绝缘层，形成于所述第一金属层及所述有源层上；
    一第二金属层，形成于所述绝缘层上，包含一数据线、一公共线、所述薄膜晶体管的一源极及一漏极，其中所述数据线连接所述源极；
    一第二绝缘层，形成于所述第二金属层上；及
    一透明导电层，形成于所述第二金属层上，包含一像素电极及一公共电极；
    其中，所述像素构造另包含一储存电容，其包含：
    一第一电容层，形成于所述像素构造的一侧边；
    一第二电容层，形成在所述第一电容层的上方并包含一第一区域及一第二区域，所述第二电容层的第一区域连接所述漏极，所述第二电容层的第二区域连接所述公共线，形成所述公共线的一凸起部；
    一第一过孔及一第二过孔，所述第一过孔位在所述第一电容层与所述第二电容层的第一区域交接处，所述第一过孔的一部分连接所述第一电容层，其另一部分贯穿及连接所述第二电容层的第一区域，使此处的所述第一电容层与所述第二电容层连接；以及所述第二过孔贯穿所述第二电容层的第二区域，使此处的所述第一电容层与所述第二电容层连接；及
    一第三电容层，包含一第一区域及一第二区域，所述第三电容层的第一区域的一部份位所述第一过孔的上方并连接所述第一过孔，其另一部份位在所述公共线的上方，并连接所述像素电极；所述第三电容层的第二区域位在所述第二过孔的上方并连接所述第二过孔，并连接所述公共电极。
  6. 如权利要求5所述的像素构造，其中所述薄膜晶体管邻近所述扫描线及所述数据线。
  7. 如权利要求5所述的像素构造，其中所述公共线与所述数据线平行。
  8. 如权利要求5所述的像素构造，其中所述储存电容位于所述数据线及所述公共线之间。
  9. 如权利要求5所述的像素构造，其中所述第二电容层的第一区域邻近所述漏极。
  10. 如权利要求5所述的像素构造，其中所述像素电极由所述第三电容层的第一区域沿所述扫描线的一正方向形成多个梳状分支；所述公共电极的一部分重迭于所述扫描线的上方，其另一部分形成在相对于所述储存电容的另一侧边，并沿所述扫描线的一反方向形成多个梳状分支，所述像素电极的多个梳状分支与所述公共电极的多个梳状分支形成相互穿插对应。
  11. 一种液晶显示面板的像素构造的制作方法，其中其包含以下步骤：
    (a) 形成一第一金属层于一基板上，此步骤包含形成一扫描线、一薄膜晶体管的一栅极及一储存电容的一第一电容层；
    (b) 形成所述薄膜晶体管的一有源层于所述栅极上；
    (c) 形成一第一绝缘层于所述第一金属层及所述有源层上；
    (d) 形成一第二金属层于所述绝缘层上，此步骤包含形成一数据线、一公共线、所述薄膜晶体管的一源极及一漏极、及所述储存电容的一第二电容层；其中所述数据线连接所述源极；所述第二电容层形成在所述第一电容层的上方并包含一第一区域及一第二区域，所述第二电容层的第一区域连接所述漏极，所述第二电容层的第二区域连接所述公共线，形成所述公共线的一凸起部；
    (e) 形成所述储存电容的一第一过孔及一第二过孔，所述第一过孔位在所述第一电容层与所述第二电容层的第一区域交接处，所述第一过孔的一部分连接所述第一电容层，其另一部分贯穿及连接所述第二电容层的第一区域，使此处的所述第一电容层与所述第二电容层连接；以及所述第二过孔贯穿所述第二电容层的第二区域，使此处的所述第一电容层与所述第二电容层连接；
    (f) 形成一第二绝缘层于所述第二金属层上；及
    (g) 形成一透明导电层于所述第二金属层上，此步骤包含形成一像素电极、一公共电极及一所述储存电容的一第三电容层；所述第三电容层包含一第一区域及一第二区域，所述第三电容层的第一区域的一部份位所述第一过孔的上方并连接所述第一过孔，其另一部份位在所述公共线的上方，并连接所述像素电极；所述第三电容层的第二区域位在所述第二过孔的上方并连接所述第二过孔，并连接所述公共电极。
  12. 如权利要求11所述的制作方法，其中所述薄膜晶体管邻近所述扫描线及所述数据线。
  13. 如权利要求11所述的制作方法，其中所述公共线与所述数据线平行。
  14. 如权利要求11所述的制作方法，其中所述储存电容位于所述数据线及所述公共线之间。
  15. 如权利要求11所述的制作方法，其中所述第二电容层的第一区域邻近所述漏极。
  16. 如权利要求11所述的制作方法，其中所述像素电极由所述第三电容层的第一区域沿所述扫描线的一正方向形成多个梳状分支；所述公共电极的一部分重迭于所述扫描线的上方，其另一部分形成在相对于所述储存电容的另一侧边，并沿所述扫描线的一反方向形成多个梳状分支，所述像素电极的多个梳状分支与所述公共电极的多个梳状分支形成相互穿插对应。
PCT/CN2016/070815 2015-12-28 2016-01-13 液晶显示面板的像素构造及其制作方法 Ceased WO2017113442A1 (zh)

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