WO2017113056A1 - 多通道接口测试装置 - Google Patents

多通道接口测试装置 Download PDF

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Publication number
WO2017113056A1
WO2017113056A1 PCT/CN2015/099195 CN2015099195W WO2017113056A1 WO 2017113056 A1 WO2017113056 A1 WO 2017113056A1 CN 2015099195 W CN2015099195 W CN 2015099195W WO 2017113056 A1 WO2017113056 A1 WO 2017113056A1
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WIPO (PCT)
Prior art keywords
interface
test
channel
pins
signal carrier
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PCT/CN2015/099195
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English (en)
French (fr)
Inventor
刘子雨
李连玉
Original Assignee
深圳配天智能技术研究院有限公司
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Application filed by 深圳配天智能技术研究院有限公司 filed Critical 深圳配天智能技术研究院有限公司
Priority to CN201580079832.XA priority Critical patent/CN107615076A/zh
Priority to PCT/CN2015/099195 priority patent/WO2017113056A1/zh
Publication of WO2017113056A1 publication Critical patent/WO2017113056A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals

Definitions

  • the invention relates to the technical field of electronic device testing, and in particular to a multi-channel interface testing device.
  • DO module Analog Output, analog signal output
  • the DO module will be designed with 16-64 channels of multiple DO channels.
  • each channel needs to be connected to the load required for the test (typically a resistive load).
  • the load required for the test typically a resistive load.
  • the in-line resistors of a certain power and resistance value can be manually connected to each channel one by one.
  • this method is inefficient and requires a large labor cost.
  • the invention provides a multi-channel interface testing device, which solves the problem that the method of manually inserting the in-line resistors into each channel one by one when performing the aging test of a large number of products in the prior art is low in efficiency, and requires a large labor cost technology. problem.
  • a technical solution adopted by the present invention is to provide a multi-channel interface testing device, which is characterized in that it comprises a circuit board, which is provided with a test interface, a breadboard and a signal carrier board, and a test interface.
  • the breadboard has a plurality of jacks for insertion of a test resistor, the breadboard is electrically connected to the test interface;
  • the signal carrier has a signal carrier of a plurality of pins, and the test interface passes
  • the signal carrier board is electrically connected to the breadboard, and the electrical connection manner is formed on the circuit board by printing or connected by a flying wire; wherein when the peripheral output interface needs to be tested, the peripheral output interface is plugged
  • the test interface inserts a corresponding number of test resistors into the jack according to a channel number specification of the peripheral output interface to form a channel impedance test with the test interface;
  • the test interface is a male interface and/or a female interface,
  • the male connector is disposed at an end of the signal carrier board, and the male interface has a plurality of electrical connections respectively corresponding to the plurality of pins of the signal carrier board.
  • a male interface pin; and/or the female connector is disposed at an end of the signal carrier and spaced apart from the male
  • the breadboard comprises an upper resistor plate and a lower resistor plate each having the jack.
  • the number of the jacks in the upper resistor board and the lower resistor board are not less than the number of the male interface pins and the female interface pins, respectively.
  • the number of pins is not less than the number of male interface pins and/or female interface pins.
  • the circuit board is further provided with a cable buckle disposed between the signal carrier and the breadboard to receive the flying wire.
  • the cable fastener includes a fixing portion and a receiving portion, and the fixing portion is fixed to the circuit board; the receiving portion has a receiving port, and the receiving portion is connected to the fixing portion.
  • a technical solution adopted by the present invention is to provide a multi-channel interface testing device, which comprises a circuit board, a test interface and a breadboard on a circuit board, and a test interface for outputting an interface with a peripheral device. Connection; the breadboard has a plurality of sockets for the test resistor to be inserted, and the breadboard is electrically connected to the test interface; wherein, when the peripheral output interface needs to be tested, the peripheral output interface is plugged into the test interface, and according to the peripheral output interface
  • the channel number specification is to insert a corresponding number of test resistors into the jack to form a channel impedance test with the test interface.
  • the circuit board is further provided with a signal carrier board having a plurality of pins, and the test interface is electrically connected to the breadboard through the signal carrier board.
  • the test interface is a male interface and/or a female interface, and the male interface is disposed at an end of the signal carrier board, and the male interface has a plurality of electrical connections respectively corresponding to the plurality of pins of the signal carrier board.
  • the interface pin is disposed at an end of the signal carrier board and spaced apart from the male interface, and the female interface has a plurality of female interface pins respectively electrically connected to the plurality of pins of the signal carrier board.
  • the breadboard comprises an upper resistor plate and a lower resistor plate each having a jack.
  • the number of the jacks in the upper resistor board and the lower resistor board are respectively not less than the number of the male interface pin and the female interface pin.
  • the number of pins is not less than the number of male interface pins and/or female interface pins.
  • the electrical connection manner between the test interface and the signal carrier board is formed on the circuit board by printing or connected by a flying wire.
  • the pin and the jack are electrically connected by a flying wire.
  • the circuit board is further provided with a cable buckle disposed between the signal carrier and the breadboard to receive the flying wire.
  • the cable fastener includes a fixing portion and a receiving portion, and the fixing portion is fixed to the circuit board; the receiving portion has a receiving port, and the receiving portion is connected to the fixing portion.
  • the test interface matches the DB9 interface, DB25 interface, DB37 interface, or DB62 interface.
  • the multi-channel interface testing device can insert a corresponding number on the jack of the breadboard according to the channel number specification of the peripheral output interface when the peripheral output interface needs to be tested.
  • the test resistor forms a channel impedance test with the test interface, and has a simple structure, and can test various peripheral output interfaces with different channel numbers and specifications, and the test is convenient, the cost is low, and the test efficiency is improved.
  • FIG. 1 is a top plan view of a multi-channel interface test apparatus according to an embodiment of the present invention.
  • FIG. 2 is a top plan view of a multi-channel interface test apparatus according to another embodiment of the present invention.
  • FIG. 3 is a schematic view showing the structure of a multi-channel interface test device of FIG.
  • the multi-channel interface testing device of the present invention includes a circuit board 100 on which a test interface 10 and a breadboard 20 are disposed. And a signal carrier 30.
  • the test interface 10 is for electrically connecting with a peripheral output interface.
  • the breadboard 20 has a plurality of insertion holes 21 for testing resistance insertion.
  • the test interface 10 is electrically connected to the breadboard 20 through the signal carrier 30, and the signal carrier 30 has a plurality of Pin (not shown).
  • test interface 10 When the peripheral output interface needs to be tested, the test interface 10 is plugged with the peripheral output interface, and a corresponding number of test resistors are inserted on the breadboard 20 to form a channel with the test interface 10 according to the channel number specification of the peripheral output interface. Impedance test.
  • the breadboard 20 can be locked to the circuit board 100 by screws or soldered to the circuit board by pins.
  • the test interface 10 of the present invention is a male interface 11 and a female interface 12, and may have only one male interface 11 or only one female interface 12, and the male interface 11 is disposed at the end of the signal carrier 30.
  • the head interface 11 has a plurality of male interface pins (not shown) electrically connected to the plurality of pins of the signal carrier board, and the female interface 12 is disposed at the end of the signal carrier 30 and interfaces with the male connector.
  • the female interface 12 has a plurality of female interface pins (not shown) respectively electrically connected to the plurality of pins of the signal carrier board, specifically, the first male interface pin and the signal carrier
  • the first pin of the board is electrically connected
  • the second male interface pin is electrically connected to the second pin
  • the Nth male interface pin is electrically connected to the Nth pin
  • the first female interface pin is also the same. It is electrically connected to the first pin, and the second female interface pin is also electrically connected to the second pin, and the Nth female interface pin is also electrically connected to the Nth pin...
  • the breadboard 20 includes an upper resistor plate 22 and a lower resistor plate 23, the upper resistor plate 22 is spaced apart from one side of the signal carrier 30, and the lower resistor plate 23 is spaced apart from the other side of the signal carrier 30, the upper resistor plate 22 and
  • the lower resistor boards 23 are each provided with a jack 21, and the number of the jacks 21 in the upper resistor board 22 and the lower resistor board 23 is not less than the number of the male interface pin and the female interface pin, respectively, and the number of pins of the signal carrier board 30.
  • the number of the male interface pin or the female interface pin or the number of pins of the signal carrier 30 is not less than the sum of the male interface pin and the female interface pin.
  • the upper resistor board 22, the signal carrier board 30, and the lower resistor board 23 are sequentially disposed in parallel on the circuit board 100 for the convenience of the mounting operation and the electrical connection between the parts is prevented from being short-circuited.
  • the male interface 11 and the female interface 12 are spaced apart. At one end of the circuit board 100, and at a certain interval from the signal carrier 30, preferably, as shown in FIG. 1, when the male interface 11 and the female interface 12 are spaced apart from one end of the circuit board 100, the male The length direction of the interface 11 and the female interface 12 are perpendicular to the length direction of the circuit board 100 to reduce the use of the male interface 11 and the female interface 12 to the lateral area of the circuit board 100, making the multi-channel interface test apparatus more compact.
  • the electrical connection between all the components described above may be formed on the circuit board 100 by printing, or may be connected by a flying wire.
  • the electrical connection between the test interface and the signal carrier may be formed on the circuit board 100 by printing.
  • the connection can be realized by a flying wire, and the electrical connection can be selected according to actual convenience.
  • the pin and the socket 21 are electrically connected by a flying wire.
  • the breadboard 20 is fixedly inserted with a plurality of different resistance values.
  • the test resistance when the product needs to be tested, can be selectively connected according to the number of channels of the output interface of the product using the test resistance corresponding to the number of channels; of course, the pin and the jack 21 can also be Corresponding to the flying wire electrical connection, when the product needs to be tested, the test resistance corresponding to the channel number specification can be selected on the breadboard 20 according to the channel number specification of the output interface of the product to realize the channel impedance test.
  • the flying wire of the present invention means that the wire is often pressed, causing the folded portion to be broken and the contact is poor, and the ends of the broken wire are welded by a soldering iron with a thin enameled wire.
  • FIG. 2 is a top view of a multi-channel interface testing device according to another embodiment of the present invention
  • FIG. 3 is a schematic view of a multi-channel interface testing device of FIG. Since the plurality of pins and the plurality of jacks 21 are electrically connected by the flying wires, the distribution of the plurality of flying wires between the pins and the jacks 21 causes the circuit to be disordered, and when the fly needs to be changed, it takes a lot of time to find a certain One pin corresponds to the flying lead of the jack 21. Therefore, in other embodiments, the circuit board 100 further includes a cable ties 40 disposed between the signal carrier 30 and the breadboard 20 to receive the flying leads.
  • the capacity button 40 may be one or more.
  • a plurality of cartridge buckles 40 are spaced apart from each other in the wiring region 51.
  • the wiring area 51 is divided into a plurality of sub-areas, and each sub-area is provided with a tape buckle 40 for receiving a flying line passing through the sub-area.
  • the cable ties 40 include a fixing portion 41 and a receiving portion 42 , and the fixing portion 41 is fixed to the circuit board 100 .
  • the accommodating portion 42 has a accommodating port 43 that is connected to the fixing portion 41.
  • the electrical connection of all the pins to all of the jacks 21 can also be formed on the circuit board 100 by printing.
  • the test resistors of different resistance values can be selectively inserted on the breadboard 20 according to the number of channels. Implement channel impedance testing.
  • the test interface 10 of the present invention matches the DB9 interface, DB25 interface, DB37 interface or DB62 interface of the peripheral.
  • DB refers to the D-type data interface connector
  • the DB9 interface refers to the connector with the number of interfaces of 9 pins.
  • the line sequence of the peripheral output interface can be divided into differential, common cathode, common anode and other line sequential methods.
  • the multi-channel interface testing device of the present invention has the following advantages:
  • the present invention simultaneously designs the male interface 11 and the female interface 12, and the connection is convenient and reliable, and can be applied to multiple repeated tests.
  • the resistance carrier of the present invention is connected to the test resistor in the form of a breadboard 20. When tested, it can be applied to test resistors of different power, resistance and materials.
  • the present invention connects each pin of the test interface 10 with the pin of the signal carrier 30 in the form of a breadboard 20, and can adapt to the peripheral output interface defined by different line sequences.
  • the invention has simple structure and can test peripheral output interfaces with different channel numbers and specifications, and the test is convenient, the test efficiency is improved, and the cost is low;
  • the flying wires used for electrically connecting the pins and the jacks 21 of the present invention are arranged neatly for easy searching.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种多通道接口测试装置，其电路板(100)的测试接口(10)用于与外设输出接口电连接；面包板(20)具有多个供测试电阻插入的插孔(21)，面包板(20)与测试接口(10)电连接；其中，当需要对外设输出接口进行测试时，外设输出接口插接测试接口(10)，并根据外设输出接口的通道数量规格向插孔(21)插入对应数量的测试电阻以与测试接口(10)形成通道阻抗测试。

Description

多通道接口测试装置
【技术领域】
本发明涉电子设备测试技术领域，特别是涉及一种多通道接口测试装置。
【背景技术】
工业使用的PLC（Programmable Logic Controller，可编程逻辑控制器）模块中，有一类是DO模块（Analog Output，模拟量信号输出），并根据输出信号规格、使用场合等因素，DO模块会设计有16-64路的多路DO通道。
在测试多路DO通道的最大负载、老化等测试时，需要将每个通道连接至测试所需的负载（一般为电阻负载）。在产品设计和出厂测试阶段，需要进行大量重复的此类测试。
通常的做法，若模块DO通道数量少，接口连接方便，可将一定功率和电阻值的直插电阻手动逐个接入每个通道。当进行大量产品的老化测试时，此种方法效率较低，需要较大的人工成本。
若只针对测试需要，根据一种DO模块的接线方式设计固定的负载板，能极大的提供测试效率和可靠性。但也面临如下问题：如果存在多个DO模块，并且DO模块之间存在通道数量、接口线序、负载电阻规格等差别时，设计一种负载板不足以应对所有模块的测试，若设计多块负载板，则需要较大的经济成本。
【发明内容】
本发明提供一种多通道接口测试装置，以解决现有技术中当进行大量产品的老化测试时，将直插电阻手动逐个接入每个通道的方法效率较低，需要较大的人工成本技术问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种多通道接口测试装置，其特征在于，包括电路板，该电路板上设有测试接口、面包板以及信号载板，测试接口用于与外设输出接口电连接；面包板具有多个供测试电阻插入的插孔，该面包板与该测试接口电连接；信号载板具有多个引脚的信号载板，该测试接口通过该信号载板与该面包板电连接，该电连接方式是通过印刷形成于该电路板上或通过飞线实现连接；其中，当需要对外设输出接口进行测试时，该外设输出接口插接该测试接口，并根据该外设输出接口的通道数量规格向该插孔上插入对应数量的测试电阻以与该测试接口形成通道阻抗测试；该测试接口为公头接口和/或母头接口，该公头接口设于该信号载板的端部，该公头接口具有多个分别与该信号载板的多个引脚一一对应电连接的公接口管脚；和/或该母头接口设于该信号载板的端部并与该公头接口间隔设置，该母头接口具有多个分别与该信号载板的多个引脚一一对应电连接的母接口管脚。
其中，该面包板包括均设有具有该插孔的上电阻板和下电阻板。
其中，该上电阻板与该下电阻板中的该插孔的数量分别不小于该公接口管脚与该母接口管脚的数量。
其中，该引脚的数量不小于公接口管脚和/或母接口管脚的数量。
其中，该电路板上还设有容线扣，设于该信号载板与该面包板之间，以收容该飞线。
其中，该容线扣包括固定部和收容部，固定部固定于该电路板；收容部具有收容口，该收容部与该固定部连接。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种多通道接口测试装置，其包括电路板，电路板上设有测试接口和面包板，测试接口用于与外设输出接口电连接；面包板具有多个供测试电阻插入的插孔，面包板与测试接口电连接；其中，当需要对外设输出接口进行测试时，外设输出接口插接测试接口，并根据外设输出接口的通道数量规格以向插孔插入对应数量的测试电阻以与测试接口形成通道阻抗测试。
其中，电路板上还设有具有多个引脚的信号载板，测试接口通过信号载板与面包板电连接。
其中，测试接口为公头接口和/或母头接口，公头接口设于信号载板的端部，公头接口具有多个分别与信号载板的多个引脚一一对应电连接的公接口管脚；母头接口设于信号载板的端部并与公头接口间隔设置，母头接口具有多个分别与信号载板的多个引脚一一对应电连接的母接口管脚。
其中，面包板包括上均设有插孔的上电阻板和下电阻板。
其中，上电阻板与下电阻板中的插孔的数量分别不小于公接口管脚与母接口管脚的数量。
其中，引脚的数量不小于公接口管脚和/或母接口管脚的数量。
其中，测试接口与信号载板的电连接方式通过印刷形成于电路板上或通过飞线实现连接。
其中，引脚与插孔通过飞线实现电连接。
其中，该电路板上还设有容线扣，设于该信号载板与该面包板之间，以收容该飞线。
其中，该容线扣包括固定部和收容部，固定部固定于该电路板；收容部具有收容口，该收容部与该固定部连接。
其中，测试接口与DB9接口、DB25接口、DB37接口或DB62接口匹配。
与现有技术相比，本发明所提供的多通道接口测试装置，当需要对外设输出接口进行测试时，可根据外设输出接口的通道数量规格以在面包板的插孔上插入对应数量的测试电阻以与测试接口形成通道阻抗测试，结构简单，可对通道数量规格不一的多种外设输出接口进行测试，测试方便，成本低，提高了测试效率。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，其中：
图1是本发明一实施例的多通道接口测试装置的俯视图；
图2是本发明另一实施例的多通道接口测试装置的俯视图；
图3是图2中多通道接口测试装置的容线扣结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面将结合附图和实施方式对本发明进行详细说明。
请一并参阅图1，图1是本发明一实施例的多通道接口测试装置的俯视图，本发明的多通道接口测试装置包括电路板100，电路板100上设有测试接口10、面包板20以及信号载板30。
测试接口10用于与外设输出接口电连接，面包板20具有多个供测试电阻插入的插孔21，测试接口10通过信号载板30与面包板20电连接，信号载板30具有多个引脚（图未示）。
当需要对外设输出接口进行测试时，测试接口10与外设输出接口插接，并根据外设输出接口的通道数量规格以在面包板20上插入对应数量的测试电阻以与测试接口10形成通道阻抗测试。面包板20可以通过螺钉锁于电路板100上，也可以通过插针焊接于电路板上。
本发明的测试接口10为一个公头接口11和母头接口12，也可以为只有一个公头接口11或者只有一个母头接口12，公头接口11设于信号载板30的端部，公头接口11具有多个分别与信号载板的多个引脚一一对应电连接的公接口管脚（图未示），母头接口12设于信号载板30的端部并与公头接口11间隔设置，母头接口12具有多个分别与信号载板的多个引脚一一对应电连接的母接口管脚（图未示），具体地，第1个公接口管脚与信号载板的第1个引脚电连接，第2个公接口管脚与第2个引脚电连接，第N个公接口管脚与第N个引脚电连接，第1个母接口管脚同样是与第1个引脚电连接，第2个母接口管脚同样是与第2个引脚电连接，第N个母接口管脚同样是与第N个引脚电连接……，也就是说，第1个公接口管脚与第1个母接口管脚短接至第1个引脚，第2个公接口管脚与第2个母接口管脚短接至第2个引脚，第N个公接口管脚与第N个母接口管脚短接至第N个引脚……
面包板20包括上电阻板22和下电阻板23，上电阻板22间隔设于信号载板30的一侧，下电阻板23间隔设于信号载板30的另一侧，上电阻板22和下电阻板23均设有插孔21，上电阻板22与下电阻板23中的插孔21的数量分别不小于公接口管脚与母接口管脚的数量，信号载板30的引脚数量不小于公接口管脚或母接口管脚的数量或者信号载板30的引脚数量不小于公接口管脚和母接口管脚相加的数量。
为安装操作方便以及防止各部分之间电连接避免短路，上电阻板22、信号载板30以及下电阻板23依次平行间隔设于电路板100上，公头接口11和母头接口12间隔设于电路板100的一端部，并与信号载板30形成一定的间隔，优选地，如图1所示，公头接口11和母头接口12间隔设于电路板100的一端部时，公头接口11和母头接口12的长度方向与电路板100的长度方向垂直，以减少公头接口11和母头接口12对电路板100横向面积的使用，使多通道接口测试装置更紧凑。
上述所有部件之间的电连接方式可以通过印刷形成于电路板100上，也可以通过飞线实现连接，例如，测试接口与信号载板的电连接方式可以通过印刷形成于电路板100上，也可以通过飞线实现连接，可根据实际方便需要进行选择电连接的方式，优选地，引脚与插孔21通过飞线实现电连接，具体地，面包板20上固定插有多个不同阻值的测试电阻，当需要对产品进行测试时，可根据产品的输出接口的通道数量规格来选择性地使用飞线与通道数量规格对应的测试电阻连接；当然，引脚与插孔21也可是先对应飞线电连接，当需要对产品进行测试时，可根据产品的输出接口的通道数量规格来选择在面包板20上插入与通道数量规格对应的测试电阻以实现通道阻抗测试。本发明的飞线是指排线由于经常受到按压，导致折叠部位断裂而接触不良，在断裂的两端用细的漆包线用烙铁焊接。
请一并参阅图2和图3，图2是本发明另一实施例的多通道接口测试装置的俯视图，图3是图2中多通道接口测试装置的容线扣结构示意图。由于多个引脚与多个插孔21均通过飞线电连接，多条飞线在引脚与插孔21之间分布导致电路零乱，且飞后续在需要改线时，需要花大量时间查找某一引脚对应插孔21的飞线。故在其它实施例中，进一步地，电路板100上还设有容线扣40，该容线扣40设于信号载板30与面包板20之间，以收容飞线。
信号载板30与面包板20之间具有接线区域51，引脚与插孔21电连接使用的飞线均经过该接线区域51。容线扣40可以为1个，也可以为多个。多个容线扣40间隔排列于接线区域51。具体地，接线区域51分为多个子区域，每个子区域设置一容线扣40，以收容经过该子区域的飞线。优选地，信号载板30相对的两侧的子区域分别为3个，对应地容线扣40亦为3个。容线扣40包括固定部41和收容部42，固定部41固定于电路板100。收容部42具有收容口43，收容部42与固定部41连接。
当然，所有引脚与所有的插孔21的电连接方式也可以通过印刷形成于电路板100上，此时可根据通道数量规格来选择性以在面包板20上插入不同阻值的测试电阻以实现通道阻抗测试。
本发明的测试接口10与外设的DB9接口、DB25接口、DB37接口或DB62接口匹配。其中，DB指D型数据接口连接器，DB9接口是指接口数量为9针的连接器。外设输出接口的线序可以分为差分式、共阴极式、共阳极式等多种线序方式。
与现有技术相比，本发明的多通道接口测试装置具有如下优点：
（1）本发明同时设计了公头接口11和母头接口12，连接方便可靠，可应用于多次重复的测试使用。
（2）本发明的电阻载板采用面包板20的形式与测试电阻进行连接，在进行测试时，可以适用于不同功率、阻值及材料的测试电阻。
（3）本发明采用面包板20的形式将测试接口10的每个管脚与信号载板30的引脚对应连接，可适应不同线序定义的外设输出接口。
（4）本发明结构简单，可对多种通道数量规格不一的外设输出接口进行测试，测试方便，提高了测试效率，成本较低；
（5）本发明引脚与插孔21电连接使用的飞线排布整齐，方便查找。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种多通道接口测试装置，其特征在于，包括电路板，所述电路板上设有：
    测试接口，用于与外设输出接口电连接；
    面包板，具有多个供测试电阻插入的插孔，所述面包板与所述测试接口电连接；
    信号载板，具有多个引脚，所述测试接口通过所述信号载板与所述面包板电连接，所述电连接方式是通过印刷形成于所述电路板上或通过飞线实现连接；其中，
    当需要对外设输出接口进行测试时，所述外设输出接口插接所述测试接口，并根据所述外设输出接口的通道数量规格向所述插孔上插入对应数量的测试电阻以与所述测试接口形成通道阻抗测试；
    所述测试接口为：
    公头接口，所述公头接口设于所述信号载板的端部，所述公头接口具有多个分别与所述信号载板的多个引脚一一对应电连接的公接口管脚；和/或
    母头接口，所述母头接口设于所述信号载板的端部并与所述公头接口间隔设置，所述母头接口具有多个分别与所述信号载板的多个引脚一一对应电连接的母接口管脚。
  2. 根据权利要求1所述的多通道接口测试装置，其特征在于，所述面包板包括均设有具有所述插孔的上电阻板和下电阻板。
  3. 根据权利要求2所述的多通道接口测试装置，其特征在于，所述上电阻板与所述下电阻板中的所述插孔的数量分别不小于所述公接口管脚与所述母接口管脚的数量。
  4. 根据权利要求3所述的多通道接口测试装置，其特征在于，所述引脚的数量不小于公接口管脚和/或母接口管脚的数量。
  5. 根据权利要求1所述的多通道接口测试装置，其特征在于，所述电路板上还设有容线扣，设于所述信号载板与所述面包板之间，以收容所述飞线。
  6. 根据权利要求5所述的多通道接口测试装置，其特征在于，所述容线扣包括：
    固定部，固定于所述电路板；
    收容部，具有收容口，所述收容部与所述固定部连接。
  7. 一种多通道接口测试装置，其特征在于，包括电路板，所述电路板上设有：
    测试接口，用于与外设输出接口电连接；
    面包板，具有多个供测试电阻插入的插孔，所述面包板与所述测试接口电连接；其中，
    当需要对外设输出接口进行测试时，所述外设输出接口插接所述测试接口，并根据所述外设输出接口的通道数量规格向所述插孔上插入对应数量的测试电阻以与所述测试接口形成通道阻抗测试。
  8. 根据权利要求7所述的多通道接口测试装置，其特征在于，所述电路板上还设有具有多个引脚的信号载板，所述测试接口通过所述信号载板与所述面包板电连接。
  9. 根据权利要求8所述的多通道接口测试装置，其特征在于，所述测试接口为：
    公头接口，设于所述信号载板的端部，所述公头接口具有多个分别与所述信号载板的多个引脚一一对应电连接的公接口管脚；和/或
    母头接口，设于所述信号载板的端部并与所述公头接口间隔设置，所述母头接口具有多个分别与所述信号载板的多个引脚一一对应电连接的母接口管脚。
  10. 根据权利要求9所述的多通道接口测试装置，其特征在于，所述面包板包括均设有具有所述插孔的上电阻板和下电阻板。
  11. 根据权利要求10所述的多通道接口测试装置，其特征在于，所述上电阻板与所述下电阻板中的所述插孔的数量分别不小于所述公接口管脚与所述母接口管脚的数量。
  12. 根据权利要求11所述的多通道接口测试装置，其特征在于，所述引脚的数量不小于公接口管脚和/或母接口管脚的数量。
  13. 根据权利要求8所述的多通道接口测试装置，其特征在于，所述测试接口与所述信号载板的电连接方式是通过印刷形成于所述电路板上或通过飞线实现连接。
  14. 根据权利要求9所述的多通道接口测试装置，其特征在于，所述引脚与所述插孔通过飞线电连接。
  15. 根据权利要求13所述的多通道接口测试装置，其特征在于，所述电路板上还设有容线扣，设于所述信号载板与所述面包板之间，以收容所述飞线。
  16. 根据权利要求15所述的多通道接口测试装置，其特征在于，所述容线扣包括：
    固定部，固定于所述电路板；
    收容部，具有收容口，所述收容部与所述固定部连接。
  17. 根据权利要求16所述的多通道接口测试装置，其特征在于，所述测试接口与DB9接口、DB25接口、DB37接口或DB62接口匹配。
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