WO2017107294A1 - Goa电路及液晶显示装置 - Google Patents

Goa电路及液晶显示装置 Download PDF

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Publication number
WO2017107294A1
WO2017107294A1 PCT/CN2016/072849 CN2016072849W WO2017107294A1 WO 2017107294 A1 WO2017107294 A1 WO 2017107294A1 CN 2016072849 W CN2016072849 W CN 2016072849W WO 2017107294 A1 WO2017107294 A1 WO 2017107294A1
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Prior art keywords
electrically connected
thin film
film transistor
clock signal
node
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PCT/CN2016/072849
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English (en)
French (fr)
Inventor
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/917,571 priority Critical patent/US9847069B2/en
Publication of WO2017107294A1 publication Critical patent/WO2017107294A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit and a liquid crystal display device.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • GOA technology (Gate Driver on Array) is an array substrate row driving technology.
  • the original array process of the liquid crystal display panel is used to fabricate a horizontal scanning line driving circuit on a substrate around the display area, so that it can replace the external integrated circuit board ( (Integrated Circuit, IC) to complete the horizontal scanning line drive.
  • IC integrated circuit board
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase productivity and reduce product cost, and can make LCD panels more suitable for making narrow borders or no borders. Display product.
  • LTPS-TFT liquid crystal display devices have attracted more and more attention.
  • LTPS-TFT liquid crystal display devices have high resolution, fast response, high brightness, High aperture ratio and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved.
  • a-Si amorphous silicon
  • Each level of the GOA unit includes: a control input unit 100, a voltage stabilization unit 200, a control output unit 300, a second node control unit 400, a first node pulldown unit 500, a pulldown maintenance unit 600, a global control unit 700, and global control.
  • Auxiliary unit 800 is
  • N be a positive integer, in addition to the first and second level GOA units, in the Nth level GOA unit:
  • the control input unit 100 includes: a first thin film transistor T1, a gate of the first thin film transistor T1 is electrically connected to the M+2 clock signal CK(M+2), and the source is electrically connected to the upper
  • the output terminal G(N-2) of the two-stage N-2th GOA unit is electrically connected to the third node K(N), and the output terminal G of the upper two-stage N-2th GOA unit (N- 2) outputting the scan driving signal of the N-2th GOA unit as a level transmission signal;
  • the voltage stabilizing unit 200 includes: a second thin film transistor T2, the gate of the second thin film transistor T2 is electrically connected to the constant voltage high potential VGH, and the source is electrically connected to the third node K(N), and the drain Electrically connected to the first node Q (N);
  • the output unit 300 includes a third thin film transistor T3.
  • the gate of the third thin film transistor T3 is electrically connected to the first node Q(N), and the source is electrically connected to the Mth clock signal CK(M).
  • the drain is electrically connected to the output terminal G(N); and the first capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G ( N);
  • the second node control unit 400 includes a fourth thin film transistor T4.
  • the gate of the fourth thin film transistor T4 is electrically connected to the third node K(N), and the source is electrically connected to the M+2 clock.
  • the signal CK (M+2), the drain is electrically connected to the second node P(N); and the eighth thin film transistor T8, the gate of the eighth thin film transistor T8 is electrically connected to the M+2 clock signal CK (M+2), the source is electrically connected to the constant voltage high potential VGH, and the drain is electrically connected to the second node P(N);
  • the first node pull-down unit 500 includes a sixth thin film transistor T6.
  • the gate of the sixth thin film transistor T6 is electrically connected to the Mth clock signal CK(M), and the source is electrically connected to the seventh thin film transistor.
  • a drain of the T7 is electrically connected to the third node K(N); and
  • a seventh thin film transistor T7 the gate of the seventh thin film transistor T7 is electrically connected to the second node P(N), the source Electrically connected to a constant voltage low potential VGL;
  • the pull-down maintaining unit 600 includes: a fifth thin film transistor T5, a gate of the fifth thin film transistor T5 is electrically connected to the second node P(N), and the source is electrically connected to the constant voltage low potential VGL, and the drain Electrically connected to the output terminal G (N); and a second capacitor C2, one end of the second capacitor C2 is electrically connected to the second node P (N), the other end is electrically connected to the constant voltage low potential VGL;
  • the global control unit 700 includes: a tenth thin film transistor T10, the tenth and the source of the tenth thin film transistor T10 are electrically connected to the global control signal Gas, the drain is electrically connected to the output terminal G (N); And a ninth thin film transistor T9, the gate of the ninth thin film transistor T9 is electrically connected to the global control signal Gas, the source is electrically connected to the constant voltage low potential VGL, and the drain is electrically connected to the second node P (N) );
  • the global control auxiliary unit 800 includes: an eleventh thin film transistor T11, the gate of the eleventh thin film transistor T11 is electrically connected to the global control signal Gas, and the source is electrically connected to the constant voltage low potential VGL, and the drain Electrically connected to the third node K (N).
  • the working process of the existing GOA circuit shown in FIG. 1 is mainly divided into two parts.
  • Points One part is the global control signal Gas controls the output of all GOA units to simultaneously output high potential, and the other part is driven by the GOA units of each level after the All Gate On function is completed.
  • the existing GOA circuit has an inevitable risk point.
  • the cascaded first-stage GOA unit and the third-level GOA unit as an example, wherein the source of the third thin film transistor T3 and the first thin film transistor T1 of the third-stage GOA unit in the first-stage GOA unit are described.
  • the gates are electrically connected to the first clock signal CK(1), the source of the third thin film transistor T3 in the third stage GOA unit, and the gate of the first thin film transistor T1 in the first stage GOA unit are electrically connected.
  • Connect the third clock signal CK(3) Since the level-transmitting signal of the first-stage GOA unit is STV, the GOA unit of the first stage is driven normally (normal operation starts from the third pulse signal CK(3) to generate the first pulse), and no redundant pulse is generated. signal.
  • the level-transmitted signal input by the third-stage GOA unit is the scan driving signal outputted by the output terminal G(1) of the first-stage GOA unit, and the scan driving signal outputted by the output terminal G(1) of the first-stage GOA unit affects the first The working state of the three-level GOA unit. This is because after the global control of the output of all GOA units is simultaneously outputting a high potential, the output terminal G(1) of the first stage GOA unit is held at a high level by the first capacitor C1.
  • the third stage GOA unit The first thin film transistor T1 is controlled by the first clock signal CK(1), and when the first high level of the first clock signal CK(1) comes, the output terminal G of the first stage GOA unit is The high level of (1) is transmitted to the first node Q(3) of the third stage GOA unit, causing the third stage GOA unit to operate before the first stage GOA unit and making the output G of the third stage GOA unit ( 3) Multiple redundant pulses are output. This redundant pulse will always follow the output scan drive signal to the next stage, which will affect the next stage of the scan drive signal.
  • all GOA stages controlled by the first clock signal CK(1) that is, the gate of the first thin film transistor T1 is electrically connected to the output terminal G of the GOA unit of the first clock signal CK(1) (3), G(7), G(11), etc. all generate redundant pulse signals, which eventually leads to failure of the entire GOA circuit.
  • the present invention provides a GOA circuit comprising a cascaded multi-level GOA unit, each stage GOA unit comprising: a control input unit, a voltage stabilizing unit, an output unit, a second node control unit, and a first a node pulldown unit, a pulldown maintenance unit, a global control unit, a level drop down unit, a level transfer unit, and a global control auxiliary unit;
  • N be a positive integer, in addition to the first and second level GOA units, in the Nth level GOA unit:
  • the control input unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to the M+2 clock signal, and a source is electrically connected to the upper two-stage N-2th GOA unit a level transmitting end, the drain is electrically connected to the third node;
  • the voltage stabilizing unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first constant piezoelectric position, a source is electrically connected to the third node, and a drain is electrically connected to the first node ;
  • the output unit includes: a third thin film transistor, a gate of the third thin film transistor is electrically connected to the first node, a source is electrically connected to the Mth clock signal, and a drain is electrically connected to the output end; a first capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the second node control unit includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the third node, and the source is electrically connected to the M+2 clock signal, and the drain is electrically connected The second node; and the eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to the M+2 clock signal, the source is electrically connected to the first constant piezoelectric position, and the drain is electrically connected to the drain Second node;
  • the first node pull-down unit includes: a sixth thin film transistor, a gate of the sixth thin film transistor is electrically connected to the Mth clock signal, and a source is electrically connected to a drain of the seventh thin film transistor, and the drain is electrically Connected to the third node; and a seventh thin film transistor, the gate of the seventh thin film transistor is electrically connected to the second node, and the source is electrically connected to the second constant piezoelectric position;
  • the pull-down maintaining unit includes: a fifth thin film transistor, a gate of the fifth thin film transistor is electrically connected to the second node, a source is electrically connected to the second constant piezoelectric position, and a drain is electrically connected to the output end; And a second capacitor, one end of the second capacitor is electrically connected to the second node, and the other end is electrically connected to the second constant piezoelectric position;
  • the global control unit includes: an eleventh thin film transistor, the gate of the eleventh thin film transistor is electrically connected to the global control signal, the source is electrically connected to the second constant piezoelectric potential, and the drain is electrically connected to the first a two-node; and a twelfth thin film transistor, a gate of the twelfth thin film transistor The pole and the source are electrically connected to the global control signal, and the drain is electrically connected to the output end;
  • the step-down pull-down unit includes: a tenth thin film transistor, the gate of the tenth thin film transistor is electrically connected to the second node, the source is electrically connected to the second constant voltage bit, and the drain is electrically connected to the level pass end;
  • the stage pass unit includes: a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the first node, the source is electrically connected to the Mth clock signal, and the drain is electrically connected to the level end ;
  • the global control auxiliary unit includes: a thirteenth thin film transistor, a gate of the thirteenth thin film transistor is electrically connected to the output end, and a source is electrically connected to a drain of the fourteenth thin film transistor, and the drain is electrically And a fourteenth thin film transistor, the gate of the fourteenth thin film transistor is electrically connected to the global control signal, and the source is electrically connected to the second constant voltage.
  • each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor, wherein the first constant piezoelectric potential is a constant voltage high potential, and the second constant piezoelectric potential is a constant voltage low potential.
  • each of the thin film transistors is a P-type low temperature polysilicon semiconductor thin film transistor, wherein the first constant piezoelectric potential is a constant voltage low potential, and the second constant piezoelectric potential is a constant voltage high potential.
  • the sources of the first thin film transistor T1 are electrically connected to the start signal STV of the circuit.
  • the GOA circuit includes four clock signals: first, second, third, and fourth clock signals; when the Mth clock signal is a third clock signal, the M+2th clock signal is a clock signal; when the Mth clock signal is the fourth clock signal, the M+2th clock signal is the second clock signal.
  • the first, second, third, and fourth clock signal pulse periods are the same, the first pulse signal of the first clock signal is first generated, and the first pulse signal of the first clock signal is At the same time, the first pulse signal of the second clock signal is generated, and the first pulse signal of the second clock signal ends while the first pulse signal of the third clock signal is generated.
  • the first pulse signal of the fourth clock signal is generated while the first pulse signal of the third clock signal ends, and the first pulse signal of the fourth clock signal ends with the first The second pulse signal of the clock signal is generated.
  • the present invention also provides a liquid crystal display device comprising the above GOA circuit.
  • a GOA circuit provided by the present invention is provided by adding a level transfer unit And the level transfer pull-down unit, and the global control auxiliary unit is improved, and the signal output from the level transmission end of the level transmission unit is different from the scan driving signal as the level transmission signal, and the global control auxiliary unit is used simultaneously at the output end of all the GOA units.
  • the potential of the stable level transmitting end is output during the period of the scan driving signal, so that the signal outputted by the level transmitting end is opposite to the potential of the scanning driving signal, and after completing the function of simultaneously controlling the output of all the GOA units at the same time, the prior art can be avoided.
  • the scan driving signal outputted by the GOA unit is used as a circuit failure problem caused by the level transmission signal, and the redundant pulse in the GOA circuit level transmission process is eliminated, the GOA circuit is guaranteed to work normally, and the working stability of the liquid crystal display device is improved.
  • the liquid crystal display device of the present invention includes the above GOA circuit and has good operational stability.
  • 1 is a circuit diagram of a conventional GOA circuit
  • FIG. 2 is a timing diagram of the GOA circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of a first embodiment of a GOA circuit of the present invention.
  • FIG. 4 is a timing diagram of the GOA circuit shown in FIG. 3;
  • Figure 5 is a circuit diagram of a first stage GOA unit of the GOA circuit shown in Figure 3;
  • FIG. 6 is a circuit diagram of a second stage GOA unit of the GOA circuit shown in FIG. 3;
  • Figure 7 is a circuit diagram of a second embodiment of the GOA circuit of the present invention.
  • Figure 8 is a circuit diagram of a first stage GOA unit of the GOA circuit shown in Figure 7;
  • Figure 9 is a circuit diagram of the second stage GOA unit of the GOA circuit shown in Figure 7.
  • the present invention first provides a GOA circuit, including a cascaded multi-level GOA unit, each of which includes: a control input unit 100, a voltage stabilization unit 200, an output unit 300, and a second The node control unit 400, the first node pull-down unit 500, the pull-down maintaining unit 600, the global control unit 700, the level-down pull-down unit 800, the level-transmitting unit 900, and the global control assistant unit 1000.
  • N be a positive integer, except for the first and second GOA units, at the Nth level GOA unit in:
  • the control input unit 100 includes a first thin film transistor T1.
  • the gate of the first thin film transistor T1 is electrically connected to the M+2 clock signal CK(M+2), and the source is electrically connected to the upper two.
  • the voltage stabilizing unit 200 includes: a second thin film transistor T2, the gate of the second thin film transistor T2 is electrically connected to the first constant piezoelectric position, and the source is electrically connected to the third node K(N), and the drain Electrically connected to the first node Q (N);
  • the output unit 300 includes a third thin film transistor T3.
  • the gate of the third thin film transistor T3 is electrically connected to the first node Q(N), and the source is electrically connected to the Mth clock signal CK(M).
  • the drain is electrically connected to the output terminal G(N); and the first capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G ( N);
  • the second node control unit 400 includes a fourth thin film transistor T4.
  • the gate of the fourth thin film transistor T4 is electrically connected to the third node K(N), and the source is electrically connected to the M+2 clock.
  • the signal CK (M+2), the drain is electrically connected to the second node P(N); and the eighth thin film transistor T8, the gate of the eighth thin film transistor T8 is electrically connected to the M+2 clock signal CK (M+2), the source is electrically connected to the first constant piezoelectric position, and the drain is electrically connected to the second node P(N);
  • the first node pull-down unit 500 includes a sixth thin film transistor T6.
  • the gate of the sixth thin film transistor T6 is electrically connected to the Mth clock signal CK(M), and the source is electrically connected to the seventh thin film transistor.
  • a drain of the T7 is electrically connected to the third node K(N); and
  • a seventh thin film transistor T7 the gate of the seventh thin film transistor T7 is electrically connected to the second node P(N), the source Electrically connected to the second constant piezoelectric position;
  • the pull-down maintaining unit 600 includes: a fifth thin film transistor T5, a gate of the fifth thin film transistor T5 is electrically connected to the second node P(N), and a source is electrically connected to the second constant voltage bit and has a drain Electrically connected to the output terminal G (N); and a second capacitor C2, one end of the second capacitor C2 is electrically connected to the second node P (N), the other end is electrically connected to the second constant piezoelectric position;
  • the global control unit 700 includes an eleventh thin film transistor T11.
  • the gate of the eleventh thin film transistor T11 is electrically connected to the global control signal Gas, and the source is electrically connected to the second constant voltage bit.
  • the second node P(N); and the twelfth thin film transistor T12, the gate and the source of the twelfth thin film transistor T12 are electrically connected to the global control signal Gas, and the drain is electrically connected to the output.
  • the level transfer pull-down unit 800 includes: a tenth thin film transistor T10, the gate of the tenth thin film transistor T10 is electrically connected to the second node P(N), and the source is electrically connected to the second constant voltage bit, and the drain is electrically connected Very electrically connected to the stage ST (N);
  • the level transfer unit 900 includes: a ninth thin film transistor T9, and the ninth thin film transistor T9
  • the gate is electrically connected to the first node Q (N)
  • the source is electrically connected to the Mth clock signal CK (M)
  • the drain is electrically connected to the stage ST (N);
  • the global control auxiliary unit 1000 includes: a thirteenth thin film transistor T13, a gate of the thirteenth thin film transistor T13 is electrically connected to the output terminal G(N), and a source is electrically connected to the fourteenth thin film transistor T14. a drain, a drain electrically connected to the stage ST (N); and a fourteenth thin film transistor T14, the gate of the fourteenth thin film transistor T14 is electrically connected to the global control signal Gas, the source is electrically Connected to the second constant piezoelectric position.
  • each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor; and the first constant piezoelectric potential is a constant voltage high potential VGH, The second constant piezoelectric position is a constant voltage low potential VGL; when the global control signal Gas provides a high potential, the output terminals of all the GOA units simultaneously output a high potential, and the stage terminals of all the GOA units simultaneously output a low potential.
  • a first embodiment of the invention includes four clock signals providing high potential pulses: first, second, third, and fourth clock signals CK(1), CK(2), CK(3), CK(4)
  • first, second, third, and fourth clock signals CK(1), CK(2), CK(3), CK(4) When the Mth clock signal CK(M) is the third clock signal CK(3), the M+2th clock signal CK(M+2) is the first clock signal CK(1);
  • the Mth clock signal CK(M) is the fourth clock signal CK(4), the M+2th clock signal CK(M+2) is the second clock signal CK(2).
  • the first, second, third, and fourth clock signals CK(1), CK(2), CK(3), and CK(4) have the same pulse period, and the first clock signal CK ( The first pulse signal of 1) is first generated, and the first pulse signal of the second clock signal CK(2) is generated while the first pulse signal of the first clock signal CK(1) ends.
  • the first pulse signal of the third clock signal CK(3) is generated while the first pulse signal of the second clock signal CK(2) ends, and the third clock signal CK(3)
  • the first pulse signal of the fourth clock signal CK(4) is generated while the first pulse signal ends, and the first pulse signal of the fourth clock signal CK(4) ends simultaneously
  • a second pulse signal of a clock signal CK(1) is generated.
  • each of the thin film transistors is a P-type low temperature polysilicon semiconductor thin film transistor; the first constant piezoelectric position is a constant voltage low potential VGL, and the second constant voltage The potential is a constant voltage high potential VGH; when the global control signal Gas provides a low potential, the output terminals of all GOA units simultaneously output a low potential, and the stage terminals of all GOA units simultaneously output a high potential.
  • a second embodiment of the present invention includes four clock signals providing a low potential pulse signal: first, second, third, and fourth clock signals CK(1), CK(2), CK(3), CK( 4); when the Mth clock signal CK(M) is the third clock signal CK(3), the M+2th clock signal CK(M+2) is the first clock signal CK(1) When the Mth clock signal CK(M) is the fourth clock signal CK(4), the M+2th clock signal CK(M+2) is the second clock signal. No. CK (2).
  • the first, second, third, and fourth clock signals CK(1), CK(2), CK(3), and CK(4) have the same pulse period, and the first clock signal CK ( The first pulse signal of 1) is first generated, and the first pulse signal of the second clock signal CK(2) is generated while the first pulse signal of the first clock signal CK(1) ends.
  • the first pulse signal of the third clock signal CK(3) is generated while the first pulse signal of the second clock signal CK(2) ends, and the third clock signal CK(3)
  • the first pulse signal of the fourth clock signal CK(4) is generated while the first pulse signal ends, and the first pulse signal of the fourth clock signal CK(4) ends simultaneously
  • a second pulse signal of a clock signal CK(1) is generated.
  • the source of the first thin film transistor T1 is electrically connected to the beginning of the circuit.
  • the signal STV, the gate of the first thin film transistor T1 is electrically connected to the third clock signal CK(3), and the source of the third thin film transistor T3 is electrically connected to the first clock signal CK(1);
  • the source of the first thin film transistor T1 is electrically connected to the start signal STV of the circuit, and the gate of the first thin film transistor T1 is electrically connected to the fourth clock signal CK(4), the third film.
  • the source of the transistor T3 is electrically connected to the second clock signal CK(2).
  • the GOA circuit of the present invention performs scanning by means of interlaced scanning, and the level-transmitted signal generated by the first-stage GOA unit is transmitted to the third-level GOA unit, and the second-level GOA unit generates The level-transmitted signal is transmitted to the fourth-stage GOA unit, and the level-transmitted signal generated by the third-stage GOA unit is transmitted to the fifth-level GOA unit, and the level-transmitted signal generated by the fourth-stage GOA unit is transmitted to the sixth-level GOA unit, and so on.
  • the global control signal Gas provides a high potential
  • the eleventh, twelfth, and fourteenth thin film transistors T11, T12, and T14 of all the GOA units are turned on, and the twelfth thin film transistor T12 of all the GOA units makes the output.
  • the scan drive signal output by G(N) is the high potential provided by the global control signal Gas
  • the eleventh thin film transistor T11 pulls down the second node P(N) to the constant voltage low potential VGL, and is controlled by the output terminal G(N).
  • the thirteenth thin film crystal T13 is opened, and cooperates with the fourteenth thin film crystal T14 to pull down the stage terminal ST(N) to the constant voltage low potential VGL, and the level transmission signal of the stage ST(N) output of each level GOA unit All are low potential;
  • the global control signal Gas provides a low potential
  • the output terminal G(N) of all GOA units is kept at a high potential by the action of the first capacitor C1, and the stage terminal ST(N) is still at a low potential;
  • the first clock signal CK(1) provides a high potential
  • the stage ST(1) of the first stage GOA unit remains low
  • the third stage GOA unit the first thin film transistor T1 and the eighth film
  • the transistor T8 is turned on, the first node Q(3) is at a low potential, the second node P(3) is charged to a high potential, the fifth thin film transistor T5 is turned on, the third thin film transistor T3 is turned off, and the output terminal G(3) is discharged to a constant Pressing down the potential VGL;
  • the third clock signal CK(3) and the start signal STV of the circuit provide a high potential.
  • the first stage GOA unit the first thin film transistor T1 is turned on, the first node Q(1) of the first stage GOA unit Charging to a high potential, the eighth thin film transistor T8 is turned on, the second node P(1) is charged to a high potential, the fifth thin film transistor T5 is turned on, and the output terminal G(1) is pulled down to a constant voltage low potential VGL;
  • the third stage GOA unit Medium the first node Q(3) remains low, the third thin film transistor T3 is turned off, and the output terminal G(3) is kept low, and no redundant pulse is generated;
  • the third clock signal CK(3) and the start signal STV of the circuit provide a low potential
  • the first thin film transistor T1 in the first stage GOA unit is turned off
  • the fourth thin film transistor T4 is subjected to the third node K(1). (the potential is the same as the first node Q(1)), the control is turned on, and the second node P(1) is pulled low;
  • the first clock signal CK(1) again provides a high potential.
  • the third and ninth thin film transistors T3, T9 are controlled by the control of the first node Q(1), and the level is transmitted. Both the terminal ST(1) and the output terminal G(1) output a high potential provided by the first clock signal CK(1) as a high potential of the level transmission signal and the scan driving signal, and the first node Q(1) is subjected to the first capacitance
  • the role of C1 is raised to a higher potential; in the third stage GOA unit: the first thin film transistor T1 is turned on, the first node Q(3) remains charged to a high potential, the second node P(3) remains at a high potential, and the output terminal G (3) Maintain a low potential;
  • the third clock signal CK(3) again provides a high potential.
  • the first and eighth thin film transistors T8 are turned on, and the second node P(1) is charged to a high potential, the first node Q (1) Decrease to a low potential, and the fifth and tenth thin film transistors T5 and T10 controlled by the second node are turned on, respectively, and pull down the potentials of the output terminal G(1) and the stage terminal ST(1) to a constant voltage low potential.
  • the third and ninth thin film transistors T3, T9 are controlled by the control of the first node Q(3), and the level transmitting terminal ST(3) And the output terminal G(3) outputs the high potential provided by the third clock signal CK(3) as the high potential of the level transmission signal and the scan driving signal, and the first node Q(3) is raised to the role of the first capacitor C1 to Higher potential.
  • the above GOA circuit does not generate redundant pulses during the whole working process, and the GOA circuit performs scan driving normally, which improves the working stability of the liquid crystal display device. .
  • the second embodiment shown in FIG. 7 is similar to the specific working process of the first embodiment, and only needs to change the potential of each signal and node, and details are not described herein again.
  • the present invention also provides a liquid crystal display device comprising the above GOA circuit, thereby having good operational stability.
  • the GOA circuit of the present invention improves the global control auxiliary unit by adding a level transfer unit and a level transfer pull-down unit, and the output of the level transfer unit of the level transfer unit is different from that of the sweep.
  • the signal of the driving signal is used as the level transmitting signal, and the potential of the stable level transmitting end is outputted by the global control auxiliary unit at the output end of all the GOA units at the same time, so that the signal outputted by the level transmitting end is opposite to the potential of the scanning driving signal.
  • the liquid crystal display device of the present invention includes the above GOA circuit and has good operational stability.

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Abstract

一种GOA电路及液晶显示装置，该GOA电路通过增设级传单元(900)和级传下拉单元(800)，并对全局控制辅助单元(1000)进行改进，采用级传单元(900)的级传端(ST(N))输出的不同于扫描驱动信号的信号作为级传信号，采用全局控制辅助单元(1000)在全部GOA单元的输出端(G(N))同时输出扫描驱动信号的期间稳定级传端(ST(N))的电位，使得级传端(ST(N))输出的信号与扫描驱动信号的电位相反，在完成全局控制全部GOA单元的输出端(G(N))同时输出的功能后，能够避免现有技术中以GOA单元输出的扫描驱动信号作为级传信号所导致的电路失效问题，消除GOA电路级传过程中的冗余脉冲，保证GOA电路正常工作，提升液晶显示装置的工作稳定性。

Description

GOA电路及液晶显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路及液晶显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板((Integrated Circuit，IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示装置也越来越受关注，LTPS-TFT液晶显示装置具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序，低温多晶硅半导体本身具有超高的电子迁移率，比非晶硅半导体相对高100倍以上，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。
图1所示为一种现有的用于LTPS液晶显示装置的GOA电路，包括级联的多级GOA单元，该现有的GOA电路除了具备基本的扫描驱动功能与移位寄存功能以外，还带有使各级扫描驱动信号全部同时输出(All Gate On)的功能。每一级GOA单元均包括：控制输入单元100、稳压单元200、控制输出单元300、第二节点控制单元400、第一节点下拉单元500、下拉维持单元600、全局控制单元700、及全局控制辅助单元800。
设N为正整数，除第一级与第二级GOA单元外，在第N级GOA单元中：
所述控制输入单元100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于上 两级第N-2级GOA单元的输出端G(N-2)，漏极电性连接于第三节点K(N)，上两级第N-2级GOA单元的输出端G(N-2)输出的第N-2级GOA单元的扫描驱动信号作为级传信号；
所述稳压单元200包括：第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于恒压高电位VGH，源极电性连接于第三节点K(N)，漏极电性连接于第一节点Q(N)；
所述输出单元300包括：第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于第一节点Q(N)，源极电性连接于第M条时钟信号CK(M)，漏极电性连接于输出端G(N)；以及第一电容C1，所述第一电容C1的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)；
所述第二节点控制单元400包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第三节点K(N)，源极电性连接于第M+2条时钟信号CK(M+2)，漏极电性连接于第二节点P(N)；以及第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于恒压高电位VGH，漏极电性连接于第二节点P(N)；
所述第一节点下拉单元500包括：第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第M条时钟信号CK(M)，源极电性连接于第七薄膜晶体管T7的漏极，漏极电性连接于第三节点K(N)；以及第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第二节点P(N)，源极电性连接于恒压低电位VGL；
所述下拉维持单元600包括：第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于第二节点P(N)，源极电性连接于恒压低电位VGL，漏极电性连接于输出端G(N)；以及第二电容C2，所述第二电容C2的一端电性连接于第二节点P(N)，另一端电性连接于恒压低电位VGL；
所述全局控制单元700包括：第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极和源极均电性连接于全局控制信号Gas，漏极电性连接于输出端G(N)；以及第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于全局控制信号Gas，源极电性连接于恒压低电位VGL，漏极电性连接于第二节点P(N)；
所述全局控制辅助单元800包括：第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极电性连接于全局控制信号Gas，源极电性连接于恒压低电位VGL，漏极电性连接于第三节点K(N)。
请结合图2，图1所示的现有的GOA电路的工作过程主要分为两个部 分：一个部分是全局控制信号Gas控制全部GOA单元的输出端同时输出高电位，另一个部分是在完成All Gate On功能之后，进行各级GOA单元的驱动。该现有的GOA电路存在着一个不可避免的风险点，这个风险点的存在会直接导致整个电路的失效：由于输出端G(N)上第一电容C1的存在，当全局控制信号Gas提供高电位，完成All Gate On功能之后，所有GOA单元的输出端G(N)都会一直保持全局控制信号Gas的高电平，如果输出端G(N)上的高电平不能在第M条时钟信号CK(M)的高电平来临之前放电至低电平，将会影响GOA电路的正常工作。
以级联的第一级GOA单元与第三级GOA单元为例进行说明：其中第一级GOA单元中的第三薄膜晶体管T3的源极和第三级GOA单元中的第一薄膜晶体管T1的栅极均电性连接第一条时钟信号CK(1)，第三级GOA单元中的第三薄膜晶体管T3的源极和第一级GOA单元中的第一薄膜晶体管T1的栅极均电性连接第三条时钟信号CK(3)。由于第一级GOA单元的级传信号是STV，所以第一级的GOA单元驱动正常(正常工作从第三条时钟信号CK(3)产生第一个脉冲开始)，不会产生冗余的脉冲信号。而第三级GOA单元输入的级传信号是第一级GOA单元的输出端G(1)输出的扫描驱动信号，第一级GOA单元的输出端G(1)输出的扫描驱动信号会影响第三级GOA单元的工作状态。这是因为在完成全局控制全部GOA单元的输出端同时输出高电位后，第一级GOA单元的输出端G(1)被第一电容C1保持在高电平，此时，第三级GOA单元中的第一薄膜晶体管T1受到第一条时钟信号CK(1)的控制，当第一条时钟信号CK(1)的第一个高电平到来时，将第一级GOA单元的输出端G(1)的高电平传输到第三级GOA单元的第一节点Q(3)，导致第三级GOA单元先于第一级GOA单元工作，并使得第三级GOA单元的输出端G(3)多输出了一个冗余的脉冲，这个冗余的脉冲会一直跟随着输出的扫描驱动信号向下级传，进而影响下一级的扫描驱动信号。不仅如此，所有受第一条时钟信号CK(1)控制输入的GOA级数，即第一薄膜晶体管T1的栅极电性连接于第一条时钟信号CK(1)的GOA单元的输出端G(3)、G(7)、G(11)等都会产生冗余的脉冲信号，最终导致整个GOA电路失效。
发明内容
本发明的目的在于提供一种GOA电路，在保留全局控制全部GOA单元的输出端同时输出功能的前提下，避免现有技术中以GOA单元输出的扫描驱动信号作为级传信号所导致的电路失效问题，消除GOA电路级传过程 中的冗余脉冲，保证GOA电路正常工作，提升液晶显示装置的工作稳定性。
本发明的目的还在于提供一种液晶显示装置，具有良好的工作稳定性。
为实现上述目的，本发明提供了一种GOA电路，包括级联的多级GOA单元，每一级GOA单元均包括：控制输入单元、稳压单元、输出单元、第二节点控制单元、第一节点下拉单元、下拉维持单元、全局控制单元、级传下拉单元、级传单元、及全局控制辅助单元；
设N为正整数，除第一级与第二级GOA单元外，在第N级GOA单元中：
所述控制输入单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于上两级第N-2级GOA单元的级传端，漏极电性连接于第三节点；
所述稳压单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一恒压电位，源极电性连接于第三节点，漏极电性连接于第一节点；
所述输出单元包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述第二节点控制单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第M+2条时钟信号，漏极电性连接于第二节点；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第一恒压电位，漏极电性连接于第二节点；
所述第一节点下拉单元包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于第七薄膜晶体管的漏极，漏极电性连接于第三节点；以及第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位；
所述下拉维持单元包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位，漏极电性连接于输出端；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于第二恒压电位；
所述全局控制单元包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于全局控制信号，源极电性连接于第二恒压电位，漏极电性连接于第二节点；以及第十二薄膜晶体管，所述第十二薄膜晶体管的栅 极与源极均电性连接于全局控制信号，漏极电性连接于输出端；
所述级传下拉单元包括：第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位，漏极电性连接于级传端；
所述级传单元包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于级传端；
所述全局控制辅助单元包括：第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于输出端，源极电性连接于第十四薄膜晶体管的漏极，漏极电性连接于级传端；以及第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于全局控制信号，源极电性连接于第二恒压电位。
可选的，各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管，所述第一恒压电位为恒压高电位，第二恒压电位为恒压低电位。
所述全局控制信号提供高电位时，所有GOA单元的输出端同时输出高电位，同时所有GOA单元的级传端同时输出低电位。
可选的，各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管，所述第一恒压电位为恒压低电位，第二恒压电位为恒压高电位。
所述全局控制信号提供低电位时，所有GOA单元的输出端同时输出低电位，同时所有GOA单元的级传端同时输出高电位。
在第一级GOA单元和第二级GOA单元中，所述第一薄膜晶体管T1的源极均电性连接于电路的起始信号STV。
所述GOA电路包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号；当所述第M条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号。
所述第一、第二、第三、及第四条时钟信号脉冲周期相同，所述第一条时钟信号的第一个脉冲信号首先产生，所述第一条时钟信号的第一个脉冲信号结束的同时所述第二条时钟信号的第一个脉冲信号产生，所述第二条时钟信号的第一个脉冲信号结束的同时所述第三条时钟信号的第一个脉冲信号产生，所述第三条时钟信号的第一个脉冲信号结束的同时所述第四条时钟信号的第一个脉冲信号产生，所述第四条时钟信号的第一个脉冲信号结束的同时所述第一条时钟信号的第二个脉冲信号产生。
本发明还提供一种液晶显示装置，包括上述GOA电路。
本发明的有益效果：本发明提供的一种GOA电路，通过增设级传单元 和级传下拉单元，并对全局控制辅助单元进行改进，采用级传单元的级传端输出的不同于扫描驱动信号的信号作为级传信号，采用全局控制辅助单元在全部GOA单元的输出端同时输出扫描驱动信号的期间稳定级传端的电位，使得级传端输出的信号与扫描驱动信号的电位相反，在完成全局控制全部GOA单元的输出端同时输出的功能后，能够避免现有技术中以GOA单元输出的扫描驱动信号作为级传信号所导致的电路失效问题，消除GOA电路级传过程中的冗余脉冲，保证GOA电路正常工作，提升液晶显示装置的工作稳定性。本发明的液晶显示装置包括上述GOA电路，具有良好的工作稳定性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种GOA电路的电路图；
图2为图1所示GOA电路的时序图；
图3为本发明的GOA电路的第一实施例的电路图；
图4为图3所示GOA电路的时序图；
图5为图3所示GOA电路的第一级GOA单元的电路图；
图6为图3所示GOA电路的第二级GOA单元的电路图；
图7为本发明的GOA电路的第二实施例的电路图；
图8为图7所示GOA电路的第一级GOA单元的电路图；
图9为图7所示GOA电路的第二级GOA单元的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3或图7，本发明首先提供一种GOA电路，包括级联的多级GOA单元，每一级GOA单元均包括：控制输入单元100、稳压单元200、输出单元300、第二节点控制单元400、第一节点下拉单元500、下拉维持单元600、全局控制单元700、级传下拉单元800、级传单元900、及全局控制辅助单元1000。
设N为正整数，除第一级与第二级GOA单元外，在第N级GOA单元 中：
所述控制输入单元100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于上两级第N-2级GOA单元的级传端ST(N-2)，漏极电性连接于第三节点K(N)；
所述稳压单元200包括：第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第一恒压电位，源极电性连接于第三节点K(N)，漏极电性连接于第一节点Q(N)；
所述输出单元300包括：第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于第一节点Q(N)，源极电性连接于第M条时钟信号CK(M)，漏极电性连接于输出端G(N)；以及第一电容C1，所述第一电容C1的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)；
所述第二节点控制单元400包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第三节点K(N)，源极电性连接于第M+2条时钟信号CK(M+2)，漏极电性连接于第二节点P(N)；以及第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于第一恒压电位，漏极电性连接于第二节点P(N)；
所述第一节点下拉单元500包括：第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第M条时钟信号CK(M)，源极电性连接于第七薄膜晶体管T7的漏极，漏极电性连接于第三节点K(N)；以及第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第二节点P(N)，源极电性连接于第二恒压电位；
所述下拉维持单元600包括：第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于第二节点P(N)，源极电性连接于第二恒压电位，漏极电性连接于输出端G(N)；以及第二电容C2，所述第二电容C2的一端电性连接于第二节点P(N)，另一端电性连接于第二恒压电位；
所述全局控制单元700包括：第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极电性连接于全局控制信号Gas，源极电性连接于第二恒压电位，漏极电性连接于第二节点P(N)；以及第十二薄膜晶体管T12，所述第十二薄膜晶体管T12的栅极与源极均电性连接于全局控制信号Gas，漏极电性连接于输出端G(N)；
所述级传下拉单元800包括：第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极电性连接于第二节点P(N)，源极电性连接于第二恒压电位，漏极电性连接于级传端ST(N)；
所述级传单元900包括：第九薄膜晶体管T9，所述第九薄膜晶体管T9 的栅极电性连接于第一节点Q(N)，源极电性连接于第M条时钟信号CK(M)，漏极电性连接于级传端ST(N)；
所述全局控制辅助单元1000包括：第十三薄膜晶体管T13，所述第十三薄膜晶体管T13的栅极电性连接于输出端G(N)，源极电性连接于第十四薄膜晶体管T14的漏极，漏极电性连接于级传端ST(N)；以及第十四薄膜晶体管T14，所述第十四薄膜晶体管T14的栅极电性连接于全局控制信号Gas，源极电性连接于第二恒压电位。
可选的，请参阅图3并结合图4，在本发明的第一实施例中：各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管；所述第一恒压电位为恒压高电位VGH，第二恒压电位为恒压低电位VGL；所述全局控制信号Gas提供高电位时，所有GOA单元的输出端同时输出高电位，同时所有GOA单元的级传端同时输出低电位。本发明的第一实施例包括四条提供高电位脉冲的时钟信号：第一、第二、第三、及第四条时钟信号CK(1)、CK(2)、CK(3)、CK(4)；当所述第M条时钟信号CK(M)为第三条时钟信号CK(3)时，第M+2条时钟信号CK(M+2)为第一条时钟信号CK(1)；当所述第M条时钟信号CK(M)为第四条时钟信号CK(4)时，第M+2条时钟信号CK(M+2)为第二条时钟信号CK(2)。所述第一、第二、第三、及第四条时钟信号CK(1)、CK(2)、CK(3)、CK(4)的脉冲周期相同，所述第一条时钟信号CK(1)的第一个脉冲信号首先产生，所述第一时钟信号CK(1)的第一个脉冲信号结束的同时所述第二条时钟信号CK(2)的第一个脉冲信号产生，所述第二条时钟信号CK(2)的第一个脉冲信号结束的同时所述第三条时钟信号CK(3)的第一个脉冲信号产生，所述第三条时钟信号CK(3)的第一个脉冲信号结束的同时所述第四条时钟信号CK(4)的第一个脉冲信号产生，所述第四条时钟信号CK(4)的第一个脉冲信号结束的同时所述第一条时钟信号CK(1)的第二个脉冲信号产生。
可选的，请参阅图7，在本发明的第二实施例中，各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管；所述第一恒压电位为恒压低电位VGL，第二恒压电位为恒压高电位VGH；所述全局控制信号Gas提供低电位时，所有GOA单元的输出端同时输出低电位，同时所有GOA单元的级传端同时输出高电位。本发明的第二实施例包括四条提供低电位脉冲信号的时钟信号：第一、第二、第三、及第四条时钟信号CK(1)、CK(2)、CK(3)、CK(4)；当所述第M条时钟信号CK(M)为第三条时钟信号CK(3)时，第M+2条时钟信号CK(M+2)为第一条时钟信号CK(1)；当所述第M条时钟信号CK(M)为第四条时钟信号CK(4)时，第M+2条时钟信号CK(M+2)为第二条时钟信 号CK(2)。所述第一、第二、第三、及第四条时钟信号CK(1)、CK(2)、CK(3)、CK(4)的脉冲周期相同，所述第一条时钟信号CK(1)的第一个脉冲信号首先产生，所述第一时钟信号CK(1)的第一个脉冲信号结束的同时所述第二条时钟信号CK(2)的第一个脉冲信号产生，所述第二条时钟信号CK(2)的第一个脉冲信号结束的同时所述第三条时钟信号CK(3)的第一个脉冲信号产生，所述第三条时钟信号CK(3)的第一个脉冲信号结束的同时所述第四条时钟信号CK(4)的第一个脉冲信号产生，所述第四条时钟信号CK(4)的第一个脉冲信号结束的同时所述第一条时钟信号CK(1)的第二个脉冲信号产生。
特别地，请参阅图5和图6、或图8和图9，在本发明的GOA电路的第一级GOA单元中，所述第一薄膜晶体管T1的源极电性连接于电路的起始信号STV，第一薄膜晶体管T1的栅极电性连接于第三条时钟信号CK(3)，第三薄膜晶体管T3的源极电性连接于第一条时钟信号CK(1)；第二级GOA单元中，所述第一薄膜晶体管T1的源极电性连接于电路的起始信号STV，第一薄膜晶体管T1的栅极电性连接于第四条时钟信号CK(4)，第三薄膜晶体管T3的源极电性连接于第二条时钟信号CK(2)。
具体地，请参阅图3并结合图4，本发明的GOA电路采用隔行扫描的方式进行扫描，第一级GOA单元产生的级传信号传递给第三级GOA单元，第二级GOA单元产生的级传信号传递给第四级GOA单元，第三级GOA单元产生的级传信号传递给第五级GOA单元，第四级GOA单元产生的级传信号传递给第六级GOA单元，依次类推。下面以本发明的第一实施例为例，说明本发明的GOA电路的工作过程：
首先，全局控制信号Gas提供高电位，所有GOA单元的第十一、第十二、及第十四薄膜晶体管T11、T12、T14均打开，所有GOA单元中的第十二薄膜晶体管T12使得输出端G(N)输出的扫描驱动信号为全局控制信号Gas提供的高电位，第十一薄膜晶体管T11下拉第二节点P(N)至恒压低电位VGL，同时，受输出端G(N)控制的第十三薄膜晶体T13打开，与第十四薄膜晶体T14共同作用下拉级传端ST(N)至恒压低电位VGL，各级GOA单元的级传端ST(N)输出的级传信号均为低电位；
随后，全局控制信号Gas提供低电位，所有GOA单元的输出端G(N)受第一电容C1的作用保持高电位，级传端ST(N)仍为低电位；
接下来，第一条时钟信号CK(1)提供高电位，第一级GOA单元的级传端ST(1)保持低电位，在第三级GOA单元中：第一薄膜晶体管T1和第八薄膜晶体管T8打开，第一节点Q(3)为低电位，第二节点P(3)充电至高电位，第五薄膜晶体管T5打开，第三薄膜晶体管T3关闭，输出端G(3)放电至恒 压低电位VGL；
然后，第三条时钟信号CK(3)和电路的起始信号STV提供高电位，在第一级GOA单元中：第一薄膜晶体管T1打开，第一级GOA单元的第一节点Q(1)充电至高电位，第八薄膜晶体管T8打开，第二节点P(1)充电至高电位，第五薄膜晶体管T5打开，拉低输出端G(1)至恒压低电位VGL；在第三级GOA单元中：第一节点Q(3)保持低电位，第三薄膜晶体管T3关闭，输出端G(3)保持低电位，不会产生冗余脉冲；
紧接着，第三条时钟信号CK(3)与电路的起始信号STV提供低电位，第一级GOA单元中的第一薄膜晶体管T1关闭，第四薄膜晶体管T4受第三节点K(1)(电位与第一节点Q(1)相同)控制打开，拉低第二节点P(1)为低电位；
再然后，第一条时钟信号CK(1)再次提供高电位，在第一级GOA单元中：第三、和第九薄膜晶体管T3、T9受第一节点Q(1)的控制打开，级传端ST(1)和输出端G(1)均输出第一条时钟信号CK(1)提供的高电位作为级传信号和扫描驱动信号的高电位，第一节点Q(1)受第一电容C1的作用抬升至更高电位；在第三级GOA单元中：第一薄膜晶体管T1打开，第一节点Q(3)保持充电至高电位，第二节点P(3)保持高电位，输出端G(3)保持低电位；
最后，第三条时钟信号CK(3)再次提供高电位，在第一级GOA单元中，第一和第八薄膜晶体管T8打开，第二节点P(1)被充电至高电位，第一节点Q(1)降低为低电位，受第二节点控制的第五和第十薄膜晶体管T5、T10打开，分别拉低输出端G(1)和级传端ST(1)的电位至恒压低电位VGL，作为扫描驱动信号和级传信号的低电位；在第三级GOA单元中，第三和第九薄膜晶体管T3、T9受第一节点Q(3)的控制打开，级传端ST(3)和输出端G(3)输出第三条时钟信号CK(3)提供的高电位作为级传信号和扫描驱动信号的高电位，第一节点Q(3)受第一电容C1的作用抬升至更高电位。
依次类推。
上述GOA电路在整个工作过程中不产生冗余脉冲，GOA电路正常进行扫描驱动，提升了液晶显示装置的工作稳定性。。
图7所示的第二实施例与上述第一实施例的具体工作过程类似，仅需要将各信号、节点的电位高低进行调换即可，此处不再赘述。
本发明还提供一种液晶显示装置，包括上述GOA电路，从而具有良好的工作稳定性。
综上所述，本发明的GOA电路，通过增设级传单元和级传下拉单元，并对全局控制辅助单元进行改进，采用级传单元的级传端输出的不同于扫 描驱动信号的信号作为级传信号，采用全局控制辅助单元在全部GOA单元的输出端同时输出扫描驱动信号的期间稳定级传端的电位，使得级传端输出的信号与扫描驱动信号的电位相反，在完成全局控制全部GOA单元的输出端同时输出的功能后，能够避免现有技术中以GOA单元输出的扫描驱动信号作为级传信号所导致的电路失效问题，消除GOA电路级传过程中的冗余脉冲，保证GOA电路正常工作，提升液晶显示装置的工作稳定性。本发明的液晶显示装置包括上述GOA电路，具有良好的工作稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (16)

  1. 一种GOA电路，包括级联的多级GOA单元，每一级GOA单元均包括：控制输入单元、稳压单元、输出单元、第二节点控制单元、第一节点下拉单元、下拉维持单元、全局控制单元、级传下拉单元、级传单元、及全局控制辅助单元；
    设N为正整数，除第一级与第二级GOA单元外，在第N级GOA单元中：
    所述控制输入单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于上两级第N-2级GOA单元的级传端，漏极电性连接于第三节点；
    所述稳压单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一恒压电位，源极电性连接于第三节点，漏极电性连接于第一节点；
    所述输出单元包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述第二节点控制单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第M+2条时钟信号，漏极电性连接于第二节点；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第一恒压电位，漏极电性连接于第二节点；
    所述第一节点下拉单元包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于第七薄膜晶体管的漏极，漏极电性连接于第三节点；以及第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位；
    所述下拉维持单元包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位，漏极电性连接于输出端；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于第二恒压电位；
    所述全局控制单元包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于全局控制信号，源极电性连接于第二恒压电位，漏极电 性连接于第二节点；以及第十二薄膜晶体管，所述第十二薄膜晶体管的栅极与源极均电性连接于全局控制信号，漏极电性连接于输出端；
    所述级传下拉单元包括：第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位，漏极电性连接于级传端；
    所述级传单元包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于级传端；
    所述全局控制辅助单元包括：第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于输出端，源极电性连接于第十四薄膜晶体管的漏极，漏极电性连接于级传端；以及第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于全局控制信号，源极电性连接于第二恒压电位。
  2. 如权利要求1所述的GOA电路，其中，各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管，所述第一恒压电位为恒压高电位，第二恒压电位为恒压低电位。
  3. 如权利要求2所述的GOA电路，其中，所述全局控制信号提供高电位时，所有GOA单元的输出端同时输出高电位，同时所有GOA单元的级传端同时输出低电位。
  4. 如权利要求1所述的GOA电路，其中，各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管，所述第一恒压电位为恒压低电位，第二恒压电位为恒压高电位。
  5. 如权利要求4所述的GOA电路，其中，所述全局控制信号提供低电位时，所有GOA单元的输出端同时输出低电位，同时所有GOA单元的级传端同时输出高电位。
  6. 如权利要求1所述的GOA电路，其中，在第一级GOA单元和第二级GOA单元中，所述第一薄膜晶体管的源极均电性连接于电路的起始信号。
  7. 如权利要求1所述的GOA电路，其中，包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号；当所述第M条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号。
  8. 如权利要求7所述的GOA电路，其中，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，所述第一条时钟信号的第一个脉冲信号首先产生，所述第一时钟信号的第一个脉冲信号结束的同时所述第二条 时钟信号的第一个脉冲信号产生，所述第二条时钟信号的第一个脉冲信号结束的同时所述第三条时钟信号的第一个脉冲信号产生，所述第三条时钟信号的第一个脉冲信号结束的同时所述第四条时钟信号的第一个脉冲信号产生，所述第四条时钟信号的第一个脉冲信号结束的同时所述第一条时钟信号的第二个脉冲信号产生。
  9. 一种液晶显示装置，包括GOA电路；所述GOA电路包括级联的多级GOA单元，每一级GOA单元均包括：控制输入单元、稳压单元、输出单元、第二节点控制单元、第一节点下拉单元、下拉维持单元、全局控制单元、级传下拉单元、级传单元、及全局控制辅助单元；
    设N为正整数，除第一级与第二级GOA单元外，在第N级GOA单元中：
    所述控制输入单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于上两级第N-2级GOA单元的级传端，漏极电性连接于第三节点；
    所述稳压单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一恒压电位，源极电性连接于第三节点，漏极电性连接于第一节点；
    所述输出单元包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述第二节点控制单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第M+2条时钟信号，漏极电性连接于第二节点；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第一恒压电位，漏极电性连接于第二节点；
    所述第一节点下拉单元包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于第七薄膜晶体管的漏极，漏极电性连接于第三节点；以及第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位；
    所述下拉维持单元包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位，漏极电性连接于输出端；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于第二恒压电位；
    所述全局控制单元包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于全局控制信号，源极电性连接于第二恒压电位，漏极电性连接于第二节点；以及第十二薄膜晶体管，所述第十二薄膜晶体管的栅极与源极均电性连接于全局控制信号，漏极电性连接于输出端；
    所述级传下拉单元包括：第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压电位，漏极电性连接于级传端；
    所述级传单元包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于级传端；
    所述全局控制辅助单元包括：第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于输出端，源极电性连接于第十四薄膜晶体管的漏极，漏极电性连接于级传端；以及第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于全局控制信号，源极电性连接于第二恒压电位。
  10. 如权利要求9所述的液晶显示装置，其中，各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管，所述第一恒压电位为恒压高电位，第二恒压电位为恒压低电位。
  11. 如权利要求10所述的液晶显示装置，其中，所述全局控制信号提供高电位时，所有GOA单元的输出端同时输出高电位，同时所有GOA单元的级传端同时输出低电位。
  12. 如权利要求9所述的液晶显示装置，其中，各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管，所述第一恒压电位为恒压低电位，第二恒压电位为恒压高电位。
  13. 如权利要求12所述的液晶显示装置，其中，所述全局控制信号提供低电位时，所有GOA单元的输出端同时输出低电位，同时所有GOA单元的级传端同时输出高电位。
  14. 如权利要求9所述的液晶显示装置，其中，在第一级GOA单元和第二级GOA单元中，所述第一薄膜晶体管的源极均电性连接于电路的起始信号。
  15. 如权利要求9所述的液晶显示装置，其中，包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号；当所述第M条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号。
  16. 如权利要求15所述的液晶显示装置，其中，所述第一、第二、第 三、及第四条时钟信号的脉冲周期相同，所述第一条时钟信号的第一个脉冲信号首先产生，所述第一时钟信号的第一个脉冲信号结束的同时所述第二条时钟信号的第一个脉冲信号产生，所述第二条时钟信号的第一个脉冲信号结束的同时所述第三条时钟信号的第一个脉冲信号产生，所述第三条时钟信号的第一个脉冲信号结束的同时所述第四条时钟信号的第一个脉冲信号产生，所述第四条时钟信号的第一个脉冲信号结束的同时所述第一条时钟信号的第二个脉冲信号产生。
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