WO2017101189A1 - 栅极驱动电路和使用栅极驱动电路的显示器 - Google Patents

栅极驱动电路和使用栅极驱动电路的显示器 Download PDF

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Publication number
WO2017101189A1
WO2017101189A1 PCT/CN2016/070810 CN2016070810W WO2017101189A1 WO 2017101189 A1 WO2017101189 A1 WO 2017101189A1 CN 2016070810 W CN2016070810 W CN 2016070810W WO 2017101189 A1 WO2017101189 A1 WO 2017101189A1
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Prior art keywords
electrically connected
clock signal
transistor
output
gate
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Ceased
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PCT/CN2016/070810
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English (en)
French (fr)
Inventor
李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/906,708 priority Critical patent/US9966029B2/en
Publication of WO2017101189A1 publication Critical patent/WO2017101189A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the invention relates to a display, in particular to a gate driver (Gate driver on Array, GOA) display of the circuit.
  • GOA Gate driver on Array
  • the GOA circuit uses a thin film transistor liquid crystal display Array process to fabricate a gate driver with a thin film transistor (Thin film).
  • a transistor, TFT thin film transistor array of glass substrates to achieve a progressive scan driving method.
  • the GOA circuit includes a plurality of GOA circuit units, each of which is composed of a plurality of transistors and a plurality of capacitors. Since the GOA circuit directly forms the side of the glass substrate, the smaller the number of transistors and capacitors per GOA circuit unit, the less the glass substrate area occupied by the GOA circuit. As such, a GOA circuit unit that uses fewer transistors and capacitors will facilitate a narrower edge display panel.
  • the technical solution of the present invention provides a gate driving circuit including a plurality of GOA circuit units. a plurality of the GOA circuit units are coupled in series, and each stage of the GOA circuit unit is configured to use a scan signal output by the GOA circuit unit of the previous stage, a scan signal output by the GOA circuit unit of the subsequent stage, a first clock signal, The second clock signal and the third clock signal output a scan signal at the output end.
  • Each level of the GOA circuit unit includes an input control module, an output control module, and a pull-down module. The input control module is configured to output a control signal at the control node according to the first clock signal and the third clock signal.
  • the output control module is electrically connected to the control node, and is configured to output the scan signal at the output end according to the control signal and the second clock signal.
  • the pull-down module is electrically connected to the output control module for pulling the scan signal to a low level.
  • the pull-down module includes a first transistor, a second transistor, a third transistor, and a resistor.
  • the gate of the first transistor is electrically connected to the control node, and the drain thereof is electrically connected to the pull-down driving node, and the source thereof is electrically connected to the first fixed voltage.
  • the gate of the second transistor is electrically connected to the pull-down driving node, the drain thereof is electrically connected to the output end, and the source thereof is electrically connected to the first fixed voltage.
  • the gate of the third transistor is electrically connected to the pull-down driving node, and the source thereof is electrically connected to the first fixed voltage. Both ends of the resistor are electrically connected to the second fixed voltage and the pull-down driving node, respectively.
  • the input control module comprises a fourth transistor and a fifth transistor.
  • the gate of the fourth transistor is electrically connected to the first clock signal, and the drain thereof is electrically connected to the scan signal output by the previous stage GOA circuit unit, and the source thereof is electrically connected to the control node.
  • the gate of the fifth transistor is electrically connected to the third clock signal, the drain thereof is electrically connected to the control node, and the source thereof is electrically connected to the scan signal output by the subsequent stage GOA circuit unit.
  • the output control module comprises a sixth transistor, a seventh transistor and a capacitor.
  • the gate of the sixth transistor is electrically connected to the second fixed voltage, the drain thereof is electrically connected to the control node, and the source thereof is electrically connected to the drain of the third transistor.
  • the gate of the seventh transistor is electrically connected to the source of the sixth transistor, the drain thereof is electrically connected to the second clock signal, and the source thereof is electrically connected to the output end. Both ends of the capacitor are respectively connected to a source and a gate of the seventh transistor.
  • the pulses of the first clock signal, the second clock signal and the third clock signal are sequentially output in turn, and do not overlap each other.
  • the first fixed voltage is a low level and the second fixed voltage is a high level.
  • the technical solution of the present invention also provides a display including a source driver and a gate driving circuit.
  • the source driver is configured to output a data signal to a plurality of pixel units to display gray scales
  • the gate driving circuit includes a plurality of GOA circuit units, and the plurality of the GOA circuit units are coupled in series.
  • Each level of the GOA circuit unit is used at the output end according to the scan signal output by the previous stage GOA circuit unit, the scan signal output by the subsequent stage GOA circuit unit, the first clock signal, the second clock signal, and the third clock signal.
  • the scan signal is output.
  • Each level of the GOA circuit unit includes an input control module, an output control module, and a pull-down module.
  • the input control module is configured to output a control signal at the control node according to the first clock signal and the third clock signal.
  • the output control module is electrically connected to the control node, and is configured to output the scan signal at the output end according to the control signal and the second clock signal.
  • the pull-down module is electrically connected to the output control module for pulling the scan signal to a low level.
  • the pull-down module includes a first transistor, a second transistor, a third transistor, and a resistor.
  • the gate of the first transistor is electrically connected to the control node, and the drain thereof is electrically connected to the pull-down driving node, and the source thereof is electrically connected to the first fixed voltage.
  • the gate of the second transistor is electrically connected to the pull-down driving node, the drain thereof is electrically connected to the output end, and the source thereof is electrically connected to the first fixed voltage.
  • the gate of the third transistor is electrically connected to the pull-down driving node, and the source thereof is electrically connected to the first fixed voltage. Both ends of the resistor are electrically connected to the second fixed voltage and the pull-down driving node, respectively.
  • the input control module comprises a fourth transistor and a fifth transistor.
  • the gate of the fourth transistor is electrically connected to the first clock signal, and the drain thereof is electrically connected to the scan signal output by the previous stage GOA circuit unit, and the source thereof is electrically connected to the control node.
  • the gate of the fifth transistor is electrically connected to the third clock signal, the drain thereof is electrically connected to the control node, and the source thereof is electrically connected to the scan signal output by the subsequent stage GOA circuit unit.
  • the output control module comprises a sixth transistor, a seventh transistor and a capacitor.
  • the gate of the sixth transistor is electrically connected to the second fixed voltage, the drain thereof is electrically connected to the control node, and the source thereof is electrically connected to the drain of the third transistor.
  • the gate of the seventh transistor is electrically connected to the source of the sixth transistor, the drain thereof is electrically connected to the second clock signal, and the source thereof is electrically connected to the output end. Both ends of the capacitor are respectively connected to a source and a gate of the seventh transistor.
  • the pulses of the first clock signal, the second clock signal and the third clock signal are sequentially output in turn, and do not overlap each other.
  • the first fixed voltage is a low level and the second fixed voltage is a high level.
  • each stage of the GOA circuit unit of the gate driving circuit of the present invention uses a small number of transistors and capacitors, and thus has the advantageous effect of facilitating the design of the narrow bezel display.
  • the pull-down module of the GOA circuit unit omits the capacitance, so that the power consumption caused by charging the capacitor can be reduced, which has the beneficial effect of reducing the power consumption of the overall GOA circuit.
  • FIG. 1 is a functional block diagram of a display of the present invention.
  • FIG. 2 is a circuit diagram of a GOA circuit unit of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2 in a forward scan.
  • FIG. 4 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2 in reverse scan.
  • FIG. 1 is a functional block diagram of a display 10 of the present invention.
  • Display 10 can be a liquid crystal display or an organic light emitting diode display.
  • the display 10 includes a glass substrate 14 and a source driver (source) Driver)16.
  • a plurality of pixels arranged in a matrix and a gate driving (GOA) circuit 12 are disposed on the glass substrate 14, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB).
  • RGB red, green and blue
  • the GOA circuit 12 outputs a scan signal such that the transistors 22 of each row are sequentially turned on, and the source driver 16 outputs corresponding data signals to an entire column of pixel units 20 to charge them to respective required voltages to display different gray scales. .
  • the GOA circuit 12 turns off the scan signal of the row, and then the GOA circuit 12 outputs the scan signal to turn on the transistor 22 of the next row, and then the source driver 16 charges the pixel unit 20 of the next row. Discharge. This is continued until all the pixel units 20 are fully charged, and charging starts from the first line.
  • the source driver 16 charges and discharges the pixel unit 20 to a desired voltage during the 21.7 ⁇ s period to display the corresponding gray scale.
  • FIG. 2 is a circuit diagram of a GOA circuit unit SR(n) according to the first embodiment of the present invention.
  • the GOA circuit 12 includes a plurality of cascade-connected GOA circuit units SR(n). Each stage of the GOA circuit unit SR(n) is used to output the scan signal G(n-1) outputted by the previous stage GOA circuit unit SR(n-1) and the subsequent stage GOA circuit unit SR(n+1).
  • the scan signal G(n+1), the first clock signal CKV1, the second clock signal CKV2, and the third clock signal CKV3 output a scan signal G(n) at the output terminal OUT.
  • Each level of the GOA circuit unit SR(n) includes an input control module 100, an output control module 200, and a pull down module 300.
  • the input control module 100 is configured to output a control signal Q(n) at the control node Q according to the first clock signal CKV1 and the third clock signal CKV3.
  • the output control module 200 is electrically connected to the control node Q for outputting the scan signal G(n) at the output terminal OUT according to the control signal Q(n) and the second clock signal CKV2.
  • the pull-down module 300 is electrically connected to the output control module 200 for pulling the scan signal G(n) to a low level.
  • the pull-down module 300 includes a first transistor T1, a second transistor T2, a third transistor T3, and a resistor R1.
  • the gate of the first transistor T1 is electrically connected to the control node Q, and the drain thereof is electrically connected to the pull-down driving node P, and the source thereof is electrically connected to the first fixed voltage VGL.
  • the gate of the second transistor T2 is electrically connected to the pull-down driving node P, the drain thereof is electrically connected to the output terminal OUT, and the source thereof is electrically connected to the first fixed voltage VGL.
  • the gate of the third transistor T3 is electrically connected to the pull-down driving node P, and the source thereof is electrically connected to the first fixed voltage VGL. Both ends of the resistor R1 are electrically connected to the second fixed voltage VGH and the pull-down drive node P, respectively.
  • the input control module 100 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is electrically connected to the first clock signal CKV1, and the drain thereof is electrically connected to the scan signal G(n-1) outputted by the previous stage GOA circuit unit SR(n-1), and its source is electrically Connect to control node Q.
  • the gate of the fifth transistor T5 is electrically connected to the third clock signal CKV3, and the drain thereof is electrically connected to the control node Q, and the source thereof is electrically connected to the scan signal G output by the first-stage GOA circuit unit SR(n+1) ( n+1).
  • the output control module 200 includes a sixth transistor T6, a seventh transistor T7, and a capacitor C1.
  • the gate of the sixth transistor T6 is electrically connected to the second fixed voltage VGH, and the drain thereof is electrically connected to the control node Q, and the source thereof is electrically connected to the drain of the third transistor T3.
  • the gate of the seventh transistor T7 is electrically connected to the source of the sixth transistor T6, the drain thereof is electrically connected to the second clock signal CKV2, and the source thereof is electrically connected to the output terminal OUT. Both ends of the capacitor C1 are respectively connected to the source and the gate of the seventh transistor T7.
  • each transistor is an N-type metal oxide.
  • Semiconductor, NMOS complementary metal oxide.
  • the pulses of the first clock signal CKV1, the second clock signal CKV2, and the third clock signal CKV3 are sequentially output in turn, and do not overlap each other.
  • the first fixed voltage VGL is at a low level
  • the second fixed voltage VGH is at a high level.
  • FIG. 3 is a timing diagram of various input signals, output signals and node voltages shown in FIG. 2 during forward scanning.
  • the first clock signal CKV1 and the scan signal G(n-1) are both at a high level, and at this time, the transistor T4 is turned on, so that the high-level scan signal G(n-1) is passed through Transistor T4 is transferred to control node Q, at which time control signal Q(n) is also at a high level. Since the second fixed voltage VGH is always at a high level, the transistor T6 will remain on at all times, at which time the transistor T6 conducts a high level control signal Q(n) to charge the capacitor C1.
  • the transistor T1 is also turned on by the high-level control signal Q(n), so that the first fixed voltage VGL of the low level is transmitted to the pull-down driving node P through the transistor T1, so the pull-down driving signal P(n) is low. Level.
  • the transistor T7 since the capacitor C1 maintains a charge factor, the transistor T7 turns on to turn on the high level second clock signal CKV2 to the output terminal OUT, so that the scan signal G(n) becomes a high level.
  • the third clock signal CKV3 and the scan signal G(n+1) are both at a high level, at which time the transistor T5 is turned on, so that the high level scan signal G(n+1) is transmitted to the control via the transistor T5.
  • the high level control signal Q(n) is transferred to the gate of the transistor T7 through the transistor T6, so that the transistor T7 turns on the low level second clock signal CKV2 to the output terminal OUT. At this time, the scanning signal G(n) becomes a low level.
  • the first clock signal CKV1 is at a high level and the scan signal G(n-1) is at a low level, at which time the transistor T4 is turned on.
  • the low level scan signal G(n-1) is transmitted to the control node Q via the transistor T4, causing the control signal Q(n) to go low.
  • the transistor T1 is turned off, and the pull-down drive signal P(n) becomes a high level due to the influence of the second fixed voltage VGH.
  • the transistors T2 and T3 conduct the first fixed voltage VGL of the low level, so the potential of the transistor T7 and the scanning signal G(n) are both low at this time. Therefore, it can be ensured that the control signal Q(n) and the scanning signal G(n) are stable low levels.
  • FIG. 4 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2 in reverse scan.
  • the difference between FIG. 4 and FIG. 3 is that the timings of the forward scan and the reverse scan are slightly different, but those skilled in the art can understand the timing difference between the two according to the architecture of the GOA circuit unit SR(n) disclosed in FIG. 2, This will not be repeated.
  • Each of the transistors in this embodiment is exemplified by an NMOS transistor.
  • those skilled in the art can replace all or part of the NMOS transistors with PMOS transistors in accordance with the circuit of the present invention to realize the same function of the GOA circuit unit. No longer.
  • the pull-down module 300 of each stage of the GOA circuit unit SR(n) of the gate drive circuit 12 of the present invention uses a smaller number of transistors and capacitors, thus having the benefit of facilitating the design of a narrow bezel display.
  • the pull-down module 300 of the GOA circuit unit SR(n) omits the capacitance, so that the power consumption caused by charging the capacitor can be reduced, which has the beneficial effect of reducing the power consumption of the overall GOA circuit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种栅极驱动电路(12)，其包含数个GOA电路单元(SR(n))。每一级GOA电路单元(SR(n))包含输入控制模块(100)、输出控制模块(200)和下拉模块(300)。下拉模块(300)包含第一晶体管(T1)、第二晶体管(T2)、第三晶体管(T3)和电阻(R1)。栅极驱动电路(12)的每一级GOA电路单元(SR(n))使用数量较少的晶体管和电容，因此具有便于窄边框显示器设计的有益效果。另外，GOA电路单元(SR(n))的下拉模块(300)省略电容，因此可以减少因对该电容充电而产生的功耗，具有减少整体GOA电路功耗的有益效果。

Description

栅极驱动电路和使用栅极驱动电路的显示器 技术领域
本发明是有关于一种显示器，尤指一种使用栅极驱动(Gate driver on array，GOA)电路的显示器。
 背景技术
GOA电路是利用薄膜晶体管液晶显示器Array制程将栅极驱动器制作在具有薄膜晶体管(Thin film transistor，TFT)阵列的玻璃基板上，以实现逐行扫描的驱动方式。
GOA电路包含数个GOA电路单元，每一GOA电路单元由数个晶体管和数个电容构成。由于GOA电路直接形成玻璃基板的侧边上，因此每一GOA电路单元的晶体管和电容的数量越少，GOA电路占用的玻璃基板面积就越少。如此一来，使用较少晶体管和电容的GOA电路单元将有利于窄边化的显示面板。
因此如何制造一种使用较少晶体管和电容的GOA电路单元的栅极驱动电路是业界努力的目标。
 技术问题
有鉴于此，本发明的目的是提供一种栅极驱动电路和使用栅极驱动电路的显示器，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种栅极驱动电路，其包含数个GOA电路单元。数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、以及第三时钟信号，在输出端输出扫描信号。每一级GOA电路单元包含输入控制模块、输出控制模块和下拉模块。所述输入控制模块用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号。所述输出控制模块电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号。所述下拉模块电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平。所述下拉模块包含第一晶体管、第二晶体管、第三晶体管和电阻。所述第一晶体管的栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压。所述第二晶体管的栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压。所述第三晶体管的栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压。所述电阻的两端分别电性连接第二固定电压和所述下拉驱动节点。
根据本发明的实施例，所述输入控制模块包含第四晶体管和第五晶体管。所述第四晶体管的栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号，其源极电性连接所述控制节点。所述第五晶体管的栅极电性连接所述第三时钟信号，其漏极电性连接所述控制节点，其源极电性连接所述后一级GOA电路单元输出的扫描信号。
根据本发明的实施例，所述输出控制模块包含第六晶体管、第七晶体管和电容。所述第六晶体管的栅极电性连接所述第二固定电压，其漏极电性连接所述控制节点，其源极电性连接所述第三晶体管的漏极。所述第七晶体管的栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端。所述电容的两端分别连接所述第七晶体管的源极和栅极。
根据本发明的实施例，所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的脉冲是依序轮流输出，且互不重叠。
根据本发明的实施例，所述第一固定电压为低电平，所述第二固定电压为高电平。
本发明的技术方案还提供一种显示器，其包含源极驱动器以及栅极驱动电路。所述源极驱动器用来输出数据信号至数个像素单元使其显示灰阶，所述栅极驱动电路包含数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接。每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、以及第三时钟信号，在输出端输出扫描信号。每一级GOA电路单元包含输入控制模块、输出控制模块和下拉模块。所述输入控制模块用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号。所述输出控制模块电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号。所述下拉模块电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平。所述下拉模块包含第一晶体管、第二晶体管、第三晶体管和电阻。所述第一晶体管的栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压。所述第二晶体管的栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压。所述第三晶体管的栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压。所述电阻的两端分别电性连接第二固定电压和所述下拉驱动节点。
根据本发明的实施例，所述输入控制模块包含第四晶体管和第五晶体管。所述第四晶体管的栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号，其源极电性连接所述控制节点。所述第五晶体管的栅极电性连接所述第三时钟信号，其漏极电性连接所述控制节点，其源极电性连接所述后一级GOA电路单元输出的扫描信号。
根据本发明的实施例，所述输出控制模块包含第六晶体管、第七晶体管和电容。所述第六晶体管的栅极电性连接所述第二固定电压，其漏极电性连接所述控制节点，其源极电性连接所述第三晶体管的漏极。所述第七晶体管的栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端。所述电容的两端分别连接所述第七晶体管的源极和栅极。
根据本发明的实施例，所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的脉冲是依序轮流输出，且互不重叠。
根据本发明的实施例，所述第一固定电压为低电平，所述第二固定电压为高电平。
 有益效果
相较于现有技术，本发明的栅极驱动电路的每一级GOA电路单元使用数量较少的晶体管和电容，因此具有便于窄边框显示器设计的有益效果。另外，GOA电路单元的下拉模块省略电容，因此可以减少因对该电容充电而产生的功耗，具有减少整体GOA电路功耗的有益效果。
 附图说明
图1是本发明的显示器的功能方块图。
图2是本发明一实施例的栅极驱动电路的GOA电路单元的电路图。
图3是图2所示各种输入信号、输出信号和节点电压在正向扫描时的时序图。
图4是图2所示各种输入信号、输出信号和节点电压在反向扫描时的时序图。
 本发明的最佳实施方式
请参阅图1，图1是本发明的显示器10的功能方块图。显示器10可以是液晶显示器或是有机发光二极管显示器。显示器10包含玻璃基板14以及源极驱动器(source driver)16。玻璃基板14上设置数个呈矩阵排列的像素(pixel)和栅极驱动(GOA)电路12，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。以一个1024 × 768分辨率的液晶显示器10来说，共需要1024 × 768 × 3个像素单元20组合而成。GOA电路12输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，GOA电路12便将该行的扫描信号关闭，然后GOA电路12再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到所有像素单元20都充电完成，再从第一行开始充电。
在目前的液晶显示面板设计中，GOA电路12即每隔一固定间隔输出扫描信号。以一个1024 × 768分辨率的液晶显示器10以及60Hz的更新频率为例，每一个画面的显示时间约为1/60=16.67ms。所以每一个扫描信号的脉冲为16.67ms/768=21.7μs。而源极驱动器16则在这21.7μs的时间内，将像素单元20充放电到所需的电压，以显示出相对应的灰阶。
请参阅图2，图2是本发明第一实施例的GOA电路单元SR(n)的电路图。GOA电路12包含数个串接(cascade-connected)的GOA电路单元SR(n)。每一级GOA电路单元SR(n)用来依据前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)、后一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)、第一时钟信号CKV1、第二时钟信号CKV2、第三时钟信号CKV3，在输出端OUT输出扫描信号G(n)。每一级GOA电路单元SR(n)包含输入控制模块100、输出控制模块200和下拉模块300。输入控制模块100用来依据第一时钟信号CKV1和第三时钟信号CKV3，在控制节点Q输出控制信号Q(n)。输出控制模块200电性连接于控制节点Q，用来依据控制信号Q(n)和第二时钟信号CKV2，在输出端OUT输出扫描信号G(n)。下拉模块300电性连接输出控制模块200，用来将扫描信号G(n)下拉至低电平。
下拉模块300包含第一晶体管T1、第二晶体管T2、第三晶体管T3和电阻R1。第一晶体管T1的栅极电性连接控制节点Q，其漏极电性连接下拉驱动节点P，其源极电性连接第一固定电压VGL。第二晶体管T2的栅极电性连接下拉驱动节点P，其漏极电性连接输出端OUT，其源极电性连接第一固定电压VGL。第三晶体管T3的栅极电性连接下拉驱动节点P，其源极电性连接第一固定电压VGL。电阻R1的两端分别电性连接第二固定电压VGH和下拉驱动节点P。
输入控制模块100包含第四晶体管T4和第五晶体管T5。第四晶体管T4的栅极电性连接第一时钟信号CKV1，其漏极电性连接前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)，其源极电性连接控制节点Q。第五晶体管T5的栅极电性连接第三时钟信号CKV3，其漏极电性连接控制节点Q，其源极电性连接后一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)。
输出控制模块200包含第六晶体管T6、第七晶体管T7和电容C1。第六晶体管T6的栅极电性连接第二固定电压VGH，其漏极电性连接控制节点Q，其源极电性连接第三晶体管T3的漏极。第七晶体管T7的栅极电性连接第六晶体管T6的源极，其漏极电性连接第二时钟信号CKV2，其源极电性连接输出端OUT。电容C1的两端分别连接第七晶体管T7的源极和栅极。
依据图2所示的实施例，每一晶体管皆为N型金氧半导体(N-type metal oxide semiconductor，NMOS)晶体管。第一时钟信号CKV1、第二时钟信号CKV2和第三时钟信号CKV3的脉冲是依序轮流输出，且互不重叠。第一固定电压VGL为低电平，第二固定电压VGH为高电平。
请一并参阅图2和图3，图3是图2所示各种输入信号、输出信号和节点电压在正向扫描时的时序图。在图3所示的t1期间，第一时钟信号CKV1和扫描信号G(n-1)皆为高电平，此时晶体管T4开启，使得高电平的扫描信号G(n-1)会经由晶体管T4传送至控制节点Q，此时控制信号Q(n)也是处于高电平。因为第二固定电压VGH一直处于高电平，所以晶体管T6会一直保持开启，此时晶体管T6导通高电平的控制信号Q(n)以对电容C1充电。同时，晶体管T1也会因为高电平的控制信号Q(n)而开启，使得低电平的第一固定电压VGL通过晶体管T1传送至下拉驱动节点P，所以下拉驱动信号P(n)处于低电平。在t2期间，因为电容C1保持电荷的因素，因此晶体管T7会开启以导通高电平的第二时钟信号CKV2至输出端OUT，使得扫描信号G(n)变为高电平。在t3期间，第三时钟信号CKV3和扫描信号G(n+1)皆为高电平，此时晶体管T5开启，使得高电平的扫描信号G(n+1)会经由晶体管T5传送至控制节点Q。高电平的控制信号Q(n)通过晶体管T6传送至晶体管T7的栅极，使得晶体管T7导通低电平的第二时钟信号CKV2至输出端OUT。此时扫描信号G(n)变为低电平。在t4期间，第一时钟信号CKV1为高电平而扫描信号G(n-1)为低电平，此时晶体管T4开启。低电平的扫描信号G(n-1)会经由晶体管T4传送至控制节点Q，导致控制信号Q(n)变为低电平。在t5期间，因为控制信号Q(n)处于低电平，因此晶体管T1断开，下拉驱动信号P(n)会因为第二固定电压VGH的影响而变为高电平。此时晶体管T2和T3导通低电平的第一固定电压VGL，因此晶体管T7的电位和扫描信号G(n)此时皆为低电平。所以可以保证控制信号Q(n)及扫描信号G(n)为稳定的低电平。
图4是图2所示各种输入信号、输出信号和节点电压在反向扫描时的时序图。图4与图3的差异在于正向扫描和反向扫描的时序稍有不同，但是本领域技术人员可依据图2所揭示的GOA电路单元SR(n)的架构了解两者的时序差异，在此不另赘述。
本实施例的每一晶体管是以NMOS晶体管为例做说明，但是本领域技术人员可以根据本发明的电路将其中全部或是部分NMOS晶体管以PMOS晶体管取代，以实现同样功能的GOA电路单元，以下不再赘述。
本发明的栅极驱动电路12的每一级GOA电路单元SR(n)的下拉模块300使用数量较少的晶体管和电容，因此具有便于窄边框显示器设计的有益效果。另外，GOA电路单元SR(n)的下拉模块300省略电容，因此可以减少因对该电容充电而产生的功耗，具有减少整体GOA电路功耗的有益效果。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号及第三时钟信号，在输出端输出扫描信号，其中每一级GOA电路单元包含：
    输入控制模块，用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号；
    输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；及
    下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平，其包含：
    第一晶体管，其栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压；
    第二晶体管，其栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压；
    第三晶体管，其栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压；及
    电阻，其两端分别电性连接第二固定电压和所述下拉驱动节点，其中所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的脉冲是依序轮流输出，且互不重叠，所述第一固定电压为低电平，所述第二固定电压为高电平。
  2. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号及第三时钟信号，在输出端输出扫描信号，其中每一级GOA电路单元包含：
    输入控制模块，用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号；
    输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；及
    下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平，其包含：
    第一晶体管，其栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压；
    第二晶体管，其栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压；
    第三晶体管，其栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压；及
    电阻，其两端分别电性连接第二固定电压和所述下拉驱动节点。
  3. 如权利要求2所述的栅极驱动电路，其中所述输入控制模块包含：
    第四晶体管，其栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号，其源极电性连接所述控制节点；
    第五晶体管，其栅极电性连接所述第三时钟信号，其漏极电性连接所述控制节点，其源极电性连接所述后一级GOA电路单元输出的扫描信号。
  4. 如权利要求3所述的栅极驱动电路，其中所述输出控制模块包含：
    第六晶体管，其栅极电性连接所述第二固定电压，其漏极电性连接所述控制节点，其源极电性连接所述第三晶体管的漏极；
    第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端；及
    电容，其两端分别连接所述第七晶体管的源极和栅极。
  5. 如权利要求2所述的栅极驱动电路，其中所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的脉冲是依序轮流输出，且互不重叠。
  6. 如权利要求2所述的栅极驱动电路，其中所述第一固定电压为低电平，所述第二固定电压为高电平。
  7. 一种显示器，其包含源极驱动器以及栅极驱动电路，所述源极驱动器用来输出数据信号至数个像素单元使其显示灰阶，所述栅极驱动电路包含：数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号及第三时钟信号，在输出端输出扫描信号，其中每一级GOA电路单元包含：
    输入控制模块，用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号；以及
    输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；
    下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平，其包含：
    第一晶体管，其栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压；
    第二晶体管，其栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压；
    第三晶体管，其栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压；及
    电阻，其两端分别电性连接第二固定电压和所述下拉驱动节点。
  8. 如权利要求7所述的显示器，其中所述输入控制模块包含：
    第四晶体管，其栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号，其源极电性连接所述控制节点；
    第五晶体管，其栅极电性连接所述第三时钟信号，其漏极电性连接所述控制节点，其源极电性连接所述后一级GOA电路单元输出的扫描信号。
  9. 如权利要求8所述的显示器，其中所述输出控制模块包含：
    第六晶体管，其栅极电性连接所述第二固定电压，其漏极电性连接所述控制节点，其源极电性连接所述第三晶体管的漏极；
    第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端；及
    电容，其两端分别连接所述第七晶体管的源极和栅极。
  10. 如权利要求7所述的显示器，其中所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的脉冲是依序轮流输出，且互不重叠。
  11. 如权利要求7所述的显示器，其中所述第一固定电压为低电平，所述第二固定电压为高电平。
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