WO2017096626A1 - 一种在石墨烯表面形成栅介质层及制备晶体管的方法 - Google Patents

一种在石墨烯表面形成栅介质层及制备晶体管的方法 Download PDF

Info

Publication number
WO2017096626A1
WO2017096626A1 PCT/CN2015/097200 CN2015097200W WO2017096626A1 WO 2017096626 A1 WO2017096626 A1 WO 2017096626A1 CN 2015097200 W CN2015097200 W CN 2015097200W WO 2017096626 A1 WO2017096626 A1 WO 2017096626A1
Authority
WO
WIPO (PCT)
Prior art keywords
graphene
gate dielectric
substrate
dielectric layer
water vapor
Prior art date
Application number
PCT/CN2015/097200
Other languages
English (en)
French (fr)
Inventor
梁晨
张臣雄
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2015/097200 priority Critical patent/WO2017096626A1/zh
Priority to CN201580085275.2A priority patent/CN108369910B/zh
Publication of WO2017096626A1 publication Critical patent/WO2017096626A1/zh

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Definitions

  • the present invention relates to the field of electronic components, and in particular, to a method of forming a gate dielectric layer on a graphene surface and preparing a field effect transistor (FET).
  • FET field effect transistor
  • Graphene is a two-dimensional thin film material formed by carbon atoms arranged in a regular hexagonal honeycomb lattice. Its unique electronic structure gives graphene many superior and peculiar electrical properties.
  • the mobility can theoretically reach 200,000 cm 2 V -1 s -1 , which is 140 times that of silicon material and the conductivity is up to 10 6 S/m. It is known as the next generation of electronic materials that can replace silicon.
  • Graphene is widely used in many electronic devices because of its excellent electrical properties. Among them, the most representative electronic device is a field effect transistor.
  • the gate dielectric layer is an important part of the FET structure, and its quality will have an important impact on the sub-threshold swing, frequency response, transconductance and other performance parameters of the FET.
  • a silicon oxide layer under the graphene is used as the bottom gate dielectric layer.
  • the currently proposed solution is a graphene FET using a top gate or a double gate structure.
  • a film layer having a high thickness of a certain thickness is deposited on the surface of the graphene as a top gate dielectric layer.
  • the method for forming the top gate dielectric layer is mainly an atomic layer deposition (ALD) method, in which a proper amount of water vapor is first introduced into the reactor, and then a suitable gate dielectric gas is passed through.
  • ALD atomic layer deposition
  • the water vapor on the surface of the graphene and the gate dielectric source gas can be deposited on the graphene surface after a certain period of time, and then an inert gas is used for cleaning, and then the above process is repeated, thereby forming a single layer.
  • a uniform, thickness-controllable film layer is repeatedly grown in a single layer.
  • the first method is to form a gate dielectric layer by using ALD after functionalizing the graphene.
  • the surface of the graphene is treated with a strong reactive gas such as ozone (O 3 ) or xenon difluoride (XeF 2 ) or plasma to cause defects in the graphene lattice, thereby enhancing the hydrophilicity of the graphene, and then A gate dielectric layer is formed on the surface of the graphene by ALD.
  • a strong reactive gas such as ozone (O 3 ) or xenon difluoride (XeF 2 ) or plasma to cause defects in the graphene lattice, thereby enhancing the hydrophilicity of the graphene
  • a gate dielectric layer is formed on the surface of the graphene by ALD.
  • the second method is to form a seed layer on the surface of the graphene and then form a gate dielectric layer by using ALD.
  • the exfoliated graphene is annealed to remove surface impurities, and then immersed in a perylene tetracarboxylic acid (PTCA) solution to add a layer of PTCA seed on the surface of the graphene or form a surface on the graphene.
  • PTCA perylene tetracarboxylic acid
  • a layer of amorphous carbon film seed layer Since the formed seed layer is hydrophilic, the ALD can be used to form the top gate dielectric layer after the seed layer is formed.
  • the introduction of the seed layer by the method increases the overall thickness of the top gate dielectric layer on the one hand, and it is difficult to achieve the requirements of the ultra-thin gate dielectric layer; on the other hand, the presence of the seed layer reduces the purity of the gate dielectric layer and increases the interface effect. The performance of the graphene FET is affected.
  • Embodiments of the present invention provide a method of forming a gate dielectric layer on a graphene surface and fabricating an FET, which can form a large-area uniform high-quality gate dielectric layer on the surface of the graphene.
  • a method of forming a gate dielectric layer on a surface of a graphene, the graphene being on a substrate comprising: adsorbing a hydrophilic volatile gas on a surface of the graphene; a substrate of graphene is placed in the ALD reaction chamber, and water vapor is introduced to adsorb the water vapor by the hydrophilic volatile gas adsorbed on the surface of the graphene; and the temperature of the ALD reaction chamber is raised to a predetermined temperature.
  • the embodiment of the present invention can change the surface of the graphene from hydrophobic to hydrophilic by utilizing the hydrophilic volatile gas on the surface of the graphene to adsorb water vapor, so that not only will not be destroyed.
  • the lattice structure of graphene, and the hydrophilic volatile gas can be volatilized at a high temperature, and does not remain on the surface of the graphene, thus ensuring that the formed gate dielectric has high purity and is easy to form an ultra-thin gate dielectric layer. Therefore, the method provided by the embodiments of the present invention can form a large-area uniform high-quality gate dielectric layer on the surface of the graphene.
  • the adsorbing the hydrophilic volatile gas on the surface of the graphene comprises: placing the substrate on which the graphene is formed in a hydrophilic volatile gas In the environment, the surface of the graphene is adsorbed by a hydrophilic volatile gas.
  • the substrate on which the graphene is formed is placed in an ALD reaction chamber, and water vapor is introduced to make the hydrophilicity adsorbed on the surface of the graphene
  • the volatile gas adsorbing the water vapor comprises: placing a substrate on which the graphene is formed in an ALD reaction chamber, maintaining a room temperature, and introducing water vapor to cause a hydrophilic volatile gas adsorbed on the surface of the graphene. The water vapor is adsorbed.
  • the hydrophilic volatile gas comprises one of ammonia gas, hydrogen chloride, nitrogen dioxide, and carbon dioxide.
  • the hydrophilic volatile gas is adsorbed on the surface of the graphene, and the hydrophilicity of the hydrophilic volatile gas is used to change the surface of the graphene from hydrophobic to hydrophilic, and the hydrophilic volatile gas is used at a high temperature.
  • the volatile nature of the film makes the surface of the graphene free of materials other than the gate dielectric, thereby forming a high quality gate dielectric layer on the surface of the graphene.
  • the gate dielectric layer has a relative dielectric constant ⁇ greater than 5.
  • the performance of the field effect transistor produced is superior.
  • the gate dielectric source gas comprises one of trimethylaluminum vapor and hafnium tetrachloride vapor.
  • the gate dielectric source gas is one of trimethylaluminum vapor or hafnium tetrachloride vapor.
  • trimethylaluminum vapor or hafnium tetrachloride vapor is a common steam, which is relatively easy to obtain.
  • the ⁇ value of the gate dielectric layer formed by the reaction of trimethylaluminum vapor or ruthenium tetrachloride vapor with water vapor is greater than 5.
  • the graphene is a single layer graphene, or a bilayer graphene, or a multilayer graphene.
  • a method for fabricating a field effect transistor comprising: sequentially forming a graphene, a top gate dielectric layer, a source electrode and a drain electrode, and a top gate electrode on a substrate, wherein the top gate dielectric layer can be The above method of forming a gate dielectric layer on the surface of graphene is formed.
  • the obtained field effect transistor since the surface of the graphene is formed to have a high quality of the gate dielectric layer, the obtained field effect transistor also has excellent performance.
  • the substrate is one of a silicon oxide substrate, a quartz substrate, a glass substrate, and a silicon nitride substrate.
  • the method further includes forming a bottom gate electrode on a side of the substrate remote from the graphene.
  • the substrate is a silicon oxide substrate.
  • the method before the forming the graphene, further comprises: sequentially forming a bottom gate electrode and a bottom on a side of the substrate close to the graphene a gate dielectric layer, the bottom gate dielectric layer being in contact with the graphene.
  • the substrate is a quartz substrate, a glass substrate or a silicon nitride substrate.
  • the field effect transistor of the double gate structure is formed. Since the top gate electrode and the bottom gate electrode can simultaneously modulate the electrical properties of the graphene material, the prepared double gate structure graphene FET has more excellent performance.
  • the substrate is a silicon oxide substrate
  • the silicon oxide substrate can serve as a carrier
  • the silicon oxide substrate can correspond to the bottom gate dielectric layer.
  • the forming the graphene on the substrate comprises: preparing the graphene by a chemical vapor deposition method; Transferring the graphene to PMMA; forming graphene with the PMMA on the substrate to dissolve the PMMA.
  • the graphene prepared by the chemical vapor deposition method is high in mass, large in area, and easy to transfer graphene to the substrate by using PMMA, it is preferable to prepare graphene by chemical vapor deposition in the present embodiment.
  • FIG. 1 is a schematic structural view of a substrate on which graphene is formed according to an embodiment of the present invention
  • FIG. 2 is a schematic flow chart of a method for forming a gate dielectric layer on a graphene surface according to an embodiment of the present invention
  • 3a is a schematic view showing the structure of adsorbing hydrophilic volatile gas on the surface of graphene according to an embodiment of the present invention
  • 3b is a schematic view showing the structure of adsorbing hydrophilic volatile gas and water vapor on the surface of graphene according to an embodiment of the invention
  • 3c is a schematic structural view of forming a single layer of a gate dielectric layer on a surface of a graphene according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of forming a gate dielectric layer on a graphene surface according to an embodiment of the present invention
  • FIG. 4 is a schematic flow chart of a method for forming a gate dielectric layer of aluminum oxide on a graphene surface according to an embodiment of the present invention
  • FIG. 5 is a schematic flow chart of a method for forming a gate dielectric layer of cerium oxide on a graphene surface according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional structural diagram of a FET of a top gate structure according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional structural diagram of a FET of a double gate structure according to an embodiment of the present invention.
  • FIG. 8 is a cross-sectional structural diagram of another FET having a double gate structure according to an embodiment of the present invention.
  • FIG. 9 is a schematic flow chart of a method for forming a source and a drain in a FET structure according to an embodiment of the present invention.
  • FIG. 10 is a schematic flow chart of a method for forming a top gate electrode in a FET structure according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method of forming a gate dielectric layer on a graphene surface, wherein, as shown in FIG. 1, graphene 20 is located on a substrate 10.
  • the graphene 20 since the graphene 20 must be located on the substrate 10 for carrying the load, a gate dielectric layer can be formed on the surface thereof. Therefore, in the embodiment of the present invention, the gate dielectric layer is formed on the surface of the graphene 20 by the graphene 20 It is premised on the substrate 10. Wherein, the graphene 20 may be a single layer of graphene, or a double layer graphene, or a multilayer graphene.
  • the substrate 10 is not limited in the embodiment of the present invention, and may be only a substrate for carrying, for example, a silicon oxide substrate, a quartz substrate, a glass substrate or a silicon nitride substrate. Any one. Of course, it may also be a substrate which has both a supporting effect and a specific structure, for example, including a specific film layer structure in addition to the carrier substrate.
  • the method includes the following steps:
  • the hydrophilic volatile gas 30 is not limited as long as the gas is both hydrophilic and volatile.
  • the gas may be a gas such as ammonia gas, hydrogen chloride, nitrogen dioxide, or carbon dioxide.
  • the method of adsorbing the hydrophilic volatile gas 30 on the surface of the graphene 20 is not limited. It is sufficient that a certain amount of the hydrophilic volatile gas 30 can be adsorbed on the surface of the graphene 20.
  • the substrate 10 on which the graphene 20 is formed is placed in an ALD reaction chamber, and water vapor is introduced thereto, as shown in FIG. 3b, so that the hydrophilic volatile gas 30 adsorbed on the surface of the graphene 20 adsorbs the water vapor 40.
  • the temperature of the ALD reaction chamber before the introduction of water vapor should be such that the hydrophilic volatile gas 30 is not easily volatilized, and it is not easy to condense after passing through the water vapor 40.
  • the gate dielectric source gas is not limited, as long as the gate dielectric layer formed by the reaction between the gate dielectric source gas and the water vapor has a high ⁇ value, and in the embodiment of the invention, the ⁇ value is preferably greater than 5.
  • the predetermined temperature is not limited, and the predetermined temperature should be appropriately set according to the temperature at which the water vapor and the gate medium source gas react. Suitable reaction temperatures for ALD are generally from 250 ° C to 400 ° C. If the predetermined temperature is low, the water vapor and the gate dielectric source gas may be sufficiently adsorbed and reacted on the surface of the graphene 20 due to the surface chemisorption reaction barrier; if the predetermined temperature is too high, the water vapor and the gate dielectric source gas are obtained. The reaction product is easily decomposed by high temperature or desorbed from the surface.
  • the temperature is too high or too low, the quality of a single layer 50 of the generated gate dielectric layer is affected, thereby affecting the quality of the gate dielectric layer, and therefore the temperature according to the reaction of the water vapor 30 and the gate dielectric source gas should be reasonably set.
  • the predetermined temperature since the temperature is too high or too low, the quality of a single layer 50 of the generated gate dielectric layer is affected, thereby affecting the quality of the gate dielectric layer, and therefore the temperature according to the reaction of the water vapor 30 and the gate dielectric source gas should be reasonably set.
  • the predetermined temperature since the temperature is too high or too low, the quality of a single layer 50 of the generated gate dielectric layer is affected, thereby affecting the quality of the gate dielectric layer, and therefore the temperature according to the reaction of the water vapor 30 and the gate dielectric source gas should be reasonably set. The predetermined temperature.
  • the temperature in the ALD reaction chamber can be maintained at the predetermined temperature.
  • the number of repetitions is not limited, and the number of repetitions may be set according to the thickness of the gate dielectric layer 60 to be formed. Since the thickness of one single layer 50 of the gate dielectric layer 60 is the thickness of one atomic layer, that is, about 0.1 nm, the gate dielectric layer 60 of about 0.1 nm can be formed by repeating once. For example, for the ultra-thin gate dielectric layer 60, the thickness is generally between 10 nm and 50 nm, so it is repeated 100-500 times.
  • the unreacted water vapor 40 and the gate dielectric source gas are preferred, specifically by removing the excess water vapor by introducing an inert gas into the ALD reaction chamber. 40 and gate dielectric source gas.
  • the inert gas may be, for example, nitrogen (N 2 ) or argon (Ar) or the like.
  • the surface of the graphene 20 can be made hydrophobic. Change to hydrophilic. Based on this, when the gate dielectric source gas is re-introduced, the water vapor 40 and the gate dielectric source gas react to form a single layer 50 of the gate dielectric layer on the surface of the graphene 20. Thereafter, water vapor 40 and a gate dielectric source gas are repeatedly introduced into the ALD reaction chamber to form other single layers of the gate dielectric layer until the desired thickness of the gate dielectric layer 60 is reached.
  • the embodiment of the present invention can make graphene 20 by adsorbing water vapor by using hydrophilic volatile gas 30 on the surface of graphene 20.
  • the surface is changed from hydrophobic to hydrophilic, so that not only does the lattice structure of the graphene 20 not be destroyed, but also the hydrophilic volatile gas 30 volatilizes at a high temperature and does not remain on the surface of the graphene 20, thereby ensuring
  • the formed gate dielectric layer 60 has high purity and is easy to form the ultra-thin gate dielectric layer 60. Therefore, the method provided by the embodiment of the present invention can form a large-area uniform high-quality gate dielectric layer 60 on the surface of the graphene 20.
  • step S101 can be specifically implemented by:
  • the substrate 10 on which the graphene 20 is formed is placed in an environment of the hydrophilic volatile gas 30, and the surface of the graphene 20 is adsorbed to the hydrophilic volatile gas 30.
  • the environment of the hydrophilic volatile gas 30 is preferably an environment of a high concentration of the hydrophilic volatile gas 30, and the high concentration means that the mass of the hydrophilic volatile gas accounts for 85% to 100% of the mass of the mixed gas in the entire environment.
  • the time during which the substrate 10 on which the graphene 20 is formed is placed in the environment of the hydrophilic volatile gas 30 is not limited, and it is ensured that the surface of the graphene 20 sufficiently adsorbs the hydrophilic volatile gas 30.
  • Step S102 can be specifically implemented in the following manner:
  • the substrate on which the graphene 20 is formed is placed in an ALD reaction chamber, kept at room temperature, and water vapor 40 is introduced to adsorb the water vapor 40 by the hydrophilic volatile gas 30 adsorbed on the surface of the graphene 20.
  • the substrate 10 on which the graphene 20 is formed is taken out and placed in the ALD counter. Should be in the cavity. Under the condition of room temperature, water vapor 40 is introduced, and the hydrophilic volatile gas 30 on the surface of the graphene 20 can adsorb a certain amount of water vapor 40.
  • the process of the embodiment of the present invention is simpler.
  • the gate dielectric source gas includes one of trimethylaluminum vapor and hafnium tetrachloride vapor. Based on this, trimethylaluminum vapor and water vapor react to form alumina with a K value of 7. The ruthenium tetrachloride vapor reacts with water vapor to form cerium oxide having a K value of 10.
  • Embodiment 1 A gate dielectric layer 60 for forming aluminum oxide on the surface of graphene 20, as shown in FIG. 4, specifically includes the following steps:
  • the graphene 20 is peeled off from the graphite by a micromechanical lift-off method, and the graphene is formed on a 300 nm silicon oxide substrate.
  • step S202 The substrate 10 in which the graphene 20 is formed in step S201 is placed in an 85% ammonia atmosphere to adsorb ammonia molecules.
  • the graphene 20 adsorbing ammonia gas in S202 is placed in an ALD reaction chamber, and water vapor 40 is introduced at room temperature to adsorb water molecules on the surface of the graphene 20.
  • Embodiment 2 A gate dielectric layer 60 for forming a cerium oxide on the surface of the graphene 20, as shown in FIG. 5, specifically includes the following steps:
  • step S302 The substrate 10 in which the graphene 20 is formed in step S301 is placed in a 90% hydrogen chloride environment to adsorb hydrogen chloride molecules.
  • the graphene 20 adsorbing hydrogen chloride in step 302 is placed in an ALD reaction chamber, and water vapor 40 is introduced at room temperature to adsorb water molecules on the surface of the graphene 20.
  • Embodiments of the present invention also provide a method of fabricating an FET as shown in FIGS. 6-8, which includes sequentially forming graphene 20, a top gate dielectric layer 70, a source electrode 801, and a drain electrode 802 on a substrate 10. And a top gate electrode 90.
  • the top gate dielectric layer 70 can be formed by the method of forming the gate dielectric layer 60 on the surface of the graphene 20 as described above.
  • the structure of the FET is not limited.
  • the FET of the top gate structure as shown in FIG. 6 or the FET of the double gate structure as shown in FIGS. 7-8 may be used.
  • the source electrode 801 and the drain electrode 802 are formed on the graphene. As shown in FIG. 9, the method includes the following steps:
  • the top gate dielectric layer 70 corresponding to the source electrode 801 region and the drain electrode 802 region is etched by an electron beam lithography process.
  • step S402. On the basis of step S401, a photoresist is formed on the top gate dielectric layer 70.
  • step S402 the metal layer is precipitated by electron beam evaporation or sputtering.
  • step S404 the sample obtained in step S403 is placed in an acetone solution to peel off the photoresist and the metal layer thereon, and form a source electrode 801 and a drain electrode which are spaced apart on the surface of the graphene 20. 802.
  • the material of the source electrode 801 and the drain electrode 802 is Ti (titanium), Al (aluminum), Cr (chromium), Au (gold), Pt (platinum), TiN (titanium nitride) or TaN (tantalum nitride). A combination of one or more of the materials. In order to simplify the preparation process of the graphene FET, it is preferable that the source electrode 801 and the drain electrode 802 have the same material, both of which are Ti/Au.
  • a top gate electrode 90 is formed on the top gate dielectric layer 70, as shown in FIG. 10, specifically including the following steps:
  • step S502 On the basis of step S501, a photoresist is formed on a region of the top gate dielectric layer 70 except the top gate electrode 90.
  • step S503 on the basis of step S502, depositing a metal layer by electron beam evaporation or sputtering.
  • step S504 the sample obtained in step S503 is placed in an acetone solution to peel off the photoresist and the metal layer thereon, and a top gate electrode 90 is formed on the top gate dielectric layer 70 between the source electrode 801 and the drain electrode 802.
  • the material constituting the top gate electrode 90 is one or a combination of materials of Ti, Al, Cr, Au, Pt, TiN or TaN.
  • the material of the top gate electrode 90 is Ti/Au.
  • the substrate 10 may be one of a silicon oxide substrate, a quartz substrate, a glass substrate, and a silicon oxide substrate. This is because these substrates are relatively easy to obtain and cost less.
  • the method further includes forming a bottom gate electrode 100 as shown in FIG. 7 on the side of the substrate 10 away from the graphene 20.
  • the substrate 10 is a silicon oxide substrate. At this time, the substrate 10 may correspond to a bottom gate dielectric layer.
  • the method further includes: sequentially forming a bottom gate electrode 100 and a bottom gate dielectric layer 110 on a side of the substrate 10 adjacent to the graphene 20, The bottom gate dielectric layer 110 is in contact with the graphene 20.
  • the substrate 10 is a quartz substrate, a glass substrate or a silicon nitride substrate.
  • the material of the bottom gate dielectric layer 110 may be silicon oxide.
  • the material thereof may be the same as that of the top gate electrode 90.
  • the prepared double gate structure graphene FET has more excellent breaking.
  • the performance, higher carrier mobility, and smaller gate leakage current make the performance of the prepared graphene FET more excellent.
  • a method of forming graphene on a substrate includes: preparing graphene by chemical vapor deposition; transferring graphene to polymethyl methacrylate PMMA; and forming graphene with PMMA on substrate 10. On top, dissolve the PMMA.
  • graphene 20 can also be formed on substrate 10 by micromechanical lift-off and epitaxial growth.
  • the process of forming graphene on the substrate 10 by the micro-mechanical stripping method is specifically: first removing a layer of graphite from the highly oriented pyrolytic graphite (HOPG) with a tape, and repeatedly pasting between the tapes, the graphite sheet layer Will be thinner and thinner.
  • HOPG highly oriented pyrolytic graphite
  • a single layer of graphene, a double layer of graphene or a plurality of layers of graphene is formed during the repeated pasting process, and then the tape is attached to the substrate 10, and the tape is peeled off so that some graphene is released from the tape on the substrate 10.
  • a single layer of graphene, a double layer graphene or a multilayer graphene can be formed on the substrate 10.
  • the process for preparing graphene by epitaxial growth is specifically: first, the surface of the silicon nitride substrate is etched or H 2 etched, and then the silicon nitride substrate is under a high vacuum (1.32 ⁇ 10 -8 Pa). It is heated to 1000 ° C by electron bombardment to remove oxides, and the surface oxide is removed by Auger electron spectroscopy. After the oxide is completely removed, the silicon nitride substrate is heated to 1250 ° C ⁇ 1450 ° C, which can be used in nitrogen. The surface of the silicon substrate forms graphene 20. The thickness of the formed graphene 20 is determined by the heating temperature.
  • the process for preparing graphene by chemical vapor deposition is specifically: using a carbonaceous compound such as methane as a carbon source, and pyrolyzing a carbon source on a metal substrate having a carbonaceous amount such as nickel or copper, and the temperature is generally 800 to 1200 ° C.
  • Graphene 20 is then formed on the surface of the metal substrate by forced cooling.
  • the formed graphene 20 can be transferred to the substrate 10 by the method of PMMA, specifically: first coating a water-soluble layer on the other substrate 10, and then coating the water-soluble layer.
  • PMMA Polymethyl methacrylate, polymethyl methacrylate
  • the graphene-grown metal matrix is placed in an etching solution (FeCl3 solution or acid solution) to corrode the metal matrix.
  • the graphene sheet floats on the liquid surface, and the graphene sheet is transferred onto the PMMA; the whole is placed in the deionized water solution, and after the water-soluble layer is dissolved, the substrate sinks into the bottom of the water, and PMMA and The graphene sheets thereon will float on the water surface to obtain a graphene sheet with PMMA on one side.
  • the graphene sheets are then transferred to a substrate 10 which is fixed to a robot of an optical microscope.
  • the PMMA face of the graphene sheet is then aligned and bonded to the substrate with the aid of an optical microscope.
  • the substrate 10 needs to be heated to 110 ° C in order to remove excess moisture adsorbed on the graphene 20 or the substrate 10 and promote the bonding of the PMMA to the substrate 10. After the transfer is completed, it is placed in an acid to dissolve the PMMA on the graphene sheet, so that the graphene 20 is formed on the substrate 10.
  • Single layer graphene, double layer graphene and multilayer graphene can be formed by the above three methods.
  • the graphene prepared by the chemical vapor deposition method is high in mass, large in area, and easy to transfer graphene to the substrate by using PMMA, it is preferable to prepare graphene by chemical vapor deposition in the present embodiment.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供了一种在石墨烯表面形成栅介质层及制备FET的方法，涉及电子元器件技术领域，可在石墨烯表面形成大面积均匀高质量的栅介质层。该方法包括：使石墨烯的表面吸附亲水易挥发气体；将形成有石墨烯的衬底置于ALD反应腔中，通入水蒸气，以使吸附在石墨烯表面的亲水易挥发气体吸附所述水蒸气；将ALD反应腔的温度升到预定温度，通入栅介质源气体，使所述水蒸汽和栅介质源气体发生反应，生成栅介质层的一个单层，并使所述亲水易挥发气体挥发；重复在所述ALD反应腔中通入水蒸气以及栅介质源气体，以形成所述栅介质层的其他单层，形成所述栅介质层。用于制备FET。

Description

一种在石墨烯表面形成栅介质层及制备晶体管的方法 技术领域
本发明涉及电子元器件技术领域，尤其涉及一种在石墨烯表面形成栅介质层及制备场效应晶体管(Field Effect Transistors，简称FET)的方法。
背景技术
石墨烯是由碳原子排列成正六边形蜂窝状点阵所形成的二维薄膜材料，其独特的电子结构赋予了石墨烯众多优越和奇特的电学特性。当片状石墨烯载流子浓度为n＝1012cm-3时，迁移率理论上可达到200000cm2V-1s-1，是硅材料的140倍，电导率可达106S/m，被誉为可以取代硅的下一代电子材料。
由于石墨烯具有优异的电学特性，因而被广泛应用于众多电子器件中。其中，最具有代表性的电子器件是场效应晶体管。
其中，栅介质层是FET结构中的重要组成部分，其质量会对FET的亚阈值摆幅、频率响应、跨导等多种性能参数产生重要的影响。传统背栅结构的石墨烯FET中，使用石墨烯下面的氧化硅层作为底栅介质层。这种结构的石墨烯FET制备工艺简单，然而由于氧化硅层的相对介电常数κ不高(κ＝3.9)，厚度也较大(通常为300nm左右)，因此会影响FET的栅压调制性能。
为了解决上述问题，目前提出的解决方案是采用顶栅或双栅结构的石墨烯FET。具体是在石墨烯表面沉积一定厚度的高κ值的薄膜层作为顶栅介质层。而目前形成该顶栅介质层的方法主要是采用原子层沉积(Atomic Layer Deposition，简称ALD)法，其过程为先将适量的水蒸汽通入反应器中，再将适当的栅介质源气体通入反应器，石墨烯表面的水蒸汽和栅介质源气体在一定的时间内反应后可在石墨烯表面沉积一层薄膜，随后再通入惰性气体进行清洗，之后重复上述过程，从而一个单层、一个单层地重复生长出均匀、厚度可控的薄膜层。
然而，使用普通的水基ALD方法在石墨烯表面生长顶栅介质层存在以下问题：由于石墨烯表面疏水，水分子很难在石墨烯表面吸附，从 而导致生长的栅介质难以成膜或成膜致密性不好而导致无法绝缘。
现有技术中，在石墨烯表面获得大面积均匀的顶栅介质层的方法主要有两种：
第一种方法是:对石墨烯进行功能化处理后再利用ALD形成栅介质层。具体是利用臭氧(O3)、二氟化氙(XeF2)等强反应性气体或等离子体对石墨烯表面进行处理，使石墨烯晶格出现缺陷，从而增强石墨烯的亲水性，之后再利用ALD在石墨烯表面形成栅介质层。该方法虽然可以在石墨烯表面获得大面积均匀的栅介质层，然而却破坏了石墨烯的晶格结构，从而影响了制备的石墨烯FET的性能。
第二种方法是：先在石墨烯表面形成种子层，再利用ALD形成栅介质层。具体是对剥离的石墨烯进行退火去除表面杂质后将其浸入到苝四羧酸(Perylene tetracarboxylic acid，简称PTCA)溶液，以在石墨烯表面加上一层PTCA种子层，或者在石墨烯表面形成一层无定型碳薄膜种子层。由于形成的种子层具有亲水性，因此形成种子层后便可以利用ALD形成顶栅介质层。然而，该方法引入种子层，一方面会使顶栅介质层整体厚度增加，难以达到超薄栅介质层的要求；另一方面种子层的存在降低了栅介质层的纯度，增加了界面效应，使得石墨烯FET的性能受到影响。
发明内容
本发明的实施例提供一种在石墨烯表面形成栅介质层及制备FET的方法，可在石墨烯表面形成大面积均匀高质量的栅介质层。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种在石墨烯表面形成栅介质层的方法，所述石墨烯位于衬底上，所述方法包括：使所述石墨烯的表面吸附亲水易挥发气体；将形成有所述石墨烯的衬底置于ALD反应腔中，通入水蒸气，以使吸附在所述石墨烯表面的亲水易挥发气体吸附所述水蒸气；将所述ALD反应腔的温度升到预定温度，通入栅介质源气体，使所述水蒸汽和所述栅介质源气体发生反应，生成栅介质层的一个单层，并使所述亲水易挥发气体挥发；重复在所述ALD反应腔中通入水蒸气以及栅介质源气体，以形成所述栅介质层的其他单层，形成所述栅介质层。
本发明实施例提供的技术方案与现有技术中对石墨烯表面进行功能 化处理后或引入种子层相比，本发明实施例通过利用在石墨烯表面的亲水易挥发气体吸附水蒸气，可以使石墨烯的表面由疏水性转变为亲水性，这样不仅不会破坏石墨烯的晶格结构，而且亲水易挥发气体在高温时即可挥发，并不会残留在石墨烯的表面，因此确保了形成的栅介质具有高的纯度且易形成超薄栅介质层。因此，本发明实施例提供的方法，可在石墨烯表面形成大面积均匀高质量的栅介质层。
结合第一方面，在第一种可能的实现方式中，所述使所述石墨烯的表面吸附亲水易挥发气体，包括：将形成有所述石墨烯的衬底置于亲水易挥发气体的环境中，使所述石墨烯的表面吸附亲水易挥发气体。
结合第一方面，在第二种可能的实现方式中，所述将形成有所述石墨烯的衬底置于ALD反应腔中，通入水蒸气，以使吸附在所述石墨烯表面的亲水易挥发气体吸附所述水蒸气，包括：将形成有所述石墨烯的衬底置于ALD反应腔中，保持室温，通入水蒸气，以使吸附在所述石墨烯表面的亲水易挥发气体吸附所述水蒸气。
结合第一方面，在第三种可能的实现方式中，所述亲水易挥发气体包括氨气、氯化氢、二氧化氮以及二氧化碳中的一种。
本发明实施例中在石墨烯表面吸附亲水易挥发气体，利用亲水易挥发气体的亲水性特征使石墨烯表面由疏水性转变为亲水性，又利用亲水易挥发气体的在高温时易挥发的特征，使得石墨烯表面不残留除栅介质以外的其它材料，从而在石墨烯表面形成高质量的栅介质层。
结合第一方面，在第四种可能的实现方式中，所述栅介质层的相对介电常数κ大于5。
本发明实施例中选用κ值大于5的栅介质层时，生产的场效应晶体管的性能较为优异。
结合第一方面的第四种可能的实现方式，在第五种可能的实现方式中，所述栅介质源气体包括三甲基铝蒸汽和四氯化铪蒸汽中的一种。
本发明实施例中栅介质源气体选用三甲基铝蒸汽或四氯化铪蒸汽中的一种，一方面，三甲基铝蒸汽或四氯化铪蒸汽都是常见的蒸汽，比较容易获得，另一方面，三甲基铝蒸汽或四氯化铪蒸汽与水蒸气反应生成的栅介质层的κ值均大于5。
结合第一方面或第一方面的任意一种可能的实现方式，在第六种可能的实现方式中，所述石墨烯为单层石墨烯，或双层石墨烯，或多层石墨烯。
第二方面，提供了一种制备场效应晶体管的方法，包括在衬底上依次形成石墨烯、顶栅介质层、源电极和漏电极以及顶栅电极，其中，所述顶栅介质层可以采用上述在石墨烯表面形成栅介质层的方法形成。
本发明实施例提供的制备场效应晶体管的方法中，由于石墨烯表面形成栅介质层具有高的质量，因此得到的场效应晶体管也具有优异的性能。
结合第二方面，在第一种可能的实现方式中，所述衬底为氧化硅衬底、石英衬底、玻璃衬底以及氮化硅衬底中的一种。
结合第二方面，在第二种可能的实现方式中，所述方法还包括：在所述衬底远离所述石墨烯的一侧形成底栅电极。其中，所述衬底为氧化硅衬底。
结合第二方面，在第三种可能的实现方式中，在形成所述石墨烯之前，所述方法还包括：在所述衬底的靠近所述石墨烯的一侧依次形成底栅电极和底栅介质层，所述底栅介质层与所述石墨烯接触。其中，所述衬底为石英衬底、玻璃衬底或氮化硅衬底。
本发明实施例中，形成双栅结构的场效应晶体管，由于顶栅电极和底栅电极可以同时调制石墨烯材料的电学性能，使制备的双栅结构的石墨烯FET具有更加优异性能。其中，当衬底是氧化硅衬底时，一方面，氧化硅衬底可以起承载作用，另一方面，氧化硅衬底可以相当于底栅介质层。
结合第二方面或第二方面的任意一种可能的实现方式，在第四种可能的实现方式中，所述在衬底上形成石墨烯，包括：通过化学气相沉积法制备所述石墨烯；将所述石墨烯转移到PMMA上；将带有所述PMMA的石墨烯形成在所述衬底上，溶解所述PMMA。
由于化学气相沉积法制备的石墨烯质量高、面积大，且便于利用PMMA将石墨烯转移到衬底上，因而本实施例中优选的利用化学气相沉积法制备石墨烯。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种形成有石墨烯的衬底的结构示意图；
图2为本发明实施例提供的一种在石墨烯表面形成栅介质层的方法流程示意图；
图3a为本发明实施例提供一种在石墨烯表面吸附亲水易挥发气体的结构示意图；
图3b为本发明实施例提供一种在石墨烯表面吸附亲水易挥发气体及水蒸气的结构示意图；
图3c为本发明实施例提供一种在石墨烯表面形成栅介质层一个单层的结构示意图；
图3d为本发明实施例提供一种在石墨烯表面形成栅介质层的结构示意图；
图4为本发明实施例提供的一种在石墨烯表面形成氧化铝的栅介质层的方法流程示意图；
图5为本发明实施例提供的一种在石墨烯表面形成二氧化铪的栅介质层的方法流程示意图；
图6为本发明实施例提供的一种顶栅结构的FET的剖面结构示意图；
图7为本发明实施例提供的一种双栅结构的FET的剖面结构示意图；
图8为本发明实施例提供的另一种双栅结构的FET的剖面结构示意图；
图9为本发明实施例提供的一种在FET结构中形成源极和漏极的方法流程示意图；
图10为本发明实施例提供的一种在FET结构中形成顶栅电极的方法流程示意图。
附图标记：
10-衬底；20-石墨烯；30-亲水易挥发气体；40-水蒸气；50-栅介质层的一个单层；60-栅介质层；70-顶栅介质层；801-源电极；802-漏电极；90-顶栅电极；100-低栅电极；110-低栅介质层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种在石墨烯表面形成栅介质层的方法，其中，如图1所示，石墨烯20位于衬底10上。
此处，由于石墨烯20必须位于起承载作用的衬底10上，才能在其表面形成栅介质层，因此，本发明实施例中，在石墨烯20表面形成栅介质层是以石墨烯20已经形成在衬底10上为前提的。其中，所述石墨烯20可以是单层石墨烯，或双层石墨烯，或多层石墨烯。
需要说明的是，本发明实施例不对衬底10进行限定，其可以仅仅是起承载作用的衬底，例如可以是氧化硅衬底、石英衬底、玻璃衬底或氮化硅衬底中的任一种。当然，也可以是既起承载作用，又具有特定结构的衬底，例如除包括承载基板外，还包括特定的膜层结构。
基于此，如图2所示，该方法包括如下步骤：
S101、如图3a所示，使石墨烯20的表面吸附亲水易挥发气体30。
其中，不对亲水易挥发气体30进行限定，只要该气体既亲水又易挥发即可。例如，可以是氨气、氯化氢、二氧化氮、二氧化碳等气体。在此基础上，不对石墨烯20的表面吸附亲水易挥发气体30的方法进行限 定，只要能在石墨烯20的表面吸附一定量的亲水易挥发气体30即可。
S102、将形成有石墨烯20的衬底10置于ALD反应腔中，通入水蒸气，如图3b所示，以使吸附在石墨烯20表面的亲水易挥发气体30吸附水蒸气40。
在本步骤中，对于通入水蒸气之前的ALD反应腔，其温度应保证亲水易挥发气体30不易挥发，且通入水蒸气40后不易冷凝为宜。
S103、将ALD反应腔的温度升到预定温度，通入栅介质源气体，使水蒸汽和栅介质源气体发生反应，如图3c所示，生成栅介质层的一个单层50，并使所述亲水易挥发气体挥发。
其中，不对栅介质源气体进行限定，只要该栅介质源气体和水蒸气发生反应生成的栅介质层具有高的κ值即可，本发明实施例中，κ值优选大于5。
在此基础上，不对预定温度进行限定，该预定温度应根据水蒸气和栅介质源气体发生反应的温度进行合理的设定。ALD的适宜反应温度一般为250℃～400℃。若预定温度较低，则水蒸气和栅介质源气体可能因表面化学吸附反应势垒作用而难以在石墨烯20表面充分吸附和反应；若预定温度过高，则水蒸气和栅介质源气体得到的反应产物易高温分解或从表面脱附。基于此，由于温度过高或过低都会影响生成的栅介质层的一个单层50的质量，从而影响栅介质层的质量，因此应根据水蒸气30和栅介质源气体发生反应的温度设置合理的预定温度。
S104、重复在ALD反应腔通入水蒸气40以及栅介质源气体，如图3d所示，以形成栅介质层的其他单层50，从而形成所述栅介质层60。
在本步骤中，在形成栅介质层的其他单层50时，可使ALD反应腔中的温度保持上述预定温度即可。
其中，不对重复的次数进行限定，具体可根据需要形成的栅介质层60的厚度来设置重复的次数。由于栅介质层60的一个单层50的厚度为一个原子层的厚度，即为0.1nm左右，因此重复一次即可形成0.1nm左右的栅介质层60。例如，对于超薄栅介质层60，其厚度一般在10nm-50nm之间，因此需重复100-500次。
基于上述，在每生成栅介质层的一个单层50后，优选排除未发生反应的水蒸汽40和栅介质源气体，具体可以是通过在ALD反应腔中通入惰性气体来清除多余的水蒸汽40和栅介质源气体。此处，惰性气体例如可以是氮气(N2)或氩气(Ar)等。
本发明实施例通过使亲水易挥发气体30吸附在石墨烯20表面，当通入水蒸气40时，由于亲水易挥发气体30可以吸附水蒸气40，因此可以使石墨烯20的表面由疏水性转变为亲水性。基于此，当再通入栅介质源气体时，水蒸气40和栅介质源气体反应便可在石墨烯20表面形成栅介质层的一个单层50。之后，重复在ALD反应腔通入水蒸气40以及栅介质源气体，以形成栅介质层的其他单层，直到达到栅介质层60所需的厚度。与现有技术中对石墨烯20表面进行功能化处理后或引入种子层相比，本发明实施例通过利用在石墨烯20表面的亲水易挥发气体30吸附水蒸气，可以使石墨烯20的表面由疏水性转变为亲水性，这样不仅不会破坏石墨烯20的晶格结构，而且亲水易挥发气体30在高温时即可挥发，并不会残留在石墨烯20的表面，因此确保了形成的栅介质层60具有高的纯度且易形成超薄栅介质层60。因此，本发明实施例提供的方法，可在石墨烯20表面形成大面积均匀高质量的栅介质层60。
优选的，步骤S101具体可以通过以下方式实现：
将形成有石墨烯20的衬底10置于亲水易挥发气体30的环境中，使石墨烯20的表面吸附亲水易挥发气体30。
此处，亲水易挥发气体30的环境优选为高浓度的亲水易挥发气体30的环境，高浓度即指亲水易挥发气体的质量占整个环境中混合气体质量的85％～100％。
其中，不对形成有石墨烯20的衬底10置于亲水易挥发气体30的环境中的时间进行限定，应确保石墨烯20表面充分吸附亲水易挥发气体30。
步骤S102具体可以通过以下方式实现：
将形成有石墨烯20的衬底置于ALD反应腔中，保持室温，通入水蒸气40，以使吸附在石墨烯20表面的亲水易挥发气体30吸附水蒸气40。
当石墨烯20的表面在亲水易挥发气体30的环境中吸附一定的亲水易挥发气体30后，取出该形成有石墨烯20的衬底10，将其放入ALD反 应腔中。在室温条件下，通入水蒸气40，石墨烯20表面的亲水易挥发气体30便可吸附一定量的水蒸气40。
由于在室温条件下就可使石墨烯20表面的亲水易挥发气体30吸附一定量的水蒸气40，而无需其他工艺步骤，因此，本发明实施例的工艺更为简单。
基于上述，优选的，栅介质源气体包括三甲基铝蒸汽和四氯化铪蒸汽中的一种。基于此，三甲基铝蒸汽和水蒸气反应可生成氧化铝，其κ值为7。四氯化铪蒸汽与水蒸气反应生成可二氧化铪，其κ值为10。
下面提供两个具体实施例以详细描述在石墨烯20表面分别形成高κ值的氧化铝或二氧化铪的栅介质层。
实施例一：在石墨烯20表面形成氧化铝的栅介质层60，如图4所示，具体包括如下步骤：
S201、利用微机械剥离法从石墨上剥离石墨烯20，并使石墨烯形成在300nm的氧化硅衬底上。
S202、将步骤S201中形成有石墨烯20的衬底10置于85％的氨气环境中，吸附氨气分子。
S203、将S202中吸附氨气的石墨烯20置于ALD反应腔中，在室温条件下，通入水蒸气40，使石墨烯20表面吸附水分子。
S204、将ALD反应腔的温度升高至300℃，通入三甲基铝蒸汽，三甲基铝蒸汽与石墨烯20表面吸附的水分子反应生成氧化铝的栅介质层60的一个单层50，同时由于高温，氨气分子解吸附并挥发。
S205、向ALD反应腔中通入氩气，排出ALD反应腔中未反应的水蒸气40和三甲基铝蒸汽。
S206、将ALD反应腔的温度保持在300℃，重复步骤S203-S205，形成由200个单层构成的所述氧化铝的栅介质层60。
实施例二：在石墨烯20表面形成二氧化铪的栅介质层60，如图5所示，具体包括如下步骤：
S301、利用化学气相沉积法形成石墨烯20，并利用 PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)将石墨烯20转移到石英表面。
S302、将步骤S301中形成有石墨烯20的衬底10置于90％的氯化氢环境中，吸附氯化氢分子。
S303、将步骤302中吸附氯化氢的石墨烯20置于ALD反应腔中，在室温条件下，通入水蒸气40，石墨烯20表面吸附水分子。
S304、将ALD反应腔的温度升高至300℃，通入四氯化铪蒸汽，四氯化铪蒸汽与石墨烯20表面吸附的水分子反应生成二氧化铪的栅介质层60的一个单层50，同时由于高温，氯化氢分子解吸附并挥发。
S305、向ALD反应腔中通入氮气，排出ALD反应腔出未反应的水蒸气40和四氯化铪蒸汽。
S306、将ALD反应腔的温度保持在300℃，重复步骤S303-S305，形成由300个单层构成的所述二氧化铪的栅介质层60。
本发明实施例还提供了一种制备如图6-图8所示的FET的方法，该方法包括在衬底10上依次形成石墨烯20、顶栅介质层70、源电极801、漏电极802以及顶栅电极90。其中，所述顶栅介质层70可以采用上述在石墨烯20表面形成栅介质层60的方法形成。
本发明实施例中，不对FET的结构进行限定，例如可以是如图6所示的顶栅结构的FET，也可以是如图7-图8所示的双栅结构的FET。
其中，在石墨烯上形成源电极801和漏电极802，如图9所示，具体包括如下步骤：
S401、采用电子束光刻工艺，刻蚀与源电极801区域和漏电极802区域对应的顶栅介质层70。
S402、在步骤S401的基础上，在所述顶栅介质层70上形成光刻胶。
S403、在步骤S402的基础上，利用电子束蒸发或溅射法，沉淀金属层。
S404、将步骤S403得到的样品放入丙酮溶液中，使光刻胶以及其上的金属层剥离，在石墨烯20表面形成间隔分布的源电极801和漏电极 802。
其中，源电极801和漏电极802的材料为Ti(钛)、Al(铝)、Cr(铬)、Au(金)、Pt(铂)、TiN(氮化钛)或TaN(氮化钽)中的一种或几种材料的组合。为了简化石墨烯FET的制备工艺，优选源电极801和漏电极802的材料相同，均为Ti/Au。
在此基础上，在顶栅介质层70上形成顶栅电极90，如图10所示，具体包括如下步骤：
S501、采用电子束光刻工艺在顶栅介质层70的表面定义出顶栅电极90区域。
S502、在步骤S501的基础上，在所述顶栅介质层70的除顶栅电极90的区域上形成光刻胶。
S503、在步骤S502的基础上，利用电子束蒸发或溅射法，沉淀金属层。
S504、将步骤S503得到的样品放入丙酮溶液中，使光刻胶以及其上的金属层剥离，在源电极801和漏电极802之间的顶栅介质层70上形成顶栅电极90。
其中，构成顶栅电极90的材料为Ti、Al、Cr、Au、Pt、TiN或TaN中的一种或几种材料的组合。优选的，顶栅电极90的材料为Ti/Au。
基于上述，优选的，所述衬底10可以为氧化硅衬底、石英衬底、玻璃衬底以及氧化硅衬底中的一种。这是由于这几种衬底较为容易得到，且成本较低。
在此基础上，当石墨烯FET为双栅结构时，所述方法还包括：在衬底10远离石墨烯20一侧形成如图7所示的底栅电极100。
其中，所述衬底10为氧化硅衬底。此时，该衬底10可相当于底栅介质层。
或者，如图8所示，在形成所述石墨烯20之前，所述方法还包括：在所述衬底10的靠近石墨烯20的一侧依次形成底栅电极100和底栅介质层110，底栅介质层110与石墨烯20接触。
其中，所述衬底10为石英衬底、玻璃衬底或氮化硅衬底。所述底栅介质层110的材料可以为氧化硅。
对于底栅电极100，其材料可以与顶栅电极90的材料相同。
本发明实施例中双栅结构的石墨烯FET，由于顶栅电极90和底栅电极100可以同时调制石墨烯20材料的电学性能，使制备的双栅结构的石墨烯FET具有更加优异的开断性能，更高的载流子迁移率以及更小的栅漏电流，因而使得制备的石墨烯FET的性能更加优异。
基于上述，在衬底上形成石墨烯的方法，包括：通过化学气相沉积法制备石墨烯；将石墨烯转移到聚甲基丙烯酸甲酯PMMA上；将带有PMMA的石墨烯形成在衬底10上，溶解所述PMMA。
当然，也可通过微机械剥离法和外延生长法在衬底10上形成石墨烯20。
其中，通过微机械剥离法在衬底10上形成石墨烯的过程具体是：先用胶带从高定向热解石墨(HOPG)上揭下一层石墨，再在胶带之间反复粘贴，石墨片层会越来越薄。其中，在反复粘贴过程中会形成单层石墨烯、双层石墨烯或多层石墨烯，然后将胶带贴在衬底10上，撕揭胶带使得有些石墨烯脱离胶带留在衬底10上，即可在衬底10上形成单层石墨烯、双层石墨烯或多层石墨烯。
通过外延生长法制备石墨烯的过程具体是：首先将氮化硅衬底的表面通过氧化或者H2刻蚀，然后将该氮化硅衬底在高真空(1.32×10-8Pa)下，采用电子轰击加热到1000℃以去除氧化物，并用俄歇电子能谱检测表面氧化物的去除情况，氧化物被完全去除后将氮化硅衬底加热至1250℃～1450℃，即可在氮化硅衬底的表面形成石墨烯20。形成的石墨烯20的厚度由加热温度决定。
化学气相沉积法制备石墨烯的过程具体是：以甲烷等含碳化合物作为碳源，在镍、铜等具有溶碳量的金属基体上通过将碳源高温分解，一般温度为800～1200℃，然后采用强迫冷却的方式在金属基体表面形成石墨烯20。
在此基础上，形成的石墨烯20可以利用PMMA的方法转移到衬底10上，具体是：先在另一衬底10上涂上一层水溶层，再在水溶层上涂上 PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)，然后将生长有石墨烯的金属基体放入腐蚀液中(FeCl3溶液或酸溶液)腐蚀金属基体。腐蚀完成后，石墨烯片会漂浮在液面上，将石墨烯片转移在PMMA上；再将其整个放于去离子水溶液中，水溶性层溶解后，该衬底沉入水底，而PMMA以及其上的石墨烯片将会漂浮在水面上，得到一面带有PMMA的石墨烯片。然后再将石墨烯片转移到衬底10上，这个衬底10被固定在光学显微镜的机械手上。然后在光学显微镜的帮助下使石墨烯片的PMMA面与衬底对准粘合。在转移过程中，衬底10需要被加热到110℃以便于去除吸附在石墨烯20或者衬底10上的多余水分，并促进了PMMA与衬底10的结合。转移完成后，将其放入酸中使石墨烯片上的PMMA溶解，从而使石墨烯20形成在衬底10上。
利用以上三种方法均可形成单层石墨烯、双层石墨烯及多层石墨烯。
由于化学气相沉积法制备的石墨烯质量高、面积大，且便于利用PMMA将石墨烯转移到衬底上，因而本实施例中优选的利用化学气相沉积法制备石墨烯。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种在石墨烯表面形成栅介质层的方法，所述石墨烯位于衬底上，其特征在于，所述方法包括：
    使所述石墨烯的表面吸附亲水易挥发气体；
    将形成有所述石墨烯的衬底置于原子层沉积ALD反应腔中，通入水蒸气，以使吸附在所述石墨烯表面的亲水易挥发气体吸附所述水蒸气；
    将所述ALD反应腔的温度升到预定温度，通入栅介质源气体，使所述水蒸汽和所述栅介质源气体发生反应，生成栅介质层的一个单层，并使所述亲水易挥发气体挥发；
    重复在所述ALD反应腔中通入水蒸气以及栅介质源气体，以形成所述栅介质层的其他单层，形成所述栅介质层。
  2. 根据权利要求1所述的方法，其特征在于，所述使所述石墨烯的表面吸附亲水易挥发气体，包括：
    将形成有所述石墨烯的衬底置于亲水易挥发气体的环境中，使所述石墨烯的表面吸附亲水易挥发气体。
  3. 根据权利要求1所述的方法，其特征在于，所述将形成有所述石墨烯的衬底置于ALD反应腔中，通入水蒸气，以使吸附在所述石墨烯表面的亲水易挥发气体吸附所述水蒸气，包括：
    将形成有所述石墨烯的衬底置于ALD反应腔中，保持室温，通入水蒸气，以使吸附在所述石墨烯表面的亲水易挥发气体吸附所述水蒸气。
  4. 根据权利要求1所述的方法，其特征在于，所述亲水易挥发气体包括氨气、氯化氢以及二氧化碳中的一种。
  5. 根据权利要求1所述的方法，其特征在于，所述栅介质层的相对介电常数κ大于5。
  6. 根据权利要求5所述的方法，其特征在于，所述栅介质源气体包括三甲基铝蒸汽和四氯化铪蒸汽中的一种。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述石墨烯为单层石墨烯，或双层石墨烯，或多层石墨烯。
  8. 一种制备场效应晶体管FET的方法，包括在衬底上依次形成石墨烯、顶栅介质层、源电极和漏电极以及顶栅电极，其特征在于，通过权利要求1-7任一项所述的方法形成所述顶栅介质层。
  9. 根据权利要求8所述的方法，其特征在于，所述衬底为氧化硅衬 底、石英衬底、玻璃衬底以及氮化硅衬底中的一种。
  10. 根据权利要求8所述的方法，其特征在于，所述方法还包括：在所述衬底远离所述石墨烯的一侧形成底栅电极；
    其中，所述衬底为氧化硅衬底。
  11. 根据权利要求8所述的方法，其特征在于，在形成所述石墨烯之前，所述方法还包括：在所述衬底的靠近所述石墨烯的一侧依次形成底栅电极和底栅介质层，所述底栅介质层与所述石墨烯接触；
    其中，所述衬底为石英衬底、玻璃衬底或氮化硅衬底。
  12. 根据权利要求8-11任一项所述的方法，其特征在于，所述在衬底上形成石墨烯，包括：
    通过化学气相沉积法制备所述石墨烯；
    将所述石墨烯转移到聚甲基丙烯酸甲酯PMMA上；
    将带有所述PMMA的石墨烯形成在所述衬底上，溶解所述PMMA。
PCT/CN2015/097200 2015-12-11 2015-12-11 一种在石墨烯表面形成栅介质层及制备晶体管的方法 WO2017096626A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2015/097200 WO2017096626A1 (zh) 2015-12-11 2015-12-11 一种在石墨烯表面形成栅介质层及制备晶体管的方法
CN201580085275.2A CN108369910B (zh) 2015-12-11 2015-12-11 一种在石墨烯表面形成栅介质层及制备晶体管的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/097200 WO2017096626A1 (zh) 2015-12-11 2015-12-11 一种在石墨烯表面形成栅介质层及制备晶体管的方法

Publications (1)

Publication Number Publication Date
WO2017096626A1 true WO2017096626A1 (zh) 2017-06-15

Family

ID=59012545

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/097200 WO2017096626A1 (zh) 2015-12-11 2015-12-11 一种在石墨烯表面形成栅介质层及制备晶体管的方法

Country Status (2)

Country Link
CN (1) CN108369910B (zh)
WO (1) WO2017096626A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112986356A (zh) * 2019-12-12 2021-06-18 福建海峡石墨烯产业技术研究院有限公司 一种石墨烯场效应晶体管生物传感器及其制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113078053B (zh) * 2021-03-25 2024-02-27 中国科学院上海微系统与信息技术研究所 一种顶栅结构的制备方法及半导体结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008085183A2 (en) * 2006-02-07 2008-07-17 President And Fellows Of Harvard College Gas-phase functionalization of carbon nanotubes
CN102891077A (zh) * 2012-09-26 2013-01-23 复旦大学 采用水基原子层沉积技术在石墨烯表面制备高k栅介质的方法
CN102945801A (zh) * 2012-11-22 2013-02-27 复旦大学 一种石墨烯表面高k栅介质的集成方法
US20140205905A1 (en) * 2013-01-18 2014-07-24 GM Global Technology Operations LLC Ultrathin surface coating on negative electrodes to prevent transition metal deposition and methods for making and use thereof
CN104851791A (zh) * 2015-04-29 2015-08-19 西交利物浦大学 石墨烯表面原子层沉积高k栅介质的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101443215B1 (ko) * 2007-06-13 2014-09-24 삼성전자주식회사 앰비폴라 물질을 이용한 전계효과 트랜지스터 및 논리회로
US8530886B2 (en) * 2011-03-18 2013-09-10 International Business Machines Corporation Nitride gate dielectric for graphene MOSFET
CN102600802A (zh) * 2012-03-16 2012-07-25 华中师范大学 一种石墨基二氧化碳吸附剂及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008085183A2 (en) * 2006-02-07 2008-07-17 President And Fellows Of Harvard College Gas-phase functionalization of carbon nanotubes
CN102891077A (zh) * 2012-09-26 2013-01-23 复旦大学 采用水基原子层沉积技术在石墨烯表面制备高k栅介质的方法
CN102945801A (zh) * 2012-11-22 2013-02-27 复旦大学 一种石墨烯表面高k栅介质的集成方法
US20140205905A1 (en) * 2013-01-18 2014-07-24 GM Global Technology Operations LLC Ultrathin surface coating on negative electrodes to prevent transition metal deposition and methods for making and use thereof
CN104851791A (zh) * 2015-04-29 2015-08-19 西交利物浦大学 石墨烯表面原子层沉积高k栅介质的方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112986356A (zh) * 2019-12-12 2021-06-18 福建海峡石墨烯产业技术研究院有限公司 一种石墨烯场效应晶体管生物传感器及其制备方法

Also Published As

Publication number Publication date
CN108369910B (zh) 2020-06-16
CN108369910A (zh) 2018-08-03

Similar Documents

Publication Publication Date Title
US8501531B2 (en) Method of forming graphene on a surface
Wei et al. Critical crystal growth of graphene on dielectric substrates at low temperature for electronic devices.
JP5137066B2 (ja) グラフェンシートの製造方法
KR101626181B1 (ko) 그라핀 필름의 제어된 성장 방법
US8119032B2 (en) Gas-phase functionalization of surfaces including carbon-based surfaces
US20160111180A1 (en) Method of forming amorphous carbon monolayer and electronic device including amorphous carbon monolayer
CN103981507B (zh) 一种石墨烯制备方法
US20120021224A1 (en) Graphene/graphene oxide platelet composite membranes and methods and devices thereof
CN102220566A (zh) 一种化学气相沉积制备单层和多层石墨烯的方法
Li et al. Atomic layer deposition of Al2O3 directly on 2D materials for high‐performance electronics
US20160005881A1 (en) Stacked films and method for producing stacked films
CN103606514B (zh) 基于GaN衬底CVD外延生长石墨烯的化学腐蚀转移方法
JP2008172244A (ja) 電子素子用ＺｎＯ半導体膜の形成方法及び前記半導体膜を含む薄膜トランジスタ
US20150004329A1 (en) Short-time growth of large-grain hexagonal graphene and methods of manufacture
JP5578639B2 (ja) グラファイト膜製造方法
WO2017096626A1 (zh) 一种在石墨烯表面形成栅介质层及制备晶体管的方法
CN112174121B (zh) 一种大尺寸清洁石墨烯材料的制备方法
TWI762150B (zh) 石墨烯奈米帶複合結構及其製備方法
TW201507033A (zh) 薄膜電晶體的製造方法
JP2004111928A5 (zh)
TWI785993B (zh) 原子級調制人造二維材料之設備及方法
TWI842006B (zh) 石墨烯基板及其形成方法
JP2013177659A (ja) グラフェン構造の製造方法
TW202436214A (zh) 在基板上形成石墨烯之方法
JP2024116966A (ja) ヘテロ積層デバイスの製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15910100

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15910100

Country of ref document: EP

Kind code of ref document: A1