WO2017092408A1 - 一种多晶硅高阻的制造方法 - Google Patents

一种多晶硅高阻的制造方法 Download PDF

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Publication number
WO2017092408A1
WO2017092408A1 PCT/CN2016/096045 CN2016096045W WO2017092408A1 WO 2017092408 A1 WO2017092408 A1 WO 2017092408A1 CN 2016096045 W CN2016096045 W CN 2016096045W WO 2017092408 A1 WO2017092408 A1 WO 2017092408A1
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region
polysilicon
layer
ion implantation
type
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French (fr)
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李伟
郝龙
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing high resistance of polysilicon.
  • a resistor device with high resistance and high precision is usually needed.
  • the commonly used polysilicon is high resistance in the industry. Due to its unique advantages: wide range of resistance values, small area and good linearity. Wait.
  • the active area resistance or polysilicon resistance parasitic on the process platform is usually not used because of insufficient resistance or insufficient precision.
  • the existing polysilicon high-resistance manufacturing method also has its inherent disadvantages: it requires special manufacturing and requires a separate process to be realized, so that the production cost is high, the process is cumbersome, and there is no advantage. Therefore, it is necessary to propose a new manufacturing method of polysilicon high resistance to solve the above technical problems.
  • a method for manufacturing high resistance of polysilicon comprising:
  • a method for manufacturing high resistance of polysilicon comprising:
  • the above-mentioned polysilicon high-resistance manufacturing method injects N-type and P-type impurities into the same polysilicon resistance layer by high-doping implantation in the source/drain regions, so that the two impurities are neutralized with each other, thereby achieving a lower net doping concentration.
  • the purpose of high resistance does not require a separate layer of lithography and a single step of ion implantation, which is achieved by an active drain region process, which achieves high resistance while saving cost and simplifying the process.
  • FIGS. 1A to 1F are schematic cross-sectional views showing a structure in which a polysilicon high resistance manufacturing method of an embodiment is sequentially performed;
  • FIG. 2 is a plan view showing a high-resistance of polysilicon manufactured by a method for manufacturing a high-resistance polysilicon according to an embodiment
  • FIG. 3 is a flow chart showing a method of manufacturing a polysilicon high resistance of an embodiment
  • FIG. 4 shows a specific flow chart of step S110 in the embodiment shown in FIG.
  • the withstand voltage structure of the semiconductor device is provided in the semiconductor device for improving the breakdown voltage of the semiconductor device, and the lateral diffusion metal oxide semiconductor is taken as an example for description.
  • the high polysilicon resistance involved in the embodiment is also called a high resistance polysilicon resistor, which is made of lightly doped polysilicon, has the advantages of wide resistance range, small area and good linearity, and has become The most promising device to replace the depletion load in MOS integrated circuits.
  • a method for manufacturing a polysilicon high resistance includes the following steps:
  • a semiconductor substrate 300 is provided.
  • the semiconductor substrate 300 includes a PMOS region, an NMOS region, and a polysilicon high resistance region, and a patterned polysilicon resistance layer is formed on the polysilicon high resistance region.
  • the constituent material of the semiconductor substrate 300 may be undoped single crystal silicon, doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and stacked on insulator. Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is selected from single crystal silicon.
  • step S110 includes the following specific steps, as shown in FIG.
  • a semiconductor substrate 300 is provided, in which an isolation structure 301 is formed, which is a shallow trench isolation (STI) structure 301.
  • the step of forming the shallow trench isolation structure 301 may include: forming a first silicon oxide layer and a nitride layer on the substrate of the defined active region; etching the first silicon oxide layer, the nitride layer And a portion of the depth of the substrate to form a shallow trench between the active regions, the trench depth is about 3000 to 8000 angstroms according to different technical requirements; forming a layer of isolation material in the shallow trench The layer of isolation material covers the nitride layer; the layer of isolation material is planarized to expose a nitride layer covering the active region; and the nitride layer is removed.
  • STI shallow trench isolation
  • Step S112 while referring to FIG. 1B, the semiconductor substrate 300 is ion-implanted to form a well region 302 in the semiconductor substrate 300, and a gate oxide layer 303 is formed on the surface of the semiconductor substrate 300. .
  • the doping type of the well region 302 is P-type; for the PMOS, the doping type of the well region 302 is N-type.
  • the thickness of the gate oxide layer 303 may be 200 to 800 angstroms, but is not limited to the above range, and other suitable values are also applicable to the present embodiment.
  • the gate oxide layer 303 can be formed by any method known to those skilled in the art. For example, oxidation processes known to those skilled in the art such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), and in situ water vapor oxidation (ISSG) can be employed. And forming a gate oxide layer 303 of a silicon oxide material.
  • Step S113 and referring to FIG. 1C, a polysilicon layer is deposited on the surface of the gate oxide layer 303, and the polysilicon layer is patterned to form the polysilicon resistor layer 304.
  • a patterned polysilicon resistor layer 304 is formed in a region of the gate oxide layer 303 corresponding to the polysilicon high resistance region.
  • a polysilicon layer may be first deposited on the surface of the gate oxide layer 303 on the semiconductor substrate 300, and then patterned by a photolithography process and an etching process to form the polysilicon resistor layer 304 as described in FIG. 1C.
  • the deposition method of the polysilicon resistance layer 304 may select one of molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD), and selective epitaxial growth (SEG). kind.
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • LAD laser ablation deposition
  • SEG selective epitaxial growth
  • the method of forming the polysilicon resistive layer 304 may be formed by an epitaxial method.
  • silicon is further exemplified, and the reactive gas may include silicon tetrachloride (SiCl 4 carried by hydrogen (H 2 ). ) or trichlorosilane (SiHCl 3), silane (SiH 4) and silicon-dichloro hydrogen (SiH 2 Cl 2), and the like is placed into the at least one reaction chamber of the silicon substrate, a high temperature chemical reaction in the reaction chamber The silicon-containing reactive gas is reduced or thermally decomposed, and the generated silicon atoms are epitaxially grown on the surface of the gate oxide layer.
  • the polysilicon resistor layer 304 can be formed synchronously with the gates of devices such as NMOS or PMOS around it.
  • step S120 simultaneously performing N-type ion implantation on the region in which the source/drain region is predetermined to be formed in the NMOS region and the polysilicon resistance layer, and the region in which the source/drain region is predetermined to be formed in the PMOS region and the
  • the polysilicon resistance layer simultaneously performs P-type ion implantation to form a high resistance region of the polysilicon resistance layer by neutralization doping of the P-type ions and the N-type ions.
  • the implantation dose of the N-type ion implantation is different from the implantation dose of the P-type ion implantation.
  • a step of forming spacers 305 on both sidewalls of the polysilicon resistor layer 304 prior to ion implantation is performed.
  • the sidewall 305 may include at least one oxide layer and/or at least one nitride layer. It should be noted that the sidewall spacer 305 is optional and unnecessary, and is mainly used to protect the sidewalls of the gate structure and the polysilicon resistor layer from damage during subsequent etching or ion implantation.
  • the region of the NMOS region where the source/drain region is predetermined to be formed and the polysilicon resistor layer 304 are simultaneously subjected to N-type ion implantation, and the region of the PMOS region where the source/drain region is predetermined to be formed and the polysilicon resistor layer 304 are simultaneously P-type ion implantation is performed, wherein an implantation dose of the N-type ions is different from an implantation dose of the P-type ions, and a high-resistance region of the polysilicon resistance layer 304 passes through the P-type ions and the N-type ions Formed by neutralization doping.
  • the polysilicon layer resistance layer 304 is implanted while the source and drain regions of the NMOS region and the PMOS region are implanted. Further, the step of performing separate ion implantation doping for the polysilicon resistor layer is avoided, thereby saving time and cost and simplifying the process.
  • the implantation dose of the N-type ions is greater than the implantation dose of the P-type ions. Since the implantation dose of the N-type ions is greater than the implantation dose of the P-type ions, after two ion implantations, the high-resistance region of the polysilicon resistance layer 304 is neutralized by the P-type ions and the N-type ions. Formed heterogeneously, the final polysilicon resistive layer 304 behaves as an N-type dopant. In another example, if the implanted dose of the N-type ions is less than the implanted dose of the P-type ions. Then, the polysilicon resistive layer 304 can also exhibit P-type doping, and can also achieve a higher high resistance value.
  • the implantation dose of the N-type ion implantation and the P-type ion implantation is not specifically limited.
  • the N-type ions are arsenic and or phosphorus, that is, the N-type ions may be arsenic and phosphorus. Or a combination of arsenic and phosphorus.
  • the implantation dose of the N-type ion implantation may be 5.0E+15 atom/cm 2 to 7 .0E+15 atom/cm 2 .
  • the P-type ion is boron, and the implantation dose of the P-type ion implantation is 2.0E+15 atom/cm 2 to 5.0E+15 atom/cm 2 .
  • step S130 a silicide blocking layer 306 is formed on a portion of the polysilicon resistive layer 304.
  • the silicide blocking layer 306 is a SAB oxide such as silicon oxide, silicon oxynitride, etc., and any prior art known to those skilled in the art, such as chemical vapor deposition, can be employed.
  • step S140 contact holes respectively electrically connected to the polysilicon resistance layer and the source/drain regions are formed.
  • contact holes 307 are formed which are electrically connected to the polysilicon resistor layer 304 and the source/drain regions of the NMOS or PMOS devices on the semiconductor device, respectively.
  • the contact hole 307 can be formed by any method known to those skilled in the art.
  • the device on the semiconductor substrate 300 may be covered with an interlayer dielectric layer, and then the interlayer dielectric layer is formed on the polysilicon resistance layer 304 and the source/drain regions.
  • the electrically connected openings are filled with metal to form the final contact holes 307.
  • the metal may be aluminum, copper, tungsten or the like.
  • FIG. 2 The layout of the polysilicon resistive layer 304 fabricated in this embodiment is shown in FIG. 2, wherein TO represents an active region; HR represents a high resistance; HV represents a high voltage region; NX represents a high voltage N well; SP represents a P-type source-drain implant; Represents N-type source-drain implant; GT stands for gate; SI stands for alloy barrier; W1 stands for contact hole.
  • TO represents an active region
  • HR represents a high resistance
  • HV represents a high voltage region
  • NX represents a high voltage N well
  • SP represents a P-type source-drain implant
  • GT gate
  • SI alloy barrier
  • W1 stands for contact hole.
  • the above has completed the introduction of the key steps of the high-resistance manufacturing method of polysilicon, and other intermediate steps or subsequent steps are required for the fabrication of the complete device, and will not be described herein.
  • the high resistance of the polysilicon obtained by the conventional process is 1000 ohms/square
  • the high resistance of the polysilicon obtained by the manufacturing method provided by the embodiment is 980 ohms/square, and the resistance is very close, which can satisfy the circuit design. Claim.
  • the present invention injects N-type and P-type impurities into the same polysilicon resistor layer during high-doping implantation in the source and drain regions, so that the two impurities neutralize each other, thereby achieving a lower net doping concentration.
  • This new method does not require a separate layer of lithography and a single step of ion implantation, which is achieved by an active drain region process, which achieves high resistance while saving cost and simplifying the process.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种多晶硅高阻的制造方法，包括：提供半导体衬底（300），该半导体衬底包括PMOS区、NMOS区和多晶硅高阻区，在该多晶硅高阻区内形成图案化的多晶硅电阻层（304）；对该NMOS区内预定形成源/漏区的区域和该多晶硅电阻层同时进行N型离子注入，对该PMOS区内预定形成源/漏区的区域和该多晶硅电阻层同时进行P型离子注入，以通过该P型离子和该N型离子的中和掺杂而形成该多晶硅电阻层的高阻区；其中，该N型离子注入的注入剂量与该P型离子注入的注入剂量不同。

Description

一种多晶硅高阻的制造方法
【技术领域】
本发明涉及半导体技术领域，具体而言涉及一种多晶硅高阻的制造方法。
【背景技术】
在模拟电路设计中，通常需要用到一种阻值较高且精度较高的电阻器件，业界常用的是多晶硅高阻，由于其独到的优点：电阻值宽范围可调，面积小和线性好等。而工艺平台寄生的有源区电阻或者多晶硅电阻，因为阻值不够或者精度不够，通常不被采用。
而现有的多晶硅高阻的制造方法也有其固有的缺点：需要特别制造，要求用一层单独的工艺来实现，因此生产成本较高，工艺过程繁琐，没有优势。 因此，有必要提出一种新的多晶硅高阻的制造方法，以解决上述技术问题。
【发明内容】
基于此，有必要提供一种节省成本的多晶硅高阻的制造方法。
一种多晶硅高阻的制造方法，包括：
提供半导体衬底，所述半导体衬底包括PMOS区、NMOS区和多晶硅高阻区，在所述多晶硅高阻区内形成图案化的多晶硅电阻层；
对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区；其中，所述N型离子注入的注入剂量与所述P型离子注入的注入剂量不同。
一种多晶硅高阻的制造方法，包括：
提供半导体衬底，所述半导体衬底包括PMOS区、NMOS区和多晶硅高阻区，在所述多晶硅高阻区内形成图案化的多晶硅电阻层；
在所述多晶硅电阻层的两侧壁上形成侧墙；
对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区；其中，所述N型离子注入的注入剂量与所述P型离子注入的注入剂量不同。
上述多晶硅高阻的制造方法通过在源漏区高掺杂注入时，将N型和P型杂质注入同一多晶硅电阻层，使两种杂质相互中和，从而实现较低的净掺杂浓度，达到高阻的目的。这种新方法不需要单独的一层光刻和单独的一步离子注入，借用已有源漏区工艺来实现，在达到高阻值的同时，节省了成本，简化了工艺。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1A至图1F示出了一实施例的多晶硅高阻的制造方法依次实施所获得结构的剖面示意图；
图2示出了一实施例提供的多晶硅高阻的制造方法制造的多晶硅高阻的版图；
图3示出了一实施例的多晶硅高阻的制造方法的流程图；
图4示出了图3所示实施例中步骤S110的具体流程图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和／或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了更清楚的解释本发明提供的半导体器件耐压结构，以下结合实施例作具体的说明。在以下实施例中，半导体器件耐压结构设置于半导体器件中，用于提高半导体器件的击穿电压，且以横向扩散金属氧化物半导体为例进行说明。
下面，参考图1A至图1F、图2和图3对多晶硅高阻的制造方法进行详细描述。需要说明的是，本实施例中涉及的多晶硅高阻也称为高阻多晶硅电阻，其由轻掺杂多晶硅制作而成，具有电阻值宽范围可调、面积小和线性好等优势，已经成为取代MOS集成电路中耗尽型负载的最有潜力的器件。
作为示例，一实施例提供的多晶硅高阻的制造方法，如图3和图1A所示，包括以下步骤：
首先，执行步骤S110，提供半导体衬底300，所述半导体衬底300包括PMOS区、NMOS区和多晶硅高阻区，在所述多晶硅高阻区上形成图案化的多晶硅电阻层。
具体地，提供半导体衬底300的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S-SiGeOI）、绝缘体上锗化硅（SiGeOI）以及绝缘体上锗（GeOI）等。作为示例，在本实施例中，半导体衬底300的构成材料选用单晶硅。
具体地，步骤S110包括以下具体步骤，如图4所示。
步骤S111，提供半导体衬底300，在半导体衬底300中形成有隔离结构301，所述隔离结构为浅沟槽隔离(STI)结构301。示例性地，形成浅沟槽隔离结构301的步骤可以包括：在已定义有源区的衬底上形成第一氧化硅层和氮化层；刻蚀所述第一氧化硅层、氮化层和部分深度的衬底，以在所述有源区之间形成浅沟槽，根据不同的技术需求，沟槽深度约为3000~8000埃；在所述浅沟槽内形成隔离材料层，所述隔离材料层覆盖所述氮化层；平整化所述隔离材料层，以暴露覆盖所述有源区的氮化层；去除所述氮化层。
步骤S112，同时请参考图1B，对所述半导体衬底300进行离子注入，以形成位于所述半导体衬底300中的阱区302，在所述半导体衬底300的表面上形成栅氧层303。
其中，对于NMOS而言，所述阱区302的掺杂类型为P型；对于PMOS而言，所述阱区302的掺杂类型为N型。
栅氧层303的厚度可以为200~800埃，但并不局限于上述范围，其他合适的数值也可适用于本实施例。可采用本领域技术人员熟知的任何方法形成栅氧层303，例如，可以采用本领域技术人员所习知的氧化工艺例如炉管氧化、快速热退火氧化(RTO)、原位水蒸气氧化(ISSG)等形成氧化硅材质的栅氧层303。
步骤S113，同时请参考图1C，在所述栅氧层303的表面上沉积形成多晶硅层，并图案化所述多晶硅层以形成所述多晶硅电阻层304。
其中，在所述栅氧层303表面对应多晶硅高阻区的区域内形成图案化的多晶硅电阻层304。具体地可先在半导体衬底300上栅氧层303表面沉积多晶硅层，再通过光刻工艺和刻蚀工艺进行图案化形成如图1C中所述的多晶硅电阻层304。
多晶硅电阻层304的沉积方法可以选择分子束外延(MBE)、金属有机化学气相沉积(MOCVD)、低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种。
在该实施例中，形成多晶硅电阻层304的方法可以选用外延方法形成，在具体实施例中以硅为例作进一步说明，反应气体可以包括氢气（H2）携带的四氯化硅（SiCl4）或三氯氢硅（SiHCl3）、硅烷（SiH4）和二氯氢硅（SiH2Cl2）等中的至少一种进入放置有硅衬底的反应室，在反应室进行高温化学反应，使含硅反应气体还原或热分解，所产生的硅原子在栅氧层表面上外延生长。
值得一提的是，该多晶硅电阻层304可与其周围的NMOS或者PMOS等器件的栅极同步形成。
接着，进行步骤S120，对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区。其中，所述N型离子注入的注入剂量与所述P型离子注入的注入剂量不同。
示例性地，如图1D所示，在进行离子注入之前，先在所述多晶硅电阻层304的两侧壁上形成侧墙305的步骤。其中，侧墙305可以包括至少一层氧化物层和/或至少一层氮化物层。需要说明的是，侧墙305是可选的而非必需的，其主要用于在后续进行蚀刻或离子注入时保护栅极结构和多晶硅电阻层的侧壁不受损伤。
之后，对NMOS区的预定形成源/漏区的区域和所述多晶硅电阻层304同时进行N型离子注入，对所述PMOS区的预定形成源/漏区的区域和所述多晶硅电阻层304同时进行P型离子注入，其中，所述N型离子的注入剂量与所述P型离子的注入剂量不同，所述多晶硅电阻层304的高阻区通过所述P型离子和所述N型离子的中和掺杂而形成。也即在进行NMOS区和PMOS区的源漏区注入的同时对多晶硅层电阻层304进行注入。进而避免使用对于多晶硅电阻层进行单独的离子注入掺杂的步骤，因此节省了时间和成本，简化了工艺。
本实施中，所述N型离子的注入剂量大于所述P型离子的注入剂量。由于N型离子的注入剂量大于P型离子的注入剂量，因此，经过两次离子注入后，所述多晶硅电阻层304的高阻区通过所述P型离子和所述N型离子的中和掺杂而形成，最终多晶硅电阻层304表现为N型掺杂。在另一示例中，若所述N型离子的注入剂量小于所述P型离子的注入剂量。则多晶硅电阻层304还可以表现为P型掺杂，也可实现较高的高阻值。
根据实际工艺以及器件的不同，对于N型离子注入和P型离子注入的注入剂量不作具体限制，本实施例中，所述N型离子为砷和或磷，即N型离子可以为砷、磷或者砷和磷的组合这三种类型。所述N型离子注入的注入剂量可以为5.0E+15atom/cm2~7 .0E+15atom/cm2。所述P型离子为硼，所述P型离子注入的注入剂量为2.0E+15 atom/cm2~5.0E+15 atom/cm2。
接着，进行步骤S130，在部分所述多晶硅电阻层304上形成硅化物阻挡层306。
如图1E所示，硅化物阻挡层306为SAB氧化物，例如氧化硅、氮氧化硅等，可以采用本领域技术人员熟知的任何现有技术，例如化学气相沉积法。
最后，进行步骤S140，形成分别与所述多晶硅电阻层和源/漏区电连接的接触孔。
如图1F所示，形成分别与所述多晶硅电阻层304和半导体器件上的NMOS或者PMOS元件的源/漏区电连接的接触孔307。可采用本领域技术人员熟知的任何方法形成该接触孔307。示例性地，在形成接触孔307之前，可先采用层间介电层覆盖半导体衬底300上的器件，再刻蚀层间介电层形成于与所述多晶硅电阻层304和源/漏区电连接的开口，采用金属填充开口形成最终的接触孔307。该金属可以为铝、铜、钨等。
本实施例制造的多晶硅电阻层304的版图如图2所示，其中，TO代表有源区；HR代表高阻；HV代表高压区；NX代表高压N阱；SP代表P型源漏注入；SN代表N型源漏注入；GT代表栅；SI代表合金阻挡区；W1代表接触孔。由图可以看出，对于多晶硅电阻层既进行了N型离子注入也进行了P型离子注入。
以上完成了对于多晶硅高阻的制造方法的关键步骤的介绍，对于完整的器件的制作还需其他的中间步骤或者后续步骤，在此均不再赘述。通过实测数据验证，常规工艺做出来的多晶硅高阻值为1000欧姆/方块，而根据本实施例提供的制造方法获得的多晶硅高阻值为980欧姆/方块，阻值非常接近，可以满足电路设计要求。
综上所述，本发明通过在源漏区高掺杂注入时，将N型和P型杂质注入同一多晶硅电阻层，使两种杂质相互中和，从而实现较低的净掺杂浓度，达到高阻的目的。这种新方法不需要单独的一层光刻和单独的一步离子注入，借用已有源漏区工艺来实现，在达到高阻值的同时，节省了成本，简化了工艺。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种多晶硅高阻的制造方法，包括：
    提供半导体衬底，所述半导体衬底包括PMOS区、NMOS区和多晶硅高阻区，在所述多晶硅高阻区内形成图案化的多晶硅电阻层；及
    对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区；其中，所述N型离子注入的注入剂量与所述P型离子注入的注入剂量不同。
  2. 根据权利要求1所述的方法，其特征在于，提供半导体衬底，所述半导体衬底包括PMOS区、NMOS区和多晶硅高阻区，在所述多晶硅高阻区内形成图案化的多晶硅电阻层的步骤包括：
    提供半导体衬底，在所述半导体衬底中形成隔离结构；
    对所述半导体衬底进行离子注入，以形成位于所述半导体衬底中的阱区，在所述半导体衬底的表面上形成栅氧层；
    在所述栅氧层的表面上沉积形成多晶硅层，并图案化所述多晶硅层以形成所述多晶硅电阻层。
  3. 根据权利要求1所述的方法，其特征在于，在对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区的步骤之前，所述方法还包括：
    在所述多晶硅电阻层的两侧壁上形成侧墙。
  4. 根据权利要求1所述的方法，其特征在于，在对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区的步骤之后，所述方法还包括：
    在部分所述多晶硅电阻层上形成硅化物阻挡层；
    形成分别与所述多晶硅电阻层和源/漏区电连接的接触孔。
  5. 根据权利要求1所述的方法，其特征在于，所述N型离子的注入剂量大于所述P型离子的注入剂量。
  6. 根据权利要求1所述的方法，其特征在于，所述N型离子为砷和/或磷，所述N型离子注入的注入剂量为5.0E+15atom/cm2~7.0E+15atom/cm2。
  7. 根据权利要求1所述的方法，其特征在于，所述P型离子为硼，所述P型离子注入的注入剂量为2.0E+15 atom/cm2~5.0E+15 atom/cm2。
  8. 根据权利要求1所述的方法，其特征在于，所述半导体衬底的材料为未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅、绝缘体上层叠硅、绝缘体上层叠锗化硅、绝缘体上锗化硅或绝缘体上锗。
  9. 根据权利要求2所述的方法，其特征在于，所述隔离结构为浅沟槽隔离结构。
  10. 根据权利要求2所述的方法，其特征在于，所述栅氧层的厚度为200埃至800埃。
  11. 根据权利要求2所述的方法，其特征在于，所述栅氧层通过炉管氧化、快速热退火氧化或原位水蒸气氧化方式来形成。
  12. 根据权利要求2所述的方法，其特征在于，在所述栅氧层的表面上沉积形成多晶硅层，并图案化所述多晶硅层以形成所述多晶硅电阻层的步骤为：
    在所述栅氧层的表面上沉积形成多晶硅层，并在所述多晶硅层上通过光刻工艺和刻蚀工艺进行图案化以形成所述多晶硅电阻层。
  13. 根据权利要求3所述的方法，其特征在于，所述侧墙包括至少一层氧化物层和/或至少一层氮化物层。
  14. 根据权利要求1所述的方法，其特征在于，所述N型离子的注入剂量小于所述P型离子的注入剂量。
  15. 一种多晶硅高阻的制造方法，包括：
    提供半导体衬底，所述半导体衬底包括PMOS区、NMOS区和多晶硅高阻区，在所述多晶硅高阻区内形成图案化的多晶硅电阻层；
    在所述多晶硅电阻层的两侧壁上形成侧墙；
    对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区；其中，所述N型离子注入的注入剂量与所述P型离子注入的注入剂量不同。
  16. 根据权利要求15所述的方法，其特征在于，提供半导体衬底，所述半导体衬底包括PMOS区、NMOS区和多晶硅高阻区，在所述多晶硅高阻区内形成图案化的多晶硅电阻层的步骤包括：
    提供半导体衬底，在所述半导体衬底中形成隔离结构；
    对所述半导体衬底进行离子注入，以形成位于所述半导体衬底中的阱区，在所述半导体衬底的表面上形成栅氧层；
    在所述栅氧层的表面上沉积形成多晶硅层，并图案化所述多晶硅层以形成所述多晶硅电阻层。
  17. 根据权利要求15所述的方法，其特征在于，在对所述NMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行N型离子注入，对所述PMOS区内预定形成源/漏区的区域和所述多晶硅电阻层同时进行P型离子注入，以通过所述P型离子和所述N型离子的中和掺杂而形成所述多晶硅电阻层的高阻区的步骤之后，所述方法还包括：
    在部分所述多晶硅电阻层上形成硅化物阻挡层；
    形成分别与所述多晶硅电阻层和源/漏区电连接的接触孔。
  18. 根据权利要求15所述的方法，其特征在于，所述N型离子的注入剂量大于所述P型离子的注入剂量。
  19. 根据权利要求15所述的方法，其特征在于，所述N型离子为砷和/或磷，所述N型离子注入的注入剂量为5.0E+15atom/cm2~7.0E+15atom/cm2。
  20. 根据权利要求15所述的方法，其特征在于，所述P型离子为硼，所述P型离子注入的注入剂量为2.0E+15 atom/cm2~5.0E+15 atom/cm2。
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