WO2017092407A1 - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
WO2017092407A1
WO2017092407A1 PCT/CN2016/095769 CN2016095769W WO2017092407A1 WO 2017092407 A1 WO2017092407 A1 WO 2017092407A1 CN 2016095769 W CN2016095769 W CN 2016095769W WO 2017092407 A1 WO2017092407 A1 WO 2017092407A1
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device region
semiconductor substrate
region
gate structure
lightly doped
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French (fr)
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李健
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method of fabricating a semiconductor device.
  • LDD lightly doped drain
  • a semiconductor chip manufacturing process includes forming a polysilicon gate structure on a semiconductor substrate, polysilicon of source and drain regions on both sides of the polysilicon gate structure is etched away, and a surface of the semiconductor substrate retains about 20 angstroms of silicon oxide. As a barrier to subsequent LDD injection. Covering N-type metal oxide semiconductors with a photoresist layer (N-Metal Oxide Semiconductor, NMOS) region exposes P-type metal oxide semiconductors (P-Metal Oxide Semiconductor, The PMOS) region is subjected to a P-LDD implantation process on the semiconductor substrate on both sides of the gate structure of the PMOS region, and the photoresist layer is removed by a wet de-glue step.
  • the photoresist layer is used to cover the PMOS region to expose the NMOS region, and the semiconductor substrate on both sides of the gate structure of the NMOS region is subjected to an N-LDD implantation process.
  • the photoresist is removed by a wet stripping step after each injection.
  • the chemical reagent used in the wet stripping step is a mixture of sulfuric acid, hydrogen peroxide, and deionized water (Sulphuric). Acid/hydrogen peroxide/DI water, SPM) also known as (SC-3) and a mixture of ammonium hydroxide, hydrogen peroxide and deionized water (Ammoniun Hydroxide/hydro peroxide/DI water mixture, APM) (also known as SC-1) cleaning solution.
  • the disadvantage of the prior art is that the wet degumming step after LDD injection causes a whole batch of wafers to be immersed in the APM acid tank for a long time when an abnormal situation such as alarm or power failure of the machine occurs.
  • the cleaning time is much longer than the process time, causing the APM liquid to over-etch the silicon oxide in the source and drain regions and the semiconductor substrate underneath.
  • the depth of the LDD implanted into the semiconductor substrate is very shallow, generally only 100 to 200 angstroms, and APM is silicon oxide.
  • Si There is a certain corrosion rate.
  • the immersion time is long, not only the 20 ⁇ silicon oxide will be completely etched, but also the bottom semiconductor substrate will have a loss of 50-100 angstroms, resulting in LDD injection failure.
  • the working current becomes very small, causing the entire batch of wafers to be scrapped.
  • the protective layer is removed.
  • the semiconductor substrate of the source/drain regions is protected by the protective layer before the LDD process is performed, and the corrosion of the semiconductor substrate of the source/drain regions by the APM in the wet de-glue step can be isolated and prevented.
  • the energy of the LDD implantation needs to be appropriately increased so that the implantation depth is consistent with the depth required for the device.
  • the corresponding increase of injection energy solves the problem that the injection energy is too small to approach the limit of the machine in the prior art, and the process window is added, so that the injection depth can be better controlled.
  • 1A-1E are cross-sectional views showing a structure obtained by sequentially manufacturing a semiconductor device of an embodiment
  • FIG. 2 is a flow chart showing a method of manufacturing a semiconductor device of an embodiment.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature. Thus, the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • Embodiments of the invention are described herein with reference to cross-section illustrations of schematic representations of the preferred embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown can be expected as a result, for example, of manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the specific shapes of the regions illustrated herein, but rather include variations in the shape, for example. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implanted concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. The regions shown in the figures are, therefore, are not intended to limit the scope of the invention.
  • a method of fabricating a semiconductor device includes the following steps:
  • a semiconductor substrate including a first device region and a second device region, and the first device region and the second device region of the semiconductor substrate are formed with a gate structure.
  • the constituent material of the semiconductor substrate 200 may be undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium (S-SiGeOI), silicon germanium (SiGeOI) on insulator, and germanium germanium (GeOI) are laminated on the insulator.
  • the constituent material of the semiconductor substrate 200 is selected from single crystal silicon.
  • An isolation structure 201 is also formed in the semiconductor substrate 200, and the isolation structure is a shallow trench (STI) isolation structure or a local silicon oxide (LOCOS) isolation structure.
  • STI shallow trench
  • LOC local silicon oxide
  • the semiconductor substrate 200 includes a first device region and a second device region that are isolated by the isolation structure 201.
  • the first device region is an NMOS region
  • the second device region is a PMOS region
  • the first device region is a PMOS region
  • the second device region is an NMOS region.
  • Various well regions are further formed in the semiconductor substrate 200, wherein the doping type of the well region is P type for the NMOS and the N type for the PMOS.
  • a gate structure 204 is formed on the semiconductor substrate of the first device region and the second device region.
  • the gate structure 204 includes a gate dielectric layer 202 and a gate material layer 203 stacked from bottom to top.
  • the gate dielectric layer 202 includes an oxide layer, such as a silicon dioxide (SiO 2 ) layer.
  • the gate material layer 203 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, wherein the constituent material of the metal layer may be tungsten (W Nickel (Ni) or titanium (Ti); the conductive metal nitride layer comprises a titanium nitride (TiN) layer; the conductive metal oxide layer comprises an iridium oxide (IrO 2 ) layer; and the metal silicide layer comprises titanium silicide ( TiSi) layer.
  • the gate material layer 203 includes a polysilicon layer.
  • the method of forming the gate dielectric layer 202 and the gate material layer 203 may be any prior art known to those skilled in the art, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor phase. Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low temperature chemical vapor deposition
  • RTCVD Rapid Thermal Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • an oxide layer (not shown) is further formed on a surface of the semiconductor substrate on which the source/drain regions are to be formed in the first device region and the second device region, and the oxide layer may be dielectrically bonded to the gate.
  • the layer 202 is formed simultaneously, which can protect the semiconductor substrate 200 after ion implantation, and has a thickness of 5 to 50 angstroms, preferably about 20 angstroms.
  • offset sidewalls that abut the gate structure 204 are formed on both sides of the gate structure 204.
  • the offset spacer is composed of an oxide, a nitride, or a combination of both.
  • the constituent material of the offset spacer is an oxide. The process of forming the offset sidewalls is well known to those skilled in the art and will not be described herein.
  • step S302 is performed to form a protective layer covering the exposed surface of the semiconductor substrate and the gate structure by deposition.
  • a deposition forming protective layer 205 covers the exposed surface of the semiconductor substrate 200 and the surface of the gate structure 204.
  • the material of the protective layer 205 includes silicon nitride and/or silicon oxynitride.
  • the material of the protective layer 205 is not limited to this example, and may be any other suitable material.
  • the protective layer 205 may have a thickness ranging from 30 to 80 angstroms, such as 30 angstroms, 40 angstroms, 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, and the like.
  • the protective layer can be formed by any deposition method well known to those skilled in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.
  • step S303 a first light doping drain process is performed on the semiconductor substrate on both sides of the gate structure of the first device region, and the semiconductor substrate on both sides of the gate structure of the second device region is performed.
  • the second lightly doped drain process is performed on the semiconductor substrate on both sides of the gate structure of the first device region, and the semiconductor substrate on both sides of the gate structure of the second device region is performed.
  • the step S303 includes the steps of: forming a first photoresist layer on a surface of the semiconductor substrate corresponding to the first device region, exposing the second device region;
  • the second light doping drain process is performed on the semiconductor substrate on both sides of the gate structure of the device region to form a lightly doped source/drain region 206p having a second conductivity type, as shown in FIG.
  • a photoresist layer, a second photoresist layer is formed on a surface of the semiconductor substrate corresponding to the second device region, exposing the first device region; and a gate structure of the first device region
  • the first light doping drain process is performed on the semiconductor substrates on both sides to form a lightly doped source/drain region 206n having a first conductivity type, as shown in FIG. 1C; and the second photoresist layer is removed.
  • the first device region is an NMOS region
  • the second device region is a PMOS region
  • the first conductivity type is an N type
  • the second conductivity type is a P type.
  • the first device region is a PMOS region
  • the second device region is an NMOS region
  • the first conductivity type is a P type
  • the second conductivity type is an N type.
  • the implanted ions of the LDD are different.
  • the implanted ions may be phosphorus, arsenic, etc.
  • the implanted ions may be boron or the like.
  • the energy of the LDD implantation needs to be appropriately increased to make the implantation depth consistent with the depth required for the device.
  • the corresponding increase of injection energy solves the problem that the injection energy is too small to approach the limit of the machine in the prior art, and the process window is added, so that the injection depth can be better controlled.
  • the implantation depth of the first lightly doped drain process and the second lightly doped drain process may range from 100 to 200 angstroms.
  • the doping ions implanted by the first lightly doped drain process may be phosphorus ions or arsenic ions or the like.
  • the doping ions implanted by the first lightly doped drain process are phosphorus ions
  • the ion implantation energy ranges from 1 to 20 keV
  • the ion implantation dose is 1.0 ⁇ e 14 -1.0 ⁇ e 15 cm -2 .
  • the dopant ions implanted by the second lightly doped drain process may be boron ions or indium ions or the like.
  • the ion implantation energy ranges from 0.5 to 10 keV
  • the ion implantation dose is 1.0 ⁇ e 14 - 1.0 ⁇ e 15 cm -2 .
  • the photoresist can be removed by a wet degumming step after each injection.
  • the chemical reagents used in the wet degumming step are SPM (the main components are sulfuric acid, hydrogen peroxide and deionized water) and APM (the main component is Ammonium hydroxide, hydrogen peroxide and deionized water). Since the etching rate of the protective layer 205 (for example, SION) by the APM is low, the protective layer 205 can be used as a protective layer of the lightly doped source/drain regions 206n, 206p of the source and drain regions, and the alarm is turned off at the machine. When an abnormality occurs, the APM can be isolated and prevented from corroding the semiconductor substrate 200 of the source and drain regions.
  • step S304 is performed to remove the protective layer 205.
  • the protective layer 205 is removed.
  • removal of the protective layer 205 may be performed by any method known to those skilled in the art including, but not limited to, wet cleaning or dry etching processes, and the like.
  • the protective layer 205 is preferably removed by a wet cleaning method.
  • the wet cleaning solution may employ a solution including phosphoric acid. It can also be carried out in hot phosphoric acid, and the reaction temperature of the hot phosphoric acid can range from 100 ° C to 200 ° C.
  • the wet cleaning has a high etch selectivity ratio of the protective layer 205 to the semiconductor substrate 200.
  • a step of forming a sidewall structure 207 on both sidewalls of the gate structure 204 is also included, as shown in FIG. 1E.
  • the process step of forming the sidewall structure 207 includes: forming a sidewall material layer covering the gate structure 204 on the semiconductor substrate 200, the constituent material of which may be silicon nitride, silicon oxide or a combination thereof; using sidewall etching (blanket The etch process etches the sidewall material layer to form the sidewall structure 207.
  • source/drain region implantation and annealing are performed on the first device region and the second device region, respectively, to form source/drain regions 208p, 208n in the semiconductor substrate 200, and activate the previously formed inactive LDD region 206p. And LDD area 206n.
  • Annealing can be high temperature rapid annealing, furnace tube annealing, etc., can use high temperature of 900 to 1050 ° C to activate the doping in the source/drain region, and simultaneously repair the crystal on the surface of the damaged semiconductor substrate in each ion implantation process. Grid structure.
  • the semiconductor substrate of the source/drain region is protected by a protective layer before the LDD process is performed, and the semiconductor of the source-drain region of the APM in the wet-de-glue step can be isolated and prevented.
  • Corrosion of the substrate in addition, since a certain thickness of the protective layer exists on the semiconductor substrate of the source/drain regions, the energy of the LDD implantation needs to be appropriately increased so that the implantation depth is consistent with the depth required by the device; and the corresponding implantation
  • the increase of energy solves the problem that the injection energy is too small to approach the limit of the machine in the prior art, and the process window is added, so that the injection depth can be better controlled.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体器件的制造方法，包括：提供半导体衬底，所述半导体衬底包括第一器件区和第二器件区，所述半导体衬底的第一器件区和所述第二器件区形成有栅极结构；通过沉积形成覆盖所述半导体衬底以及所述栅极结构的保护层；对所述第一器件区的栅极结构两侧的半导体衬底进行第一轻掺杂漏工艺，对所述第二器件区的栅极结构两侧的半导体衬底进行第二轻掺杂漏工艺；及，去除所述保护层。

Description

半导体器件的制造方法
【技术领域】
本发明涉及半导体技术领域，具体而言涉及一种半导体器件的制造方法。
【背景技术】
随着互补金属氧化物半导体晶体管制造技术的不断发展，集成度越来越高，其栅极的线宽也越做越小，栅极下方导电沟道的长度也不断的减小。为避免或抑制导电沟道长度缩短引起源极和漏极之间的漏电流，业界引入轻掺杂漏（Light Doped Drain，简称LDD）注入工艺，即在进行源极和漏极的重掺杂之前，先进行浅结注入。
一种半导体芯片制造流程，包括在半导体衬底上形成形成多晶硅栅极结构，多晶硅栅极结构两侧的源漏区的多晶硅被刻蚀掉，半导体衬底的表面保留20埃左右的氧化硅，作为后续LDD注入的阻挡层。采用光刻胶层覆盖N型金属氧化物半导体（N-Metal Oxide Semiconductor，NMOS）区暴露P型金属氧化物半导体（P-Metal Oxide Semiconductor， PMOS）区，并对PMOS区栅极结构两侧的半导体衬底进行P-LDD注入工艺，进行湿法去胶步骤去除光刻胶层。再采用光刻胶层覆盖PMOS区暴露NMOS区，对NMOS区栅极结构两侧的半导体衬底进行N-LDD注入工艺。每次注入后都要通过湿法去胶步骤将光刻胶去除，湿法去胶步骤采用的化学试剂为硫酸、过氧化氢、去离子水的混合物（Sulphuric acid/hydrogen peroxide/DI water，SPM）也称为（SC-3）和氢氧化铵、过氧化氢和去离子水的混合物（Ammoniun hydroxide/ hydrogen peroxide/DI water mixture，APM）（也称为SC-1）清洗液。
现有工艺的缺点在于：LDD注入后的湿法去胶步骤，当遇到机台报警、断电等异常情况发生的时候，会导致一整批晶圆长时间浸泡在APM酸槽内，使清洗时间远超工艺时间，造成APM液体对源漏区的氧化硅和其下方的半导体衬底的过腐蚀。由于LDD注入到半导体衬底内的深度很浅，一般只有100~200埃，而APM对氧化硅 和Si 都有一定的腐蚀速率，当浸泡时间较长的时候，不仅20埃的氧化硅会被全部腐蚀掉，连底部的半导体衬底也会有50-100埃的损失，从而导致LDD注入失效，器件的工作电流变得很小，造成整批圆片报废。
【发明内容】
基于此，有必要提供一种可以更好的控制注入深度的半导体器件的制造方法，包括：
提供半导体衬底，所述半导体衬底包括第一器件区和第二器件区，所述半导体衬底的第一器件区和所述第二器件区上形成有栅极结构；
通过沉积形成覆盖所述半导体衬底以及所述栅极结构的保护层；
对所述第一器件区的栅极结构两侧的半导体衬底进行第一轻掺杂漏工艺，对所述第二器件区的栅极结构两侧的半导体衬底进行第二轻掺杂漏工艺；及
去除所述保护层。
根据上述制造方法，在进行LDD工艺之前，采用保护层对源/漏区的半导体衬底进行保护，可以隔离和防止湿法去胶步骤中APM对源漏区的半导体衬底的腐蚀。另外，由于源/漏区的半导体衬底上存在一定厚度的保护层，因此LDD注入的能量需要适当增加，以使注入深度和器件所需要的深度保持一致。而相应的注入能量的增加，解决了现有工艺中注入能量过小接近机台极限的问题，增加了工艺窗口，可以更好的控制注入深度。
【附图说明】
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A-1E示出了一实施方式的半导体器件的制造方法依次实施所获得结构的剖视图；
图2为一实施方式的半导体器件的制造方法的流程图。
【具体实施方式】
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、 第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
下面，参考图1A-1E以及图2对一具体实施例的半导体器件的制造方法做详细描述。请参阅图2，一具体实施例的半导体器件的制造方法，包括以下步骤：
首先，进行步骤S301，提供半导体衬底，所述半导体衬底包括第一器件区和第二器件区，所述半导体衬底的第一器件区和所述第二器件区形成有栅极结构。
具体地，如图1A所示，半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S-SiGeOI）、绝缘体上锗化硅（SiGeOI）以及绝缘体上锗（GeOI）等。作为示例，在本实施例中，半导体衬底200的构成材料选用单晶硅。在半导体衬底200中还形成有隔离结构201，所述隔离结构为浅沟槽(STI)隔离结构或者局部氧化硅(LOCOS)隔离结构。本实施例中，半导体衬底200包括第一器件区和第二器件区，其通过隔离结构201相隔离。作为示例，在所述第一器件区为NMOS区，所述第二器件区为PMOS区，或者，在所述第一器件区为PMOS区，所述第二器件区为NMOS区。
在半导体衬底200中还形成有各种阱区，其中，对于NMOS而言，所述阱区的掺杂类型为P型；对于PMOS而言，所述阱区的掺杂类型为N型。
在所述第一器件区和所述第二器件区的半导体衬底上形成有栅极结构204。作为示例，栅极结构204包括自下而上层叠的栅极介电层202和栅极材料层203。栅极介电层202包括氧化物层，例如二氧化硅（SiO2）层。栅极材料层203包括多晶硅层、金属层、导电性金属氮化物层、导电性金属氧化物层和金属硅化物层中的一种或多种，其中，金属层的构成材料可以是钨（W）、镍（Ni）或钛（Ti）；导电性金属氮化物层包括氮化钛（TiN）层；导电性金属氧化物层包括氧化铱（IrO2）层；金属硅化物层包括硅化钛（TiSi）层。本实施例中，栅极材料层203包括多晶硅层。栅极介电层202和栅极材料层203的形成方法可以采用本领域技术人员所熟习的任何现有技术，优选化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(RTCVD)、等离子体增强化学气相沉积(PECVD)。
在一个示例中，在第一器件区和第二器件区预定形成源/漏区的半导体衬底的表面上还形成有氧化物层（未示出），该氧化物层可与栅极介电层202同步形成，其可在之后离子注入时对半导体衬底200起到保护作用，其厚度可以为5~50埃，较佳地，其厚度约为20埃。
示例性地，在栅极结构204的两侧形成紧靠栅极结构204的偏移侧墙。偏移侧墙由氧化物、氮化物或者二者的组合构成，作为示例，在本实施例中，偏移侧墙的构成材料为氧化物。形成偏移侧墙的工艺过程为本领域技术人员所熟习，在此不再加以赘述。
接着，进行步骤S302，通过沉积形成覆盖所述半导体衬底暴露的表面以及所述栅极结构的保护层。
如图1B所示，沉积形成保护层205覆盖所述半导体衬底200暴露的表面以及所述栅极结构204的表面。示例性地，所述保护层205的材料包括氮化硅和/或氮氧化硅。保护层205的材料并不仅限于该示例，还可以为其他任何适合的材料。可选地，所述保护层205的厚度范围可以为30~80埃，例如30埃、40埃、50埃、60埃、70埃、80埃等。可采用本领域技术人员熟知的任何沉积方法形成该保护层，例如化学气相沉积（CVD）、物理气相沉积(PVD)、原子层沉积（ALD）等。
接着，进行步骤S303，对所述第一器件区的栅极结构两侧的半导体衬底进行第一轻掺杂漏工艺，对所述第二器件区的栅极结构两侧的半导体衬底进行第二轻掺杂漏工艺。
在一个示例中，所述步骤S303包括步骤：在所述半导体衬底的对应所述第一器件区的表面上形成第一光刻胶层，暴露所述第二器件区；对所述第二器件区的栅极结构两侧的半导体衬底进行所述第二轻掺杂漏工艺，以形成具有第二导电类型的轻掺杂源/漏区206p，如图1C所示；去除所述第一光刻胶层，在所述半导体衬底的对应所述第二器件区的表面上形成第二光刻胶层，暴露所述第一器件区；对所述第一器件区的栅极结构两侧的半导体衬底进行所述第一轻掺杂漏工艺，以形成具有第一导电类型的轻掺杂源/漏区206n，如图1C所示；去除所述第二光刻胶层。
其中，在所述第一器件区为NMOS区，所述第二器件区为PMOS区，所述第一导电类型为N型，所述第二导电类型为P型。或者，在所述第一器件区为PMOS区，所述第二器件区为NMOS区，所述第一导电类型为P型，所述第二导电类型为N型。
对于不同的导电类型，其LDD的注入离子不同，对于N型而言，其注入离子可以为磷、砷等，对于P型而言，其注入离子可以为硼等。
由于源/漏区的半导体衬底200上存在一定厚度的保护层205，因此， LDD注入的能量需要适当增加，使注入深度和器件所需要的深度保持一致。而相应的注入能量的增加，解决了现有工艺中注入能量过小接近机台极限的问题，增加了工艺窗口，可以更好的控制注入深度。本实施例中，第一轻掺杂漏工艺和第二轻掺杂漏工艺的注入深度范围可以为100~200埃。示例性地，当所述第一器件区为NMOS区，所述第二器件区为PMOS区时，第一轻掺杂漏工艺注入的掺杂离子可以是磷离子或者砷离子等。当第一轻掺杂漏工艺注入的掺杂离子为磷离子时，离子注入的能量范围为1-20keV，离子注入的剂量为1.0×e14-1.0×e15cm-2。第二轻掺杂漏工艺注入的掺杂离子可以是硼离子或者铟离子等。例如为硼离子时，离子注入的能量范围为0.5-10keV，离子注入的剂量为1.0×e14-1.0×e15cm-2。
示例性地，每次注入后可通过湿法去胶步骤将光刻胶去除，湿法去胶步骤采用的化学试剂为SPM（主要成分为硫酸、双氧水和去离子水）和APM(主要成分为氢氧化铵、过氧化氢和去离子水）。由于APM对保护层205（例如，SION）的腐蚀速率较低，因此保护层205可以用来作为源漏区的轻掺杂源/漏区206n、206p的保护层，在机台报警断电等异常发生情况发生的时候，可以隔离和防止APM对源漏区的半导体衬底200的腐蚀。
接着，进行步骤S304，去除所述保护层205。
如图1D所示，去除所述保护层205。根据保护层205的材料，可选择本领域技术人员熟知的任何方法进行保护层205的去除，包括但不限于湿法清洗或者干法刻蚀工艺等。本实施例中，较佳地采用湿法清洗的方法去除所述保护层205。湿法清洗的溶液可以采用包括磷酸的溶液。还可在热磷酸中进行，该热磷酸的反应温度范围可以为100℃至200℃。该湿法清洗具有保护层205对半导体衬底200的高的刻蚀选择比。
之后，还包括在所述栅极结构204的两侧壁上形成侧墙结构207的步骤，如图1E所示。作为示例，形成侧墙结构207的工艺步骤包括：在半导体衬底200上形成覆盖栅极结构204的侧墙材料层，其构成材料可以为氮化硅、氧化硅或其组合；采用侧墙蚀刻（blanket etch）工艺蚀刻侧墙材料层，以形成侧墙结构207。
接下来，对第一器件区和第二器件区分别执行源/漏区注入并退火，以在半导体衬底200中形成源/漏区208p、208n，并激活此前形成的未激活的LDD区206p和LDD区206n。退火可以为高温快速退火、炉管退火等，可利用900至1050℃的高温来活化源/漏区域内的掺杂质，并同时修补在各离子注入工艺中受损的半导体衬底表面的晶格结构。
综上所述，根据本发明的制造方法，在进行LDD工艺之前，采用保护层对源/漏区的半导体衬底进行保护，可以隔离和防止湿法去胶步骤中APM对源漏区的半导体衬底的腐蚀；另外，由于源/漏区的半导体衬底上存在一定厚度的保护层，因此LDD注入的能量需要适当增加，以使注入深度和器件所需要的深度保持一致；而相应的注入能量的增加，解决了现有工艺中注入能量过小接近机台极限的问题，增加了工艺窗口，可以更好的控制注入深度。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (12)

  1. 一种半导体器件的制造方法，包括：
    提供半导体衬底，所述半导体衬底包括第一器件区和第二器件区，所述半导体衬底的第一器件区和所述第二器件区上形成有栅极结构；
    通过沉积形成覆盖所述半导体衬底以及所述栅极结构的保护层；
    对所述第一器件区的栅极结构两侧的半导体衬底进行第一轻掺杂漏工艺，对所述第二器件区的栅极结构两侧的半导体衬底进行第二轻掺杂漏工艺；及
    去除所述保护层。
  2. 如权利要求1所述的方法，其特征在于，所述保护层的材料包括氮化硅和/或氮氧化硅。
  3. 如权利要求1所述的方法，其特征在于，所述保护层的厚度范围为30~80埃。
  4. 如权利要求1所述的方法，其特征在于，所述栅极结构包括采用化学气相沉积法自下而上依次沉积的栅极介电层和栅极材料层。
  5. 如权利要求1所述的方法，其特征在于，对所述第一器件区的栅极结构两侧的半导体衬底进行第一轻掺杂漏工艺，对所述第二器件区的栅极结构两侧的半导体衬底进行第二轻掺杂漏工艺包括：
    在所述半导体衬底的所述第一器件区的表面上形成第一光刻胶层，暴露所述第二器件区；
    对所述第二器件区的栅极结构两侧的半导体衬底进行所述第二轻掺杂漏工艺，以形成具有第二导电类型的轻掺杂源/漏区；
    去除所述第一光刻胶层，在所述半导体衬底的所述第二器件区的表面上形成第二光刻胶层，暴露所述第一器件区；
    对所述第一器件区的栅极结构两侧的半导体衬底进行所述第一轻掺杂漏工艺，以形成具有第一导电类型的轻掺杂源/漏区；及
    去除所述第二光刻胶层。
  6. 如权利要求5所述的方法，其特征在于，所述第一器件区为NMOS区，所述第二器件区为PMOS区，所述第一导电类型为N型，所述第二导电类型为P型。
  7. 如权利要求5所述的方法，其特征在于，所述第一器件区为PMOS区，所述第二器件区为NMOS区，所述第一导电类型为P型，所述第二导电类型为N型。
  8. 如权利要求5所述的制造方法，其特征在于，所述第一轻掺杂漏工艺和所述第二轻掺杂漏工艺的注入深度范围均为100~200埃。
  9. 如权利要求5所述的制造方法，其特征在于，采用湿法腐蚀去胶工艺去除所述第一光刻胶层和所述第二光刻胶层。
  10. 如权利要求1所述的方法，其特征在于，采用湿法清洗的方法去除所述保护层。
  11. 如权利要求10所述的方法，其特征在于，采用包括磷酸的溶液进行所述湿法清洗。
  12. 如权利要求1所述的方法，其特征在于，在去除所述保护层之后，还包括在所述栅极结构的两侧壁上形成侧墙结构。
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