WO2017088242A1 - 时序控制芯片内启示信号控制方法、芯片及显示面板 - Google Patents

时序控制芯片内启示信号控制方法、芯片及显示面板 Download PDF

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Publication number
WO2017088242A1
WO2017088242A1 PCT/CN2015/099211 CN2015099211W WO2017088242A1 WO 2017088242 A1 WO2017088242 A1 WO 2017088242A1 CN 2015099211 W CN2015099211 W CN 2015099211W WO 2017088242 A1 WO2017088242 A1 WO 2017088242A1
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Prior art keywords
timing
signal
rgb data
stv
lvds
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PCT/CN2015/099211
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English (en)
French (fr)
Inventor
吴晶晶
熊志
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深圳市华星光电技术有限公司
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Priority to US14/907,553 priority Critical patent/US9898993B2/en
Publication of WO2017088242A1 publication Critical patent/WO2017088242A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
    • H04J3/26—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially in which the information and the address are simultaneously transmitted
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
    • H04Q9/14—Calling by using pulses
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13213—Counting, timing circuits

Definitions

  • the present invention relates to the field of display, and in particular, to a method, a chip and a display panel for controlling a revelation signal in a timing control chip.
  • RGB Red (red)
  • G stands for Green (green)
  • B stands for Blue (blue)
  • line synchronization English
  • Hsync English full name: horizontal synchronization
  • field synchronization English abbreviation: Vsync, English full name: Vertical synchronization
  • data enable English abbreviation: DE, English full name: Data Enable
  • pixel clock and other signals.
  • LVDS low-voltage differential signal
  • LVDS low-voltage differential signaling
  • the signal arrangement is shown in Figure 1.
  • Two transmission modes are defined in the LVDS transmission protocol: data enable mode (English abbreviation: DE mode, English full name: Data Enable mode) and synchronization mode (English abbreviation: Sync mode, English full name: synchronization mode); DE mode only DE
  • the signal is synchronized with RGB data, and Sync mode needs to synchronize RGB data with Hsync and Vsync.
  • the timing relationship diagram is shown in Figure 2.
  • both transmission modes need to store a whole source line data signal to the data buffer of the timing control chip (English: TCON IC, English name: Timing Controller integrated circuit) (English: line buffer) Delayed for a while.
  • TCON IC English name: Timing Controller integrated circuit
  • the line buffer needs to be set in the TCON IC to store the delayed Data signal, resulting in higher TCON IC cost.
  • timing control chip intra-apocalypse signal control method controls the timing of the start signal (STV), and the start timing of the STV is before the timing of the input RGB signal, so that it is not necessary Delays the input RGB signal, which reduces the line buffer and reduces the cost of the TCON IC.
  • a method for controlling a revelation signal in a timing control chip comprising the following steps:
  • the LVDS signal Decoding the LVDS signal to obtain a transistor-transistor logic RGB data signal TTL RGB data signal and a control signal;
  • the control signal includes: a start signal STV, a line sync Hsync, and a field sync Vsync;
  • the improved low voltage differential signal mini-LVDS data is obtained by processing the input RGB data.
  • the controlling the STV timing before the mini-LVDS data timing is specific, including :
  • the STV timing t STV is delayed by a first set time t1 with the Vsync timing t Vsync as a reference; wherein t Vsync +t1 ⁇ t m ; the t m is the input RGB data timing.
  • the controlling the STV timing before the input RGB data timing comprises:
  • the mode of the LVDS signal is:
  • Synchronous mode sync mode or enable mode DE mode Synchronous mode sync mode or enable mode DE mode.
  • a timing control chip TCON IC comprising: a low voltage differential signal receiver LVDS receiver, an improved low voltage differential signal data mapping module mini-LVDS output data mapping, a transmission module transmit, and a timing controller timing controller ;among them,
  • the LVDS receiver is configured to receive a low voltage differential signal LVDS signal; the LVDS signa is decoded to obtain a transistor-transistor logic RGB data signal TTL RGB data signal and a control signal; the control signal includes: a start signal STV, a line synchronization Hsync, and Field synchronization Vsync; sending the TTLRGB data signal to the mini-LVDS output data mapping, and sending the control signal to the timing controller;
  • the mini-LVDS output data mapping is used to process the TTLRGB data signal to obtain input RGB data, and send the input RGB data to the transmit;
  • the timing controller is configured to control the STV timing before the input RGB data timing
  • the transmit is used to process the input RGB data to obtain an improved low voltage differential signal mini-LVDS data.
  • the timing controller is specifically configured to be used
  • the STV timing t STV is delayed by a first set time t1 with the Vsync timing t Vsync as a reference; wherein t Vsync +t1 ⁇ t m ; the t m is the input RGB data timing.
  • the timing controller is specifically configured to be used
  • the mode of the LVDS signal is:
  • Synchronous mode sync mode or enable mode DE mode Synchronous mode sync mode or enable mode DE mode.
  • a display panel comprising the timing control chip provided by the second aspect, the first alternative of the second aspect, the second alternative of the second aspect or the second aspect The third option.
  • a display device comprising the display panel provided in the third aspect.
  • each of the above embodiments controls the timing of the enable signal (STV), and the start timing of the STV is before the timing of the input RGB signal. There is no need to delay the input RGB signal, which reduces the line buffer and reduces the cost of the TCON IC.
  • FIG. 1 is a schematic diagram of a signal arrangement manner in the prior art
  • FIG. 2 is a schematic diagram of signal timing in a TCON IC in the prior art
  • FIG. 3 is a schematic diagram of signal timing in a TCON IC according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for controlling a revelation signal in a timing control chip according to a first preferred embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a TCON IC in the prior art
  • FIG. 6 is a flowchart of a method for controlling a revelation signal in a timing control chip according to a second preferred embodiment of the present invention.
  • Figure 7 is a flow chart of a preferred method provided by a second preferred embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a timing control chip according to a third preferred embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 4 illustrates a method for controlling a revelation signal in a timing control chip according to a first preferred embodiment of the present invention.
  • the method may be performed by a TCON IC, and the TCON IC may be disposed in a display panel or a display. 4, including the following steps:
  • Step S401 receiving an LVDS signal
  • the receiving LVDS signal in the above step S401 can be received by the LVDS receiver (Chinese: low voltage differential signal receiver), and the first preferred embodiment of the present invention does not limit the manner in which the LVDS receiver receives signals.
  • the above LVDS signal can have two modes, and the two modes can be: synchronous mode sync mode or enable mode DE mode.
  • the specific receiving mode and the specific structure of the LVDS receiver can be used in the prior art.
  • the first preferred embodiment of the present invention does not limit the manner of receiving the signal, and the specific structure of the LVDS receiver is not limited.
  • Step S402 performing decoding processing on the LVDS signal to obtain a transistor-transistor logic RGB data signal TTL RGB data signal and a control signal;
  • the LVDS signal is obtained by decoding the LVDS signal in the above step S402 to obtain the TTL RGB data signal and the control signal.
  • the LVDS receiver can be decoded by the prior art, for example, the LVDS signal is rearranged.
  • the TTL RGB data signal, the first preferred embodiment of the present invention can decode the LVDS signal by using any one or more processing methods of the prior art to obtain a TTL RGB data signal and a control signal.
  • the first preferred embodiment of the present invention The specific form of the above processing method is not limited.
  • the control signal in the above step S402 may specifically include: STV, DE, Hsync, and Vsync; the foregoing control signal may be specifically generated by the TCON IC.
  • Step S403 processing TTL RGB data signal to obtain input RGB data input RGB data;
  • the method for processing the TTL RGB data signal to obtain the input RGB data in the above step S403 can be various.
  • the first preferred embodiment of the present invention can process the TTL RGB data signal by using any one or more processing methods of the prior art.
  • Input RGB data the first preferred embodiment of the present invention does not limit the specific form of the above processing method.
  • Step S404 controlling the STV timing before the input RGB data timing
  • the generating STV signal in the above step S404 can be specifically completed by the TCON IC, and the TCON IC needs to control the STV timing before the input RGB data timing, and the STV timing can be controlled before the input RGB data timing.
  • the preferred embodiment does not limit the specific manifestation of the timing control implementation described above.
  • Step S405 processing the input RGB data to obtain mini-LVDS data.
  • the format of the input RGB data in the above step S405 may be TTL (English full name: Transistor-Transistor Logic, Chinese: Transistor-Transistor Logic) format data, and the format of the mini-LVDS data may be LVDS format data, the processing specific It can be that the data of the input RGB data is arranged to obtain mini-LVDS data.
  • FIG. 5 is a timing diagram of each signal in the TCON IC provided by the prior art
  • FIG. 5 is a structural diagram of the TCON IC provided by the prior art, wherein the TCON IC includes: LVDS receiver (Chinese: low voltage differential signal receiving) , mini-LVDS output data mapping, improved line buffer, transmit module, and timing controller.
  • input DE can be the input enable signal
  • input RGB data can input RGB data for line buffer in TCON IC
  • output RGB data can output RGB data for line buffer in TCON IC
  • STV is a TCON IC
  • the start signal generated or generated, the STV's role is to process input RGB data in the TCON IC after the STV timing; assuming the input RGB data timing is before the STV timing, then the input RGB data before the STV timing may There will be lost or unprocessed conditions, which will affect the data reception of the display, which will affect its display effect. Therefore, the prior art obtains output RGB data by line buffer for input RGB data delay t2 time (ie, line buffer).
  • the timing is a reference delay of one t3, and the control t3 ⁇ t2, that is, the STV timing can be set before the output RGB data timing, as shown in FIG. 3, in FIG. 3, Vsync can be the field synchronization signal of TCON IC; Prevent the loss of input RGB data, but this setting needs to set a buffer, that is, line buffer to store the delayed output data RGB data.
  • the technical solution adopted by the first preferred embodiment of the present invention directly controls the STV timing before the input RGB data timing when generating the STV, so that no buffering is required, because TCON is used in the first preferred embodiment of the present invention.
  • TCON IC can directly process input RGB data without the occurrence of input RGB data loss or unprocessed, so the first comparison of the present invention
  • the preferred implementation does not require a delay of input RGB data, so that the line buffer can be removed, thereby reducing the cost.
  • the technical solution provided by the first preferred embodiment of the present invention receives the LVDS signal, and then processes the LVDS signal to obtain the TTL RGB data signal and the control signal; generates the STV, and controls the STV timing before the input RGB data timing, for the TTL RGB
  • the data signal is processed to obtain input RGB data; the input RGB data is processed to obtain mini-LVDS data.
  • the above data processing is directly processed on the input RGB data, so it does not delay the input RGB data, so there is no need for the line buffer buffer, so it reduces the line buffer and has the advantage of reducing the cost.
  • FIG. 6 is a schematic diagram of a method for controlling a revelation signal in a timing control chip according to a second preferred embodiment of the present invention.
  • the method may be implemented by a TCON IC, and the TCON IC may be disposed in a display panel or a display. As shown in 6, it includes the following steps:
  • Step S601 receiving an LVDS signal
  • the receiving LVDS signal in the above step S601 can be received by the LVDS receiver (Chinese: low voltage differential signal receiver), and the second preferred embodiment of the present invention does not limit the manner in which the LVDS receiver receives signals.
  • the above LVDS signal can have two modes, and the two modes can be: synchronous mode sync mode or enable mode DE mode.
  • the specific receiving manner and the specific structure of the LVDS receiver may be the signal receiving manner of the prior art.
  • the second preferred embodiment of the present invention does not limit the manner of receiving the signal, and the specific structure of the LVDS receiver is not limited.
  • Step S602 performing decoding processing on the LVDS signal to obtain a TTL RGB data signal and a control signal;
  • the LVDS signal is decoded by the LVDS signal in the above step S602 to obtain the TTL RGB data signal and the control signal can also be completed by the LVDS receiver.
  • the specific decoding processing mode of the LVDS receiver can be performed by using a prior art decoding processing method, for example, rearranging the LVDS signal.
  • the TTL RGB data signal, the second preferred embodiment of the present invention can decode the LVDS signal by using any one or more processing methods of the prior art to obtain a TTL RGB data signal and a control signal, and the second preferred embodiment of the present invention
  • the specific form of the above processing method is not limited.
  • the control signal in the above step S602 may specifically include: STV, DE, Hsync, and Vsync; the foregoing control signal may be specifically generated by the TCON IC.
  • Step S603 processing TTL RGB data signal to obtain input RGB data input RGB data;
  • the method for processing the TTL RGB data signal to obtain the input RGB data in the above step S403 can be various.
  • the second preferred embodiment of the present invention can process the TTL RGB data signal by using any one or more processing methods of the prior art. Input RGB data, the second preferred embodiment of the present invention does not limit the specific form of the above processing method.
  • Step S604 delaying the STV timing t STV with the Vsync timing t Vsync as a reference for a first set time t1; wherein, t Vsync +t1 ⁇ t m ;
  • the generating STV in the above step S604 can be specifically completed by the TCON IC, and the TCON IC needs to delay the STV timing t STV with the Vsync timing t Vsync as the reference for the first set time t1; where t Vsync +t1 ⁇ t m ; m can be the timing of input RGB data.
  • Step S605 processing the input RGB data to obtain mini-LVDS data.
  • FIG. 5 is a timing diagram of each signal in the TCON IC provided by the prior art
  • FIG. 5 is a structural diagram of the TCON IC provided by the prior art, wherein the TCON IC includes: LVDS receiver (Chinese: low voltage differential signal receiving) , mini-LVDS output data mapping, improved line buffer, transmit module, and timing controller.
  • input DE can be the input enable signal
  • input RGB data can input RGB data for line buffer in TCON IC
  • output RGB data can be line buffer in TCON IC
  • STV is a start signal generated or generated in a TCON IC.
  • the function of the STV is to process input RGB data in the TCON IC after the STV timing; assume that the timing of the input RGB data is before the STV timing. Then the input RGB data before the STV timing may be lost or unprocessed. This situation will affect the data reception of the display, which will affect its display effect. Therefore, the prior art delays the input RGB data by line buffer t2.
  • Time to get output RGB data (that is, the data stored in the line buffer), and then delay the STV timing with the input DE timing as a reference t3, control t3 ⁇ t2, that is, the STV timing can be set before the output RGB data timing, as shown in Figure 3.
  • Vsync can be the field sync signal of TCON IC; this setting prevents the loss of input RGB data, but this setting requires setting a buffer, ie line buffer, to store the data output after the delay. RGB data.
  • the technical solution adopted by the first preferred embodiment of the present invention directly controls the STV timing before the input RGB data timing when generating the STV, so that no buffering is required, because TCON is used in the first preferred embodiment of the present invention.
  • TCON IC can directly process input RGB data without the occurrence of input RGB data loss or unprocessed, so the second comparison of the present invention
  • the preferred implementation does not require a delay of input RGB data, so that the line buffer can be removed, thereby reducing the cost.
  • step S604 of the second preferred embodiment of the present invention may be replaced by the following steps; as shown in FIG. 7, the step may specifically be:
  • Step S701 generating a reference signal, synchronizing the STV timing with the reference signal timing, and controlling the reference signal timing t reference to delay the second set time tx with the Vsync timing t Vsync as a reference; wherein, t Vsync +tx ⁇ t m ;
  • the generating STV and the reference signal in the above step S701 can be specifically completed by the TCON IC, and the TCON IC needs to delay the reference signal timing t reference with the Vsync timing t Vsync as the reference for the second set time tx; wherein, t Vsync +tx ⁇ t m ;
  • the above t m can be specifically the timing of input RGB data.
  • the disadvantage of this approach is that it requires a more reference signal, which increases the amount of computation of the TCON IC.
  • FIG. 8 is a timing control chip TCON IC800 according to a third preferred embodiment of the present invention.
  • the TCON IC 800 includes: an LVDS receiver 801, a mini-LVDS output data mapping 802, a transmit 803, and a timing controller 804.
  • LVDS receiver 801 for receiving low voltage differential signal LVDS signal; LVDS signal Performing a decoding process to obtain a TTL RGB data signal and a control signal; the control signal includes: a start signal STV, a line sync Hsync, and a field sync Vsync; and the TTL RGB data signal is sent to the mini-LVDS output data mapping 802, Sending the control signal to the timing controller 804;
  • the third preferred embodiment of the present invention does not limit the manner in which the LVDS receiver receives signals.
  • the above LVDS signal can have two modes, and the two modes can be: synchronous mode sync mode or enable mode DE mode.
  • the mini-LVDS output data mapping 802 is configured to process the TTL RGB data signal to obtain the input RGB data input RGB data, and send the nput RGB data to the transmit 803;
  • the first preferred embodiment of the present invention may adopt any one or more processing methods of the prior art to the TTL.
  • the RGB data signal process obtains input RGB data, and the first preferred embodiment of the present invention does not limit the specific form of the above processing manner.
  • a timing controller 804 configured to control the STV timing before the input RGB data timing
  • the STV signal generated in the above timing controller 804 can be specifically completed by the TCON IC.
  • the TCON IC needs to control the STV timing before the input RGB data timing, and the implementation of the STV timing before the input RGB data timing can be implemented in various ways.
  • the third preferred embodiment does not limit the specific manifestation of the timing control implementation described above.
  • the transmit 803 is configured to process the input RGB data to obtain an improved low voltage differential signal mini-LVDS data.
  • the format of input RGB data in the above transmit 803 may be TTL (English full name: Transistor-Transistor Logic, Chinese: Transistor-Transistor Logic) format data, and the format of mini-LVDS data may be LVDS format data, the processing specific It can be that the data of the input RGB data is arranged to obtain mini-LVDS data.
  • the technical solution provided by the third preferred embodiment of the present invention enables the STV timing to be before the input RGB data timing by setting the STV timing, so that the TCON IC loses the input RGB data due to the STV timing
  • FIG. 2 and FIG. 5 is a timing diagram of each signal in the TCON IC provided by the prior art
  • FIG. 5 is a structural diagram of the TCON IC provided by the prior art.
  • the TCON IC includes: LVDS receiver (Chinese: low voltage differential signal receiver), mini-LVDS output data mapping (improved low voltage differential signal data mapping module), data buffer (line buffer), transmit (transmission module) and timing Controller (timing controller).
  • input DE can be the input enable signal
  • input RGB data can input RGB data for line buffer in TCON IC
  • output RGB data can output RGB data for line buffer in TCON IC
  • STV is a TCON IC
  • the start signal generated or generated, the STV's role is to process input RGB data in the TCON IC after the STV timing; assuming the input RGB data timing is before the STV timing, then the input RGB data before the STV timing may There will be lost or unprocessed conditions, which will affect the data reception of the display, which will affect its display effect. Therefore, the prior art obtains output RGB data by line buffer for input RGB data delay t2 time (ie, line buffer).
  • Vsync can be TCON IC's field sync signal; this setting prevents the loss of input RGB data, but this setting requires setting a buffer, ie line Buffer to store the delayed output data RGB data.
  • the technical solution adopted by the first preferred embodiment of the present invention directly controls the STV timing before the input RGB data timing when generating the STV, so that no buffering is required, because TCON is used in the first preferred embodiment of the present invention.
  • TCON IC can directly process input RGB data without input RGB data loss or unprocessed, so the third comparison of the present invention
  • the preferred implementation does not require a delay of input RGB data, so that the line buffer can be removed, thereby reducing the cost.
  • the technical solution provided by the third preferred embodiment of the present invention receives the LVDS signal, and then processes the LVDS signal to obtain the TTL RGB data signal and the control signal; generates the STV, and controls the STV timing before the input RGB data timing, for the TTL RGB
  • the data signal is processed to obtain input RGB data; the input RGB data is processed to obtain mini-LVDS data.
  • the above data processing is directly processed on the input RGB data, so it does not delay the input RGB data, so there is no need for the line buffer buffer, so it reduces the line buffer and has the advantage of reducing the cost.
  • the timing controller 804 can be specifically used for
  • the STV timing t STV is delayed by a first set time t1 with the Vsync timing t Vsync as a reference; wherein t Vsync +t1 ⁇ t m ; the t m is the input RGB data timing.
  • the generating STV in the above timing controller 804 can be specifically completed by the TCON IC, and the TCON IC needs to delay the STV timing t STV with the Vsync timing t Vsync as a reference for the first set time t1; wherein t Vsync +t1 ⁇ t m ; t m can be the timing of input RGB data.
  • the timing controller 804 can be specifically used for
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • the display panel 900 includes a timing control chip 800.
  • the structure of the timing control chip 800 can be referred to the structure provided by the third preferred embodiment of the present invention.
  • a specific embodiment of the present invention further provides a display device, which may include a display panel, and the display panel includes the above-described timing control chip.
  • the structure of the timing control chip 800 can be referred to the structure provided by the third preferred embodiment of the present invention.

Abstract

一种时序控制芯片（800）内启始信号控制方法、芯片（800）及显示面板（900），所述方法包括：接收低压差分信号LVDS signal（401）；对LVDS signal进行解码处理得到晶体管-晶体管逻辑RGB数据信号TTL RGB data signal和控制信号（402）；所述控制信号包括：启动信号STV、行同步Hsync和场同步Vsync；对TTL RGB data signal处理得到输入RGB数据input RGB data（403）；将所述STV时序控制在所述input RGB data时序之前（404）；对所述input RGB data处理得到改进低压差分信号mini-LVDS data（405）。该技术方案具有成本低的优点。

Description

时序控制芯片内启示信号控制方法、芯片及显示面板
本申请要求于2015年11月25日提交中国专利局、申请号为201510837163.X、发明名称为“时序控制芯片内启示信号控制方法、芯片及显示面板”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种时序控制芯片内启示信号控制方法、芯片及显示面板。
背景技术
液晶屏(英文：panel)又称LCD(英文全称：Liquid Crystal Display，中文：液晶显示器)，其是目前常用的电子显示设备，LCD驱动板输出的数字信号除了包括RGB数据信号外，RGB即是代表红、绿、蓝三个通道的颜色，即通常人们所说的三原色，其中，R代表Red(红色)，G代表Green(绿色)，B代表Blue(蓝色)；还包括行同步(英文简称：Hsync，英文全称：horizontal synchronization)、场同步(英文简称：Vsync，英文全称：Vertical synchronization)、数据使能(英文简称：DE，英文全称：Data Enable)、像素时钟等信号。以低压差分信号(英文简称：LVDS，英文全称：low-voltage differential signaling)接口的输出为例，各信号排列方式如图1所示。LVDS传输协议中定义两种传输模式：数据使能模式(英文简称：DE mode，英文全称：Data Enable mode)和同步模式(英文简称：Sync mode，英文全称：synchronization mode)；DE mode只需DE信号同步RGB data，Sync mode需要用Hsync和Vsync同步RGB data，上述时序关系图如图二所示。
在实现现有技术的方案中，发现现有技术存在如下技术问题：
参阅图2，两种传输模式都需先将一整条source line的数据信号存到时序控制芯片(英文简称：TCON IC，英文全称：Timing Controller integrated circuit)的数据缓冲器(英文：line buffer)延迟一段时间。例如，对于解析度为 1920*1080/8bit的面板来说，TCON IC内部每条source line的数据量就有1920*3*8bit＝46080bits，因此就需要46kB存储容量的line buffer存储延迟的Data信号(该延迟的Data信号对应图2中的output RGB信号)，所以该TCON IC内需要设置line buffer来存储延迟的Data信号，导致TCON IC成本较高。
发明内容
提供一种时序控制芯片内启示信号控制方法，所述时序控制芯片内启示信号控制方法对启动信号(STV)的时序进行控制，是的STV的开始时序在input RGB信号的时序之前，这样就无需对input RGB信号延时，从而减少了line buffer，降低了TCON IC成本。
第一方面，提供一种时序控制芯片内启示信号控制方法，所述方法包括如下步骤：
接收低压差分信号LVDS signal；
对LVDS signal进行解码处理得到晶体管-晶体管逻辑RGB数据信号TTL RGB data signal和控制信号；所述控制信号包括：启动信号STV、行同步Hsync和场同步Vsync；
对TTL RGB data signal处理得到输入RGB数据input RGB data；
将所述STV时序控制在所述input RGB data时序之前；
对所述input RGB data处理得到改进低压差分信号mini-LVDS data。
结合第一方面提供的一种时序控制芯片内启示信号控制方法，在第一方面的第一种可选方案中，所述将所述STV时序控制在所述mini-LVDS data时序之前具体，包括：
将所述STV时序tSTV以所述Vsync时序tVsync为基准延时第一设定时间t1；其中，tVsync+t1＜tm；所述tm为所述input RGB data时序。
结合第一方面提供的一种时序控制芯片内启示信号控制方法，在第一方面的第二种可选方案中，所述将所述STV时序控制在所述input RGB data时序之前具体，包括：
生成参考信号，将所述STV时序与所述参考信号时序同步，控制参考信号时序t参考以Vsync时序tVsync为基准延时第二设定时间tx；其中，tVsync+tx＜tm； 所述tm为所述input RGB data时序。
结合第一方面提供的一种时序控制芯片内启示信号控制方法、第一方面第一种可选方案或第一方面第二种可选方案，在第一方面的第三种可选方案中，所述LVDS signal的模式为：
同步模式sync mode或使能模式DE mode。
第二方面，提供一种时序控制芯片TCON IC，所述TCON IC包括：低压差分信号接收器LVDS receiver、改进低压差分信号数据映射模块mini-LVDS output data mapping、传输模块transmit和时序控制器timing controller；其中，
所述LVDS receiver，用于接收低压差分信号LVDS signal；将LVDS signa进行解码处理得到晶体管-晶体管逻辑RGB数据信号TTL RGB data signal和控制信号；所述控制信号包括：启动信号STV、行同步Hsync和场同步Vsync；将所述TTLRGB data signal发送给所述mini-LVDS output data mapping，将所述控制信号发送给所述timing controller；
所述mini-LVDS output data mapping，用于对TTLRGB data signal处理得到input RGB data，将所述input RGB data发送给所述transmit；
所述timing controller，用于将所述STV时序控制在所述input RGB data时序之前；
所述transmit，用于对所述input RGB data处理得到改进低压差分信号mini-LVDS data。
结合第二方面提供的一种时序控制芯片，在第二方面的第一种可选方案中，所述timing controller具体，用于
将所述STV时序tSTV以所述Vsync时序tVsync为基准延时第一设定时间t1；其中，tVsync+t1＜tm；所述tm为所述input RGB data时序。
结合第二方面提供的一种时序控制芯片，在第二方面的第二种可选方案中，所述timing controller具体，用于
生成参考信号，将所述STV时序与所述参考信号时序同步，控制参考信号时序t参考以Vsync时序tVsync为基准延时第二设定时间tx；其中，tVsync+tx＜tm；所述tm为所述input RGB data时序。
结合第二方面提供的一种时序控制芯片、第二方面第一种可选方案或第二 方面第二种可选方案，在第二方面的第三种可选方案中，所述LVDS signal的模式为：
同步模式sync mode或使能模式DE mode。
第三方面，提供一种显示面板，所述显示面板包括第二方面提供的时序控制芯片、第二方面的第一种可选方案、第二方面的第二种可选方案或第二方面的第三种可选方案。
第四方面，提供一种显示装置，所述显示装置包括第三方面提供的显示面板。
根据各实施方式提供的时序控制芯片内启示信号控制方法、芯片及显示面板，上述各实施方式对启动信号(STV)的时序进行控制，是的STV的开始时序在input RGB信号的时序之前，这样就无需对input RGB信号延时，从而减少了line buffer，降低了TCON IC成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中信号排列方式示意图；
图2为现有技术中TCON IC内的信号时序示意图；
图3为本发明具体实施方式中的TCON IC内的信号时序示意图；
图4为本发明第一较佳实施方式中的时序控制芯片内启示信号控制方法的流程图；
图5为现有技术中TCON IC内的结构示意图；
图6为本发明第二较佳实施方式中的时序控制芯片内启示信号控制方法的流程图；
图7为本发明第二较佳实施方式提供的优选方法的流程图；
图8为本发明第三较佳实施方式提供的时序控制芯片结构示意图；
图9为本发明具体实施方式提供的显示面板结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参阅图4，图4为本发明第一较佳实施方式提供的时序控制芯片内启示信号控制方法，该方法可以有TCON IC执行，该TCON IC可以设置在显示面板或显示器内，该方法如图4所示，包括如下步骤：
步骤S401、接收LVDS signal；
上述步骤S401中接收LVDS signal可以由LVDS receiver(中文：低压差分信号接收器)接收，本发明第一较佳实施方式并不限制LVDS receiver接收信号的方式。上述LVDS signal可以有两种模式，两种模式分别可以为：同步模式sync mode或使能模式DE mode。
上述LVDS receiver的具体接收方式以及具体结构可以采用现有技术的信号接收方式，本发明第一较佳实施方式对该信号接收的方式并不限定，对LVDS receiver的具体结构也不限定。
步骤S402、对LVDS signal进行解码处理得到晶体管-晶体管逻辑RGB数据信号TTL RGB data signal和控制信号；
上述步骤S402中对LVDS signal进行解码处理得到TTL RGB data signal和控制信号也可以由LVDS receiver完成，该LVDS receiver具体解码处理方式可以采用现有技术的解码处理方式，例如对LVDS signal进行重新排列得到TTL RGB data signal，本发明第一较佳实施方式可以采用现有技术的任意一种或多种处理方式对LVDS signal进行解码处理得到TTL RGB data signal和控制信号，本发明第一较佳实施方式对上述处理方式的具体形式并不限定。
上述步骤S402中的控制信号具体可以包括：STV、DE、Hsync和Vsync；上述控制信号具体可以由TCON IC生成。
步骤S403、对TTL RGB data signal处理得到输入RGB数据input RGB data；
上述步骤S403中对TTL RGB data signal处理得到input RGB data的方法可以有多种，本发明第一较佳实施方式可以采用现有技术的任意一种或多种处理方式对TTL RGB data signal处理得到input RGB data，本发明第一较佳实施方式对上述处理方式的具体形式并不限定。
步骤S404、控制STV时序在input RGB data时序之前；
上述步骤S404中的生成STV信号具体可以由TCON IC完成，TCON IC需要控制STV时序在input RGB data时序之前，将STV时序控制在input RGB data时序之前的实现方式可以有多种，本发明第一较佳实施方式并不限制上述时序控制实现方式的具体表现形式。
步骤S405、对input RGB data处理得到mini-LVDS data。
上述步骤S405中的input RGB data的格式可以是TTL(英文全称：Transistor-Transistor Logic，中文：晶体管-晶体管逻辑)格式的数据，而mini-LVDS data的格式可以是LVDS格式的数据，该处理具体可以为，对input RGB data进行数据的排列得到mini-LVDS data。
本发明第一较佳实施方式提供的技术方案通过对STV时序的设置，使得STV时序在input RGB data时序之前，这样能够避免因为STV时序的原因，使得TCON IC丢失input RGB data，参阅图2和图5；图2为现有技术提供的TCON IC中各个信号的时序图，图5为现有技术提供的TCON IC的结构图，其中，该TCON IC包括：LVDS receiver(中文：低压差分信号接收器)、mini-LVDS output data mapping(改进低压差分信号数据映射模块)、数据缓冲器(line buffer)、transmit(传输模块)和timing controller(时序控制器)。如图2所示，input DE可以为输入的使能信号，input RGB data可以为TCON IC内line buffer输入RGB数据，output RGB data可以为TCON IC内line buffer输出RGB数据，STV是一个TCON IC内生成或产生的起始信号，该STV的作用是在STV时序之后，TCON IC中的才会处理input RGB data；假设input RGB data的时序在STV时序之前，那么位于STV时序之前的input RGB data可能会出现丢失或未处理的情况，此种情况会影响显示屏的数据接收，进而影响其显示效果，所以现有技术通过line buffer对input RGB data延时t2时间得到output RGB data(即line buffer的存储数据)，然后将STV时序以input DE 时序为基准延时一个t3，控制t3＜t2，即可以实现STV时序设置在output RGB data时序之前，如图3所示，图3中，Vsync可以为TCON IC的场同步信号；这种设置来防止input RGB data的丢失，但是此种设置是需要设置一个缓存器，即line buffer来存储延时后的数据output RGB data。而本发明第一较佳实施方式采用的技术方案在生成STV时，直接将STV时序控制在input RGB data时序之前，这样就不需要进行缓存，因为对于本发明第一较佳实施方式中的TCON IC来说，此时STV的时序已经控制在input RGB data时序之前，TCON IC已经可以直接对input RGB data进行处理而不会出现input RGB data丢失或未处理的情况发生，所以本发明第一较佳实施方式也无需进行input RGB data的延时，这样就可以去掉line buffer，进而降低成本。
本发明第一较佳实施方式提供的技术方案在接收到LVDS signal，然后对LVDS signal处理得到TTL RGB data signal和控制信号；生成STV，并控制该STV时序在input RGB data时序之前，对TTL RGB data signal处理得到input RGB data；对input RGB data处理得到mini-LVDS data。上述数据处理是直接对input RGB data处理的，所以其并没有对input RGB data进行延时处理，所以也无需line buffer缓存，所以其减少了line buffer，具有降低成本的优点。
参阅图6，图6为本发明第二较佳实施方式提供的时序控制芯片内启示信号控制方法，该方法可以有TCON IC执行，该TCON IC可以设置在显示面板或显示器内，该方法如图6所示，包括如下步骤：
步骤S601、接收LVDS signal；
上述步骤S601中接收LVDS signal可以由LVDS receiver(中文：低压差分信号接收器)接收，本发明第二较佳实施方式并不限制LVDS receiver接收信号的方式。上述LVDS signal可以有两种模式，两种模式分别可以为：同步模式sync mode或使能模式DE mode。
上述LVDS receiver的具体接收方式以及具体结构可以采用现有技术的信号接收方式，本发明第二较佳实施方式对该信号接收的方式并不限定，对LVDS receiver的具体结构也不限定。
步骤S602、对LVDS signal进行解码处理得到TTL RGB data signal和控制信号；
上述步骤S602中对LVDS signal进行解码处理得到TTL RGB data signal和控制信号也可以由LVDS receiver完成，该LVDS receiver具体解码处理方式可以采用现有技术的解码处理方式，例如对LVDS signal进行重新排列得到TTL RGB data signal，本发明第二较佳实施方式可以采用现有技术的任意一种或多种处理方式对LVDS signal进行解码处理得到TTL RGB data signal和控制信号，本发明第二较佳实施方式对上述处理方式的具体形式并不限定。
上述步骤S602中的控制信号具体可以包括：STV、DE、Hsync和Vsync；上述控制信号具体可以由TCON IC生成。
步骤S603、对TTL RGB data signal处理得到输入RGB数据input RGB data；
上述步骤S403中对TTL RGB data signal处理得到input RGB data的方法可以有多种，本发明第二较佳实施方式可以采用现有技术的任意一种或多种处理方式对TTL RGB data signal处理得到input RGB data，本发明第二较佳实施方式对上述处理方式的具体形式并不限定。
步骤S604、将STV时序tSTV以Vsync时序tVsync为基准延时第一设定时间t1；其中，tVsync+t1＜tm；
上述步骤S604中的生成STV具体可以由TCON IC完成，TCON IC需要将STV时序tSTV以Vsync时序tVsync为基准延时第一设定时间t1；其中，tVsync+t1＜tm；上述tm具体可以为input RGB data的时序。
步骤S605、对input RGB data处理得到mini-LVDS data。
本发明第二较佳实施方式提供的技术方案通过对STV时序的设置，使得STV时序在input RGB data时序之前，这样能够避免因为STV时序的原因，使得TCON IC丢失input RGB data，参阅图2和图5；图2为现有技术提供的TCON IC中各个信号的时序图，图5为现有技术提供的TCON IC的结构图，其中，该TCON IC包括：LVDS receiver(中文：低压差分信号接收器)、mini-LVDS output data mapping(改进低压差分信号数据映射模块)、数据缓冲器(line buffer)、transmit(传输模块)和timing controller(时序控制器)。如图2所示，input DE可以为输入的使能信号，input RGB data可以为TCON IC 内line buffer输入RGB数据，output RGB data可以为TCON IC内line buffer 输出RGB数据，STV是一个TCON IC内生成或产生的起始信号，该STV的作用是在STV时序之后，TCON IC中的才会处理input RGB data；假设input RGB data的时序在STV时序之前，那么位于STV时序之前的input RGB data可能会出现丢失或未处理的情况，此种情况会影响显示屏的数据接收，进而影响其显示效果，所以现有技术通过line buffer对input RGB data延时t2时间得到output RGB data(即line buffer的存储数据)，然后将STV时序以input DE时序为基准延时一个t3，控制t3＜t2，即可以实现STV时序设置在output RGB data时序之前，如图3所示，图3中，Vsync可以为TCON IC的场同步信号；这种设置来防止input RGB data的丢失，但是此种设置是需要设置一个缓存器，即line buffer来存储延时后的数据output RGB data。而本发明第一较佳实施方式采用的技术方案在生成STV时，直接将STV时序控制在input RGB data时序之前，这样就不需要进行缓存，因为对于本发明第一较佳实施方式中的TCON IC来说，此时STV的时序已经控制在input RGB data时序之前，TCON IC已经可以直接对input RGB data进行处理而不会出现input RGB data丢失或未处理的情况发生，所以本发明第二较佳实施方式也无需进行input RGB data的延时，这样就可以去掉line buffer，进而降低成本。
优选的，本发明第二较佳实施方式的步骤S604也可以采用下述步骤来替换；如图7所示，该步骤具体可以为：
步骤S701、生成参考信号，将STV时序与参考信号时序同步，控制参考信号时序t参考以Vsync时序tVsync为基准延时第二设定时间tx；其中，tVsync+tx＜tm；
上述步骤S701中的生成STV和参考信号具体可以由TCON IC完成，TCON IC需要将参考信号时序t参考以Vsync时序tVsync为基准延时第二设定时间tx；其中，tVsync+tx＜tm；上述tm具体可以为input RGB data的时序。此种方式的缺点在于需要多生成一个参考信号，这样会增加TCON IC的计算量。
参阅图8，图8为本发明第三较佳实施方式提供一种时序控制芯片TCON IC800，TCON IC800包括：LVDS receiver801、mini-LVDS output data mapping802、transmit803和timing controller 804；其中，
LVDS receiver 801，用于接收低压差分信号LVDS signal；将LVDS signal 进行解码处理得到TTL RGB数据信号TTL RGB data signal和控制信号；所述控制信号包括：启动信号STV、行同步Hsync和场同步Vsync；将所述TTL RGB data signal发送给mini-LVDS output data mapping802，将所述控制信号发送给timing controller804；
本发明第三较佳实施方式并不限制LVDS receiver接收信号的方式。上述LVDS signal可以有两种模式，两种模式分别可以为：同步模式sync mode或使能模式DE mode。
mini-LVDS output data mapping 802，用于对TTL RGB data signal处理得到输入RGB数据input RGB data，将所述nput RGB data发送给所述transmit 803；
上述mini-LVDS output data mapping 802中对TTL RGB data signal处理得到input RGB data的方法可以有多种，本发明第一较佳实施方式可以采用现有技术的任意一种或多种处理方式对TTL RGB data signal处理得到input RGB data，本发明第一较佳实施方式对上述处理方式的具体形式并不限定。
timing controller 804，用于将所述STV时序控制在所述input RGB data时序之前；
上述timing controller 804中的生成STV信号具体可以由TCON IC完成，TCON IC需要控制STV时序在input RGB data时序之前，将STV时序控制在input RGB data时序之前的实现方式可以有多种，本发明第三较佳实施方式并不限制上述时序控制实现方式的具体表现形式。
transmit 803，用于对所述input RGB data处理得到改进低压差分信号mini-LVDS data。
上述transmit 803中的input RGB data的格式可以是TTL(英文全称：Transistor-Transistor Logic，中文：晶体管-晶体管逻辑)格式的数据，而mini-LVDS data的格式可以是LVDS格式的数据，该处理具体可以为，对input RGB data进行数据的排列得到mini-LVDS data。
本发明第三较佳实施方式提供的技术方案通过对STV时序的设置，使得STV时序在input RGB data时序之前，这样能够避免因为STV时序的原因，使得TCON IC丢失input RGB data，参阅图2和图5；图2为现有技术提供的TCON IC中各个信号的时序图，图5为现有技术提供的TCON IC的结构图， 其中，该TCON IC包括：LVDS receiver(中文：低压差分信号接收器)、mini-LVDS output data mapping(改进低压差分信号数据映射模块)、数据缓冲器(line buffer)、transmit(传输模块)和timing controller(时序控制器)。如图2所示，input DE可以为输入的使能信号，input RGB data可以为TCON IC内line buffer输入RGB数据，output RGB data可以为TCON IC内line buffer输出RGB数据，STV是一个TCON IC内生成或产生的起始信号，该STV的作用是在STV时序之后，TCON IC中的才会处理input RGB data；假设input RGB data的时序在STV时序之前，那么位于STV时序之前的input RGB data可能会出现丢失或未处理的情况，此种情况会影响显示屏的数据接收，进而影响其显示效果，所以现有技术通过line buffer对input RGB data延时t2时间得到output RGB data(即line buffer的存储数据)，然后将STV时序以input DE时序为基准延时一个t3，控制t3＜t2，即可以实现STV时序设置在output RGB data时序之前，如图3所示，图3中，Vsync可以为TCON IC的场同步信号；这种设置来防止input RGB data的丢失，但是此种设置是需要设置一个缓存器，即line buffer来存储延时后的数据output RGB data。而本发明第一较佳实施方式采用的技术方案在生成STV时，直接将STV时序控制在input RGB data时序之前，这样就不需要进行缓存，因为对于本发明第一较佳实施方式中的TCON IC来说，此时STV的时序已经控制在input RGB data时序之前，TCON IC已经可以直接对input RGB data进行处理而不会出现input RGB data丢失或未处理的情况发生，所以本发明第三较佳实施方式也无需进行input RGB data的延时，这样就可以去掉line buffer，进而降低成本。
本发明第三较佳实施方式提供的技术方案在接收到LVDS signal，然后对LVDS signal处理得到TTL RGB data signal和控制信号；生成STV，并控制该STV时序在input RGB data时序之前，对TTL RGB data signal处理得到input RGB data；对input RGB data处理得到mini-LVDS data。上述数据处理是直接对input RGB data处理的，所以其并没有对input RGB data进行延时处理，所以也无需line buffer缓存，所以其减少了line buffer，具有降低成本的优点。
优选的，timing controller 804具体可以用于
将所述STV时序tSTV以所述Vsync时序tVsync为基准延时第一设定时间t1； 其中，tVsync+t1＜tm；所述tm为所述input RGB data时序。
上述timing controller 804中的生成STV具体可以由TCON IC完成，TCON IC需要将STV时序tSTV以Vsync时序tVsync为基准延时第一设定时间t1；其中，tVsync+t1＜tm；上述tm具体可以为input RGB data的时序。
优选的，timing controller 804具体可以用于
生成参考信号，将所述STV时序与所述参考信号时序同步，控制参考信号时序t参考以Vsync时序tVsync为基准延时第二设定时间tx；其中，tVsync+tx＜tm；所述tm为所述input RGB data时序。
参阅图9，图9为本发明具体实施方式提供的显示面板结构示意图，该显示面板900包括时序控制芯片800，该时序控制芯片800的结构可以参见本发明第三较佳实施方式提供的结构。
另外，本发明具体实施方式还提供一种显示装置，该显示装置可以包括显示面板，该显示面板包括上述时序控制芯片。该时序控制芯片800的结构可以参见本发明第三较佳实施方式提供的结构。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种时序控制芯片内启示信号控制方法，其特征在于，所述方法包括如下步骤：
    接收低压差分信号LVDS signal；
    对LVDS signal进行解码处理得到晶体管-晶体管逻辑RGB数据信号TTL RGB data signal和控制信号；所述控制信号包括：启动信号STV、行同步Hsync和场同步Vsync；
    对TTL RGB data signal处理得到输入RGB数据input RGB data；
    将所述STV时序控制在所述input RGB data时序之前；
    对所述input RGB data处理得到改进低压差分信号mini-LVDS data。
  2. 根据权利要求1所述的方法，其特征在于，所述将所述STV时序控制在所述mini-LVDS data时序之前具体，包括：
    将所述STV时序tSTV以所述Vsync时序tVsync为基准延时第一设定时间t1；其中，TVsync+t1＜tm；所述tm为所述input RGB data时序。
  3. 根据权利要求1所述的方法，其特征在于，所述将所述STV时序控制在所述input RGB data时序之前具体，包括：
    生成参考信号，将所述STV时序与所述参考信号时序同步，控制参考信号时序t参考以Vsync时序tVsync为基准延时第二设定时间tx；其中，tVsync+tx＜tm；所述tm为所述input RGB data时序。
  4. 根据权利要求1-3任一所述的方法，其特征在于，所述LVDS signal的模式为：
    同步模式sync mode或使能模式DE mode。
  5. 一种时序控制芯片TCON IC，其特征在于，所述TCON IC包括：低压差分信号接收器LVDS receiver、改进低压差分信号数据映射模块mini-LVDS output data mapping、传输模块transmit和时序控制器timing controller；其中，
    所述LVDS receiver，用于接收低压差分信号LVDS signal；将LVDS signa进行解码处理得到晶体管-晶体管逻辑RGB数据信号TTL RGB data signal和控制信号；所述控制信号包括：启动信号STV、行同步Hsync和场同步Vsync；将所述TTLRGB data signal发送给所述mini-LVDS output data mapping，将所 述控制信号发送给所述timing controller；
    所述mini-LVDS output data mapping，用于对TTLRGB data signal处理得到input RGB data，将所述input RGB data发送给所述transmit；
    所述timing controller，用于将所述STV时序控制在所述input RGB data时序之前；
    所述transmit，用于对所述input RGB data处理得到改进低压差分信号mini-LVDS data。
  6. 根据权利要求5所述的芯片，其特征在于，所述timing controller具体，用于
    将所述STV时序tSTV以所述Vsync时序tVsync为基准延时第一设定时间t1；其中，tVsync+t1＜tm；所述tm为所述input RGB data时序。
  7. 根据权利要求5所述的芯片，其特征在于，所述timing controller具体，用于
    生成参考信号，将所述STV时序与所述参考信号时序同步，控制参考信号时序t参考以Vsync时序tVsync为基准延时第二设定时间tx；其中，tVsync+tx＜tm；所述tm为所述input RGB data时序。
  8. 根据权利要求5-7任一所述的芯片，其特征在于，所述LVDS signal的模式为：
    同步模式sync mode或使能模式DE mode。
  9. 一种显示面板，其特征在于，所述显示面板包括如权利要求5-8任一所述的时序控制芯片。
  10. 一种显示装置，其特征在于，所述显示装置包括如权利要求9所述的显示面板。
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