WO2017076117A1 - 一种 led 外延结构及制作方法 - Google Patents

一种 led 外延结构及制作方法 Download PDF

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Publication number
WO2017076117A1
WO2017076117A1 PCT/CN2016/097803 CN2016097803W WO2017076117A1 WO 2017076117 A1 WO2017076117 A1 WO 2017076117A1 CN 2016097803 W CN2016097803 W CN 2016097803W WO 2017076117 A1 WO2017076117 A1 WO 2017076117A1
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Prior art keywords
layer
superlattice
pit
epitaxial structure
led epitaxial
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PCT/CN2016/097803
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English (en)
French (fr)
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张洁
冯向旭
杜成孝
刘建明
徐宸科
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厦门市三安光电科技有限公司
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Publication of WO2017076117A1 publication Critical patent/WO2017076117A1/zh
Priority to US15/849,566 priority Critical patent/US10665748B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to the field of semiconductor optoelectronic devices, and in particular, to an LED epitaxial structure and a fabrication method thereof.
  • a light-emitting diode (Light Emitting Diode in English) is a semiconductor solid-state light-emitting device that uses a semiconductor PN junction as a light-emitting material to directly convert electricity into light.
  • InGa N/GaN light-emitting diodes are regarded as the most promising light source today, but because of the lower hole concentration and lower hole mobility of P-GaN materials, the depth is implanted in multiple quantum wells (MQW).
  • MQW multiple quantum wells
  • the limitation is limited, which further limits the further improvement of the luminous efficiency of GaN-based LEDs.
  • V-type defects are very important hole injection channels in GaN-based LEDs, which greatly improves the efficiency of hole injection.
  • the principle of the V-shaped pit (Pits) naturally formed by the conventional structure is that the temperature of the superlattice growth layer is low, and the lateral epitaxial ability of the nitride (such as GaN) is poor, and the twisting dislocations form a V-pit (Pits).
  • the initial positions of the V-pits are relatively consistent, and the size of the V-pits is also uniform, resulting in higher hole injection efficiency at a specific quantum well (QW) position.
  • QW quantum well
  • Other quantum well (QW) injection efficiency is low, which affects the luminous efficiency.
  • An object of the present invention is to provide an LED epitaxial structure and a manufacturing method thereof, which can significantly improve an LED by inserting at least one layer of a granular dielectric layer during superlattice growth to form V-shaped pits of different widths and depths.
  • the hole injection efficiency and the spatial distribution of holes in the MQW improve the utilization efficiency of all QW holes and the luminous efficiency of the LED.
  • a high hole injection efficiency LED epitaxial structure comprising, in order from bottom to top, a substrate, a first conductive type semiconductor layer, a superlattice, a multiple quantum well layer, and a first a second conductive type semiconductor layer, characterized in that at least one layer of granular dielectric layer is inserted in the superlattice, The particulate dielectric layer is used to form V-shaped pits of different widths and depths in the superlattice, and the multiple quantum well layer fills the V-pit and is located on the top surface of the superlattice.
  • a buffer layer is formed on the substrate, and the material is preferably InAlGaN.
  • the first conductive type semiconductor layer includes an N-GaN layer, or includes a U-GaN layer and N-Ga
  • the second conductive type semiconductor layer includes a P-GaN layer or includes an electron blocking layer and
  • the P-GaN layer or includes an electron blocking layer, a P-GaN layer, and a contact layer.
  • the particle dielectric layer has a particle diameter of 0.5 to 5 nm, and the V-shaped pit has a width of 50 to 500 nm.
  • the V-pit depth H depends on the total thickness of the superlattice T1, the total thickness of the multiple quantum well layer ⁇ 2, and the position of the granular dielectric layer in the superlattice layer, and satisfies ⁇ 2 ⁇ 1+ ⁇ 2.
  • the density of the granular medium layer is substantially corresponding to the V-pit density, and the density is between lx10 7 cm.
  • the granular dielectric layer is made of magnesium nitride (Mg X N y ) or silicon nitride (Si X N y ) or silicon oxide (Si x )
  • Ti x O y titanium oxide
  • Zr x O y zirconia
  • yttrium oxide Hf x O y
  • yttrium oxide Ta x O y
  • a method for fabricating an LED epitaxial structure includes the following steps: (1) providing a substrate; (2) growing a first conductive type semiconductor layer on the substrate (3) growing a superlattice on the first conductive type semiconductor layer, and inserting at least one layer of a granular dielectric layer in the superlattice growth process, the granular dielectric layer being used to form a difference in the superlattice a V-shaped pit of width and depth; (4) growing a plurality of quantum well layers on the V-shaped pit and the top surface of the superlattice; (5) growing a second conductive type semiconductor layer on the multiple quantum well layer .
  • a buffer layer is grown on the substrate, and the material is preferably InAlGaN.
  • the first conductive type semiconductor layer comprises an N-GaN layer, or comprises a U-GaN layer and N-Ga
  • the second conductive type semiconductor layer comprises a P-GaN layer or comprises an electron blocking layer and
  • the P-GaN layer or includes an electron blocking layer, a P-GaN layer, and a contact layer.
  • the particle dielectric layer has a particle diameter of 0.5 to 5 nm, and the V-shaped pit has a width of 50 to 500 nm.
  • the V-pit depth H depends on the total thickness of the superlattice T1, the total thickness of the multiple quantum well layer ⁇ 2, and the particle size The position of the layer in the superlattice layer and satisfies T2 ⁇ H ⁇ T1 + T2.
  • the density of the granular medium layer substantially corresponds to the V-pit density, and the density is between lx10 7 cm -2 and 1 x 10 9 cm 2 .
  • the granular dielectric layer is made of magnesium nitride (Mg X N y ) or silicon nitride (Si X N y ) or silicon oxide (Si x )
  • Ti x O y titanium oxide
  • Zr x O y zirconia
  • yttrium oxide Hf x O y
  • yttrium oxide Ta x O y
  • the superlattice has a growth temperature of 700 to 900 °C.
  • At least one layer of the granular dielectric layer is inserted during the superlattice growth process, and the lateral epitaxial ability is weak due to the lower growth temperature of the superlattice, and the self-extended surface is easy to be self-extended.
  • a V-shaped pit is formed at the layer of the granular medium.
  • the present invention includes at least the following technical effects with respect to the prior art:
  • the present invention adjusts the number of generations of microparticles by introducing and controlling the number of layers, positions, and growth conditions of the granular dielectric layer during superlattice growth. Position, density, and thus control the matching of different depths and densities of the V-shaped pit to change the hole injection effect, effectively improve the hole injection efficiency and the uniformity of distribution in all quantum wells (QW), and improve the luminous efficiency of the LED.
  • QW quantum wells
  • the figure indicates: 1 : substrate; 2: buffer layer; 3: U-GaN layer; 4: N-GaN layer; 5: superlattice;
  • FIG. 1 is a cross-sectional view showing an epitaxial structure of an LED fabricated in accordance with the present invention.
  • FIG. 2 is a schematic top view of an epitaxial structure of an LED fabricated in accordance with the present invention.
  • FIG. 3 is a schematic view showing the position of hole injection of V-holes in different depths in MQW.
  • the embodiment provides an LED epitaxial structure, which includes, in order from bottom to top, a substrate 1, a buffer layer 2, and a first layer including a U-GaN layer 3 and an N-GaN layer 4. a conductive type semiconductor layer, a superlattice 5, a multiple quantum well layer 7, and a second conductive type semiconductor layer including the electron blocking layer 8, the P-GaN layer 9, and the contact layer 10, at least one layer inserted in the superlattice A particulate dielectric layer 6 for forming V-shaped pits of different widths and depths in the superlattice, the multi-quantum well layer 7 filling a V-shaped pit and located above the superlattice.
  • the substrate 1 of the present embodiment is selected from at least one of sapphire (A1 2 0 3 ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge, preferably a flat sapphire substrate.
  • the sapphire substrate may also be a patterned sapphire substrate (PSS), and thus, the embodiment is not limited thereto.
  • the material of the buffer layer 2 is selected from an InAlGaN semiconductor material, formed on the substrate 1 to reduce lattice mismatch caused by the difference in lattice constant between the substrate 1 and the first conductive type semiconductor layer, and to improve epitaxial growth. Quality
  • the U-GaN layer 3 and the N-GaN layer 4 constitute a first conductive type semiconductor layer, which are sequentially formed on the buffer layer 2, and the U-GaN layer 3 can be reduced between the substrate 1 and the N-GaN layer 4 Lattice mismatch caused by poor lattice constant. Moreover, the U-GaN layer 3 can enhance the crystallinity of the semiconductor layer formed on the layer.
  • the superlattice 5 is formed on the first conductive type semiconductor layer by repeatedly alternately stacking the InGaN layer and the GaN layer about 15 times to about 25 times.
  • a three-layered particulate dielectric layer 6 (6A, 6B, 6C) is inserted in the superlattice 5 for forming a V-shaped pit in the superlattice.
  • the granular dielectric layer is made of magnesium nitride (Mg XN y ) or silicon nitride (Si X N y ) or silicon oxide (Si x O y ) or titanium oxide (Ti x O y ) or zirconia (Zr x O y Or oxidation ⁇ (Hf x O y ) or yttrium oxide (Ta x O y ) or a combination thereof, in this embodiment, silicon nitride (Si X N y ), particle size of 0.5 to 5 nm, V-pit depth H (such as H 6A ) is preferred.
  • the density of the silicon nitride particle dielectric layer is The V-shaped pit density corresponds basically, and the density is between lx 10 7 cm -2 and lx 10 "cm - 2 .
  • the semiconductor material of the composition is formed by alternately stacking a plurality of well layers and a plurality of barrier layers, and the number of alternate stacking is preferably 4 to 20 times.
  • the electron blocking layer 8, the P-GaN layer 9, and the contact layer 10 constitute a second conductive type semiconductor layer, which are sequentially formed on the multiple quantum well layer 7.
  • QW-6A, QW-6B and QW-6C respectively indicate the hole injection concentration of the main position of the three deep V-shaped pits in the MQW, and 6A is the deepest V-shaped pit, and the holes pass.
  • the V-pit of this layer is implanted into MQ W, the hole injection is distributed in the lowermost QW; 6B is the V-pit in the middle layer, and holes are injected into the MQW through the V-pit of the layer, and the hole injection is mainly distributed.
  • To the middle QW; 6C is the shallowest V-shaped pit, holes are injected into the MQW through the V-pit of the layer, and the hole injection is mainly distributed to the uppermost QW.
  • the invention improves the spatial distribution and hole injection concentration of holes in the MQW in the LED by adjusting the size, depth and density of the V-shaped pits of each layer of 6A, 6B and 6C, and improves the injection efficiency of all QW holes and the LED. Luminous efficiency.
  • the embodiment provides a method for fabricating an LED epitaxial structure, which includes the following process steps:
  • the substrate can be selected from sapphire (A1 2 0 3
  • At least one of SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge is preferably a patterned sapphire substrate (PSS).
  • PSS patterned sapphire substrate
  • the epitaxial growth method may be selected by MOCVD (metal organic chemical vapor deposition) method, CVD (chemical vapor deposition) method, PECVD (plasma enhancement) Chemical vapor deposition) method, MBE (molecular beam epitaxy) method, HVP E (hydride vapor phase epitaxy) method, preferably MOCVD, but the embodiment is not limited thereto.
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhancement
  • MBE molecular beam epitaxy
  • HVP E hydrogen vapor phase epitaxy
  • the particle dielectric layer preferably has a particle diameter of 0.5 to 5 nm, and the V-shaped pit has a width of 50 to 500 ⁇ m.
  • the V-pit depth H depends on the total thickness of the superlattice T1, the total thickness of the multiple quantum well layer ⁇ 2, and the particles.
  • the position of the dielectric layer in the superlattice layer satisfies ⁇ 2 ⁇ 1+ ⁇ 2; the density of the granular medium layer corresponds to the V-type pit density, and the density ranges from 1x10 7 cm 2 to 1x10 "cm 2
  • the growth order of the three granular media layers is: 6A, 6B and 6C.
  • the size, depth and density of the V-shaped pit need to be optimized with the chip design and operating current. According to the theoretical calculation and reference to the experimental results
  • the depth relationship of the three types of V-shaped pits is preferably: 6A>6B>6C; the depth relationship is: 6A>6B>6C
  • the density relationship is: 6B>6C>6A.
  • the epitaxial growth of the electron blocking layer 8 on the multiple quantum well layer 7, the P-GaN layer 9, and the contact layer 10 constitute a second conductive type semiconductor layer.

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Abstract

提供一种LED外延结构及制作方法，从下至上依次包括：衬底（1）、第一导电类型半导体层（4）、超晶格（5）、多量子阱层（7）以及第二导电类型半导体层（9），其特征在于：在所述超晶格（5）中至少插入一层颗粒介质层（6），所述颗粒介质层（6）用于在所述超晶格（5）中形成不同宽度和深度的V型坑，多量子阱层（7）填充所述V型坑并位于超晶格（5）顶表面上。

Description

发明名称：一种 LED外延结构及制作方法 技术领域
[0001] 本发明涉及半导体光电器件领域， 尤其涉及一种 LED外延结构及制作方法。
背景技术
[0002] 发光二极管 （英文为 Light Emitting Diode, 简称 LED) 是一种半导体固体发光 器件， 其利用半导体 PN结作为发光材料， 可以直接将电转换为光。 现阶段 InGa N/GaN发光二极管被视为当今最有潜力的发光源， 但是因为 P-GaN材料较低的空 穴浓度和较低的空穴迁移率， 在多量子阱 （MQW) 中注入深度比较有限， 严重 限制了 GaN基 LED发光效率的进一步提升。
[0003] 目前越来越多理论研究和试验结果， 证实 V型缺陷是 GaN基 LED中非常重要的 空穴注入通道， 极大地提高了空穴注入效率。 常规结构自然形成的 V型坑 （Pits ) 的原理是超晶格生长层温度较低， 氮化物 （如 GaN) 侧向外延能力较差， 此吋 穿透位错会形成 V型坑 （Pits) ， 但是通过 TEM和 AFM分析可以发现 V型坑 （Pits ) 的形成初始位置比较一致， V型坑 （Pits) 的尺寸也比较一致， 导致在特定的 量子阱 （QW) 位置空穴注入效率较高， 而其它量子阱 （QW) 注入效率较低， 从而影响了发光效率。
技术问题
问题的解决方案
技术解决方案
[0004] 本发明的目的在于： 提供一种 LED外延结构及制作方法， 通过在超晶格生长过 程中插入至少一层颗粒介质层， 以形成不同宽度和深度的 V型坑， 从而明显改善 LED中空穴注入效率和空穴在 MQW中的空间分布， 提高所有 QW对空穴的利用 效率及 LED的发光效率。
[0005] 本发明的第一方面， 提供一种高空穴注入效率 LED外延结构， 该外延结构从下 至上依次包括： 衬底、 第一导电类型半导体层、 超晶格、 多量子阱层以及第二 导电类型半导体层， 其特征在于： 在所述超晶格中至少插入一层颗粒介质层， 所述颗粒介质层用于在所述超晶格中形成不同宽度和深度的 V型坑， 多量子阱层 填充所述 V型坑并位于超晶格顶表面上。
[0006] 优选地， 在所述衬底上形成缓冲层， 材质优选 InAlGaN。
[0007] 优选地， 所述第一导电类型半导体层包括 N-GaN层， 或者包括 U-GaN层及 N-Ga
N层。
[0008] 优选地， 所述第二导电类型半导体层包括 P-GaN层， 或者包括电子阻挡层以及
P-GaN层， 或者包括电子阻挡层、 P-GaN层以及接触层。
[0009] 优选地， 所述颗粒介质层的粒径为 0.5~5nm， 所述 V型坑的宽度为 50~500nm。
[0010] 优选地， 所述 V型坑深度 H取决于超晶格总厚 Tl、 多量子阱层总厚 Τ2及颗粒介 质层在超晶格层中的位置， 并满足 Τ2<Η<Τ1+Τ2。
[0011] 优选地， 所述颗粒介质层的密度为与 V型坑密度基本对应， 密度介于 lxl0 7cm
2至 lxl0 9cm 2。
[0012] 优选地， 所述颗粒介质层材质为氮化镁 (Mg XN y)或氮化硅 (Si XN y)或氧化硅 (Si x
O y)或氧化钛 (Ti xO y)或氧化锆 (Zr xO y)或氧化铪 (Hf xO y)或氧化钽 (Ta xO y)或其组 合。
[0013] 本发明的第二方面， 再提供一种 LED外延结构的制作方法， 包括以下工艺步骤 ： (1) 提供一衬底； （2) 在所述衬底上生长第一导电类型半导体层； （3) 在 所述第一导电类型半导体层上生长超晶格， 在超晶格生长过程中至少插入一层 颗粒介质层， 所述颗粒介质层用于在所述超晶格中形成不同宽度和深度的 V型坑 ； (4) 在所述 V型坑及所述超晶格顶表面上生长多量子阱层； （5) 在所述多量 子阱层上生长第二导电类型半导体层。
[0014] 优选地， 在所述衬底上生长缓冲层， 材质优选 InAlGaN。
[0015] 优选地， 所述第一导电类型半导体层包括 N-GaN层， 或者包括 U-GaN层及 N-Ga
N层。
[0016] 优选地， 所述第二导电类型半导体层包括 P-GaN层， 或者包括电子阻挡层以及
P-GaN层， 或者包括电子阻挡层、 P-GaN层以及接触层。
[0017] 优选地， 所述颗粒介质层的粒径为 0.5~5nm， 所述 V型坑的宽度为 50~500nm。
[0018] 优选地， 所述 V型坑深度 H取决于超晶格总厚 Tl、 多量子阱层总厚 Τ2及颗粒介 质层在超晶格层中的位置， 并满足 T2<H<T1+T2。
[0019] 优选地， 所述颗粒介质层密度与 V型坑密度基本对应， 密度介于 lxl0 7cm - 2至 1 xl0 9cm 2。
[0020] 优选地， 所述颗粒介质层材质为氮化镁 (Mg XN y)或氮化硅 (Si XN y)或氧化硅 (Si x
O y)或氧化钛 (Ti xO y)或氧化锆 (Zr xO y)或氧化铪 (Hf xO y)或氧化钽 (Ta xO y)或其组 合。
[0021] 优选地， 所述超晶格的生长温度为 700~900°C。
[0022] 优选地， 所述步骤 （3) 中， 在超晶格生长过程中至少插入一层颗粒介质层， 由于超晶格的生长温度较低， 侧向外延能力较弱， 容易自外延表面于颗粒介质 层处形成 V型坑。
发明的有益效果
有益效果
[0023] 本发明相对于现有技术， 至少包括以下技术效果： 本发明通过在超晶格生长过 程中引入并控制颗粒介质层的层数、 位置和生长条件， 来调整微颗粒的产生次 数、 位置、 密度， 从而控制 V型坑的不同深度和密度的匹配， 以改变空穴的注入 效果， 有效提高空穴注入效率以及在所有量子阱 （QW) 中的分布均匀性， 提高 LED的发光效率。 对附图的简要说明
附图说明
[0024] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明实 施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描述 概要， 不是按比例绘制。
[0025] 图中标示： 1 : 衬底； 2: 缓冲层； 3: U-GaN层； 4： N-GaN层； 5： 超晶格； 6
(6A、 6B、 6C) ： 颗粒介质层； 7: 多量子阱层； 8: 电子阻挡层； 9: P-GaN层 ； 10： 接触层。
[0026] 图 1为本发明制作的 LED外延结构的剖视示意图。
[0027] 图 2为本发明制作的 LED外延结构的俯视示意图。
[0028] 图 3为不同深度 V型坑空穴注入在 MQW中的位置示意图。 本发明的实施方式
[0029] 下面结合示意图对本发明进行详细的描述， 在进一步介绍本发明之前， 应当理 解， 由于可以对特定的实施例进行改造， 因此， 本发明并不限于下述的特定实 施例。 还应当理解， 由于本发明的范围只由所附权利要求限定， 因此所采用的 实施例只是介绍性的， 而不是限制性的。 除非另有说明， 否则这里所用的所有 技术和科学用语与本领域的普通技术人员所普遍理解的意义相同。
[0030] 实施例 1
[0031] 请参照图 1和图 2， 本实施例提供一种 LED外延结构， 从下至上依次包括： 衬底 1、 缓冲层 2、 包括 U-GaN层 3和 N-GaN层 4的第一导电类型半导体层、 超晶格 5、 多量子阱层 7以及包括电子阻挡层 8、 P-GaN层 9以及接触层 10的第二导电类型半 导体层， 在所述超晶格中至少插入一层颗粒介质层 6， 所述颗粒介质层 6用于在 所述超晶格中形成不同宽度和深度的 V型坑， 多量子阱层 7填充 V型坑并位于所述 超晶格之上。
[0032] 具体来说， 本实施例的衬底 1选用蓝宝石 （A1 20 3) 、 SiC、 GaAs、 GaN、 ZnO 、 Si、 GaP、 InP以及 Ge中的至少一种， 优选平片蓝宝石衬底， 尽管图中未示出 ， 但是蓝宝石衬底也可以是图形化蓝宝石衬底 （PSS) ， 因此， 实施例不限于此
[0033] 缓冲层 2材质选用 InAlGaN半导体材料， 形成于衬底 1上， 以减少由于衬底 1和第 一导电类型半导体层之间的晶格常数差而导致的晶格错配， 改善外延生长质量
[0034] U-GaN层 3和 N-GaN层 4构成第一导电类型半导体层， 依次形成于缓冲层 2上， U -GaN层 3能够减少由于衬底 1和 N-GaN层 4之间的晶格常数差导致的晶格错配。 而 且， U-GaN层 3能够增强形成在该层上的半导体层结晶性能。
[0035] 超晶格 5形成于第一导电类型半导体层上， 采用重复地交替堆叠 InGaN层和 GaN 层大约 15次至大约 25次。 在超晶格 5中插入三层颗粒介质层 6 (6A、 6B、 6C) ， 该颗粒介质层用于在所述超晶格中形成 V型坑。 颗粒介质层材质为为氮化镁 (Mg XN y)或氮化硅 (Si XN y)或氧化硅 (Si xO y)或氧化钛 (Ti xO y)或氧化锆 (Zr xO y)或氧化 铪 (Hf xO y)或氧化钽 (Ta xO y)或其组合， 本实施例优选氮化硅 (Si XN y )， 粒径为 0.5~5nm， V型坑深度 H (如 H 6A) 取决于超晶格总厚 Tl、 多量子阱层 总厚 Τ2及颗粒介质层在超晶格层中的位置， 并满足 Τ2<Η<Τ1+Τ2; 氮化硅颗粒介 质层的密度为与 V型坑密度基本对应， 密度介于 lx 10 7cm -2至 lx 10 "cm -2。
[0036] 多量子阱层 7， 填充 V型坑并位于超晶格 5顶表面上， 多量子阱层可以选择包括 I n XA1 yGa yN (θ≤χ≤1 , 0≤y≤l， 0<x+y≤l) 组成式的半导体材料， 通过交替地 堆叠多个阱层和多个势垒层形成， 交替堆叠次数优选 4~20次。
[0037] 电子阻挡层 8、 P-GaN层 9以及接触层 10构成第二导电类型半导体层， 依次形成 于多量子阱层 7上。
[0038] 请参照图 3， QW-6A、 QW-6B和 QW-6C分别表示三种深度 V型坑在 MQW中的 主要位置空穴注入浓度， 6A为最深一层 V型坑， 空穴通过该层 V型坑注入到 MQ W中吋， 空穴注入分布在最下面的 QW; 6B为中间一层 V型坑， 空穴通过该层 V 型坑注入到 MQW中吋， 空穴注入主要分布至中间的 QW; 6C为最浅一层 V型坑 ， 空穴通过该层 V型坑注入到 MQW中吋， 空穴注入主要分布至最上面的 QW。 本 发明通过对 6A、 6B和 6C各层 V型坑的大小、 深度和密度调控， 改善 LED中空穴 在 MQW中的空间分布和空穴注入浓度， 提高所有 QW对空穴的注入效率及 LED 的发光效率。
[0039] 实施例 2
[0040] 请参照图 1和图 2， 本实施例提供一种 LED外延结构制作方法， 包括以下工艺步 骤：
[0041] (1) 提供一衬底 1， 衬底可以选用蓝宝石 （A1 20 3
) 、 SiC、 GaAs、 GaN、 ZnO、 Si、 GaP、 InP以及 Ge中的至少一种， 优选图形化 蓝宝石衬底 (PSS) 。
[0042] (2) 在衬底 1上外延生长缓冲层 2， 优选 InAlGaN半导体材料， 外延生长方法可 以选用 MOCVD (金属有机化学气相沉积） 方法、 CVD (化学气相沉积） 方法、 PECVD (等离子体增强化学气相沉积） 方法、 MBE (分子束外延） 方法、 HVP E (氢化物气相外延） 方法， 优选 MOCVD, 但实施例不限于此。
[0043] (3) 在缓冲层 2上依次外延生长 U-GaN层 3和 N-GaN层 4， 构成第一导电类型半 导体层。
[0044] (4) 在第一导电类型半导体层上继续外延生长超晶格 5， 生长温度控制在 700~ 900°C， 采用重复地交替堆叠 InGaN层和 GaN层大约 15次至 25次。 在超晶格 5中插 入 3层氮化硅 (Si xN y)颗粒介质层 6 (6A、 6B、 6C) ， 由于超晶格的生长温度较低 ， 侧向外延能力较弱， 容易自外延表面于颗粒介质层处形成不同大小和深度的 V 型坑。 本实施例优选颗粒介质层的粒径为 0.5~5nm， V型坑的宽度介于 50至 500η m， V型坑深度 H取决于超晶格总厚 Tl、 多量子阱层总厚 Τ2及颗粒介质层在超晶 格层中的位置， 并满足 Τ2<Η<Τ1+Τ2; 颗粒介质层密度与 V型坑密度基本对应， 密度介于 1x10 7cm 2至 1x10 "cm 2
。 其中 3层颗粒介质层的生长顺序依次为： 6A、 6B及 6C。 V型坑的大小、 深度和 密度需要与芯片设计和工作电流搭配设计优化， 根据理论推算并参照实验结果
， 本实施例优选 3种 V型坑的深度关系为： 6A>6B>6C; 深度关系为： 6A>6B>6C
； 密度关系为： 6B>6C>6A。
[0045] (5) 在 V型坑以及超晶格顶表面 5上外延生长多量子阱层 7， 多量子阱层材料选 用 In XA1 yGa ^ x— yN (θ≤χ≤1 , 0≤y≤l， 0<x+y≤l) ， 通过交替地堆叠多个阱层和多 个势垒层形成， 交替堆叠次数优选 4~20次。
[0046] (6) 在多量子阱层 7上继续外延生长电子阻挡层 8、 P-GaN层 9以及接触层 10构 成第二导电类型半导体层。
[0047] 以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普通技术 人员， 在不脱离本发明原理的前提下， 还可以做出若干改进和润饰， 这些改进 和润饰也应视为本发明的保护范围。

Claims

权利要求书
[权利要求 1] 一种 LED外延结构， 从下至上依次包括： 衬底、 第一导电类型半导体 层、 超晶格、 多量子阱层以及第二导电类型半导体层， 其特征在于： 在所述超晶格中至少插入一层颗粒介质层， 所述颗粒介质层用于在所 述超晶格中形成不同宽度和深度的 V型坑， 多量子阱层填充所述 V型 坑并位于超晶格顶表面上。
[权利要求 2] 根据权利要求 1所述的一种 LED外延结构， 其特征在于： 所述颗粒介 质层的粒径为 0.5~5nm， 所述 V型坑的宽度为 50~500nm。
[权利要求 3] 根据权利要求 1所述的一种 LED外延结构， 其特征在于： 所述 V型坑 深度 H取决于超晶格总厚 T1、 多量子阱层总厚 T2及颗粒介质层在超晶 格层中的位置， 并满足 T2<H<T1+T2。
[权利要求 4] 根据权利要求 1所述的一种 LED外延结构， 其特征在于： 所述颗粒介 质层密度与 V型坑密度基本对应， V型坑密度介于 1x10 7cm -2至 1x10 " cm - 2。
[权利要求 5] —种 LED外延结构的制作方法， 包括以下工艺步骤：
(1) 提供一衬底；
(2) 在所述衬底上生长第一导电类型半导体层；
(3) 在所述第一导电类型半导体层上生长超晶格， 在超晶格生长过 程中至少插入一层颗粒介质层， 所述颗粒介质层用于在所述超晶格中 形成不同宽度和深度的 V型坑；
(4) 在所述 V型坑及所述超晶格顶表面上生长多量子阱层；
(5) 在所述多量子阱层上生长第二导电类型半导体层。
[权利要求 6] 根据权利要求 5所述的一种 LED外延结构的制作方法， 其特征在于： 所述颗粒介质层的粒径为 0.5~5nm， 所述 V型坑的宽度为 50~500nm。
[权利要求 7] 根据权利要求 5所述的一种 LED外延结构的制作方法， 其特征在于： 所述 V型坑深度 H取决于超晶格总厚 T1、 多量子阱层总厚 T2及颗粒介 质层在超晶格层中的位置， 并满足 T2<H<T1+T2。
[权利要求 8] 根据权利要求 5所述的一种 LED外延结构的制作方法， 其特征在于： 所述颗粒介质层密度与 V型坑密度基本对应， 密度介于 lxl0 7cm - 2至丄 xl0 ¾m 2。
[权利要求 9] 根据权利要求 5所述的一种 LED外延结构的制作方法， 其特征在于： 所述颗粒介质层材质为氮化镁 (Mg XN y)或氮化硅 (Si XN y)或氧化硅 (Si x O y)或氧化钛 (Ti xO y)或氧化锆 (Zr xO y)或氧化铪 (Hf xO y)或氧化钽 (Ta x O y)或其组合。
[权利要求 10] 根据权利要求 5所述的一种 LED外延结构的制作方法， 其特征在于： 所述超晶格的生长温度为 700~900°C。
[权利要求 11] 根据权利要求 5所述的一种 LED外延结构的制作方法， 其特征在于： 所述步骤 （3) 中， 在超晶格生长过程中至少插入一层颗粒介质层， 由于超晶格的生长温度较低， 侧向外延能力较弱， 容易自外延表面于 颗粒介质层处形成 V型坑。
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