WO2017067338A1 - Transistor en couches minces et son procédé de production, substrat matriciel et dispositif d'affichage - Google Patents

Transistor en couches minces et son procédé de production, substrat matriciel et dispositif d'affichage Download PDF

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Publication number
WO2017067338A1
WO2017067338A1 PCT/CN2016/098090 CN2016098090W WO2017067338A1 WO 2017067338 A1 WO2017067338 A1 WO 2017067338A1 CN 2016098090 W CN2016098090 W CN 2016098090W WO 2017067338 A1 WO2017067338 A1 WO 2017067338A1
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Prior art keywords
thin film
film transistor
electrode pattern
region
strip
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PCT/CN2016/098090
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English (en)
Chinese (zh)
Inventor
顾可可
杨妮
胡伟
苟中平
刘信
齐智坚
侯宇松
陈帅
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US15/501,797 priority Critical patent/US10361317B2/en
Publication of WO2017067338A1 publication Critical patent/WO2017067338A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present disclosure relates to display technologies, and in particular, to a thin film transistor and a method of fabricating the same, an array substrate, and a display device.
  • a TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the potential on the pixel electrode has a strict correspondence with the grayscale value of the pixel.
  • Whether the potential of the pixel electrode can reach the required value is mainly determined by performance parameters such as the opening current of the TFT.
  • the aspect ratio (W/L, where W is the channel width and L is the channel length) of the TFT plays a large role in the performance parameters of the TFT.
  • the channel length of the TFT is difficult to be reduced due to the limitation of the process capability, so the method for improving the performance parameter mainly increases the channel width, for example, the channel along the entire direction. Elongated.
  • this type of method increases the size of the TFT, thereby occupying a portion of the area of the light-transmitting region, reducing the aperture ratio of the pixel, and affecting the display effect.
  • the present disclosure provides a thin film transistor and a method of fabricating the same, an array substrate, and a display device, which can increase the aspect ratio of the thin film transistor without reducing the pixel aperture ratio.
  • the present disclosure provides a thin film transistor including a first electrode pattern and a second electrode pattern disposed in a same layer; the first electrode pattern includes a first strip extending in a first direction, the first The two electrode pattern includes a curved portion surrounding the first end of the first strip; the second electrode pattern further includes a second strip extending from the first end of the curved portion in the first direction a region where the channel of the thin film transistor is formed includes a region sandwiched between the bent portion and the first strip portion, and a region sandwiched between the second strip and the first strip.
  • the first electrode pattern further includes a body portion that is in contact with the second end of the first strip.
  • the first electrode pattern and the second electrode pattern are covered with an insulating layer, and a via hole for connecting the body portion is formed in the insulating layer.
  • the shape of the via is circular, semi-circular, square or rectangular.
  • one end of the second strip is aligned with a side edge of the body portion; the channel forming region of the thin film transistor further includes between the second strip portion and the body portion The area of the clip.
  • the thin film transistor further includes an active layer pattern; a formation region of a channel of the thin film transistor is located in a set region of the active layer pattern.
  • the thin film transistor further includes a gate electrode pattern, and the disposed region of the gate electrode pattern includes a formation region of the channel.
  • the thin film transistor further includes an active layer pattern
  • a projection of a formation region of a channel of the thin film transistor in a second direction is within a projection of a set region of the active layer pattern in a second direction; the second direction is perpendicular to the gate electrode pattern.
  • the thin film transistor further includes a gate electrode pattern, and a projection of the formation region of the channel of the thin film transistor in the second direction is located in a set region of the gate electrode pattern.
  • a side of the second strip away from the curved portion is aligned with a side of the body portion away from the curved portion; a forming region of a channel of the thin film transistor further includes the second A region between the strip portion and the body portion.
  • the shape of the curved portion is U-shaped and L-shaped.
  • the present disclosure further provides a method for fabricating any of the above thin film transistors, including:
  • a conductive layer including the first electrode pattern and the second electrode pattern is formed.
  • the present disclosure further provides an array substrate including a thin film transistor disposed in a pixel region; wherein the thin film transistor is a thin film transistor of any of the above.
  • the present disclosure also provides a display device comprising the array substrate of any of the above.
  • the present disclosure can increase the channel width without increasing the installation area of the thin film transistor by the arrangement of the second strip in the second electrode pattern, so that it can be used for device properties. Can increase or reduce the area.
  • the present disclosure can be realized only by changing the pattern shape of the patterning process in the related art, which is advantageous in reducing product cost and improving product performance.
  • FIG. 1 is a schematic structural view of a thin film transistor in the related art
  • FIG. 2 is a partial structural schematic view of a thin film transistor in some embodiments of the present disclosure
  • FIG. 3 is a schematic structural view of a thin film transistor in some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural view of a thin film transistor in some embodiments of the present disclosure.
  • the channel of the TFT is the active layer 12 in the U-shaped region between the source electrode 13 and the drain electrode 14, and the formation region thereof is located in the disposed region of the gate electrode 11. Due to the limitations of the process capability, the channel length of the TFT (such as the spacing between the source electrode 13 and the drain electrode 14 in FIG. 1) is difficult to be reduced, so the method of improving the performance parameter is mainly to increase the channel width (as shown in FIG. 1). The length of the track of the U-shaped channel, such as the channel is elongated in either direction. However, this type of method increases the size of the TFT, thereby occupying a portion of the area of the light-transmitting region, reducing the aperture ratio of the pixel, and affecting the display effect.
  • the thin film transistor includes a first electrode pattern and a second electrode pattern disposed in the same layer.
  • the first electrode pattern as shown in FIG. 2 includes a first strip portion 21a extending in the first direction R1
  • the second electrode pattern includes a first end portion surrounding the first strip portion 21a (in FIG. 2
  • the curved portion 22a is specifically the left end.
  • the second electrode pattern further includes a second strip portion 22b extending from the first end of the curved portion 22a (specifically, the end indicated by a broken line in FIG. 2) in the first direction R1.
  • the channel formation region of the thin film transistor includes both the region A1 sandwiched between the curved portion 22a and the first strip portion 21a, and the second strip portion 22b and the first strip portion 21a. Area A2 sandwiched between. It can be understood that the first electrode pattern and the second electrode pattern respectively form one of a source electrode and a drain electrode of the thin film transistor.
  • first electrode pattern and the second electrode pattern in the embodiment of the present disclosure are disposed in the same layer, and thus can be simultaneously formed by using a predetermined conductor material in a single patterning process.
  • the embodiment of the present disclosure can be realized by changing the shape of the pattern with respect to the patterning process of the drain electrode and the source electrode in the related art.
  • the other structures of the thin film transistor that are not described in the embodiments of the present disclosure may be set according to the type of the selected thin film transistor according to the related art, which is not limited in the disclosure.
  • the channel of the thin film transistor should be located in a layer structure mainly formed of a semiconductor material, and the layer structure should be in direct contact with the first electrode pattern and the second electrode pattern.
  • the embodiment of the present disclosure can increase the channel width without increasing the installation area of the thin film transistor by the arrangement of the second strip in the second electrode pattern, thereby being used for improving device performance or Set the area to decrease.
  • the embodiment of the present disclosure can be realized only by changing the pattern shape of the patterning process in the related art, which is advantageous for the reduction of the product cost and the improvement of the product performance.
  • FIG. 3 is a schematic structural view of a thin film transistor in some embodiments of the present disclosure.
  • the thin film transistor is identical to the thin film transistor shown in FIG. 2: the thin film transistor includes a first electrode pattern and a second electrode pattern disposed in the same layer, wherein the first electrode pattern includes an extension along the first direction R1. a first strip 21a; and the second electrode pattern includes a curved portion 22a surrounding the first end (specifically, the left end in FIG. 3) of the first strip portion 21a, and a first end from the curved portion 22a ( In FIG. 3, specifically, one end marked with a broken line) a second strip extending in the first direction R1 Shape 22b.
  • the thin film transistor in some embodiments of the present disclosure has the following features:
  • the thin film transistor further includes an active layer pattern 23, and a formation region of a channel of the thin film transistor is located in a set region of the active layer pattern.
  • the forming material of the active layer pattern 23 is a semiconductor, and the active layer pattern 23 is in contact with the first electrode pattern and the second electrode pattern to be in the first electrode pattern and the second electrode pattern.
  • a channel of the thin film transistor is formed in a region sandwiched therebetween.
  • the thin film transistor further includes a gate electrode pattern 24, and the set region of the gate electrode pattern 24 includes a formation region of a channel of the thin film transistor.
  • the formation region of the channel of the thin film transistor needs to be covered by the gate electrode of the thin film transistor, and therefore the active layer pattern 23 needs to intersect the gate electrode pattern 24 at least in the formation region of the channel.
  • Stack It can be understood that in order to maintain electrical insulation of each other, an insulating layer (which may be referred to as a "gate insulating layer”) not shown in the drawing should be provided between the active layer pattern 23 and the gate electrode pattern 24, and the present disclosure This is not a limitation.
  • the first electrode pattern further includes a body portion 21b that is in contact with the second end of the first strip portion 21a (specifically, the right end in FIG. 3).
  • the body portion 21b can be used to form an electrical connection of the first electrode pattern.
  • the first electrode pattern and the second electrode pattern may be covered with an insulating layer, and a via hole H1 for connecting the body portion 21b may be formed in the insulating layer.
  • the electrical connection of the conductor layer to the first electrode pattern can be formed in the via hole H1 by forming a conductor layer on this basis.
  • the shape of the via hole H1 may be a circular shape, a semicircular shape, a square shape or a rectangular shape, which is not limited in the present disclosure.
  • the second strip 22b, the body portion 21b, the insulating layer 24, and the via H1 may be disposed as shown in FIG. As shown in FIG. 4, the second direction R2 is perpendicular to the second strip portion 22b, the body portion 21b, and the insulating layer 24.
  • one end of the second strip portion 22b is aligned with one side edge of the main body portion 21b, and specifically, the right end of the second strip portion 22b is aligned with the right side edge of the main body portion 21b in FIG.
  • the formation region of the channel of the thin film transistor is apart from the region A1 between the curved portion 22a and the first strip portion 21a, and the second strip portion 22b and the first strip portion 21a.
  • the area A3 sandwiched between the second strip portion 22b and the body portion 21b is also included. It can be seen that the regions A1, A2 and A3 are covered with the active layer pattern 23 and the gate electrode pattern 24, thus The channels in these regions can form a voltage between the first electrode pattern and the second electrode pattern.
  • the thin film transistor shown in FIG. 3 has the above five features, in other embodiments of the present disclosure, any plurality of features may be selected according to the needs of the application scenario to achieve the desired
  • the technical effect which obviously includes the characteristics of the thin film transistor shown in FIG. 2, can also increase the channel width without increasing the installation area of the thin film transistor, and is advantageous for the reduction of product cost and the improvement of product performance.
  • the disclosure does not limit this.
  • the shape of the curved portion 22a may be L-shaped (all may have a predetermined degree of bending) in addition to being U-shaped. That is, the curved portion 22a may surround the first end of the first strip portion 21a in a U shape or may surround the first end of the first strip portion 21a in an L shape depending on the needs of the specific application. Thereby, the bent portion 22a can surround the first strip portion 21a by other means to form other thin film transistors which can have a larger channel width than the thin film transistor in the related art in a given arrangement area.
  • any of the above thin film transistors may be an N-type transistor or a P-type transistor, and may have a top gate structure or a bottom gate structure, and may be an amorphous silicon (a-Si) TFT or a polysilicon (p-Si) TFT. Any one of the single crystal silicon TFT and the metal oxide semiconductor TFT is not limited in the present disclosure. Therefore, depending on the type of the thin film transistor, the first electrode pattern corresponding to the source electrode or the drain electrode of the transistor can be determined according to the application scenario. In particular, when the thin film transistor has a structure in which the source electrode and the drain electrode are symmetrical, the source electrode and the drain electrode may not be particularly distinguished.
  • some embodiments of the present disclosure provide a method of fabricating any of the above thin film transistors.
  • the method includes forming a conductive layer including the first electrode pattern and the second electrode pattern.
  • the first electrode pattern and the second electrode pattern are disposed in the same layer, and thus can be simultaneously formed in one conductive layer by using a predetermined conductor material in a single patterning process.
  • the embodiment of the present disclosure can be realized by changing the shape of the pattern with respect to the patterning process of the drain electrode and the source electrode in the related art.
  • the embodiments of the present disclosure can be used for improving device performance or reducing the installation area, which is advantageous for product cost reduction and product performance improvement.
  • the method of the embodiments of the present disclosure may include steps of forming other structures than the conductive layer according to the manner of the related art, depending on the specific type and structure of the selected thin film transistor. No restrictions.
  • some embodiments of the present disclosure provide an array substrate, the array base The board includes a thin film transistor disposed in a pixel region; the thin film transistor is a thin film transistor of any of the above.
  • the array substrate of some embodiments of the present disclosure may be disposed in a TFT-LCD or an Active-Matrix Organic Light Emitting Diode (AMOLED) display, and any of the above thin film transistors may be used.
  • AMOLED Active-Matrix Organic Light Emitting Diode
  • an embodiment of the present disclosure provides a display device including the array substrate of any of the above.
  • the display device in this embodiment may be any product or component having a display function, such as a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like. Due to the array substrate including any of the above, the display device provided by the embodiments of the present disclosure can have a higher refresh frequency and pixel resolution, as well as lower product cost and higher product performance.
  • the orientation or positional relationship of the terms “upper”, “lower” and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present disclosure and simplified description. It is not intended or implied that the device or the component of the invention may have a particular orientation, and is constructed and operated in a particular orientation, and thus is not to be construed as limiting the disclosure.
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un transistor en couches minces et un procédé pour sa production, un substrat matriciel et un dispositif d'affichage. Le transistor en couches minces comprend : un premier motif d'électrode et un second motif d'électrode agencés dans la même couche ; le premier motif d'électrode comprend une première partie bande (21a) s'étendant le long d'une première direction (R1), et le second motif d'électrode comprend une partie courbée (22a) entourant une première extrémité de la première partie bande (21a) ; le second motif d'électrode comprend en outre une seconde partie bande (22b) s'étendant depuis la première extrémité de la partie courbée (22a) le long de la première direction (R1) ; la région de formation de canal du transistor en couches minces comprend une région (A1) intercalée entre la partie courbée (22a) et la première partie bande (21a), et une région (A2) intercalée entre la seconde partie bande (22b) et la première partie bande (21a).
PCT/CN2016/098090 2015-10-20 2016-09-05 Transistor en couches minces et son procédé de production, substrat matriciel et dispositif d'affichage WO2017067338A1 (fr)

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CN201510684583.9A CN105140300B (zh) 2015-10-20 2015-10-20 薄膜晶体管及其制作方法、阵列基板和显示装置

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CN105140300B (zh) 2015-10-20 2019-01-18 重庆京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN107204375B (zh) * 2017-05-19 2019-11-26 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法
CN110620154A (zh) * 2019-08-22 2019-12-27 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、阵列基板、显示面板及装置

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KR100497569B1 (ko) * 2002-10-04 2005-06-28 엘지.필립스 엘시디 주식회사 횡전계방식 액정표시장치용 어레이기판
KR101257811B1 (ko) * 2006-06-30 2013-04-29 엘지디스플레이 주식회사 액정표시장치용 어레이 기판과 그 제조방법
KR101339001B1 (ko) * 2012-07-04 2013-12-09 엘지디스플레이 주식회사 액정표시장치용 어레이기판 및 제조방법
CN103178119B (zh) * 2013-03-25 2015-07-29 京东方科技集团股份有限公司 阵列基板、阵列基板制备方法以及显示装置
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CN101354505A (zh) * 2007-07-26 2009-01-28 北京京东方光电科技有限公司 具有螺旋交互源漏电极结构的液晶显示装置
US20120112195A1 (en) * 2010-11-10 2012-05-10 Boe Technology Group Co., Ltd. Array substrate and manufacturuing method thereof, active display
CN105140300A (zh) * 2015-10-20 2015-12-09 重庆京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置

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US10361317B2 (en) 2019-07-23
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CN105140300B (zh) 2019-01-18

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