WO2017067203A1

WO2017067203A1 - Shared protocol layer multi-channel display interface signal generating system

Info

Publication number: WO2017067203A1
Application number: PCT/CN2016/087209
Authority: WO
Inventors: 郑增强; 许恩; 欧昌东; 许笛; 帅敏; 邓标华
Original assignee: 武汉精测电子技术股份有限公司
Priority date: 2015-10-23
Filing date: 2016-06-27
Publication date: 2017-04-27
Also published as: JP6592596B2; KR102070533B1; CN105427772B; KR20180072790A; JP2019504521A; CN105427772A

Abstract

A shared protocol layer multi-channel display interface signal generating system, comprising a data packet and control symbol generating unit (1), a data multiplexing unit (2) and a state monitoring and assembly unit (3), wherein, a signal output end of the data packet and control symbol generating unit (1) is connected through the data multiplexing unit (2) to a signal input end of the state monitoring and assembly unit (3), the state monitoring and assembly unit (3) comprises a plurality of signal assembly channels, and a controlling signal communications terminal of the data multiplexing unit (2) is for connecting a testing state monitoring terminal of each signal assembly channel. The system can reduce occupation of a logic resource by a field programmable gate array, reducing the area occupied by a field programmable gate array resource, while at the same time reducing power consumption by the field programmable gate array, and improving the level of integration thereof.

Description

Multi-channel display interface signal generation system and method for sharing protocol layer

Technical field

The present invention relates to the field of display and test of a liquid crystal module of a DP (DisplayPort display interface) interface, and in particular, to a multi-channel display interface signal generation system and method sharing a protocol layer.

Background technique

As the resolution of small and medium-sized LCD modules (ie, liquid crystal modules of no more than 15 inches) increases, the traditional LVDS (Low-Voltage Differential Signaling) interface cannot meet the size of small-sized LCD modules. Requirements for EMI (Electromagnetic Interference) and power consumption. The reason why the traditional LVDS interface can not meet the above requirements is as follows: as the resolution increases, the bandwidth required for the signal increases accordingly, and the rate of each group of wires of the LVDS interface is low. If the bandwidth is to be increased sharply, A large number of wires are required, and a large number of wires are not conducive to the development of small and medium-sized liquid crystal modules in a thin and light direction, and the cost of wires is also increased, which cannot meet the requirements of volume, EMI and cost.

Therefore, technicians began to use the DP interface as a test interface for small and medium-sized LCD modules. When testing small and medium-sized LCD modules, it is necessary to generate multiple identical DP signals. At present, the method of generating the above multiple multiple DP signals is mainly generated by multiple ASIC (Application Specific Integrated Circuit) dedicated chips. Or FPGA (Field-Programmable Gate Array) direct copy generation, the above conventional methods have the following disadvantages:

1. The ASIC proprietary chip can only support the output of the signal of the separate display interface. When generating the multi-channel display interface signal, multiple chips are needed, and multiple controllers are needed at the same time, which is large in size and high in power consumption.

2. Due to the complexity of the display interface protocol, for the direct copying of the FPGA, the multi-channel display interface is implemented in the field programmable gate array, and the display interface encoder resource is occupied more, occupying the field programmable gate array FPGA resource area.

Summary of the invention

An object of the present invention is to provide a multi-channel display interface signal generating system and method sharing a protocol layer, The system and method can reduce the occupation of the field programmable gate array logic resources, reduce the occupied area of the field programmable gate array resources, reduce the power consumption of the field programmable gate array, and improve the integration degree of the field programmable gate array.

To achieve the above object, a multi-channel display interface signal generating system of a shared protocol layer designed by the present invention includes a data group packet and control symbol generating unit, a data multiplexing unit, and a state monitoring and assembling unit, wherein the data group The signal output end of the packet and control symbol generating unit is connected to the signal input end of the state monitoring and assembling unit through the data multiplexing unit, the state monitoring and assembling unit includes a plurality of signal assembly channels, and the control signal communication end of the data multiplexing unit is used. a test state monitoring end connected to each signal assembly channel; the data packet and control symbol generating unit is configured to generate data stream structure attribute information, a test sequence, and a frame control symbol required by the display interface protocol according to the received external image signal, And grouping the pixel data of the received external image signal according to the display interface protocol; the data multiplexing unit assembling the channel test state according to the signal acquired from the test state monitoring end of the corresponding signal assembly channel, and corresponding data stream structure attribute Information, test sequences, frame control symbols, and pixel data Assigning to a corresponding signal assembly channel in the state monitoring and assembly unit; the state monitoring and assembling unit is configured to receive the received data stream structure attribute information, the test sequence, the frame control symbol, and the pixel data packet according to the test state of each assembly channel Generate corresponding multi-channel display interface signals.

A multi-channel display interface signal generating method sharing a protocol layer includes the following steps:

Step 1: The data group packet and the control symbol generating unit receive external image information, and the data stream packet and the main data stream attribute generator of the control symbol generating unit generate data stream structure attribute information of the display interface protocol according to the external image information;

At the same time, the test sequence generation module generates various types of test sequences required for displaying the interface protocol according to the external image information;

At the same time, the frame control symbol generating module generates a frame control character of the display interface protocol according to the external image information;

At the same time, the pixel data packet module forms a corresponding data packet for the pixel data in the external image information according to the display interface protocol;

Step 2: The data multiplexing unit assembles the channel test state information from the corresponding signal acquired by the test state monitoring end of each signal assembly channel, and according to the test state information, the corresponding data stream structure attribute information, the test sequence, the frame control character, and Pixel data packets are allocated to corresponding signal assembly channels in the state monitoring and assembly unit;

Step 3: Each auxiliary channel signal control and status monitoring module monitors an auxiliary channel of the corresponding liquid crystal display module a communication link test state of the signal communication end, the corresponding control unit assembles the data stream structure attribute information, the test sequence, the frame control character, and the pixel data packet under the rule of the display interface protocol according to the communication link state control signal assembly module, Finally, each signal assembly module generates a corresponding display interface signal, that is, the generation of the multi-channel display interface signal is completed.

The beneficial effects of the invention are:

Compared with the traditional multi-ASIC display chip to generate multi-channel display interface signals, the present invention only needs three data modules: a data packet and a control symbol generating unit, a data multiplexing unit, and a state monitoring and assembling unit. Small, low energy consumption, more suitable for testing small and medium size LCD modules. In addition, compared with the traditional field programmable gate array directly copying and generating the multi-channel display interface signal, the present invention adopts the data multiplexing unit for data distribution, so that the front end only needs to set one data group packet and the control symbol generating unit. The logic resource occupation of the field programmable gate array is reduced, the integration degree of the display interface signal generation system is improved, and the liquid crystal module of more and more miniaturization can be better adapted.

DRAWINGS

Figure 1 is a block diagram showing the structure of the present invention.

Among them, 1 - data packet and control symbol generation unit, 1.1 - main stream attribute generator, 1.2 - test sequence generation module, 1.3 - frame control symbol generation module, 1.4 - pixel data packet module, 2 - data multiplexing Unit, 3-state monitoring and assembly unit, 3.1-signal assembly module, 3.2-control unit, 3.3-auxiliary channel signal control and status monitoring module, 4-serial deserializer.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

The multi-channel display interface signal generating system of the shared protocol layer as shown in FIG. 1 includes a data packet and control symbol generating unit 1, a data multiplexing unit 2, and a state monitoring and assembling unit 3, as described in FIG. The signal output end of the data packet and control symbol generating unit 1 is connected to the signal input end of the state monitoring and assembling unit 3 through the data multiplexing unit 2. The state monitoring and assembling unit 3 includes a plurality of signal assembly channels, and data multiplexing The control signal communication end of unit 2 is used to connect the test state monitoring end of each signal assembly channel; the data group package and the control symbol are generated. The unit 1 is configured to generate data stream structure attribute information, a test sequence, and a frame control symbol required by the display interface protocol according to the received external image signal, and group the pixel data of the received external image signal according to the display interface protocol; The multiplexing unit 2 assembles the channel test state according to the signal acquired from the test state monitoring end of the corresponding signal assembly channel, and assigns the corresponding data stream structure attribute information, the test sequence, the frame control symbol, and the pixel data packet to the state monitoring and assembling unit 3 a corresponding signal assembly channel; the state monitoring and assembling unit 3 is configured to generate the corresponding multi-channel display interface signal according to the test state of each assembly channel by the received data stream structure attribute information, the test sequence, the frame control character and the pixel data packet. .

In the above technical solution, each of the signal assembly channels in the state monitoring and assembling unit 3 includes a signal assembly module 3.1, a control unit 3.2, and an auxiliary channel signal control and status monitoring module 3.3, wherein the signal assembly module 3.1 The signal input end is connected to the signal output end corresponding to the data multiplexing unit 2, and the signal output end of the signal assembly module 3.1 is an output channel of the signal assembly channel, and the output channel of the signal assembly channel is used for connecting the high-speed data signal corresponding to the liquid crystal display module. And a hot plug detection (HPD, Hot Plug Detection) communication terminal, the auxiliary channel signal (AUX, Auxiliary) control and the first communication end of the state monitoring module 3.3 are connected to the auxiliary of the liquid crystal display module The channel signal communication end (ie, the input end), the auxiliary channel signal control and the signal output end of the state monitoring module 3.3 are connected to the signal input end of the corresponding control unit 3.2, and the control signal output end of the control unit 3.2 is connected to the control end of the corresponding signal assembly module 3.1. , the auxiliary channel signal control and the test status monitoring terminal of the status monitoring module 3.3 are connected to the data. The control signal communication terminal of the multiplexing unit 2. The auxiliary channel signal control and status monitoring module 3.3 is responsible for communicating with the auxiliary channel signal communication terminal of the liquid crystal module and monitoring the state of the link. The signal assembly module 3.1 is responsible for assembling the data from the data multiplexing unit 2 into display interface signals according to the state of the link. The control unit 3.2 detects the state of the current link through the auxiliary channel signal control and status monitoring module 3.3, and the control signal assembly module 3.1 operates.

In the above technical solution, the data packet and control symbol generating unit 1 includes a main stream attribute generator 1.1 (MSA Gen, Main Stream Attribute Generator), a test sequence generating module 1.2 (TP Gen), and a frame control symbol generating module 1.3. (Frame Control Symbol Generator) and Pixel Packetizer, wherein the main stream attribute generator 1.1, the test sequence generation module 1.2, the frame control symbol generation module 1.3, and the pixel data packet module 1.4 The signal input terminal can receive external image signals, the main data stream attribute generator 1.1, the test sequence generation module 1.2, the frame control symbol generation module 1.3, and the pixel data group package module 1.4. The signal output terminal is connected to the signal input terminal of the data multiplexing unit 2.

In the above technical solution, the output channels of each of the signal assembly channels are connected with corresponding serial deserializers 4 (SERDES), and the output channels of each signal assembly channel are connected by corresponding serial deserializers 4 High-speed data signal and hot-swap detection signal communication terminal of the liquid crystal display module. The serial deserializer 4 is used to convert the encoded parallel data into serial data output.

Step 1: The data packet and control symbol generating unit 1 receives external image information, which may be generated by a video signal generator, or may be through a TTL signal (transistor transistor logic) or an LVDS signal or MIPI signal (Mobile Industry Processor Interface) or VX1 signal (V-By-One, digital interface standard dedicated to image transmission) demodulated, the data packet and control symbol generating unit 1 main The data stream attribute generator 1.1 generates data stream structure attribute information of the display interface protocol according to the external image information;

At the same time, the test sequence generation module 1.2 generates various types of test sequences required for displaying the interface protocol according to the external image information;

At the same time, the frame control symbol generating module 1.3 generates a frame control character of the display interface protocol according to the external image information;

At the same time, the pixel data group packet module 1.4 forms a corresponding data packet for the pixel data in the external image information according to the display interface protocol;

Step 2: The data multiplexing unit 2 assembles the channel test state information from the corresponding signal obtained by the test state monitoring end of each signal assembly channel, and according to the test state information, the corresponding data stream structure attribute information, the test sequence, and the frame control character. And the pixel data packet is allocated to the corresponding signal assembly channel in the state monitoring and assembling unit 3;

Step 3: Each auxiliary channel signal control and status monitoring module 3.3 monitors the communication link test status of the auxiliary channel signal communication end of the corresponding liquid crystal display module, and the corresponding control unit 3.2 assembles the module 3.1 pair data according to the communication link state control signal. The stream structure attribute information, the test sequence, the frame control character and the pixel data packet are assembled under the rules of the display interface protocol, and finally each signal assembly module 3.1 generates a corresponding display interface signal, that is, the generation of the multi-channel display interface signal is completed.

In the above technical solution, the data stream structure attribute information includes a position parameter between the field synchronization signal, the line synchronization signal, and the data valid signal.

In the above technical solution, the position parameters between the field sync signal, the line sync signal and the data valid signal include a front shoulder, a back shoulder, a pulse width, and a field blanking and line blanking parameter.

In the above technical solution, the frame control character includes a blank start control (BS, Blank Start), a blank end control (BE, Blank End), and a video frame start control (FS, Frame Start). And the video frame end control character (FE, Frame End).

In the above technical solution, the communication link test state of the auxiliary channel signal communication end of the liquid crystal display module includes a recovery clock training state, a symbol alignment training state, and a video mode state.

The test sequence in step 1 of the above technical solution includes a recovery clock training test sequence and a symbol alignment training test sequence.

The contents not described in detail in the specification belong to the prior art known to those skilled in the art.

Claims

A multi-channel DP interface signal generating system sharing a protocol layer, comprising: a data group packet and a control symbol generating unit (1) and a state monitoring and assembling unit (3) disposed in a field programmable gate array, The state monitoring and assembling unit (3) includes a plurality of signal assembly channels; wherein

The data packet and control symbol generating unit (1) is configured to generate data stream structure attribute information, a test sequence, and a frame control symbol required by the DP interface protocol according to the external image signal, and use the DP interface protocol to the external unit according to the DP interface protocol. Pixel data of the image signal is subjected to a group packet operation to generate a pixel data packet;

The state monitoring and assembling unit (3) is configured to: the data stream structure attribute information, the test sequence, the frame control character, and the pixel according to the communication link state control signal and the DP interface protocol in each of the signal assembly channels The data packet is assembled to generate a plurality of DP interface signals corresponding to the respective signal assembly channels.
The multi-channel DP interface signal generating system of the shared protocol layer according to claim 1, wherein each of said signal assembling channels in said state monitoring and assembling unit (3) comprises a signal assembling module (3.1) and Auxiliary channel signal control and status monitoring module (3.3);

The auxiliary channel signal control and status monitoring module (3.3) is configured to receive and monitor a communication link state control signal of the auxiliary channel of the signal assembly channel;

The signal assembly module (3.1) is configured to assemble the data stream structure attribute information, the test sequence, the frame control function, and the pixel data packet according to the communication link state control signal and the DP interface protocol to generate a DP interface. signal.
The multi-channel DP interface signal generating system of the shared protocol layer according to claim 1, further comprising a data multiplexing unit (2) disposed in the field programmable gate array, the data multiplexing unit (2) assigning the data stream structure attribute information, the test sequence, the frame control character, and the pixel data packet to the respective signal assembly channels according to communication link state control signals of the respective signal assembly channels.
The multi-channel DP interface signal generating system of the shared protocol layer according to claim 1, wherein the data packet and control symbol generating unit (1) comprises a main stream attribute generator (1.1) and a test sequence generating module. (1.2), a frame control symbol generating module (1.3) and a pixel data packet module (1.4); wherein

The primary data stream attribute generator (1.1) is configured to generate, according to the external image information, the data stream structure attribute information required by the DP interface protocol;

The test sequence generating module (1.2) is configured to generate the test sequence required by the DP interface protocol according to the external image information;

The frame control symbol generating module (1.3) is configured to generate, according to the external image information, the frame control character required by a DP interface protocol;

The pixel data packet module (1.4) is configured to perform the grouping operation on the pixel data of the external image signal according to the DP interface protocol to generate the pixel data packet.
A multi-channel DP interface signal generating method sharing a protocol layer, characterized in that it comprises the following steps:

Step 1: receiving an external image signal, and generating data stream structure attribute information, a test sequence, and a frame control symbol required by the DP interface protocol according to the external image signal; and simultaneously, the external image signal according to the DP interface protocol Pixel data is grouped to generate a pixel data packet;

Step 2: Acquire a communication link state control signal of each signal assembly channel, and allocate the data stream structure attribute information, a test sequence, a frame control symbol, and a pixel data packet to the respective according to the communication link state control signal. Signal assembly channel;

Step 3: assembling the data stream structure attribute information, the test sequence, the frame control function, and the pixel data packet according to the communication link state control signal and the DP interface protocol in each of the signal assembly channels to generate the respective The multi-channel DP interface signal corresponding to the signal assembly channel.
The multi-channel DP interface signal generating method of the shared protocol layer according to claim 5, wherein the data stream structure attribute information comprises a position parameter between the field sync signal, the line sync signal and the data valid signal.
The multi-channel DP interface signal generating method of the shared protocol layer according to claim 6, wherein the positional parameter between the field sync signal, the line sync signal and the data valid signal comprises a front shoulder, a back shoulder, and a pulse width. , as well as field blanking and line blanking parameters.
The multi-channel DP interface signal generating method of the shared protocol layer according to claim 5, wherein the frame control character comprises a blanking area start control character, a blanking area end control character, and a video frame start control character. And the video frame end control character.
The multi-channel DP interface signal generating method of the shared protocol layer according to claim 5, wherein the communication link state control signal comprises a recovery clock training state, a symbol alignment training state, and a video mode state.
The multi-channel DP interface signal generating method of the shared protocol layer according to claim 5, wherein the test sequence comprises a recovery clock training test sequence and a symbol alignment training test sequence.