CN213960238U

CN213960238U - Display device and system

Info

Publication number: CN213960238U
Application number: CN202022752956.0U
Authority: CN
Inventors: 张海; 魏杰
Original assignee: Suzhou HYC Technology Co Ltd
Current assignee: Suzhou HYC Technology Co Ltd
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2021-08-13
Anticipated expiration: 2030-11-25

Abstract

An embodiment of the utility model provides a display device and system, this display device includes: an image outputter including a plurality of signal transmission lines; a bridge comprising a signal interface coupled to each signal transmission line; and the display module is coupled with the bridge connector and displays images. The utility model provides a display device, structurally reasonable in design, easy operation, extensive applicability easily realizes and uses, merges multichannel image signal into the mode for showing the signal through setting up the bridge, realizes the stronger advantage of variability, and compatible less resolution ratio is to the functional demand of higher resolution ratio and various refresh rates, and this display device operation is stable, and the display module group display effect is good, has good application prospect.

Description

Display device and system

Technical Field

The utility model relates to a show technical field, more specifically relates to a display device and system.

Background

With the rapid development of technologies in the fields of communication, media, games, etc., more and more applications require higher resolution, higher refresh rate, and lower latency in order to accomplish their tasks, such as gesture recognition, automatic driving, etc. A high refresh rate may not only improve the quality of moving images, but also help to improve the experience of people with 3D video. Particularly, with the development of the display industry in recent years, the market demand for display modules with high refresh rate and high resolution is increasing.

The display module is a modern flat display screen formed by dot matrix modules or pixel units, and has the advantages of high luminous efficiency, long service life, wide visual angle range, rich colors, strong adaptability to indoor and outdoor environments and the like.

However, no device is currently available that can light up the high resolution (e.g., 2560x 1440 resolution) and high refresh rate (e.g., 120Hz refresh rate) requirements.

SUMMERY OF THE UTILITY MODEL

The present application is directed to a display device and a system, which solve at least one of the problems of the prior art.

In order to achieve the purpose, the following technical scheme is adopted in the application:

a first aspect of the present application provides a display device comprising:

an image outputter including a plurality of signal transmission lines;

a bridge comprising a signal interface coupled to each signal transmission line;

and the display module is coupled with the bridge and displays images.

In one possible implementation manner, the method further includes:

and the main control chip is in communication connection with the image output device and an external upper computer, and is used for receiving the display parameter information sent by the upper computer and outputting the display parameter information to the image output device so that the image output device generates the display time sequence.

In one possible implementation, the image outputter includes:

the processing chip and the memory are respectively coupled with the main control chip, the processing chip receives display parameter information to further generate the display time sequence, and the memory receives and stores the image signal.

In a possible implementation manner, the main control chip is an ARM chip.

In one possible implementation, the display device further includes:

and the power supply controller receives the display module power supply information transmitted by the ARM chip and generates a voltage regulation signal.

In one possible implementation manner, the processing chip is an FPGA chip; and/or

The bridge is an FPGA chip.

In one possible implementation manner, the bridge includes an MIPI CPHY output interface, the display module includes an MIPI CPHY input interface, and the MIPI CPHY output interface is coupled with the MIPI CPHY input interface.

In one possible implementation, the MIPI CPHY interface is of the model SSD 2832.

In one possible implementation, the number of signal transmission lines is 4.

A second aspect of the present application provides a display system comprising: the display device, the main control chip and the upper computer; the display device includes:

an image outputter including a plurality of signal transmission lines;

the display module is coupled with the bridge and displays images;

the main control chip is in communication connection with the image output device and the upper computer.

The beneficial effects of the utility model

The utility model provides a display device and system, this display device includes: an image output device including a plurality of signal transmission lines, each of which transmits one of the image signals according to a display timing; a bridge including a signal interface coupled to each signal transmission line and for combining the image signals into a display signal; and display module assembly receives the display signal to the demonstration corresponds the image, the utility model provides a display device, structurally reasonable in design, easy operation, extensive applicability easily realizes and uses, merges multichannel image signal into the mode of showing the signal through setting up the bridge, realizes the stronger advantage of variability, and compatible less resolution ratio is to the functional demand of higher resolution ratio and various refresh rates, and this display device operation is stable, and display module assembly display effect is good, has good application prospect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic view of a display device according to an embodiment of the present invention.

Reference numerals: 1. processing the chip; 2. a memory; 3. a power supply controller; 4. a main control chip; 5. a bridge; 6. a display module; 7. a memory module; 8. a storage module; 9. and (4) an upper computer.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, the "coupling" of the first and second components may include an embodiment in which the first and second components are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first and second components, so that the first and second components may not be in direct contact, or the first and second components may also be connected by a signal.

In addition, the technical solutions in the embodiments can be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or can not be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

In order to solve the above problem, please refer to fig. 1, an embodiment of the present invention provides a display device, including: an image output device (as the

reference numbers

1 and 2 in the figure jointly form) comprising a plurality of signal transmission lines, wherein each signal transmission line transmits one path of image signals according to the display time sequence; a bridge 5 including a signal interface coupled to each signal transmission line, and for combining the image signals into a display signal; and a display module 6 coupled to the bridge 5 for receiving the display signal and displaying a corresponding image.

The utility model provides a display device, structurally reasonable in design, easy operation, extensive applicability easily realizes and uses, merges the mode for showing the signal with multichannel image signal through setting up the bridge to output the image of higher resolution ratio and higher refresh rate, and this display device operation is stable, and the display module display effect is good, has good application prospect.

It can be understood that the embodiment of the utility model discloses the mode of embodiment is for showing the signal through setting up the bridge and merging the multichannel image signal, through the image data merge, realizes the stronger advantage of variability, compatible less resolution ratio to the functional requirement of higher resolution ratio and various refresh rates.

It should be noted that the present invention provides a method for implementing existence in the prior art, which can integrate the above-mentioned merging method through the existing control chip, the core of the present invention is the structural combination of the bridge cooperating with the display device, which achieves the effect of displaying the corresponding image, and the method of how to execute the control chip to the bridge can adopt the known technology in the art, and is not repeated herein.

It can be understood that the display module is used for displaying corresponding images, can be LCD, OLED, LED, etc., the utility model discloses do not do the restriction.

In some preferred embodiments, the display device further comprises: and the main control chip 4 is in communication connection with the image output device (formed by the

reference numerals

1 and 2 in the figure) and an external upper computer 9, and is used for receiving display parameter information sent by the upper computer 9 and outputting the display parameter information to the image output device so that the image output device generates the display time sequence.

It is understood that the communication connection may be a wired connection, such as a USB interface; or wireless network connection, such as 4G signal connection, 5G signal connection etc., the utility model discloses do not do the restriction, make there is signal transmission between main control chip 4 and image output ware (constitute like

reference numeral

1 and 2 in the figure jointly) and the outside host computer 9.

It should be noted that the display parameter information includes the resolution, the front and back shoulders, the refresh rate, the image data, the power information of the display module 6, and the like, which are acquired from the upper computer 9 by the main control chip 4 through network communication.

In some preferred embodiments, the image outputter includes: the display device comprises a processing chip 1 and a memory 2, wherein the processing chip 1 and the memory 2 are respectively coupled with the main control chip 4, the processing chip 1 receives display parameter information to further generate the display time sequence, and the memory 2 receives and stores the image signal.

In a further embodiment, the main control chip 4 further includes a memory unit 7 and a storage unit 8, the resolution, the front shoulder, the back shoulder, the refresh rate, the image data, and the display module power information of the display module 6 acquired from the upper computer 9 are stored in the file system of the main control chip 4, after each start-up, the image data is transmitted to the memory 2 through the PCIE communication method, and all the parameter information of the display module 6 is transmitted to the processing chip 1.

Those skilled in the art know that PCIE, i.e., PCI express (peripheral component interconnect express), is a high-speed serial computer expansion bus standard. PCIE belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, connected equipment distributes independent channel bandwidth and does not share bus bandwidth, and mainly supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like.

Preferably, the main control chip 4 is an ARM chip.

In some preferred embodiments, the display device further comprises: and the power controller 3 receives the display module power information transmitted by the ARM chip 4 and generates a voltage regulation signal.

The power controller 3 supplies power to all the sub-modules, and generates corresponding voltage according to the display module power information transmitted by the ARM chip 4 and sends the voltage into the display module.

It can be understood that after each start, the image data is transmitted to the memory 2 in a PCIE communication manner, all parameter information of the display module 6 is transmitted to the processing chip 1, and meanwhile, power information of the display module 6 is also transmitted to the power controller 3. The power controller 3 receives the display module power information transmitted by the ARM chip 4 and generates a voltage regulation signal, and then the power controller 3 generates a voltage matched with the display module 6 to drive the display module to display a corresponding image.

Preferably, the processing chip is an FPGA chip; and/or the bridge is an FPGA chip.

It is understood that an FPGA (Field-Programmable Gate Array), which is a product of further development on the basis of Programmable devices such as PAL, GAL, CPLD, etc., is a Field-Programmable Gate Array. It appears as a semi-custom circuit in the Application Specific Integrated Circuit (ASIC) field, the utility model discloses embodiment adopts the FPGA chip both to solve the not enough of custom circuit, has overcome the limited shortcoming of original programmable device gate circuit number again.

The Field Programmable Gate Array (FPGA) has high-speed parallel data processing capacity, and is suitable for being used as a control core of a large-scale real-time system. The programmable technology of the FPGA device makes the programmable device more convenient to use. Therefore, the FPGA is used for realizing the processes of video image acquisition, storage, data processing, display and the like, and has the advantages of high refresh rate, real-time display, long-time stable operation and the like.

It can be understood that the processing chip 1 outputs the configuration signal according to the parameter information of the display module transmitted by the ARM chip 4, further configures the bridge 5, generates the corresponding display module display time sequence at the same time, and outputs the RGB image signals corresponding to the number of paths according to the time sequence requirement while outputting the time sequence.

In some preferred embodiments, the bridge includes a MIPI CPHY output interface, the display module includes a MIPI CPHY input interface, and the MIPI CPHY output interface is coupled to the MIPI CPHY input interface.

Correspondingly, the transmission signal between the bridge and the display module is an MIPI CPHY signal.

It can be known that the bridge 5 completes the configuration of the bridge 5 itself according to the received configuration signal, specifically, the bridge converts the input RGB signal into the MIPI-CPHY signal, so that the bridge needs to be informed first of the resolution corresponding to the input signal, the blanking region, the number of channels of the input signal and some initialization codes that need to be issued to the module end through the bridge, so that the bridge analyzes and converts the input RGB signal into the corresponding MIPI-CPHY signal according to the parameters. After the configuration is completed, the multi-path image signals and the module display timing sequence output by the processing chip 1 are transmitted to the bridge 5. The bridge 5 combines the multi-path image signals input by the processing chip 1 into MIPI CPHY signals and outputs the MIPI CPHY signals to the display module 6, so that images with corresponding resolution and refresh rate are displayed.

It should be noted that, because the pixel clocks of the multiple channels are independent, when the bridge is switched, according to the configuration of the bridge, under the condition of multiple channels, the bridge samples a pixel clock waveform, each pixel always samples image data of several channels in one period, then multiplies the pixel clock by multiple frequencies (several channels multiply by several times), then uses a new multiplied clock to convert the sampled data of several channels into single-channel RGB signals, and then the signals are converted into MIPI CPHY signals by the bridge and sent to the module end.

It should be noted that the bridge 5 may be formed by an existing chip module and a peripheral circuit, or may be formed by another FPGA chip to implement the above functions

Preferably, the MIPI CPHY interface is in the model of SSD 2832.

It can be understood that the image output device includes a plurality of signal transmission lines, such as 4-way, 6-way, 8-way, etc., without limitation.

In some embodiments, the number of the signal transmission lines is 4, and the module display signal corresponding to the resolution and the refresh rate can be output through image data combination.

In a specific embodiment, the above embodiment is implemented by an ARM chip, an FPGA chip, and an SSD2832 mobile interface, and the implementation of the architecture has the advantage of strong variability, and is compatible with functional requirements from a small resolution to a high resolution and various refresh rates. And a Linux operating system is operated in the ARM, network instructions are processed, and image data is stored and transmitted. And (3) outputting RGB image data corresponding to the resolution and the refresh rate in the FPGA chip through verilog and IP core coordination processing. The SSD2832 automatically combines the multiple RGB image data according to the input of the image data and converts the combined image data into an MIPI CPHY signal.

Equally, the utility model provides an embodiment is the method of existence among the prior art, can be through the integrated above-mentioned merging methods of current control chip, the utility model discloses a core lies in setting up ARM chip, FPGA chip and SSD2832 and removes interface cooperation display device's structural grouping, reaches the effect that shows corresponding image, can adopt the technique known in the art to how to carry out ARM chip, FPGA chip and SSD2832 and remove the method of interface, does not do here and describe repeatedly.

Can know from above-mentioned embodiment, the utility model provides a display device, structural design is reasonable, easy operation, and extensive applicability easily realizes and uses, merges multichannel image signal into the mode of showing the signal through setting up the bridge, realizes the advantage that the variability is stronger, and compatible less resolution ratio is to the functional demand of higher resolution ratio and various refresh rates, and this display device operation is stable, and display module display effect is good, has good application prospect.

Based on the same concept of the present invention, please refer to fig. 1, another embodiment of the present invention provides a display system, which includes: the display device, the main control chip 4 and the upper computer 9; the display device includes: an image output device (such as a processing chip 1 and a memory 2 combined in the figure) comprising a plurality of signal transmission lines, wherein each signal transmission line transmits a path of image signals according to a display time sequence; a bridge 5 including a signal interface coupled to each signal transmission line, and for combining the image signals into a display signal; and a display module 6 coupled to each bridge 5 for receiving the display signal and displaying a corresponding image.

Specifically, the main control chip 4 is in communication connection with the image output device and the upper computer 9, and is configured to receive display parameter information sent by the upper computer 9 and output the display parameter information to the image output device, so that the image output device generates the display time sequence.

The utility model provides a display system, structurally reasonable in design, easy operation, extensive applicability easily realizes and uses, merges multichannel image signal into the mode for showing the signal through setting up the bridge, realizes the stronger advantage of variability, and compatible less resolution ratio is to the functional demand of higher resolution ratio and various refresh rates, and this display device operation is stable, and the display module group display effect is good, has good application prospect.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the system embodiment, since it is substantially similar to the device embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the device embodiment.

In the description of the present specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present specification. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.

Furthermore, the various embodiments or examples and features of the various embodiments or examples described in this specification can be combined and combined by those skilled in the art without contradiction. The above description is only an embodiment of the present disclosure, and is not intended to limit the present disclosure. Various modifications and changes may occur to those skilled in the art to which the embodiments of the present disclosure pertain. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present specification should be included in the scope of the claims of the embodiments of the present specification.

Claims

1. A display device, comprising:

an image outputter including a plurality of signal transmission lines;

and the display module is coupled with the bridge and displays images.

2. The apparatus of claim 1, further comprising:

and the main control chip is in communication connection with the image output device and an external upper computer, and is used for receiving the display parameter information sent by the upper computer and outputting the display parameter information to the image output device so that the image output device generates a display time sequence.

3. The apparatus of claim 2, wherein the image outputter comprises:

the processing chip and the memory are respectively coupled with the main control chip, the processing chip receives display parameter information to further generate the display time sequence, and the memory receives and stores image signals.

4. The apparatus of claim 3, wherein the main control chip is an ARM chip.

5. The apparatus of claim 4, wherein the display device further comprises:

6. The apparatus of claim 3,

the processing chip is an FPGA chip; and/or

The bridge is an FPGA chip.

7. The apparatus of claim 3,

the bridge comprises an MIPI CPHY output interface, the display module comprises an MIPI CPHY input interface, and the MIPI CPHY output interface is coupled with the MIPI CPHY input interface.

8. The apparatus of claim 7,

the model of the MIPI CPHY interface is SSD 2832.

9. The apparatus of claim 1,

the number of the signal transmission lines is 4.

10. A display system, comprising: the display device, the main control chip and the upper computer; the display device includes:

an image outputter including a plurality of signal transmission lines;

the display module is coupled with the bridge and displays images;