KR101550810B1 - Connector for mhl/hdmi and signal converting method using the same - Google Patents

Abstract

In the present invention, a parallel HDMI signal is converted using an HDLCP-certified MHL clock and data using an MHL demultiplexer. In the subsequent step, the HDMI signal is processed without discrimination from an HDMI signal And generates an HDMI Tx PHY.
The MCH EL / HMI connection device of the present invention can reduce the hardware overhead since the MHL signal is first converted into the HDMI signal before the HDMI Link Rx.

Description

TECHNICAL FIELD [0001] The present invention relates to an apparatus and a method for converting a signal,

[0001] The present invention relates to a MIL-L / DM-i connection device and a signal conversion method using the same, and more particularly, to a MIL-L / And a signal conversion method using the same.

As various multimedia environments are developed, video and audio formats are being used in a variety of high-definition formats.

Conventional monitors and digital televisions often have terminals such as HDMI (High Definition Multimedia Interface) as a video interface in order to receive a large amount of digital data from other devices such as a computer or a DVD player.

However, HDMI terminals operate at high frequencies and are standardized for personal computers. These devices are defined in situations where there is little concern about power consumption, so they usually require a lot of power and are suitable for portable terminals that require low power driving not.

In order to overcome this problem, a mobile high-definition link (MHL) is used as an interface of a portable terminal for use in transmitting data for realizing high-resolution video to a device having an HDMI terminal such as an external computer monitor or a high- The interface has been developed.

Therefore, a personal computer or a digital television needs to receive not only data input from the HDMI source but also data input from the MHL source. However, as shown in FIG. 1, data of an HDMI signal and an MHL signal have different forms. The HDMI signal (FIG. 1 (a)) is input to four signal lines and is a clock, a data stream 0, a data stream 1, and a data stream 2, . When the data converted into the parallel data by the PHY is compared according to the clock, the HDMI signal has data of blue, green, and red in one pixel clock as shown in FIG. 1 (c) While the MHL signal is synchronized with a clock three times faster than the pixel clock as shown in FIG. 1 (d), so that data relating to the blue, green, and red pixels are serially input.

2 is a block diagram of a conventional MJL / HJDMI connection device. The MCH EL / HMI connection device receives the MHL input from the MHL source, receives the HDMI input from the HDMI source, and outputs it as an HDMI signal converted into serial data. The HDMI / MHL Rx PHYs 11 and 21 are modules for converting an input serial MHL or HDMI signal into a parallel signal. An HDCP (High-bandwidth Digital Content Protection) 13 and 23 are connected to an MHL device And the MHL link Rx 15 is a module for separating video, audio, and control signals from the input parallel-transformed MHL signal, and the MHL link Tx 17 is a module for authenticating an HDMI device that provides input, And a module for generating an MHL signal for transmitting a control signal. The HDMI link Rx 25 is a module for separating video, audio, and control signals from the input parallel-converted HDMI signal. The HDMI link Tx 27 combines video, audio, and control signals to generate an HDMI signal for transmission . The clock converter 29 is a module for converting an MHL clock (three times pixel clock) into a pixel clock, and the multiplexer 42 is a module for selecting a clock-converted MHL link Tx signal and an HDMI link Tx, ), And the HDMI Tx PHY 41 is a module for serializing a parallel HDMI signal. As shown in FIG. 2, since the conventional MJL / HDMI DM connection device is converted into the same clock as the HDMI signal at the rear end of the MHL link Tx, a frequency that is three times the pixel clock is used in the previous step, In addition, since the MHL link Rx 15, the HDMI link Rx 25, the MHL link Tx 17, and the HDMI link Tx 27 must be separately configured, the hardware complexity increases.

Patent Document 1: Korean Published Patent Application No. 10-2012-0096944 (published on Aug. 31, 2012)

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method and apparatus for reducing the hardware complexity by minimizing the redundant hardware configuration and using a frequency as low as three times the pixel clock, And a signal conversion method DMF using the same.

The above object of the present invention is achieved by an MHL device for providing an MHL signal and a MIL-L / H di-i connection device for receiving an MHL input and an HDMI input input from an HDMI device providing an HDMI signal, An HDMI / MHL Rx PHY for converting an HDMI signal or an MHL signal input as a serial into a parallel signal separated into a clock and a data format, an HDCP for authenticating the MHL device and the HDMI device, a parallel-converted MHL signal An MHL demultiplexer which receives the clock and data of the HDMI clock signal and converts it into an HDMI clock and data format, a multiplexer for selecting one of the clock and data of the HDMI signal authenticated through the HDCP and the output signal of the MHL demux, An HDMI Link Rx for separating video, audio, and control signals from the parallel-converted HDMI signal selected by the multiplexer, And an HDMI Tx PHY for converting a parallel HDMI signal output from the HDMI Link Tx and the HDM Link Tx to generate a parallel HDMI signal for combining the audio signal and the control signal and outputting the converted serial signal to the HDMI Tx PHY. RTI ID = 0.0 > EL / H. < / RTI >

Yet another object of the present invention is to provide an MHL device that provides an MHL signal, and a method of converting a MHL input signal and an HDMI input signal input from an HDMI device providing an HDMI signal and outputting the MHL input and the HDMI input signal as an HDMI output signal A first step of converting an HDMI signal or an MHL signal input as a serial into a parallel signal separated into a clock and a data format; a second step of authenticating the MHL device and the HDMI device; A third step of receiving the clock and data of the parallel-converted MHL signal and converting the clock and data of the parallel-converted MHL signal into an HDMI clock and a data format, a clock and data of the HDMI signal authenticated through the HDCP, A fifth step of separating video, audio, and control signals from the parallel-converted HDMI signals selected by the fourth step; A sixth step of combining the video, audio, and control signals into a parallel HDMI signal for transmission, and a seventh step of converting the parallel HDMI signal output from the sixth step to a serial signal and outputting the serial signal. / RTI > < RTI ID = 0.0 > DM < / RTI >

Conventionally, the MJL / HDDM connection device processes the inputted MHL signal by using a clock which is three times faster than the pixel clock which processes the HDMI signal to the front of the HDMI Tx PHY, thereby greatly incurring hardware overhead. However, The HDMI Link Rx front-end uses the HDMI signal to convert the MHL signal first, thus reducing the hardware overhead.

1 is an exemplary diagram of an HDMI signal and an MHL signal;
2 is a block diagram of a conventional MJL / HJDMI connection device.
3 is a block diagram of a MJL / DM DM connection device according to the present invention;
4 is a block diagram illustrating the function of the MHL Demux 30;
5 is a timing diagram illustrating the clock and data conversion flow performed in the MHL Demux 30;

In the following, preferred embodiments, advantages and features of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram of a MJL / HJDMI connection device according to the present invention. The DMUX R / W PHY 11, HDCP 13, 23, the MHL Demux 30, the multiplexer 42, the HDMI link Rx 35, An HDMI link Tx 47, and an HDMI Tx PHY 41. [ As shown in the figure, in the previous stage of the MHL Demux 30, a clock having a frequency three times the pixel clock is used, and the remaining stages use the pixel clock frequency.

The HDMI / MHL Rx PHYs 11 and 21 are modules for converting an input serial MHL or HDMI signal into a parallel signal. An HDCP (High-bandwidth Digital Content Protection) 13 and 23 are connected to an MHL device And the HDMI link Rx 35 is a module for separating video, audio, and control signals from the input parallel-converted HDMI signal, and the HDMI link Tx 47 is a module for authenticating an HDMI device that provides input, And a control signal to generate an HDMI signal for transmission. The multiplexer 42 is a MUX for selecting one of the clock-converted MHL signal and the HDMI signal, and the HDMI Tx PHY 41 is a module for serializing the parallel HDMI signal. 4 is a block diagram illustrating the function of the MHL Demux 30. The MHL Demux 30 is a module for converting the B, G, and R signals input in serial into the pixel clock, and converting the MHL signal into the HDMI signal form, in synchronization with the triple pixel clock output from the HDCP 13 .

5 is a timing diagram illustrating the clock and data conversion flow performed in the MHL Demux 30. The MHL Clock Mask of FIG. 5 represents a clock corresponding to one of the output signals of the HDCP 13 of FIG. 4, 'clock * 3', and the MHL Data [0] B, G, and R '. The MHL Clock shown at the top of FIG. 5 represents a clock generated three times faster than a pixel clock. Generates an MHL Clock Mask C0, an MHL Clock C1 and an MHL Clock C2 sequentially excited by using the inputted MHL clock, and generates each masked data signal (MHL Masked Data []) during a cycle of the corresponding mask clock do. The generated mask clock and masked data are represented by MHL Clock Mask C0, MHL Clock Mask C1, and MHL Clock Mask C2, and the masked data signal is represented by MHL Masked Data [0], MHL Masked Data [1] Masked Data [2].

Next, the HDMI Clock and HDMI Data [0], HDMI Data [1], and HDMI Data [2] are generated using the MHL Clock Mask and MHL Masked Data [] generated next. The HDMI Clock shown in FIG. 5 corresponds to the output 'clock' of the MHL Demux 30 of FIG. 4, and the HDMI Data [0], HDMI Data [1], and HDMI Data [ B ',' G ', and' R 'data signals of the MHL Demux 30, respectively.

According to HDMI standard 1.4, the duty ratio of HDMI Tx PHY clock should be 50%. In order to generate an HDMI clock that meets these requirements, it is possible to generate an HDMI clock having a desired duty ratio by generating timings at the rising edge and the falling edge, respectively, represented by circles in the MHL clock shown at the top of FIG.

The data conversion method using the above-described MJL / HJDMI connection device of FIG. 3 will be briefly described. The HDMI / MHL Rx PHY converts an HDMI signal or an MHL signal input in serial into a parallel signal separated into a clock and a data format (first step). Next, the HDCP authenticates the MHL device and the HDMI device (step 2). Next, the MHL DIMUX receives the clock and data of the parallel-converted MHL signal output after the HDCP authentication in the second step, and then converts the clock and data into an HDMI clock and a data format (step 3). The multiplexer selects and outputs one of the clock and data of the HDMI signal authenticated through the HDCP and the output signal of the third stage (step 4). Then, the HDMI Link Rx separates video, audio, and control signals from the parallel-converted HDMI signal selected in the fourth step (fifth step), and the HDMI Link Tx separates video, audio, and control signals (Step 6), and the HDMI Tx PHY converts the parallel HDMI signal output from the sixth step into a serial signal and outputs it (step 7).

While the preferred embodiments of the present invention have been described and illustrated above using specific terms, such terms are used only for the purpose of clarifying the invention, and it is to be understood that the embodiments of the invention and the described terminology are intended to cover various modifications, It is obvious that various changes and changes can be made without departing from the scope of the present invention. Such modified embodiments should not be understood individually from the spirit and scope of the present invention, but should be regarded as being within the scope of the claims of the present invention.

11, 21: HDMI / MHL Rx PHY 13, 23: HDCP
15: MHL Link Rx 17: MHL Link Tx
29: clock converter 30: MHL Demux
35: HDMI Link Rx 42: Multiplexer
41: HDMI Tx PHY 47: HDMI Link Tx

Claims (4)

An MHL device for providing an MHL signal and an MHL input device for receiving an MHL input and an HDMI input input from an HDMI device providing an HDMI signal and outputting the MHL input and the HDMI input as an HDMI output signal,
An HDMI / MHL Rx PHY for converting an HDMI signal or an MHL signal input as a serial into a parallel signal separated into a clock and a data format,
An HDCP for authenticating the MHL device and the HDMI device,
An MHL demux for receiving the clock and data of the parallel-converted MHL signal output from the HDCP and then converting it into an HDMI clock and a data format,
A multiplexer for selecting one of a clock and data of the HDMI signal authenticated through the HDCP and an output signal of the MHL demux,
An HDMI Link Rx for separating video, audio, and control signals from the parallel-converted HDMI signal selected by the multiplexer,
An HDMI Link Tx that combines the video, audio, and control signals output from the HDMI Link Rx to generate a parallel HDMI signal for transmission and
And an HDMI Tx PHY for converting a parallel HDMI signal output from the HDM Link Tx to a serial signal and outputting the serial signal.
The method according to claim 1,
The HDMI / MHL Rx PHY includes a first HDMI / MHL Rx PHY for converting a serial input HDMI signal into a parallel signal separated into a clock and a data format, and a first HDMI / MHL Rx PHY for multiplexing an MHL signal input into the serial into a parallel signal Lt; RTI ID = 0.0 > HDMI / MHL Rx PHY < / RTI >
Wherein the HDCP comprises a first HDCP for authenticating the MHL device and a second HDCP for authenticating the HDMI device,
Wherein the MHL DIMUX receives the clock and data of the parallel-converted MHL signal output from the first HDCP, and then converts the clock and data into an HDMI clock and a data format.
3. The method of claim 2,
The operation clocks of the first HDMI / MHL Rx PHY, the second HDMI / MHL Rx PHY, the first HDCP, and the second HDCP are three times larger than the operation clocks of the HDMI Link Rx, the HDMI Link Tx, and the HDMI Tx PHY / RTI > device connected to the M / L / D.

There is provided a method of converting an MHL input signal and an HDMI input signal from an MHL device providing an MHL signal and an HDMI device providing an HDMI signal and outputting the MHL input and the HDMI input as an HDMI output signal,
A first step of converting an HDMI signal or an MHL signal input as a serial into a parallel signal separated into a clock and a data format,
A second step of authenticating the MHL device and the HDMI device through HDCP,
A third step of receiving the clock and data of the parallel-converted MHL signal output after the authentication of the second step, and then converting it into an HDMI clock and a data format;
A fourth step of selecting one of a clock and data of the HDMI signal authenticated through the HDCP and an output signal of the third step,
A fifth step of separating video, audio, and control signals from the parallel-converted HDMI signal selected by the fourth step;
A sixth step of combining the video, audio, and control signals output from the fifth step into a parallel HDMI signal for transmission;
And a seventh step of converting the parallel HDMI signal output from the sixth step into a serial signal and outputting the serial signal.

Images