WO2017067157A1 - 一种提高锗硅源漏区质量的制造方法 - Google Patents

一种提高锗硅源漏区质量的制造方法 Download PDF

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WO2017067157A1
WO2017067157A1 PCT/CN2016/082317 CN2016082317W WO2017067157A1 WO 2017067157 A1 WO2017067157 A1 WO 2017067157A1 CN 2016082317 W CN2016082317 W CN 2016082317W WO 2017067157 A1 WO2017067157 A1 WO 2017067157A1
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sige
layer
source
drain region
concentration
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French (fr)
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钟旻
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上海集成电路研发中心有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention belongs to the technical field of semiconductor manufacturing and relates to a manufacturing method for improving the quality of a SiGe source/drain region.
  • Embedded silicon germanium source-drain technology is a strained silicon technology used to improve PMOS performance. It increases the hole mobility of the PMOS by generating uniaxial compressive stress in the channel, thereby improving the current driving capability of the transistor, and is the core technology in the high performance process of the technology of 45 nm and below.
  • the principle is that a SiG layer is selectively epitaxially grown in the recess by etching a recess as a source/drain region on the Si, and the SiGe lattice constant is not matched with Si, so that the Si in the channel direction is compressed to generate a voltage. Stress, thereby increasing the hole mobility in the channel Si.
  • SEG selective epitaxial SiGe
  • PSD source-drain region
  • 1 shows a conventional manufacturing method for improving the quality of a SiGe source/drain region, comprising: etching a trench 102 in a source/drain region containing a silicon substrate 101, and epitaxially lowering a Ge-concentration SiGe buffer layer 103 by a SEG method (Seed layer) Then, a high Ge concentration SiGe body layer 104 is epitaxially deposited, and finally a Si cap layer 105 (Si cap) is epitaxially formed to finally form a PMOS source and drain region having SiGe.
  • SEG source-drain region
  • the function of the cap layer is to ensure stress retention of the underlying SiGe bulk layer, and Si reacts with Ni to form NiSi in a subsequent silicide process.
  • the Si cap layer is on the underlying SiGe body The coating property of the layer is deteriorated, which may cause direct reaction between Ni and the SiGe bulk layer in the subsequent silicide process, resulting in a large source-drain resistance, a small SiGe stress, and a decrease in device performance or even failure.
  • the SiGe source of the pattern when the SiGe source of the pattern is sparse, the thickness of the Si cap layer is normal and the SiGe body layer is completely covered.
  • the Si cap layer on the SiGe source drain of the dense region may be thinner and cannot completely cover the SiGe bulk layer (as shown in FIG. 2), which eventually leads to deterioration of device performance or device failure in the pattern dense region, and the chip yield is lowered.
  • the technical problem to be solved by the present invention is to provide a manufacturing method for improving the quality of a SiGe source/drain region, ensuring a good coating of the Si cap layer on the SiGe bulk layer, thereby enhancing device yield and improving device performance.
  • the present invention provides a manufacturing method for improving the quality of a SiGe source/drain region, comprising the following steps:
  • Step S01 providing an N-type silicon substrate formed with a gate, and etching a groove on the silicon substrate where a source/drain region is to be formed;
  • Step S02 epitaxially growing a SiGe buffer layer in the recess
  • Step S03 epitaxially growing a SiGe body layer on the buffer layer, wherein a concentration of Ge in the body layer is higher than a buffer layer;
  • Step S04 epitaxially growing a SiGe cap layer on the body layer to form a PMOS source/drain region having SiGe; wherein a concentration of Ge in the cap layer is lower than that of the body layer.
  • the Ge-containing concentration in the cap layer in the step S04 is 1-10%.
  • the concentration of Ge in the buffer layer is 5-20%, and the concentration of Ge in the host layer is 30-50%.
  • the thickness of the cap layer is the thickness of the cap layer.
  • the cap layer is epitaxially grown using a plurality of silicon source gases, which are a mixed gas of two or more of monosilane, dichlorosilane, trichlorosilane, and disilane.
  • silicon source gases which are a mixed gas of two or more of monosilane, dichlorosilane, trichlorosilane, and disilane.
  • the doping concentration of B in the cap layer is between 1 ⁇ 10 20 and 5 ⁇ 10 21 cm ⁇ 3 .
  • the upper surface of the body layer is lower or higher than the upper surface of the silicon substrate.
  • the upper surface of the body layer is flush with the upper surface of the silicon substrate.
  • the cap layer has a rectangular structure, a circular arc structure or a trapezoidal structure.
  • the groove in the step S01 is a U-shaped or a ⁇ -shaped structure.
  • the present invention provides a manufacturing method for improving the quality of a SiGe source/drain region.
  • the epitaxial growth of a low Ge concentration SiGe cap layer effectively accelerates the cap layer on a SiGe bulk layer having a high Ge concentration.
  • the growth rate thereby solving the problem of poor coating of the cap layer on the ⁇ 111> crystal plane of the SiGe main layer, enhancing the process stability and thereby improving the device performance; the invention can effectively avoid the anisotropic growth problem, but does not increase the process Difficulty, the process is stable and controllable, and the cost is low.
  • FIG. 1 is a schematic view showing the structure of a source/drain region of a SiGe in the prior art.
  • FIG. 2 is a schematic view showing the structure of a conventional cap layer that cannot completely cover the main body layer.
  • FIG. 3 is a schematic flow chart of a manufacturing method for improving the quality of a SiGe source/drain region in the present invention.
  • FIGS. 4a-4d are schematic views showing the structure of forming a SiGe source/drain region in Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural view of a cap layer of a pattern sparse area of Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural view of a cap layer of a pattern dense area in Embodiment 1 of the present invention.
  • FIG. 7a-7d are schematic views showing the structure of forming a SiGe source/drain region in Embodiment 2 of the present invention.
  • FIG. 8 is a schematic structural view of a cap layer of a pattern sparse area of Embodiment 2 of the present invention.
  • FIG. 9 is a schematic structural view of a cap layer in a pattern-dense area of Embodiment 2 of the present invention.
  • FIG. 3 is a schematic flow chart of a manufacturing method for improving the quality of a SiGe source/drain region in the present invention
  • FIGS. 4a-4d are schematic views showing a structure for forming a SiGe source/drain region in Embodiment 1 of the present invention
  • FIG. 5 is a first embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a cap layer of a pattern dense region in Embodiment 1 of the present invention;
  • FIG. 7a-7d are schematic views showing the structure of forming a SiGe source/drain region in Embodiment 2 of the present invention; and FIG. 8 is the present invention.
  • FIG. 9 is a schematic structural view of a cap layer of a pattern sparse area in Embodiment 2; FIG. 9 is a schematic structural view of a cap layer in a pattern-dense area of Embodiment 2 of the present invention.
  • the present invention provides a manufacturing method for improving the quality of a SiGe source/drain region, comprising the following steps:
  • step S01 an N-type silicon substrate 301 on which a gate electrode 304 is formed is provided, and a recess 303 in which a source/drain region is to be formed is etched on the silicon substrate 301 (refer to FIG. 4a).
  • an N-type silicon substrate formed with a gate 304 is provided, and a recess 303 where a source/drain region is to be formed is etched on the substrate 301 between the gate 304 and the shallow trench isolation STI 302.
  • the depth of the groove 303 is preferably
  • the groove 303 in this step may be a U-shaped or a ⁇ -shaped structure, and the groove 303 in this embodiment adopts a ⁇ -type structure.
  • step S02 the SiGe buffer layer 305 is epitaxially grown in the recess 303 (please refer to FIG. 4b).
  • a buffer layer 305 having a low Ge concentration is deposited in the recess 303 by a low-temperature epitaxial method, wherein the Ge-containing concentration of the buffer layer 305 is preferably 5-20%.
  • Ge-containing may be used.
  • the concentration is preferably 20% of the buffer layer 305, and the thickness of the buffer layer 305 is preferably
  • step S03 the SiGe body layer 306 is epitaxially grown on the buffer layer 305, and the concentration of Ge in the body layer 306 is higher than that of the buffer layer 305 (please refer to FIG. 4c).
  • a high-concentration body layer 306 is deposited in the recess 303 by a low-temperature epitaxial method, wherein the host layer 306 preferably has a Ge-containing concentration of 30-50%.
  • a Ge-containing layer may be used.
  • the body layer 306 is preferably 40% concentrated, and the thickness of the body layer 306 is preferably
  • the doping concentration of B in the main body layer 306 is preferably 3e 20 cm -3 .
  • the upper surface of the body layer 306 may be lower than or higher than the upper surface of the silicon substrate 301 or flush with the upper surface of the silicon substrate 301. It should be noted that when the main body layer 306 is convex on the upper surface of the silicon substrate 301 (that is, the upper surface of the main body layer 306 is higher than the upper surface of the silicon substrate 301), the SiGe cap layer containing the low Ge concentration is followed by the high Ge. The improvement in growth rate on the concentration of SiGe body layer 306 is more pronounced, especially in the ⁇ 111> crystal plane direction, so that the sides of the SiGe body layer 306 are not exposed.
  • step S04 the SiGe cap layer 307 is epitaxially grown on the body layer 306 to form a PMOS source/drain region having SiGe; wherein the Ge-containing concentration in the cap layer 307 is lower than that of the body layer 306 (please refer to FIG. 4d).
  • the Ge-containing concentration in the cap layer 307 is preferably 1-10%, and the thickness of the cap layer 307 is preferably The doping concentration of B in the cap layer 307 is preferably between 1 ⁇ 10 20 - 5 ⁇ 10 21 cm -3 .
  • the Ge concentration in the SiGe capping layer 307 should be controlled to be 1% to 10%, and the GeGe concentration in this embodiment is 5%.
  • the Ge concentration of the underlying SiGe body layer 306 and the morphology of the SiGe (below, horizontal or higher than the silicon substrate) and the Ge concentration of the cap layer 307 are The thickness determines the proportion of the mixed silicon source atmosphere used.
  • the silicon source gas in this step includes, but is not limited to, a mixed gas of two or more kinds of monosilane, dichlorosilane, trichlorosilane, and disilane. The type and ratio of the specific silicon source gas are determined according to actual conditions.
  • FIG. 5 is a schematic structural view of a cap layer of a pattern sparse region in the present invention
  • FIG. 6 is a schematic structural view of a cap layer in a pattern-dense region of the present invention.
  • the cap layer 307 has a rectangular structure in the pattern sparse area, and the cap layer 307 has a circular arc shape or a trapezoidal structure due to a slightly slow growth rate and a shape of the main layer layer in the pattern dense region, and the cap layer 307 can be completely packaged.
  • the main layer 306 of the lower layer is covered.
  • Step S01 providing an N-type silicon substrate 401 formed with a gate 404, etching a recess 403 to form a source/drain region on the substrate 401 between the gate 404 and the shallow trench isolation STI 302, the recess
  • the depth of 403 is preferably
  • the groove 403 has a U-shaped structure (please refer to FIG. 7a).
  • the SiGe buffer layer 305 is epitaxially grown in the recess 403 by a low temperature epitaxy method (please refer to FIG. 7b).
  • the buffer layer 405 preferably has a Ge concentration of 20%, and the buffer layer 405 preferably has a thickness of
  • the SiGe body layer 406 is epitaxially grown on the buffer layer 405, and the concentration of Ge in the body layer 406 is higher than that of the buffer layer 405 (please refer to FIG. 7c).
  • a body layer 406 having a Ge concentration of preferably 45% may be employed, and the thickness of the body layer 406 is The doping concentration of B in the main body layer 406 is preferably 5e 20 cm -3 .
  • the main body layer 406 is convex on the upper surface of the silicon substrate 401.
  • a SiGe capping layer 407 is epitaxially grown on the body layer 406 to form a PMOS source/drain region having SiGe (refer to FIG. 7d).
  • the Ge content in the cap layer 407 is 8%, and the thickness is The doping concentration of B is 2 ⁇ 10 21 cm -3 .
  • the SiGe bulk layer of high Ge concentration is higher than the silicon substrate, the growth rate of the cap layer on the ⁇ 111> crystal plane of the SiGe bulk layer is prevented from being too slow.
  • the problem of poor coating requires a mixed silicon source atmosphere to reduce the difference in Si growth rate on different crystal planes and the difference in Si growth rate in different pattern density regions.
  • the specific silicon source gas type and ratio are based on actual conditions. And set.
  • FIG. 8 is a schematic structural view of a cap layer of a pattern sparse region of Embodiment 2 of the present invention
  • FIG. 9 is a schematic structural view of a cap layer of a pattern-dense region of Embodiment 2 of the present invention.
  • the cap layer 307 has a rectangular structure in the pattern sparse area, and the cap layer has a circular arc or a trapezoidal structure due to a slightly slow growth rate and a shape of the main layer in the pattern dense region, and the cap layer can completely cover the lower layer.
  • the main layer is a schematic structural view of a cap layer of a pattern sparse region of Embodiment 2 of the present invention
  • FIG. 9 is a schematic structural view of a cap layer of a pattern-dense region of Embodiment 2 of the present invention.
  • the cap layer 307 has a rectangular structure in the pattern sparse area, and the cap layer has a circular arc or a trapezoidal structure due to a slightly slow growth rate and a
  • the present invention provides a manufacturing method for improving the quality of a SiGe source/drain region.
  • the cap layer 307 is effectively accelerated on a high Ge concentration SiGe bulk layer.
  • the growth rate thereby solving the problem of poor coating of the cap layer 307 on the ⁇ 111> crystal face of the SiGe body layer 306, enhancing the process stability and thereby improving the device performance; the invention can effectively avoid the anisotropic growth problem, but does not increase
  • the process is difficult, the process is stable and controllable, and the cost is low.

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Abstract

一种提高SiGe源/漏区质量的制造方法，首先提供形成有栅极（304，404）的N型硅衬底（301，401），并在该硅衬底（301，401）上刻蚀出将要形成源/漏区的凹槽（303，403）（S01）；接着在凹槽（303，403）中外延生长低Ge浓度的SiGe缓冲层（305，405）（S02）；然后在缓冲层（305，405）上外延生长高Ge浓度的SiGe主体层（306，406）（S3）；最后在主体层（306，406）上外延生长低Ge浓度的SiGe盖帽层（307，407），形成具有SiGe的PMOS源/漏区（S04）。通过外延生长低Ge浓度的SiGe盖帽层，有效加快了盖帽层在高Ge浓度的SiGe主体层上的生长速率，从而解决SiGe主体层的<111>晶面上盖帽层包覆性差的问题，增强了工艺稳定性，从而提升器件性能。

Description

一种提高锗硅源漏区质量的制造方法 技术领域
本发明属于半导体制造技术领域，涉及一种提高SiGe源/漏区质量的制造方法。
技术背景
嵌入式锗硅源漏技术(embedded SiGe，eSiGe)是一种用来提高PMOS性能的应变硅技术。它是通过在沟道中产生单轴压应力来增加PMOS的空穴迁移率，从而提高晶体管的电流驱动能力，是45nm及以下技术代高性能工艺中的核心技术。其原理是通过在Si上刻蚀出凹槽作为源漏区，在凹槽中选择性地外延生长SiGe层，利用SiGe晶格常数与Si不匹配，使沿沟道方向的Si受到压缩产生压应力，从而提高了沟道Si中的空穴迁移率。
目前主要采用选择性外延SiGe(selective epi SiGe，SEG)的方法在PMOS的源漏区域(PSD)直接外延SiGe薄膜。图1显示了现有的提高SiGe源/漏区质量的制造方法，包括：在含有硅衬底101的源漏区刻蚀凹槽102，用SEG方法外延低Ge浓度SiGe缓冲层103(Seed layer)，然后外延一层高Ge浓度的SiGe主体层104(Bulk layer)，最后外延一层Si盖帽层105(Si cap)，最终形成具有SiGe的PMOS源漏区。
盖帽层的作用是确保下层SiGe主体层的应力保持，并且在后续硅化物工艺(silicide)中Si与Ni反应生成NiSi。然而，随着SiGe主体层中Ge浓度的越来越高，Si盖帽层在高Ge浓度的SiGe主体层上的沉积越发困难，尤其是在<111>晶面，Si的生长速率极低。因此，Si盖帽层对下层的SiGe主体 层包覆性变差，在后续的硅化物工艺(silicide)中可能导致Ni与SiGe主体层直接反应，而导致源漏电阻变大，SiGe应力变小，器件性能降低甚至失效。另一方面，由于晶片上不同图形密度区域上Si生长速率不同(也称图形密度效应)，当图形稀疏区域的SiGe源漏上Si盖帽层厚度正常和对SiGe主体层包覆完整时，在图形密集区SiGe源漏上的Si盖帽层可能厚度变薄并且不能完整覆盖SiGe主体层(如图2所示)，最终导致图形密集区的器件性能恶化或器件失效，芯片的良率降低。
因此，本领域技术人员亟需提供一种提高SiGe源/漏区质量的制造方法，保证Si盖帽层对SiGe主体层的良好包覆，从而增强器件良率，提高器件性能。
发明概要
本发明所要解决的技术问题是提供一种提高SiGe源/漏区质量的制造方法，保证Si盖帽层对SiGe主体层的良好包覆，从而增强器件良率，提高器件性能。
为了解决上述技术问题，本发明提供了一种提高SiGe源/漏区质量的制造方法，包括以下步骤：
步骤S01，提供形成有栅极的N型硅衬底，并在该硅衬底上刻蚀出将要形成源/漏区的凹槽；
步骤S02，在所述凹槽中外延生长SiGe缓冲层；
步骤S03，在所述缓冲层上外延生长SiGe主体层，所述主体层中的含Ge浓度高于缓冲层；
步骤S04，在所述主体层上外延生长SiGe盖帽层，形成具有SiGe的PMOS源/漏区；其中，所述盖帽层中的含Ge浓度低于所述主体层。
优选的，所述步骤S04中的盖帽层中的含Ge浓度为1-10％。
优选的，所述缓冲层中的含Ge浓度为5-20％，所述主体层中的含Ge浓度为30-50％。
优选的，所述盖帽层的厚度为
Figure PCTCN2016082317-appb-000001
优选的，所述盖帽层采用多种硅源气体进行外延生长，所述硅源气体为甲硅烷、二氯硅烷，三氯硅烷、乙硅烷中的两种或两种以上的混合气体。
优选的，所述盖帽层中B的掺杂浓度在1×1020-5×1021cm-3之间。
优选的，所述主体层的上表面低于或高于所述硅衬底的上表面。
优选的，所述主体层的上表面与所述硅衬底的上表面平齐。
优选的，所述盖帽层呈矩形结构、圆弧形结构或梯形结构。
优选的，所述步骤S01中的凹槽为U型或Σ型结构。
与现有的方案相比，本发明提供了一种提高SiGe源/漏区质量的制造方法，通过外延生长低Ge浓度的SiGe盖帽层，有效加快了盖帽层在高Ge浓度的SiGe主体层上的生长速率，从而解决SiGe主体层的<111>晶面上盖帽层包覆性差的问题，增强了工艺稳定性，从而提升器件性能；本发明能有效避免各向异性生长问题，但不增加工艺难度，工艺稳定可控，成本低廉。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明 的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中SiGe源/漏区的结构示意图
图2是现有的盖帽层不能完整覆盖主体层的结构示意图
图3是本发明中提高SiGe源/漏区质量的制造方法的流程示意图
图4a-4d是本发明中实施例1形成SiGe源/漏区的结构示意图
图5是本发明中实施例1图形稀疏区的盖帽层的结构示意图
图6是本发明中实施例1图形密集区的盖帽层的结构示意图
图7a-7d是本发明中实施例2形成SiGe源/漏区的结构示意图
图8是本发明中实施例2图形稀疏区的盖帽层的结构示意图
图9是本发明中实施例2图形密集区的盖帽层的结构示意图
发明内容
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施方式作进一步地详细描述。本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
上述及其它技术特征和有益效果，将结合实施例及附图对本发明的提高SiGe源/漏区质量的制造方法进行详细说明。图3是本发明中提高SiGe源/漏区质量的制造方法的流程示意图；图4a-4d是本发明中实施例1形成SiGe源/漏区的结构示意图；图5是本发明中实施例1图形稀疏区的盖帽层的结构示意图；图6是本发明中实施例1图形密集区的盖帽层的结构示意图。图7a-7d是本发明中实施例2形成SiGe源/漏区的结构示意图；图8是本发明 中实施例2图形稀疏区的盖帽层的结构示意图；图9是本发明中实施例2图形密集区的盖帽层的结构示意图。
如图3所示，本发明提供了一种提高SiGe源/漏区质量的制造方法，包括以下步骤：
步骤S01，提供形成有栅极304的N型硅衬底301，并在该硅衬底301上刻蚀出将要形成源/漏区的凹槽303(请参考图4a)。
具体的，本步骤中，提供形成有栅极304的N型硅衬底，在栅极304和浅沟槽隔离STI302之间的衬底301上刻蚀出将要形成源/漏区的凹槽303，凹槽303的深度优选为
Figure PCTCN2016082317-appb-000002
本步骤中的凹槽303可以为U型或Σ型结构，本实施例凹槽303采用Σ型结构。
步骤S02，在凹槽303中外延生长SiGe缓冲层305(请参考图4b)。
具体的，本步骤中，采用低温外延方法在凹槽303中沉积低Ge浓度的缓冲层305，其中，缓冲层305的含Ge浓度优选为5-20％，本实施例中，可采用含Ge浓度优选为20％的缓冲层305，缓冲层305的厚度优选为
Figure PCTCN2016082317-appb-000003
步骤S03，在缓冲层305上外延生长SiGe主体层306，主体层306中的含Ge浓度高于缓冲层305(请参考图4c)。
具体的，本步骤中，采用低温外延方法在凹槽303中沉积高Ge浓度的主体层306，其中，主体层306的含Ge浓度优选为30-50％，本实施例中，可采用含Ge浓度优选为40％的主体层306，主体层306的厚度优选为
Figure PCTCN2016082317-appb-000004
主体层306中B的掺杂浓度优选为3e20cm-3。
本步骤中，主体层306的上表面可低于或高于硅衬底301的上表面或者与硅衬底301的上表面平齐。值得说明的是，当主体层306的凸起于硅衬底301上表面时(即主体层306的上表面高于硅衬底301上表面)，后续含有低Ge浓度的SiGe盖帽层在高Ge浓度的SiGe主体层306上的生长速率的改善更为明显，尤其是<111>晶面方向，使SiGe主体层306两侧不会裸露。
步骤S04，在主体层306上外延生长SiGe盖帽层307，形成具有SiGe的PMOS源/漏区；其中，盖帽层307中的含Ge浓度低于主体层306(请参考图4d)。
具体的，本步骤中，盖帽层307中的含Ge浓度优选为1-10％，盖帽层307的厚度优选为
Figure PCTCN2016082317-appb-000005
盖帽层307中B的掺杂浓度优选在1×1020-5×1021cm-3之间。
值得说明的是，当盖帽层307中的Ge浓度太高时，会影响后续Ni与Si反应生成NiSi，导致源漏区电阻变大。因此，SiGe盖帽层307中的Ge浓度应控制在1％-10％，本实施例中GeGe浓度为5％。
另外，当采用多种硅源气体外延SiGe盖帽层时，要根据下层SiGe主体层306的Ge浓度和SiGe的形貌(低于、水平或高于硅衬底)以及盖帽层307的Ge浓度和厚度，决定采用的混合硅源气氛比例。本步骤中硅源气体包括但不限于甲硅烷、二氯硅烷，三氯硅烷、乙硅烷中的两种或两种以上的混合气体，具体硅源气体的种类以及比例根据实际情况而定。
请参阅图5以及图6，图5是本发明中图形稀疏区的盖帽层的结构示意图；图6是本发明中图形密集区的盖帽层的结构示意图。图5中盖帽层307在图形稀疏区呈矩形结构，在图形密集区由于生长速率略慢和受主体层形貌的影响，盖帽层307呈圆弧形或梯形结构，且盖帽层307能完整包覆下层的主体层306。
实施例2：
步骤S01，提供形成有栅极404的N型硅衬底401，在栅极404和浅沟槽隔离STI302之间的衬底401上刻蚀出将要形成源/漏区的凹槽403，凹槽403的深度优选为
Figure PCTCN2016082317-appb-000006
凹槽403为U型结构(请参考图7a)。
步骤S02，采用低温外延方法在凹槽403中外延生长SiGe缓冲层305(请参考图7b)。本实施例中，缓冲层405的含Ge浓度优选为20％的缓冲 层405，缓冲层405的厚度优选为
Figure PCTCN2016082317-appb-000007
步骤S03，在缓冲层405上外延生长SiGe主体层406，主体层406中的含Ge浓度高于缓冲层405(请参考图7c)。本实施例中，可采用含Ge浓度优选为45％的主体层406，主体层406的厚度为
Figure PCTCN2016082317-appb-000008
主体层406中B的掺杂浓度优选为5e20cm-3。主体层406的凸起于硅衬底401上表面。
步骤S04，在主体层406上外延生长SiGe盖帽层407，形成具有SiGe的PMOS源/漏区(请参考图7d)。本实施例中，盖帽层407中的含Ge浓度为8％，厚度为
Figure PCTCN2016082317-appb-000009
B的掺杂浓度为2×1021cm-3。
对于抬升式SiGe源漏而言(raised source/drain area)，由于高Ge浓度的SiGe主体层高于硅衬底，为避免盖帽层在SiGe主体层的<111>晶面上生长速率过慢导致的包覆性差的问题，需要采用混合硅源气氛，减小不同晶面上Si生长速率的差异和在不同图形密度区域中的Si生长速率的差异，具体硅源气体的种类以及比例根据实际情况而定。
图8是本发明中实施例2的图形稀疏区的盖帽层的结构示意图；图9是本发明中实施例2的图形密集区的盖帽层的结构示意图。图8中盖帽层307在图形稀疏区呈矩形结构，在图形密集区由于生长速率略慢和受主体层形貌的影响，盖帽层呈圆弧形或梯形结构，且盖帽层能完整包覆下层的主体层。
综上所述，本发明提供了一种提高SiGe源/漏区质量的制造方法，通过外延生长低Ge浓度的SiGe盖帽层307，有效加快了盖帽层307在高Ge浓度的SiGe主体层上的生长速率，从而解决SiGe主体层306的<111>晶面上盖帽层307包覆性差的问题，增强了工艺稳定性，从而提升器件性能；本发明能有效避免各向异性生长问题，但不增加工艺难度，工艺稳定可控，成本低廉。
上述说明示出并描述了本发明的若干优选实施例，但如前所述，应当理解本发明并非局限于本文所披露的形式，不应看作是对其他实施例的排除， 而可用于各种其他组合、修改和环境，并能够在本文所述发明构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本发明的精神和范围，则都应在本发明所附权利要求的保护范围内。

Claims (10)

  1. 一种提高SiGe源/漏区质量的制造方法，其特征在于，包括以下步骤：
    步骤S01，提供形成有栅极的N型硅衬底，并在该硅衬底上刻蚀出将要形成源/漏区的凹槽；
    步骤S02，在所述凹槽中外延生长SiGe缓冲层；
    步骤S03，在所述缓冲层上外延生长SiGe主体层，所述主体层中的含Ge浓度高于缓冲层；
    步骤S04，在所述主体层上外延生长SiGe盖帽层，形成具有SiGe的PMOS源/漏区；其中，所述盖帽层中的含Ge浓度低于所述主体层。
  2. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述步骤S04中的盖帽层中的含Ge浓度为1-10％。
  3. 根据权利要求2所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述缓冲层中的含Ge浓度为5-20％，所述主体层中的含Ge浓度为30-50％。
  4. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述盖帽层的厚度为
    Figure PCTCN2016082317-appb-100001
  5. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述盖帽层采用多种硅源气体进行外延生长，所述硅源气体为甲硅烷、二氯硅烷，三氯硅烷、乙硅烷中的两种或两种以上的混合气体。
  6. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述盖帽层中B的掺杂浓度在1×1020-5×1021cm-3之间。
  7. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述主体层的上表面低于或高于所述硅衬底的上表面。
  8. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述主体层的上表面与所述硅衬底的上表面平齐。
  9. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述盖帽层呈矩形结构、圆弧形结构或梯形结构。
  10. 根据权利要求1所述的提高SiGe源/漏区质量的制造方法，其特征在于，所述步骤S01中的凹槽为U型或Σ型结构。
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