WO2017063460A1 - 倒装led芯片的共晶电极结构及倒装led芯片 - Google Patents

倒装led芯片的共晶电极结构及倒装led芯片 Download PDF

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Publication number
WO2017063460A1
WO2017063460A1 PCT/CN2016/097758 CN2016097758W WO2017063460A1 WO 2017063460 A1 WO2017063460 A1 WO 2017063460A1 CN 2016097758 W CN2016097758 W CN 2016097758W WO 2017063460 A1 WO2017063460 A1 WO 2017063460A1
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Prior art keywords
layer
eutectic
metal
flip
metal layer
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PCT/CN2016/097758
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English (en)
French (fr)
Inventor
何安和
林素慧
郑建森
彭康伟
林潇雄
徐宸科
Original Assignee
厦门市三安光电科技有限公司
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Application filed by 厦门市三安光电科技有限公司 filed Critical 厦门市三安光电科技有限公司
Publication of WO2017063460A1 publication Critical patent/WO2017063460A1/zh
Priority to US15/853,845 priority Critical patent/US10297736B2/en
Priority to US16/409,090 priority patent/US10707395B2/en
Priority to US16/900,538 priority patent/US10916688B2/en
Priority to US17/138,893 priority patent/US11393967B2/en
Priority to US17/806,497 priority patent/US20230088776A1/en

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Definitions

  • the present invention belongs to the field of optoelectronic technology, and specifically relates to a eutectic electrode structure of a flip-chip LED chip and a flip-chip LED chip containing the same.
  • flip-chip LED chips flip-chip in English, abbreviated as FC
  • FC flip-chip in English
  • flip-chip LED chips are different.
  • chip design and packaging process and material matching are one of the important topics in flip-chip packaging technology.
  • the relative position of the chip is the same as that of the electrode on the chip, and then the electrode on the chip is electrically connected to the gold bump on the package holder by ultrasonic pressing.
  • This method has low requirements on the package bracket and large process flexibility.
  • the use of gold bumps is large, the cost is high, and the chip alignment requires high precision, so the machine is expensive, the production efficiency is not good, and the whole production cost is too high; the second is the eutectic bonding process.
  • the selected eutectic metal layer is formed on the chip by evaporation or sputtering process, and the chip is pre-bonded to the package holder by the low temperature flux, above the eutectic metal layer.
  • the reflowing at the melting point allows the chip to form a joint with the package holder.
  • the advantage of this method is that the metal cost is low, the production speed is fast, and the alignment accuracy of the machine is relatively low, but the eutectic metal layer on the surface of the flip chip LED chip is required to be sufficient.
  • the level of the metal layer if there is a difference in the surface of the metal layer, will cause the eutectic void rate to be too high, resulting in poor eutectic, which in turn affects the package yield.
  • a conventional flip chip LED chip structure generally requires epitaxial growth of a first semiconductor layer, a light emitting layer and a second semiconductor layer on a epitaxial substrate, deposition of a transparent conductive layer, and engraving. Etching to a part of the first semiconductor layer exposed, vapor deposition of a metal layer (including extension strips), deposition of an insulating layer, evaporation of AuSn eutectic electrodes and the like. However, the structure is used for the eutectic package germanium. As shown in FIG.
  • the upper surface of the AuSn eutectic electrode has a convex structure, such as the second metal layer.
  • the upper surface of the AuSn eutectic electrode (with metal extension strip) is the highest, and can be packaged Co-eutectic welding, while the AuSn eutectic electrodes in other regions are lower, it is difficult to eutectic soldering with the package, so that the flatness of the upper surface of the eutectic electrode cannot be ensured, which will cause the eutectic void rate to be too high, resulting in eutectic defects.
  • the object of the present invention is to provide a eutectic electrode structure of a flip-chip LED chip and a flip-chip LED chip, and solve the conventional flip-chip LED chip structure in the eutectic bonding process without changing the package holder
  • the possibility of too high a eutectic void rate leads to a problem of low package yield.
  • a eutectic electrode structure of a flip chip LED chip is provided, characterized in that
  • the eutectic electrode structure is composed of a first eutectic layer and a second eutectic layer in a vertical direction from bottom to top, and is divided into a first type electrode region and a second type electrode region in a horizontal direction, and a first eutectic layer
  • the upper surface and the lower surface are not flat, and the upper surface of the second eutectic layer is flat.
  • a lower surface of the first eutectic layer is in contact with a flip chip LED chip for implementing current conduction
  • an upper surface of the second eutectic layer is higher than or equal to an upper surface of the first eutectic layer for forming a flat eutectic plane.
  • a flip chip LED chip comprising: a substrate; a first semiconductor layer on the substrate; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; The defect region is located on a portion of the second semiconductor layer and extends downward to the first semiconductor layer; the first metal layer is located on a portion of the first semiconductor layer; the second metal layer is located on a portion of the second semiconductor layer; the insulating layer is covered On the first metal layer, the second metal layer, the second semiconductor layer, and the first semiconductor layer of the local defect region, wherein the insulating layer has a gate structure, respectively located on the first metal layer and the second metal layer; the eutectic electrode
  • the structure is disposed on the insulating layer having a cornice, and is composed of a first eutectic layer and a second eutectic layer in a vertical direction from bottom to top, and is divided into a first type electrode region and a second type electrode region in
  • a lower surface of the first eutectic layer is in contact with the first metal layer and the second metal layer, respectively, for achieving current conduction.
  • the second eutectic layer does not overlap with the first metal layer and the second metal layer in the vertical direction.
  • the upper surface of the second eutectic layer is higher than or equal to The upper surface of the first eutectic layer is used to form a flat eutectic plane.
  • a height of the second eutectic layer of the first type electrode region is substantially flush with a height of the second eutectic layer of the second type electrode region.
  • first metal layer and the second metal layer are both composed of a metal body and a metal extension strip, or both the first metal layer and the second metal layer are metal bodies.
  • the cornice structure of the insulating layer is only located on the metal body.
  • the first type electrode region is equivalent in area to the second type electrode region, and the position is symmetrical.
  • a transparent conductive layer is formed on the second semiconductor, and the material is selected from indium tin oxide (IT0) or zinc oxide (ZnO) or cadmium tin oxide (CT0) or indium oxide (InO) or indium (In).
  • I0 indium tin oxide
  • ZnO zinc oxide
  • C0 cadmium tin oxide
  • InO indium oxide
  • In indium oxide
  • In indium
  • the metal layer is made of one of Cr, Ti, Pt, Au, Ag, Ni, Cu, TiW or a combination thereof.
  • the insulating layer material is one of SiO 2 , A1 2 0 3 , SiN x , Ti0 2 or a combination thereof.
  • the eutectic electrode structure material is one of Ti, Ni, Cu, Au, AuSn, SnCu, SnBi or a combination thereof.
  • the flip-chip LED chip electrode structure design of the invention solves the eutectic void rate that may occur in the eutectic bonding process by using the double-layer eutectic electrode structure without changing the package holder. High causes the package yield to be too low.
  • FIG. 1 is a top plan view of a conventional flip chip LED chip structure.
  • FIG. 2 is a cross-sectional view taken along line A-B-C of FIG. 1.
  • FIG. 3 is a cross-sectional view of a conventional flip chip LED chip structure eutectic package.
  • FIG. 4 is a plan view showing the structure of a flip-chip LED chip according to Embodiment 1 of the present invention.
  • FIG. 5 is a cross-sectional view taken along line A-B-C of FIG. 4.
  • FIG. 6 is a cross-sectional view showing a eutectic package of a flip-chip LED chip according to Embodiment 1 of the present invention.
  • FIG. 7 is a plan view showing the structure of a flip-chip LED chip according to Embodiment 2 of the present invention.
  • FIG. 8 is a cross-sectional view showing a eutectic package of a flip-chip LED chip structure according to Embodiment 2 of the present invention.
  • Each reference numeral in the drawing indicates: 100, 200, 300: substrate; 101, 201, 301: first semiconductor layer; 10 2, 202, 302: light-emitting layer; 103, 203, 303: second semiconductor layer; , 204, 304: transparent conductive layer; 105, 205, 305: second metal layer; 106, 206, 306: first metal layer; 107, 20 7, 307: insulating layer; 108, 208, 308: second type Electrode region; 109, 209, 309: first electrode region; 110, 210, 310: package holder; 2081, 2091, 3081, 3091: first eutectic layer; 20 82, 2092, 3082, 3092: second total Crystal layer.
  • the present invention proposes a two-layer eutectic electrode design suitable for flip chip LED chips without changing the package bracket. Solving the problem that the eutectic void rate which may occur in the conventional eutectic bonding process is too high, resulting in a low package yield.
  • the following examples will illustrate the eutectic electrode structure and flip chip LED chip of the present invention in conjunction with the drawings.
  • the flip-chip LED chip provided in this embodiment includes: a substrate 200; The body layer 201 is located on the substrate 200; the light emitting layer 202 is located on the first semiconductor layer 201; the second semiconductor layer 203 is located on the light emitting layer 202; the local defect region is located on a portion of the second semiconductor layer 203, and extends downward to the first semiconductor a layer 201; a transparent conductive layer 204 on a portion of the second semiconductor layer 203; a first metal layer 206 on a portion of the first semiconductor layer 201; a second metal layer 205 on the transparent conductive layer 204; an insulating layer 207, Covering the first metal layer 206, the second metal layer 205, the transparent conductive layer 204, and the first semiconductor layer 206 of the local defect region, wherein the insulating layer has a gate structure, respectively located at the first metal layer 206 and the second metal On the layer 205; a eutectic electrode structure, located on the a eutectic electrode structure, located on the first
  • the substrate 200 may be selected from a substrate suitable for epitaxial growth such as sapphire or silicon carbide or silicon or gallium nitride or aluminum nitride or zinc oxide.
  • a substrate suitable for epitaxial growth such as sapphire or silicon carbide or silicon or gallium nitride or aluminum nitride or zinc oxide.
  • sapphire is preferred; the first semiconductor layer 201 and the second semiconductor layer 202 are selected.
  • the light-emitting layer 203 is a gallium nitride (GaN) series material, but not limited thereto; the transparent conductive layer 204 is made of indium tin oxide (ITO) or zinc oxide (ZnO) or cadmium tin oxide (CTO) or oxidized.
  • ITO indium tin oxide
  • ZnO zinc oxide
  • CTO cadmium tin oxide
  • the first metal layer and the second metal layer are each composed of a metal body and a metal strip, or the first metal layer and the second metal layer are both metal bodies; in order to improve the uniformity of current spreading, the embodiment preferably A metal layer 206 and a second metal layer 205 are each composed of a circular metal body and an elongated metal strip.
  • the metal layer is made of one of Cr, Ti, Pt, Au, Ag, Ni, Cu, TiW or The combination, but not limited to it.
  • the cornice structure of the insulating layer 207 may be located on a circular metal body and an elongated metal expansion strip, or only on a circular metal body.
  • the insulating layer 207 is preferably covered in an elongated shape.
  • the opening structure of the insulating layer is only located on the circular metal body;
  • the insulating layer material is one of SiO 2 , A1 2 0 3 , SiN x , TiO 2 or a combination thereof, and the low refractive index is preferred in this embodiment.
  • the distributed SiO 2 and the high refractive index TiO 2 are alternately stacked to form a distributed Bragg reflection layer structure to facilitate reflection of light emitted from the luminescent layer and increase light emission.
  • a first eutectic layer 2081 is formed on the insulating layer 207 having a vent, such that the lower surface of the first eutectic layer 2081 is in contact with the second metal layer 205 for current conduction; the first eutectic The layer 2091 is formed on the insulating layer 207 having the vents, such that the lower surface of the first eutectic layer 2081 is in contact with the first metal layer 206 for achieving current conduction. Since the first eutectic layer 2081, 2091 has a convex second metal layer 205 underneath, the upper and lower surfaces of the first eutectic layer 2081, 2091 are not flat, that is, the upper and lower surfaces of the first eutectic layer are Concave.
  • Second eutectic layers 2082, 2092 are formed on the first eutectic layer 2081, 2091, respectively, and the second eutectic layer 2082
  • the second eutectic layer does not overlap with the first metal layer 205 and the second metal layer 206 in the vertical direction, that is, the second eutectic layer avoids the metal electrode body and the metal extension strip region; the second eutectic layer is located at the first eutectic layer a flat bottom region of the upper surface of the uneven surface to obtain a second eutectic layer having a flat upper surface; a second eutectic layer 2092 of the first type electrode region 209 and a second eutectic of the second electrode region 208 Layer 2082 is highly flush, thus forming a flat eutectic plane.
  • the flip-chip LED chip of this embodiment is used for eutectic package germanium, because the upper surface of the second eutectic layer is higher than the upper surface of the first eutectic layer, and the second eutectic layer is The upper surface is flat and highly flat, forming a flat eutectic plane, which effectively reduces the void ratio generated by the eutectic soldering process with the package holder 210; in addition, the second eutectic layer 2082, 2092 greatly exceeds the first metal layer 205, The two metal layers 206 can increase the effective area of the eutectic, and the eutectic soldering is stronger, thereby improving the package yield of the flip-chip LED chip and increasing the current stability and uniformity.
  • the difference from Embodiment 1 is that the upper surfaces of the second eutectic layers 3082 and 3092 of the present embodiment are flush with the upper surfaces of the first eutectic layers 308 1 and 3091.
  • the flat upper surface area of the eutectic electrode structure is further increased, the robustness of the eutectic soldering is enhanced, and the uniformity of the package yield and current spreading is improved.
  • the two-layer eutectic electrode design of the present invention is applied, that is, the first eutectic layer is used for current circulation with the semiconductor underlayer, and the second eutectic layer is for avoiding the metal layer (which may contain metal) Expansion strip)
  • the raised area can solve the problem of eutectic failure caused by excessive cavity ratio due to electrode height difference (flatness difference) in the eutectic process without increasing the cost of the package holder. , thereby improving the package yield of the flip-chip LED chip and increasing current stability and uniformity.

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Abstract

一种倒装LED芯片的共晶电极结构及倒装LED芯片，包括：基板（200）；第一半导体层（201）；第二半导体层（203）；局部缺陷区位于部分第二半导体层（203）上，且向下延伸至第一半导体层（201）；第一金属层（206）位于部分第一半导体层（201）上；第二金属层（205）位于部分第二半导体层（203）上；绝缘层（207），覆盖于第一金属层（206）、第二金属层（205）、第二半导体层（203）以及局部缺陷区的第一半导体层（201）上，绝缘层（207）具有开口结构，分别位于第一金属层（206）和第二金属层（205）上；共晶电极结构，位于具有开口的绝缘层（207）上，在垂直方向从下至上由第一共晶层（2081、2091）和第二共晶层（2082、2092）组成，在水平方向划分为第一型电极区（209）和第二型电极区（208）。该技术方案解决习知倒装LED芯片在共晶接合制程中可能发生共晶空洞率过高导致封装不良问题。

Description

倒装 LED芯片的共晶电极结构及倒装 LED芯片 技术领域
[0001] 本发明属于光电技术领域， 具体涉及倒装 LED芯片的共晶电极结构以及含有该 结构的倒装 LED芯片。
背景技术
[0002] 倒装 LED芯片（英文为 Flip-chip, 缩写为 FC)的应用随着其优越的散热特性及较 佳的取光效率日见被证实与量产， 然而， 倒装 LED芯片有别于习知发光二极管之 正装封装制程， 因此芯片设计与封装制程以及材料的搭配在倒装封装技术为重 要课题之一。 倒装 LED芯片封装主要分为两种： 第一种为金凸块键合制程（英文 为 Au-stub bumping process), 系先将金凸块种至封装支架上， 其金凸块于基板上 的相对位置与芯片上的电极相同， 而后藉由超音波压合， 使芯片上的电极与封 装支架上的金凸块接合完成电性连结， 此法对封装支架要求度低， 制程弹性大 ， 但其金凸块用量大， 成本高， 且芯片对位需要较高之精准度， 因此机台昂贵 ， 生产效率不佳， 导致整个生产成本过高； 第二种为共晶接合制程
(英文为 Eutectic bonding process)， 以蒸镀或溅镀制程将选定之共晶金属层制作于 芯片上， 藉由低温助焊剂将芯片预贴合至封装支架上， 在高于共晶金属层之熔 点下回焊， 使芯片与封装支架形成接合， 此法优点为金属成本低， 生产速度快 ， 对机台对位精度要求相对较低， 但要求倒装 LED芯片表面共晶金属层有足够的 水平度， 如果金属层表面有高低差， 则会造成共晶空洞率过高， 导致共晶不良 ， 进而影响封装良率。
[0003] 如图 1和图 2所示， 习知的倒装 LED芯片结构， 通常需要经过在磊晶基板上外延 生长第一半导体层、 发光层以及第二半导体层、 沉积透明导电层、 刻蚀至部分 第一半导体层裸露出来、 蒸镀金属层 （含扩展条） 、 沉积绝缘层、 蒸镀 AuSn共 晶电极等制作工艺。 但是该结构用于共晶封装吋， 如图 3所示， 由于受凸起状金 属层 （含金属扩展条） 的影响， 造成 AuSn共晶电极上表面有凸起结构， 如位于 第二金属层 （含金属扩展条） 之上的 AuSn共晶电极上表面最高， 可以与封装支 架共晶焊， 而其它区域的 AuSn共晶电极较低， 难于与封装支架共晶焊， 如此无 法确保共晶电极上表面的平整度， 会造成共晶空洞率过高， 产生共晶不良问题 技术问题
问题的解决方案
技术解决方案
[0004] 本发明的目的在于： 提供一种倒装 LED芯片的共晶电极结构及倒装 LED芯片， 在不改变封装支架的前提下， 解决习知倒装 LED芯片结构在共晶接合制程中可能 发生的共晶空洞率过高导致封装良率过低问题。
[0005] 根据本发明的第一方面， 提供一种倒装 LED芯片的共晶电极结构， 其特征在于
： 所述共晶电极结构， 在垂直方向从下至上由第一共晶层和第二共晶层组成， 在水平方向划分为第一型电极区和第二型电极区， 第一共晶层的上表面、 下表 面不平坦， 第二共晶层的上表面平坦。
[0006] 进一步地， 所述第一共晶层的下表面与倒装 LED芯片接触， 用于实现电流导通
[0007] 进一步地， 所述第二共晶层的上表面高于或等于第一共晶层的上表面， 用于形 成平整的共晶平面。
[0008] 根据本发明的第二方面， 提供一种倒装 LED芯片， 包括： 基板； 第一半导体层 位于基板上； 发光层位于第一半导体层上； 第二半导体层位于发光层上； 局部 缺陷区位于部分第二半导体层上， 且向下延伸至第一半导体层； 第一金属层， 位于部分第一半导体层上； 第二金属层， 位于部分第二半导体层上； 绝缘层， 覆盖于第一金属层、 第二金属层、 第二半导体层以及局部缺陷区的第一半导体 层上， 其中绝缘层具有幵口结构， 分别位于第一金属层和第二金属层上； 共晶 电极结构， 位于具有幵口的绝缘层上， 在垂直方向从下至上由第一共晶层和第 二共晶层组成， 在水平方向上划分为第一型电极区和第二型电极区； 第一共晶 层的上表面、 下表面不平坦， 第二共晶层的上表面平坦。
[0009] 进一步地， 所述第一共晶层的下表面分别与第一金属层、 第二金属层接触， 用 于实现电流导通。 [0010] 进一步地， 所述第二共晶层在垂直方向上与第一金属层、 第二金属层均不重叠 [0011] 进一步地， 所述第二共晶层的上表面高于或等于第一共晶层的上表面， 用于形 成平整的共晶平面。
[0012] 进一步地， 所述第一型电极区的第二共晶层高度与所述第二型电极区的第二共 晶层高度齐平。
[0013] 进一步地， 所述第一金属层、 第二金属层均由金属本体与金属扩展条组成， 或 者第一金属层、 第二金属层均为金属本体。
[0014] 进一步地， 所述绝缘层的幵口结构仅位于金属本体上。
[0015] 进一步地， 所述第一型电极区与第二型电极区面积相当， 且位置对称。
[0016] 进一步地， 所述第二半导体上形成透明导电层， 材质可选氧化铟锡 （IT0) 或 氧化锌 （ZnO) 或氧化镉锡 （CT0) 或氧化铟 （InO) 或铟 （In) 惨杂氧化锌 （Z ηθ) 或铝 （A1) 惨杂氧化锌 （ZnO) 或镓 （Ga) 惨杂氧化锌 （ZnO) 或前述任 意组合之一。
[0017] 进一步地， 所述金属层材质为 Cr、 Ti、 Pt、 Au、 Ag、 Ni、 Cu、 TiW的一种或其 组合。
[0018] 进一步地， 所述绝缘层材质为 SiO 2、 A1 20 3、 SiN x、 Ti0 2的一种或其组合。
[0019] 进一步地， 所述共晶电极结构材质为 Ti、 Ni、 Cu、 Au、 AuSn、 SnCu、 SnBi的 一种或其组合。
发明的有益效果
有益效果
[0020] 本发明的倒装 LED芯片电极结构设计， 藉由双层共晶电极结构， 在不改变封装 支架的前提下， 解决习知芯片结构于共晶接合制程可能发生之共晶空洞率过高 导致封装良率过低问题。
对附图的简要说明
附图说明
[0021] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0022] 图 1为习知的倒装 LED芯片结构的俯视图。
[0023] 图 2为图 1中沿 A-B-C方向的剖视图。
[0024] 图 3为习知的倒装 LED芯片结构共晶封装的剖视图。
[0025] 图 4为本发明实施例 1的倒装 LED芯片结构的俯视图。
[0026] 图 5为图 4中沿 A-B-C方向的的剖视图。
[0027] 图 6为本发明实施例 1的倒装 LED芯片结构共晶封装的剖视图。
[0028] 图 7为本发明实施例 2的倒装 LED芯片结构的俯视图。
[0029] 图 8为本发明实施例 2的倒装 LED芯片结构共晶封装的剖视图。
[0030] 图中各标号表示： 100， 200， 300： 基板； 101， 201， 301： 第一半导体层； 10 2， 202， 302： 发光层； 103， 203， 303： 第二半导体层； 104， 204， 304： 透明 导电层； 105， 205， 305： 第二金属层； 106， 206， 306： 第一金属层； 107， 20 7， 307： 绝缘层； 108， 208， 308： 第二型电极区； 109， 209， 309： 第一型电 极区； 110， 210， 310： 封装支架； 2081， 2091， 3081， 3091： 第一共晶层； 20 82， 2092， 3082， 3092： 第二共晶层。
本发明的实施方式
[0031] 为了能彻底地了解本发明， 将在下列的描述中提出详尽的步骤及其组成， 另外 ， 众所周知的组成或步骤并未描述于细节中， 以避免造成本发明不必要之限制 。 本发明的较佳实施例会详细描述如下， 然而除了这些详细描述之外， 本发明 还可以广泛地施行在其它的实施例中， 且本发明的范围不受限定， 以专利权利 范围为准。
[0032] 为解决习知的倒装 LED芯片结构于共晶接合制程所面临到的问题， 本发明提出 一适用于倒装 LED芯片之双层共晶电极设计， 在不改变封装支架的前提下， 解决 习知芯片结构在共晶接合制程中可能发生的共晶空洞率过高导致封装良率过低 问题。 下面实施例将配合图示说明本发明的共晶电极结构及倒装 LED芯片。
[0033] 实施例 1
[0034] 请参考图 4和图 5， 本实施例提供的倒装 LED芯片， 包括： 基板 200; 第一半导 体层 201位于基板 200上； 发光层 202位于第一半导体层 201上； 第二半导体层 203 位于发光层 202上； 局部缺陷区位于部分第二半导体层 203上， 且向下延伸至第 一半导体层 201 ; 透明导电层 204， 位于部分第二半导体层 203上； 第一金属层 20 6， 位于部分第一半导体层 201上； 第二金属层 205， 位于透明导电层 204上； 绝 缘层 207， 覆盖于第一金属层 206、 第二金属层 205、 透明导电层 204以及局部缺 陷区的第一半导体层 206上， 其中绝缘层具有幵口结构， 分别位于第一金属层 20 6和第二金属层 205上； 共晶电极结构， 位于具有幵口的绝缘层 207上， 在垂直方 向从下至上由第一共晶层 2081、 2091和第二共晶层 2082、 2092组成， 在水平方 向上划分为第一型电极区 209和第二型电极区 208， 第一型电极区 209与第二型电 极区面积 208相当， 且位置对称。
具体来说， 上述基板 200可以选择蓝宝石或碳化硅或硅或氮化镓或氮化铝或氧 化锌等适合外延生长的基板， 本实施例优选蓝宝石； 第一半导体层 201、 第二半 导体层 202与发光层 203为氮化镓 （GaN) 系列材料， 但不以此为限； 透明导电层 204， 材质可选氧化铟锡 （ITO) 或氧化锌 （ZnO) 或氧化镉锡 （CTO) 或氧化 铟 （InO) 或铟 （In) 惨杂氧化锌 （ZnO) 或铝 （A1) 惨杂氧化锌 （ZnO) 或镓
(Ga) 惨杂氧化锌 （ZnO) 或前述任意组合之一， 本实施例优选氧化铟锡 （ITO
[0036] 第一金属层、 第二金属层均由金属本体与金属扩展条组成， 或者第一金属层、 第二金属层均为金属本体； 为了提高电流扩散的均匀性， 本实施例优选第一金 属层 206、 第二金属层 205均由圆形的金属本体与长条形的金属扩展条组成， 金 属层材质为 Cr、 Ti、 Pt、 Au、 Ag、 Ni、 Cu、 TiW的一种或其组合， 但不以此为 限。
[0037] 绝缘层 207的幵口结构可以位于圆形的金属本体以及长条形的金属扩展条上， 或仅位于圆形的金属本体上， 本实施例优选绝缘层 207覆盖于长条形的金属扩展 条上， 绝缘层的幵口结构仅位于圆形的金属本体上； 绝缘层材质为 SiO 2、 A1 20 3 、 SiN x、 TiO 2的一种或其组合， 本实施例优选低折射率的 SiO 2与高折射率的 TiO 2交替堆叠组成的分布布拉格反射层结构， 以利于反射发光层发出的光线， 增加 出光。 [0038] 第一共晶层 2081， 形成于具有幵口的绝缘层 207上， 如此则第一共晶层 2081下 表面与第二金属层 205接触， 用于实现电流导通； 第一共晶层 2091， 形成于具有 幵口的绝缘层 207上， 如此则第一共晶层 2081下表面与第一金属层 206接触， 用 于实现电流导通。 由于第一共晶层 2081、 2091的下方具有凸起状第二金属层 205 ， 因此第一共晶层 2081、 2091的上、 下表面不平坦， 即第一共晶层的上、 下表 面呈凹凸状。
[0039] 第二共晶层 2082、 2092分别形成于第一共晶层 2081、 2091上， 第二共晶层 2082
、 2092在垂直方向上与第一金属层 205、 第二金属层 206均不重叠， 即第二共晶 层避幵金属电极本体及金属扩展条区域； 第二共晶层， 位于第一共晶层凹凸状 上表面的平坦底部区域， 以获得上表面平坦的第二共晶层； 第一型电极区 209的 第二共晶层 2092高度与所述第二型电极区 208的第二共晶层 2082高度齐平， 如此 形成平整的共晶平面。
[0040] 请参考图 6， 本实施例的倒装 LED芯片用于共晶封装吋， 由于第二共晶层的上 表面高于第一共晶层的上表面， 且第二共晶层的上表面平坦且高度齐平， 形成 平整的共晶平面， 有效降低与封装支架 210共晶焊过程产生的空洞率； 此外， 第 二共晶层 2082、 2092面积大大超过第一金属层 205、 第二金属层 206， 如此可以 增加共晶有效面积， 共晶焊更牢固， 从而提高倒装 LED芯片封装良率， 增加电流 稳定性与均匀性。
[0041] 实施例 2
[0042] 请参考图 7和图 8， 与实施例 1区别的是， 本实施例的第二共晶层 3082、 3092的 上表面与第一共晶层 3081、 3091的上表面齐平， 进一步增加了共晶电极结构的 平坦上表面面积， 增强共晶焊的牢固性， 提升封装良率及电流扩展的均匀性。
[0043] 由上述本发明实施方式可知， 应用本发明之双层共晶电极设计， 即第一共晶层 用于与半导体底层实现电流流通， 第二共晶层避幵金属层 （可含金属扩展条） 凸起区域， 在不增加封装支架的成本下， 可解决习知共晶电极设计在共晶制程 中因电极高度差 （平整度差） 产生过高的空洞率导致共晶失效的问题， 从而提 高倒装 LED芯片封装良率， 增加电流稳定性与均匀性。

Claims
权利要求书
倒装 LED芯片的共晶电极结构， 其特征在于： 所述共晶电极结构， 在 垂直方向从下至上由第一共晶层和第二共晶层组成， 在水平方向划分 为第一型电极区和第二型电极区， 第一共晶层的上表面、 下表面不平 坦， 第二共晶层的上表面平坦。
根据权利要求 1所述的倒装 LED芯片的共晶电极结构， 其特征在于： 所述第一共晶层的下表面与倒装 LED芯片接触， 用于实现电流导通。 根据权利要求 1所述的倒装 LED芯片的共晶电极结构， 其特征在于： 所述第二共晶层的上表面高于或等于第一共晶层的上表面， 用于形成 平整的共晶平面。
倒装 LED芯片结构， 包括： 基板； 第一半导体层位于基板上； 发光层 位于第一半导体层上； 第二半导体层位于发光层上； 局部缺陷区位于 部分第二半导体层上， 且向下延伸至第一半导体层； 第一金属层， 位 于部分第一半导体层上； 第二金属层， 位于部分第二半导体层上； 绝 缘层， 覆盖于第一金属层、 第二金属层、 第二半导体层以及局部缺陷 区的第一半导体层上， 其中绝缘层具有幵口结构， 分别位于第一金属 层和第二金属层上； 共晶电极结构， 位于具有幵口的绝缘层上， 在垂 直方向从下至上由第一共晶层和第二共晶层组成， 在水平方向上划分 为第一型电极区和第二型电极区， 第一共晶层的上表面、 下表面不平 坦， 第二共晶层的上表面平坦。
根据权利要求 4所述的倒装 LED芯片， 其特征在于： 所述第一共晶层 的下表面分别与第一金属层、 第二金属层接触， 用于实现电流导通。 根据权利要求 4所述的倒装 LED芯片， 其特征在于： 所述第二共晶层 在垂直方向上与第一金属层、 第二金属层均不重叠。
根据权利要求 4所述的倒装 LED芯片， 其特征在于： 所述第二共晶层 的上表面高于或等于第一共晶层的上表面， 用于形成平整的共晶平面
[权利要求 8] 根据权利要求 4所述的倒装 LED芯片， 其特征在于： 所述第一型电极 区的第二共晶层高度与所述第二型电极区的第二共晶层高度齐平。
[权利要求 9] 根据权利要求 4所述的倒装 LED芯片， 其特征在于： 所述第一金属层
、 第二金属层均由金属本体与金属扩展条组成， 或者第一金属层、 第 二金属层均为金属本体。
[权利要求 10] 根据权利要求 9所述的倒装 LED芯片， 其特征在于： 所述绝缘层的幵 口结构仅位于金属本体上。
[权利要求 11] 根据权利要求 4所述的倒装 LED芯片， 其特征在于： 在所述第二半导 体上形成透明导电层。
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