Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0003—Details of control, feedback or regulation circuits
  • H02M1/0009—Devices or circuits for detecting current in a converter
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
  • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
  • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

• At least certain embodiments disclosed herein relate generally to electronic circuits, and more particularly to an improved bi-directional current sensing circuit and method.
• Power conversion circuitry is employed in many applications, such as in portable devices, which utilize an external power source to operate the device and/or to charge internal batteries of the device.
• the current drawn from a source may need to be limited according to specifications published for devices drawing power from the connection.
• USB universal serial bus
• portable devices may be limited to drawing at most 500 mA from a USB 2.0 connection.
• USB 3.0 connections are typically limited to drawing 900 mA of current.
• Power conversion circuitry provides power conversion with current limiting using current sensing.
• Current sensing circuitry may be important in various power conversion devices such as battery chargers, switched-mode chargers, power converters, voltage regulators, etc. Bi-directional current sensing is needed to monitor the current in such devices during forward current mode and reverse current mode. The sensed current information may then be used for regulating the forward or reverse currents in the device, and also for fuel gauging to compute charge transfer in and out of the battery.
• FIG. 1 depicts an example of a conventional current sensing circuit utilized in a switched-mode charger according to the prior art.
• current sensing circuit 10 includes a USB IN input power source configured to supply current to a buck/boost power regulator 120.
• Circuit 10 includes two independent current sensing loops 102 and 104 for sensing current flow in both the forward and reverse directions respectively.
• current sensing circuit 10 includes a first independent loop 102 comprising a forward current sensing transistor SFET Chg and a first operational amplifier 106, and a second independent loop 104 comprising a reverse current sensing transistor
• forward current flows into the device from the USB IN input through a front porch FET transistor FP FET and into the power regulator 120.
• the feedback loop 102 comprising the forward current sensing transistor SFET Chg and operational amplifier 106 senses this current and is configured to equalize the drain-to-source voltage Vds of the power transistor FP FET and the forward current sensing transistor SFET Chg such that a sensed current " ⁇ " will be a replica of the forward current.
• the feedback loop 104 comprising the reverse current sensing transistor SFET RB and the operational amplifier 108 senses this reverse current and is configured to equalize the drain-to-source voltage Vds of the front porch transistor FP FET and the reverse current sensing transistor SFET RB such that a sensed current "12" will be a replica of the reverse current.
• Such circuits however occupy a significant amount of integrated die area, requiring two independent current sensing operational amplifiers 106 and 108, thereby increasing cost and design complexity.
• the circuit includes an area efficient bi-directional current sensing circuit using current sensing transistor gate control.
• the circuit includes a first current sensing transistor coupled between a current sensing circuit node and a first terminal of the power transistor.
• the first current sensing transistor can be configured to sense current conducting in the power transistor during a forward current mode of the circuit.
• the circuit further includes a second current sensing transistor coupled between the current sensing circuit node and a second terminal of the power transistor.
• the second current sensing transistor can be configured to sense current conducting in the power transistor during a reverse current mode of the circuit.
• the first and second current sensing transistors form a series connection in parallel with the power transistor.
• the circuit also includes a level shifter configured to provide complementary outputs depending on the mode of the circuit.
• the level shifter includes a first output coupled with the gate terminal of the first current sensing transistor to activate or deactivate the first current sensing transistor, and a second output coupled with the gate terminal of the second current sensing transistor to activate or deactivate the second current sensing transistor.
• the complementary outputs of the level shifter are configured to either turn on the first current sensing transistor and turn off the second current sensing transistor when the circuit is in forward current mode, or rum off the first current sensing transistor and turn on the second current sensing transistor when the circuit is in reverse current mode.
• the circuit comprises two current sensing loops including a first current sensing loop and a second current sensing loop. Only one of the current sensing loops is active at any one time based on the complementary outputs of the level shifter.
• the first current sensing loop comprises the first current sensing transistor coupled with an operational amplifier and the second current sensing loop comprises the second current sensing transistor coupled with the operational amplifier.
• the operational amplifier is configured to equalize voltage of the first terminal of the power transistor with a voltage of a corresponding terminal of the first current sensing transistor, or to equalize voltage of the second terminal of the power transistor with a voltage of a corresponding terminal of the second current sensing transistor.
• the circuit further comprises selection logic configured for selecting between sensing forward and reverse currents in the power transistor based on the mode of the circuit.
• the output of the selection logic will either be a signal mirroring the voltage at the first terminal of the power transistor during forward current mode, or a signal mirroring the voltage at the second terminal of the power transistor during reverse current mode.
• a method for sensing current conducting in a power transistor coupled between an input power supply and a power regulator comprises sensing current conducting in the power transistor during a forward current mode of the circuit at a first current sensing transistor coupled between a current sensing node of the circuit and a first terminal of the power transistor, and sensing current conducting in the power transistor during a reverse current mode of the circuit at a second current sensing transistor coupled between the current sensing node of the circuit and a second terminal of the power transistor.
• the first and second current sensing transistors form a series connection in parallel with the power transistor.
• the method further comprises providing complementary outputs from a level shifter depending on the mode of the circuit.
• the level shifter includes a first output coupled with the gate terminal of the first current sensing transistor to activate or deactivate the first current sensing transistor, and a second output coupled with the gate terminal of the second current sensing transistor to activate or deactivate the second current sensing transistor.
• the method activates only one of a first current sensing loop comprising the first current sensing transistor or a second current sensing loop comprising the second current sensing transistor at a time based on the complementary outputs of the level shifter by either turning on the first current sensing transistor and turning off the second current sensing transistor when the circuit is in forward current mode, or turning off the first current sensing transistor and turning on the second current sensing transistor when the circuit is in reverse current mode.
• the method further comprises selecting between sensing the forward current or the reverse current in the power transistor based on the mode of the circuit.
• the output of the selection logic will either be a signal mirroring the voltage of the first terminal of the power transistor during forward current mode, or a signal mirroring the voltage of the second terminal of the power transistor during reverse current mode.
• a circuit means for sensing current conducting in a power transistor coupled between an input power supply and a power regulator includes a means for sensing current conducting in the power transistor during a forward current mode of the circuit at a first current sensing transistor coupled between a current sensing circuit node and a first terminal of the power transistor, means for sensing current conducting in the power transistor during a reverse current mode of the circuit at a second current sensing transistor coupled between the current sensing circuit node and a second terminal of the power transistor, means for providing complementary outputs from a level shifter depending on the mode of the circuit, where the level shifter includes a first output coupled with the gate terminal of the first current sensing transistor to activate or deactivate the first current sensing transistor, and a second output coupled with the gate terminal of the second current sensing transistor to activate or deactivate the second current sensing transistor, and a means for activating only one of a first current sensing loop comprising the first current sensing transistor and a second current sensing loop
• FIG. 1 depicts an example of a conventional current sensing circuit utilized in a switched-mode power charger according to the prior art.
• FIG. 2 depicts an example circuit diagram of an embodiment of an area- efficient bi-directional current sensing circuit using current sensing transistor gate control.
• FIG. 3 depicts an equivalent circuit for the example circuit diagram embodiment of FIG. 2 during forward current mode.
• FIG. 4 depicts an equivalent circuit for the example circuit diagram embodiment of FIG. 2 during reverse current mode.
• FIG. 5 depicts an example circuit diagram of a level-shifter circuit.
• FIG. 6A depicts an example flow chart of an embodiment of a process for sensing a forward current in a bi-directional current sensing circuit designed according to the techniques described herein.
• FIG. 6B depicts an example flow chart of an embodiment of a process for sensing a reverse current in a bi-directional current sensing circuit designed according to the techniques described herein.
• FIG. 2 depicts an example circuit diagram of an embodiment of an area efficient bi-directional current sensing circuit using current sensing transistor gate control.
• Bi-directional current sensing circuit 20 includes a USB IN power input configured for forward current and/or reverse current in a buck/boost regulator 220.
• the configuration of circuit 20 combines two uni-directional current sensing feedback loops into a single bi-directional current sensing circuit configured such that only one feedback loop is activated at any one time, and thus only one operational amplifier is required for current sensing in both the forward and reverse current directions.
• Circuit 20 is configured for sensing current in the forward and reverse current directions respectively.
• circuit 20 includes a front porch power transistor FP FET, a forward current sensing transistor SFET Chg, and a reverse current sensing transistor SFET RB.
• Circuit 20 further comprises a multiplexer ("MUX") 202 for selecting between sensing the forward or reverse current based on the selected mode (mode_sel signal), a level shifter circuit 230 configured to turn on/off the forward and reverse current sensing transistors SFET Chg and SFET RB, respectively, and an operational amplifier 204 configured for sensing either the forward or reverse current and for equalizing the drain-to-source voltage Vds of the power transistor FP FET with either the forward current sensing transistor SFET Chg during forward current mode or the reverse boost current sensing transistor SFET RB during reverse current mode.
• MUX multiplexer
• Circuit 20 also includes an operational amplifier 210 for buffering the feedback signal "FB" via resistor Rl to generate a buffered feedback voltage FB Buf, which is supplied to the buck/boost regulator 220 via an input logic block 212.
• the buck/boost regulator 220 includes an inductor and a capacitor coupled with two input transistors.
• the buck/boost regulator 220 can be a voltage step down circuit adapted to step down the input power voltage supplied by USB IN to a lower voltage "Vsys" for use by internal components of the system, such as a processor,
• circuit techniques described herein are not limited to any particular semiconductor technology. It will be appreciated by persons of skill in the art that other types of transistors or equivalent devices may be used to implement the embodiments described herein. For example, embodiments may be implemented in transistor technologies including MOSFET, JFET, BJT, IGBT, GaAs, etc. In addition, it should further be noted that although the techniques described herein are based on an NFET transistor configuration, persons of skill in the art will appreciate that these techniques can also be based on a PFET transistor configuration as such is a simple design choice for a circuit designer.
• the level shifter circuit 230 only activates one of the feedback loops at any given time interval depending on the mode_sel signal at the input.
• the gates of the current sensing transistors SFET Chg and SFET RB are driven by complementary output signals from the level shifter 230.
• the level shifter circuit 230 is configured to either turn on the forward current sensing transistor SFET Chg and turn off the reverse boost current sensing transistor SFET RB, or turn off the forward current sensing transistor SFET Chg and turn on the reverse boost current sensing transistor SFET RB.
• the level shifter 230 provides an output voltage that swings between Vg (input voltage of circuit 20) and USB_IN - AY
• the level shifter 230 can be designed such that the output voltage Vg is high enough to turn on the current sensing transistors SFET Chg or SFET RB, and such that the output voltage USB IN - AV is low enough to turn off the current sensing transistors SFET Chg or SFET RB.
• the level shifter 230 is described in more detail in FIG. 5 discussed below.
• the level shifter 230 outputs the gate voltage Vg to the input gate voltage Vg_Chg of the forward current sensing transistor
• SFET Chg and the level shifter 230 outputs USB_IN - AV to the input gate voltage Vg RB of the reverse boost current sensing transistor SFET RB.
• This has the effect of turning on the current sensing transistor SFET Chg and turning off the reverse boost current sensing transistor SFET RB.
• SFET Chg will be active and mirroring the forward current in forward current mode.
• the level shifter 230 outputs the gate voltage Vg to the input gate voltage Vg_RB of the reverse boost current sensing transistor SFET RB and the level shifter 230 outputs USB IN - AV to the input gate voltage Vg_Chg of the forward current sensing transistor SFET_Chg.
• This has the effect of turning off the current sensing transistor SFET Chg and turning on the reverse boost current sensing transistor SFET RB.
• SFET RB will be active and mirroring the reverse current in reverse boost mode.
• the circuit 20 is either sensing the forward current in forward current mode or sensing the reverse current in reverse boost mode.
• MUX 202 is configured to select between the drain and source terminals of the power transistor FP FET in forward and reverse boost modes, respectively, depending on the state of the mode_sel signal. When the state of the mode_sel signal is set equal to 0, forward current mode is selected and the input sO of MUX 202 will be active while input si is inactive. The sO input of the MUX 202 will receive the signal from the drain terminal of the power transistor FP FET.
• the voltage signal at the output of the MUX 202 is provided to the negative (-) input 208 of the operational amplifier 204.
• the positive (+) input 206 of the operational amplifier is supplied with either the voltage signal taken at the current sensing node 203 via the forward current sensing transistor SFET_Chg during forward current mode, or the voltage signal taken at the current sensing node 203 via the reverse boost current sensing transistor SFET RB during reverse current mode.
• the feedback loop comprising the forward current sensing transistor SFET_Chg and the operational amplifier 204 is configured to sense the forward current and to equalize the drain-to-source voltages Vds of FP FET and SFET Chg such that the sensed current I sense mirrors the forward current.
• the feedback loop comprising the reverse current sensing transistor SFET RB and the operational amplifier 204 is configured to sense the reverse current and to equalize the drain-to-source voltage Vds of FP FET and SFET RB such that the sensed current I_sense mirrors the reverse boost current.
• the sensed current I sense is then provided as a feedback signal FB via resistor Rl, and is buffered in operational amplifier 210 to produce a buffered feedback voltage FB Buf.
• the buffered feedback FB Buf can then be supplied to the input logic block 212 of the buck/boost regulator 220.
• the buck/boost regulator 220 can be configured to receive this feedback current and use it for regulating the forward and reverse currents in the device, and also for fuel gauging to compute charge transfer in and out of the device as discussed above.
• FIG. 3 depicts an equivalent circuit for the example circuit diagram embodiment of FIG. 2 during forward current mode.
• power flows in from USB IN through the front porch power transistor FP FET and into the buck/boost regulator 320.
• the mode_sel signal is set equal to 0 and therefore the output of the level shifter 330 supplies voltage signal Vg to the gate terminal of SFET_Chg to turn it on and supplies USB IN - AV to the gate terminal of SFET RB to turn it off.
• Forward current therefore flows through SFET Chg and into the circuit as shown.
• the sO input of MUX 302 is selected and the voltage signal Vd at the drain terminal of FP FET is provided at the output of the MUX 302 and is supplied to the negative (-) input terminal 308 of the operational amplifier 304.
• the positive (+) input terminal 306 of the operational amplifier 304 is supplied with the voltage signal at the current sensing node 303 via transistor SFET Chg.
• the feedback loop comprising the forward current sensing transistor SFET Chg and the operational amplifier 304 is configured to sense the forward current and to equalize the drain-to-source voltages Vds of FP FET and SFET Chg such that the sensed current I sense mirrors the forward current.
• I sense is then provided as a feedback voltage FB via resistor Rl, and is buffered in operational amplifier 310 to produce a buffered feedback voltage FB Buf.
• the buffered feedback FB Buf can then be supplied to the input logic block 312 of the buck/boost regulator 320.
• FIG. 4 depicts an equivalent circuit for the example circuit diagram embodiment of FIG. 2 during reverse current.
• USB_IN in reverse current mode USB_IN is no longer supplying power to the circuit.
• the power accumulated in the buck/boost regulator 420 flows back from the buck/boost regulator 420 through the front porch power transistor FP FET in the opposite direction.
• the mode sel signal is set equal to 1 and therefore the output of the level shifter 430 supplies voltage signal Vg to the gate terminal of SFET RB to turn it on and supplies USB IN - AV to the gate terminal of SFET Chg to turn it off.
• Reverse boost current therefore flows through SFET RB and into the circuit as shown.
• the si input of MUX 402 is selected and the voltage signal Vs at the source terminal of FP FET is provided at the output of the MUX 402 and is supplied to the negative (-) input terminal 408 of the operational amplifier 404.
• the positive (+) input 406 of the operational amplifier 404 is supplied with the voltage signal at the current sensing node 403 via transistor SFET RB.
• the feedback loop comprising the reverse boost current sensing transistor SFET RB and the operational amplifier 404 is configured to sense the reverse current and to equalize the drain-to-source voltages Vds of FP FET and SFET RB such that the sensed current I sense mirrors the reverse current.
• I sense is then provided as a feedback signal "FB" via resistor Rl, and is buffered in operational amplifier 410 to produce a buffered feedback voltage FB Buf.
• the buffered feedback voltage FB Buf can then be supplied to the input logic block 412 of the buck/boost regulator 420.
• FIG. 5 depicts an example circuit diagram of a level shifter circuit configuration.
• level shifter circuit 50 is configured to receive at its input (1) the mode_sel signal, (2) the USB_IN power signal, and (3) the input voltage signal Vg.
• the level shifter circuit is configured to supply complementary output voltages at outputs Out and Out b.
• level shifter circuits are well known and the embodiments described herein are not limited to any particular circuit configuration so long as it provides complementary outputs where output Out is equal to Vg and output Out b is equal to USB IN - AV, or output Out is equal to USB IN - AV and output Out_b is equal to Vg.
• USB_IN - AV can be selected such that it is low enough to turn off the current sensing transistors SFET Chg and SFET RB of FIGs. 2-4
• mode_sel input signal is inverted at inverting node 502 via a first inverter 540 and inverted again at (non-inverting) node 504 via a second inverter 541.
• the inverted mode_sel signal at the inverting node 502 is supplied to activate transistors 506 and 510 and the non-inverted mode_sel signal at the non-inverting node 504 is supplied to activate transistor 508.
• inverting node 502 will deactivate transistors 506 and 510 and noninverting node 504 will activate transistor 508.
• the output voltage at output Out b will therefore be the input voltage Vg conducting down through transistors 518 and 520 and the output voltage at the output Out will be the voltage USB IN minus the voltage AV of the conducting diode D3.
• the level shifter circuit 50 in this configuration is adapted to supply complementary voltages Vg and USB IN at the outputs Out and Outb respectively during forward or reverse current mode.
• Other equivalent circuit configurations are possible.
• the operations may be embodied in computer-executable code, which causes a general-purpose or special-purpose computer to perform certain functional operations. In other in stances, these operations may be performed by specific hardware components or hardwired circuitry, or by any combination of programmed computer components and custom hardware circuitry.
• FIG. 6A depicts an example flow chart of an embodiment of a process for sensing a forward current in a bi-directional current sensing circuit designed according to the techniques described herein with reference to FIG. 2 above.
• process 600 begins at operation 601 where the current conducting in the power transistor during forward current mode is sensed at a first current sensing transistor coupled between a current sensing node of the circuit and a first terminal of the power transistor.
• the first terminal of the power transistor is the source terminal.
• Process 600 continues at operation 602 by providing complementary outputs from a level shifter 230 depending on the selected mode of the circuit.
• the level shifter 230 includes a first output coupled with the gate terminal of the first current sensing transistor SFET_Chg to activate or deactivate the first current sensing transistor and a second output coupled with the gate terminal of a second current sensing transistor SFET RB to activate or deactivate the second current sensing transistor.
• the circuit 20 comprises two current sensing loops but only one of the current sensing loops may be active at any one time based on the complementary outputs of the level shifter.
• Process 600 continues at operation 603 by turning on the first current sensing transistor SFET Chg and turning off the second current sensing transistor SFET RB via the complementary outputs of the level shifter 230 since the circuit is in forward current mode.
• the forward current conducting in the power transistor FP FET sensed in the first current sensing transistor SFET_Chg is then selected (operation 604), and the forward current is mirrored in the current sensing node 203 of the circuit (operation 605).
• the voltage of the first terminal of the power transistor FP FET can then be equalized with the voltage of the corresponding terminal of the first current sensing transistor SFET_Chg using an operational amplifier 204 (operation 606).
• Process 600 continues at FIG. 6B, which depicts an example flow chart of an embodiment of a process for sensing a reverse current in a bi-directional current sensing circuit designed according to the techniques described herein with reference to FIG. 2 above.
• process 600 continues at operation 607 where the current conducting in the power transistor FP FET during reverse current mode is sensed at a second current sensing transistor SFET RB coupled between the current sensing node 203 of the circuit and a second terminal of the power transistor.
• the second terminal of the power transistor FP FET is the drain terminal.
• Process 600 continues at operation 608 by providing complementary outputs from a level shifter 230 depending on the mode of the circuit.
• the level shifter 230 includes a first output coupled with the gate terminal of the first current sensing transistor SFET_Chg to activate or deactivate the first current sensing transistor and a second output coupled with the gate terminal of a second current sensing transistor SFET RB to activate or deactivate the second current sensing transistor.
• Process 600 continues at operation 609 by turning on the second current sensing transistor SFET RB and turning off the first current sensing transistor
• the proposed solution is therefore capable of current sensing in applications with bi-directional power flow.
• the proposed solution provides an area-efficient bidirectional current sensing solution where current sensing is required in both the forward and reverse current directions.
• the embodiments described herein are adapted to combine two unidirectional current sensing feedback loops into a single bi-directional current sensing circuit.
• the circuit is configured to mirror the current flowing in the power transistor directly in a single mirroring stage in such a manner that multiple stages of indirect current mirroring and matching is not required.
• the current flowing in the forward or reverse current directions can be directly mirrored in either the forward current sensing transistor or the reverse current sensing transistor, respectively.
• the embodiments described herein can also reduce testing time during design parameter trimming. Since some design parameters vary with processing variations and may mismatch from chip to chip, chip-level measurements are required to trim them back to a desired value.
• the sense ratio can vary with mismatch and layout parasitics, for example. This can be corrected by trimming the resistor Rl such that the overall sense gain is corrected to the desired value for each individual chip during testing. Since the trimming is done on each chip, it adds to the cost and test time. But the bi-directional current sensing technique described herein only requires trimming in one direction, which improves accuracy and reduces testing time during manufacturing.
• DSP Digital Signal Processor
• ASIC Application Specific Integrated Circuit
• FPGA Field Programmable Gate Array
• a general purpose processor may be a microprocessor, but in the altemative, the processor may be any conventional processor, controller, microcontroller, or state machine, etc.
• a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of
• microprocessors one or more microprocessors in conjunction with a DSP core, or any other such configuration.
• RAM Random Access Memory
• ROM Read Only Memory
• EPROM Electrically Programmable ROM
• EEPROM Electrically erasable ROM
• registers hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled with the processor such that the processor can read information from, and write information to, the storage medium.
• the storage medium may be integrated into the processor.
• Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
• a storage media may be any available media that can be accessed by a computer.
• such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

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