WO2017054251A1 - 用于测量接触电阻的tft及接触电阻的测量方法 - Google Patents

用于测量接触电阻的tft及接触电阻的测量方法 Download PDF

Info

Publication number
WO2017054251A1
WO2017054251A1 PCT/CN2015/091441 CN2015091441W WO2017054251A1 WO 2017054251 A1 WO2017054251 A1 WO 2017054251A1 CN 2015091441 W CN2015091441 W CN 2015091441W WO 2017054251 A1 WO2017054251 A1 WO 2017054251A1
Authority
WO
WIPO (PCT)
Prior art keywords
tft
channel
contact resistance
active layer
doped regions
Prior art date
Application number
PCT/CN2015/091441
Other languages
English (en)
French (fr)
Inventor
孙博
邹晓灵
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/896,741 priority Critical patent/US9903904B2/en
Publication of WO2017054251A1 publication Critical patent/WO2017054251A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/488—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes

Definitions

  • the present invention relates to the field of TFT technology, and in particular to a method for measuring a contact resistance of a TFT and a contact resistance.
  • TFT Thin-Film-Transistor
  • the TFT is a triode including a gate, a source, and a drain.
  • Vth initial voltage
  • the active layer When the gate voltage exceeds the initial voltage (Vth), the active layer generates carriers under the gate voltage. Aggregation and band bending, forming a conductive channel, if a non-zero voltage is applied between the source and the drain, the carriers in the conductive channel can be directionalally moved by the voltage to form Current, this is the basic principle of TFT devices as a driver.
  • R C is the contact resistance
  • R L is the channel resistance
  • L is the length of the channel in the TFT.
  • the invention provides a measuring method for a TFT for measuring contact resistance and a contact resistance, which can solve the problem that the prior art has poor uniformity caused by measurement using a plurality of devices and the measurement result is inaccurate.
  • a technical solution adopted by the present invention is to provide a TFT for measuring contact resistance
  • the TFT includes an active layer, a gate electrode and a gate insulating layer; and the active layer is provided with a trench a channel and four doped regions, wherein the two doped regions are connected by a channel, and when the contact resistance is measured, two of the doped regions are used as test points, and the active layer is organic a semiconductor material, the doped region is an N-type doped region or a P-type doped region formed by an ion implantation method; a gate is disposed corresponding to the channel; a gate insulating layer is used to isolate the active layer and The gate.
  • the doped region is an electrode of the TFT, and a distance between the two electrodes is a channel length.
  • two of the doped regions are located at both ends of the active layer.
  • the channel length between each two adjacent doped regions is different.
  • another technical solution adopted by the present invention is to provide a TFT for measuring contact resistance, the TFT including an active layer, a gate electrode, and a gate insulating layer.
  • a channel and at least three doped regions are disposed on the active layer, and the two doped regions are connected by a channel.
  • two of the doped regions are used as test points. Make measurements.
  • a gate is disposed corresponding to the channel.
  • a gate insulating layer is used to isolate the active layer and the gate.
  • the doped region is an electrode of the TFT, and a distance between the two electrodes is a channel length degree.
  • two of the doped regions are located at both ends of the active layer.
  • the active layer is provided with four doping regions.
  • the channel length between each two adjacent doped regions is different.
  • the active layer is made of an organic semiconductor material, and the doped region is an N-type doped region or a P-type doped region.
  • another technical solution adopted by the present invention is to provide a measuring method of contact resistance, the measuring method comprising the steps of: providing a channel and at least three dopings on an active layer of the TFT to be measured.
  • the impurity region, the two doped regions are connected by a channel, and two of the doped regions are measured as test points to obtain a total resistance between the two test points.
  • the test point is replaced to change the channel length, and the total resistance between the two test points after the replacement is measured and obtained, wherein the channel length is two of the doped regions. The distance between them.
  • a relationship diagram of the channel length and the total resistance is made based on at least two measurement data, and contact resistance is obtained according to the relationship diagram.
  • replacing the test point in the step of replacing the test point to change the channel length on the measured TFT, measuring and obtaining the total resistance between the two test points after replacement, replacing the test point is to replace one of the test points, or Replace both test points at the same time.
  • the present invention is activated by TFT At least three doped regions are disposed on the layer.
  • the contact resistance two of the doped regions are selected as test points to form a test point group for testing, and then the length of the channel is changed by selecting different test point groups, thereby Detecting multiple sets of total resistance values under different channel lengths, thereby realizing acquisition of multiple sets of measurement data on one TFT device without fabricating multiple TFT devices, the present invention can maximize different trenches in one TFT
  • the length of the device is integrated in the same position, and the uniformity is good, which makes the process, film quality and interface properties to be the most similar, which improves the measurement accuracy, saves the distribution area, and improves the utilization rate of the test area.
  • Figure 1 is a graph showing the relationship between the sum of contact resistance and channel resistance and the channel length
  • FIG. 2 is a schematic structural view of a TFT device required for measuring contact resistance in the prior art
  • FIG. 3 is a schematic top plan view of an embodiment of a TFT for measuring contact resistance according to the present invention.
  • FIG. 4 is a schematic view showing a layered structure of a cross section of a TFT embodiment for measuring contact resistance of the present invention
  • Fig. 5 is a flow chart showing an embodiment of a method for measuring contact resistance of the present invention.
  • FIG. 3 is a schematic top plan view of an embodiment of a TFT for measuring contact resistance according to the present invention
  • FIG. 4 is a layered view of a cross section of an embodiment of the TFT for measuring contact resistance of the present invention. Schematic.
  • the present invention provides a TFT for measuring contact resistance including an active layer, a gate electrode 300, and a gate insulating layer 500.
  • the active layer is provided with a channel 100 and at least three doped regions 200, and the two doped regions 200 are connected by a channel 100.
  • the contact resistance is measured, two of the doped regions 200 are tested. Point to measure.
  • the gate 300 is disposed corresponding to the channel 100.
  • the gate insulating layer 500 is used to isolate the active layer and the gate 300.
  • test points When measuring the contact resistance, select two test points as a test point group to perform measurement to obtain the total resistance between the two test points, and then replace the test points to change the channel between the two test points.
  • the length is measured to obtain the total resistance value at different channel lengths.
  • a straight line as shown in Fig. 1 can be made, so that the value of the contact resistance can be obtained from the intersection of the straight line and the vertical axis in the figure.
  • the more test point groups are measured, the more data is obtained, and the more accurate the resulting contact resistance value.
  • the present invention selects two of the doped regions as test points to form a test point group by measuring at least three doping regions on the active layer of the TFT, and then selecting Different test point groups are used to change the length of the channel, so that multiple sets of total resistance values under different channel lengths can be measured, thereby realizing acquisition of multiple sets of measurement data on one TFT device without making multiple TFTs.
  • the device can integrate the devices of different channel lengths at the same position in a TFT, and the uniformity is good, so that the process, the film forming quality and the interface properties are maximally similar, thereby improving the measurement accuracy and saving.
  • the distribution area improves the utilization rate of the test area.
  • the TFT of the present embodiment includes a substrate 400, a gate electrode 300, a gate insulating layer 500, and an active layer.
  • the substrate 400 may be a glass substrate having good thermal stability so as to maintain stable properties after a plurality of high temperature processes. Since the chemicals used in the TFT manufacturing process are many, the glass substrate needs to have good chemical resistance. The glass substrate also needs to have sufficient mechanical strength, good precision machining characteristics, and excellent electrical insulation properties.
  • the gate electrode 300 is disposed on the buffer layer, the gate electrode 300 is disposed corresponding to the channel 100, and the gate electrode 300 is generally formed of a material such as aluminum or aluminum alloy.
  • the gate insulating layer 500 covers the gate 300, and the gate insulating layer 500 may be a layer.
  • the gate insulating layer 500 may be SiO, SiN or AlO, and has a thickness of about 175-300 nm.
  • the gate insulating layer 500 may also be provided as two layers, and the first layer is a SiO 2 film.
  • a second layer of SiN x is added to the SiO 2 film.
  • the active layer includes a channel 100 and a doped region 200, wherein the channel 100 is formed of an organic semiconductor material over the gate insulating layer 500, and then a doping region 200 is formed on the channel 100 by ion implantation.
  • the impurity region 200 is an electrode of the TFT, that is, a source or a drain, and a distance between the two electrodes is a channel length, and the doping region 200 may be an N-type doped region or a P-type doped region.
  • doping regions 200 there are four doping regions 200 in this embodiment, and the four doping regions are disposed on the channel 100, wherein two doping regions 200 are disposed at two ends of the active layer, and the remaining two doping regions 200 Located in the middle of the active layer.
  • the channel length between each two adjacent doped regions 200 is different.
  • the channel length between each two adjacent doping regions 200 may be equal, or may be a trench between at least two adjacent doping regions 200.
  • the lengths of the tracks are different, as long as at least two different channel lengths can be obtained when selecting different test point groups.
  • the four doping regions 200 of the present embodiment are a doping region 201, a doping region 202, a doping region 203, and a doping region 204, respectively.
  • the four doping regions 200 are spaced apart on the channel 100, wherein the doping region 201 and the doping region 204 are respectively disposed at two ends of the active layer, and the doping region 202 and the doping region 203 are disposed on the active layer.
  • the middle portion wherein the channel length between the doped region 201 and the doped region 202 is the length of the channel 101, and the channel length between the doped region 202 and the doped region 203 is the length of the channel 102, doped
  • the channel length between the impurity region 203 and the doping region 204 is the length of the channel 103, and as shown in FIG. 3, the lengths of the channel 101, the channel 102, and the channel 103 are L1, L2, and L3, respectively. In the present embodiment, L1 ⁇ L2 ⁇ L3.
  • test point groups that can be selected are:
  • the doped region 201 and the doped region 202 have a channel length of L1.
  • the doped region 201 and the doped region 203 have a channel length of L1 + L2.
  • the doped region 201 and the doped region 204 have a channel length of L1+L2+L3.
  • the doped region 202 and the doped region 203 have a channel length of L2.
  • the doped region 202 and the doped region 204 have a channel length of L2+L3.
  • the doped region 203 and the doped region 204 have a channel length of L3.
  • the channel length and total can be accurately drawn. A straight line of the relationship between the resistance values, so that the contact resistance can be obtained.
  • test data of six TFTs as shown in FIG. 2 can be obtained by one TFT.
  • the number of doped regions 200 of the present invention is four or more. When there are four, the number of data points required by the TLM method is completely met. When the number of doped regions 200 is five, up to 10 test point groups can be obtained. In actual production, the number of test points, that is, the number of doped regions 200, can be determined according to different data needs. Such a device design can maximize the integration of devices of different channel lengths at the same position, so that The process, film quality and interface properties are maximally similar to achieve the closest performance to the actual material.
  • the TFT of the present embodiment may be a sample for measuring contact resistance in other methods, such as a sample for measuring contact resistance, for example, a four-probe method, so that the test can be performed by different methods. The results are confirmed to ensure the credibility of the data.
  • the TFT of this embodiment is a TFT of a bottom gate structure, and the gate 300 is disposed under the channel 100. It is worth mentioning that the present invention is also applicable to a TFT of a top gate structure.
  • FIG. 5 is a schematic flow chart of an embodiment of a method for measuring a contact resistance according to the present invention.
  • the method for measuring contact resistance provided by the present invention comprises the following steps:
  • a channel and at least three doped regions are disposed on an active layer of the measured TFT, and two doped regions are connected by a channel, and two doped regions are used as test points for measurement to obtain The total resistance between the two test points.
  • the doping region 201 and the doping region 202 are selected as test points for measurement.
  • the total resistance R total1 measured is the sum of the contact resistance and the channel resistance when the channel length is L1.
  • step S102 the test point is replaced by replacing one of the test points or replacing the two test points at the same time, as long as the channel length can be changed.
  • the doping region 201 and the doping region 203 are selected as test points for measurement.
  • the total resistance R total2 measured is the sum of the contact resistance and the channel resistance when the channel length is L1+L2.
  • the total resistance between the doped region 201 and the doped region 204 can be measured again.
  • the measured total resistance R total3 is the contact resistance and the channel length is L1+L2+L3. The sum of the channel resistances.
  • doped regions 202 and doped regions 203, and/or doped regions 202 and doped regions 204, and/or doped regions 203 and doped regions 204 may also be selected, so that up to six sets of data can be measured.
  • the channel length is taken as the abscissa and the total resistance is taken as the ordinate.
  • the doping region 201 and the doping region 203 are selected as a test point group, (L1+L2, R total2 ) can be traced , and the two points can determine a straight line of the relationship between the total resistance and the channel length.
  • a straight line that describes the relationship between the total resistance and the channel length can be determined by two points. Of course, the more points are drawn, the more accurate the line is.
  • points (L1+L2+L3, R total3 ), (L2, R total4 ), (L2+L3, R total5 ), and (L3, R total6 ) may be traced , and then according to the six The points are plotted as a straight line of the relationship between the total resistance and the channel length, and the value of the intersection of the line and the vertical axis is the value of the contact resistance.
  • the invention can acquire multiple sets of measurement data on one TFT device without forming a plurality of TFT devices, since the uniformity of the devices of different channel lengths can be maximized in one TFT, the process is good, and the process thereof is The film formation quality and the interface properties are maximally similar, so the measurement accuracy can be improved.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

一种用于测量接触电阻的TFT及接触电阻的测量方法，该TFT包括有源层、栅极（300）和栅极绝缘层（500），有源层上设有沟道（100）和至少三个掺杂区（200），两个掺杂区（200）之间通过沟道（100）连接，在测量接触电阻时，以其中两个掺杂区（200）作为测试点进行测量；栅极（300）与沟道（100）对应设置；栅极绝缘层（500）用于隔离有源层和栅极（300）。该测量方法均一性好，制程、成膜质量以及界面性质最大程度的相似，提高了测量准确性，同时节省了分布区域，提高了试验区域的利用率。

Description

用于测量接触电阻的TFT及接触电阻的测量方法 【技术领域】
本发明涉及TFT技术领域，特别是涉及一种用于测量接触电阻的TFT及接触电阻的测量方法。
【背景技术】
Thin-Film-Transistor(TFT)器件是目前半导体行业最广泛的应用，在显示、传感器以及芯片等行业有大量的应用。对于场效应电晶体的研究主要包括稳定性以及功能性。
TFT是一个三极管，包括栅极(Gate)、源极(Source)以及漏极(Drain)，当栅极电压超过起始电压(Vth)时，有源层在栅极电压作用下发生载流子聚集以及能带弯曲，形成导电沟道，这时如果在源漏极之间施加一个不为零的电压，则导电沟道中的载流子就能在该电压的作用下产生定向移动，从而形成电流，这就是TFT器件作为驱动的基本原理。
根据物理公式：I＝U/R，当电压一定时，电阻越大，电流越小。在TFT的研究中，如何在较低的Vds下获得较大的电流的导通电流一直是最核心的问题，这就要求尽量的降低源、漏极之间的电阻。由于一般的源、漏极采用金属制作，而半导体材料一般为非金属材料，故在源、漏极与半导体的界面处会有接触电阻的存在，这是由于制程方面对界面的处理以及金属半导体材料的功函数的差异，因此，沟道电阻跟接触电阻的机制是不同的，在研究中，常常要把两种电阻分开来进行研究。但是，一个TFT器件制作完成后就成为一体的，根据I-V曲线总是得到接触电阻和沟道电阻的总和：
RTotal＝RC+RL，RL＝kL(k为常数) Rtotal＝Rc+kL＝Vds/Ids
其中，RC为接触电阻，RL为沟道电阻，L为TFT中沟道的长度。采用上述公式所述的模型，只要量测不同L的器件，最后做RTotal-L图形，该直线在纵轴的截距即为所求的RC(如图1所示)，这种方法称为TLM(The Transmission  Line Modeling Method)方法。
现有技术中，采用TLM法获取接触电阻时，需要制作多个不同L的TFT器件(如图2所示)，因此，TFT器件制作的均一性会对最终结果产生影响；TFT的分布区域比较大，因而占用的实验区域较大，实验区域利用率较低；多个TFT器件的制作会涉及到界面状态以及工艺制程的重复性的影响。
【发明内容】
本发明提供一种用于测量接触电阻的TFT及接触电阻的测量方法，能够解决现有技术存在使用多个器件进行测量导致的均一性差而使测量结果不准确的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种用于测量接触电阻的TFT，该TFT包括有源层、栅极和栅极绝缘层；所述有源层上设有沟道和四个掺杂区，两个所述掺杂区之间通过沟道连接，在测量接触电阻时，以其中两个所述掺杂区作为测试点进行测量，所述有源层由有机半导体材料制成，掺杂区为通过离子注入法形成的N型掺杂区或者P型掺杂区；栅极与所述沟道对应设置；栅极绝缘层用于隔离所述有源层和所述栅极。
其中，所述掺杂区为所述TFT的电极，两个所述电极之间的距离为沟道长度。
其中，其中两个所述掺杂区位于所述有源层的两端。
其中，每两个相邻的所述掺杂区之间的沟道长度均相异。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种用于测量接触电阻的TFT，该TFT包括有源层、栅极和栅极绝缘层。所述有源层上设有沟道和至少三个掺杂区，两个所述掺杂区之间通过沟道连接，在测量接触电阻时，以其中两个所述掺杂区作为测试点进行测量。栅极与所述沟道对应设置。栅极绝缘层用于隔离所述有源层和所述栅极。
其中，所述掺杂区为所述TFT的电极，两个所述电极之间的距离为沟道长 度。
其中，其中两个所述掺杂区位于所述有源层的两端。
其中，所述有源层上设有四个掺杂区。
其中，每两个相邻的所述掺杂区之间的沟道长度均相异。
其中，所述有源层由有机半导体材料制成，所述掺杂区为N型掺杂区或者P型掺杂区。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种接触电阻的测量方法，该测量方法包括以下步骤：被测量的TFT的有源层上设有沟道和至少三个掺杂区，两个所述掺杂区之间通过沟道连接，以其中两个所述掺杂区作为测试点进行测量，以获取该两个测试点之间的总电阻。在被测量的所述TFT上，更换测试点以改变沟道长度，测量并获取更换后的两个测试点之间的总电阻，其中，所述沟道长度为两个所述掺杂区之间的距离。根据至少两次的测量数据做出沟道长度与所述总电阻的关系图，并根据所述关系图获得接触电阻。
其中，以其中两个所述掺杂区作为测试点进行测量，以获取该两个测试点之间的总电阻，的步骤中，测量的是该两个测试点之间的电压值和电流值，通过公式：Rtotal＝Vds/Ids获取所述总电阻，其中，Rtotal为总电阻，Vds为所述两个测试点之间的电压值，Ids为该两个测试点之间的电流值。
其中，在所述被测量的TFT上，更换测试点以改变沟道长度，测量并获取更换后的两个测试点之间的总电阻的步骤中，更换测试点为更换其中一个测试点，或者同时更换两个测试点。
其中，根据至少两次的测量数据做出沟道长度与所述总电阻的关系图，并根据所述关系图获得接触电阻的步骤中，根据公式：Rtotal＝RC+RL和RL＝kL做出所述沟道长度与所述总电阻的关系图，其中，RC为接触电阻，RL为沟道电阻，k为常数，L为沟道长度。
本发明的有益效果是：区别于现有技术的情况，本发明通过在TFT的有源 层上设至少三个掺杂区，测量接触电阻时，选择其中两个掺杂区作为测试点形成测试点组来进行测试，再通过选择不同的测试点组来改变沟道的长度，从而可以测得不同的沟道的长度下的多组总电阻值，从而实现了在一个TFT器件上获取多组测量数据，而无需制作多个TFT器件，本发明在一个TFT可以最大限度地将不同沟道长度的器件整合在同一位置，均一性好，使其制程、成膜质量以及界面性质最大程度的相似，提高了测量准确性，同时节省了分布区域，提高了试验区域的利用率。
【附图说明】
图1是接触电阻和沟道电阻的总和与沟道长度的关系图；
图2是现有技术测量接触电阻所需的TFT器件的结构示意图；
图3是本发明一种用于测量接触电阻的TFT实施例的俯视结构示意图；
图4是本发明一种用于测量接触电阻的TFT实施例的截面的层状结构示意图；
图5是本发明接触电阻的测量方法实施例的流程示意图。
【具体实施方式】
下面结合附图和具体实施方式对本发明进行详细说明。
请参阅图3和图4，图3是本发明一种用于测量接触电阻的TFT实施例的俯视结构示意图；图4是本发明一种用于测量接触电阻的TFT实施例的截面的层状结构示意图。
本发明提供了一种用于测量接触电阻的TFT，该TFT包括有源层、栅极300和栅极绝缘层500。
其中，有源层上设有沟道100和至少三个掺杂区200，两个掺杂区200之间通过沟道100连接，在测量接触电阻时，以其中两个掺杂区200作为测试点进行测量。
栅极300与沟道100对应设置。
栅极绝缘层500用于隔离有源层和栅极300。
在测量接触电阻的时候，选择其中两个测试点作为一个测试点组来进行测量以获取该两个测试点之间的总电阻，再更换测试点以改变两个测试点之间的沟道的长度来进行测量，从而可以获得不同沟道的长度下的总电阻值。通过获取至少两个沟道的长度的总电阻值，即可做出如图1所示的直线，从而可以根据图中直线与纵轴的交点得出接触电阻的值。当然，测量的测试点组越多，获得的数据越多，最终所得出的接触电阻的值就越精确。
区别于现有技术，本发明通过在TFT的有源层上设至少三个掺杂区，测量接触电阻时，选择其中两个掺杂区作为测试点形成测试点组来进行测试，再通过选择不同的测试点组来改变沟道的长度，从而可以测得不同的沟道的长度下的多组总电阻值，从而实现了在一个TFT器件上获取多组测量数据，而无需制作多个TFT器件，本发明在一个TFT可以最大限度地将不同沟道长度的器件整合在同一位置，均一性好，使其制程、成膜质量以及界面性质最大程度的相似，提高了测量准确性，同时节省了分布区域，提高了试验区域的利用率。
请继续参阅图1和图4，本实施例的TFT包括衬底400、栅极300、栅极绝缘层500以及有源层。
其中，衬底400可以是玻璃基板，该玻璃基板具有好的热稳定性，从而能在多次高温工艺之后保持性质稳定。由于TFT制造工艺中用到的化学药品很多，因而，该玻璃基板需具有很好的化学耐药性。该玻璃基板还需要具有足够的机械强度，还需要有很好的精密机械加工特性以及要有优良的电学绝缘特性。
栅极300设在缓冲层之上，栅极300与沟道100对应设置，栅极300通常采用铝以及铝合金等材料形成。
栅极绝缘层500覆盖在栅极300之上，栅极绝缘层500可以为一层，该层栅极绝缘层500可以是SiO，SiN或AlO，厚度在175-300nm左右。在其它实施例中，栅极绝缘层500还可以设为两层，第一层是SiO2膜，为了提高膜的质量， 在SiO2膜上增加了第二层SiNx。
有源层包括沟道100和掺杂区200，其中，沟道100由有机半导体材料形成在栅极绝缘层500之上，再通过离子注入法，在沟道100上形成掺杂区200，掺杂区200为该TFT的电极，即源极或者漏极，两个电极之间的距离为沟道长度，掺杂区200可以是N型掺杂区或者P型掺杂区。
本实施例的掺杂区200有四个，该四个掺杂区间隔设置在沟道100上，其中的两个掺杂区200设在有源层的两端，其余两个掺杂区200设在有源层的中部。在本实施例中，每两个相邻的掺杂区200之间的沟道长度均相异。
值得一提的是，在其它实施例中，每两个相邻的掺杂区200之间的沟道长度可以均相等，也可以是至少有两个相邻的掺杂区200之间的沟道长度相异，只要能实现在选择不同的测试点组时能获得至少两种不同的沟道长度即可。
举例而言，本实施例的四个掺杂区200分别是掺杂区201、掺杂区202、掺杂区203和掺杂区204。该四个掺杂区200间隔设置在沟道100上，其中，掺杂区201和掺杂区204分别设在有源层的两端，掺杂区202和掺杂区203设在有源层的中部，其中，掺杂区201和掺杂区202之间的沟道长度为沟道101的长度，掺杂区202和掺杂区203之间的沟道长度为沟道102的长度，掺杂区203和掺杂区204之间的沟道长度为沟道103的长度，如图3所示，沟道101、沟道102和沟道103的长度分别为L1、L2和L3，并且，在本实施例中，L1≠L2≠L3。
本实施例在测量的时候，可以选择的测试点组有：
(1)掺杂区201与掺杂区202，沟道长度为L1。
(2)掺杂区201与掺杂区203，沟道长度为L1+L2。
(3)掺杂区201与掺杂区204，沟道长度为L1+L2+L3。
(4)掺杂区202与掺杂区203，沟道长度为L2。
(5)掺杂区202与掺杂区204，沟道长度为L2+L3。
(6)掺杂区203与掺杂区204，沟道长度为L3。
测量接触电阻的时候，通过测量上述测试点组之间至少两组测试点组的总电阻值，例如，测量上述六组的测试点组的总电阻值，可以精确地画出沟道长度与总电阻值之间的关系的直线，从而可以获得接触电阻。
本实施例中，一个TFT即可获得如图2所示的六个TFT的测试数据。
当然，测试点组越多，能获得的测量数据就越多，所作出的沟道长度与总电阻值之间的关系的直线就越精确。本发明的掺杂区200的个数为四个，或者更多。当为四个的时候，完全符合TLM法所要求的数据点数目，当掺杂区200的个数为五个的时候，可以获得多达10个测试点组。在实际制作中，可以根据不同的数据需要来定测试点的数目，即掺杂区200的个数，这样的器件的设计，可以最大限度地将不同沟道长度的器件整合在同一位置，使其制程、成膜质量以及界面性质最大程度的相似，以期得到最接近实际材料的性能。
值得一提的是，本实施例的TFT除了可以是上述方法的测量接触电阻的样品之外，还可以是其它方法测量接触电阻的样品，例如四探针法，从而可以通过不同的方法对试验结果进行确认，保证了数据的可信度。
本实施例的TFT为底栅极结构的TFT，栅极300设在沟道100的下方，值得一提的是，本发明还适用于顶栅极结构的TFT。
请参阅图5，图5是本发明接触电阻的测量方法实施例的流程示意图。
本发明提供的接触电阻的测量方法包括以下步骤：
S101，被测量的TFT的有源层上设有沟道和至少三个掺杂区，两个掺杂区之间通过沟道连接，以其中两个掺杂区作为测试点进行测量，以获取该两个测试点之间的总电阻。
具体而言，步骤S101中选择两个测试点之后进行测量的是该两个测试点之间的电压值和电流值，通过公式：Rtotal＝Vds/Ids获取总电阻，其中，Rtotal为总电阻，Vds为两个测试点之间的电压值，Ids为该两个测试点之间的电流值。
例如，请结合参阅图3，选择掺杂区201和掺杂区202作为测试点进行测量。此时，测量出的总电阻Rtotal1为接触电阻和沟道长度为L1时的沟道电阻之和。
S102，在被测量的TFT上，更换测试点以改变沟道长度，测量并获取更换后的两个测试点之间的总电阻，其中，沟道长度为两个掺杂区之间的距离。
步骤S102中，更换测试点为更换其中一个测试点或者同时更换两个测试点，只要能改变沟道长度即可。
例如，请结合参阅图3，选择掺杂区201和掺杂区203作为测试点进行测量。此时，测量出的总电阻Rtotal2为接触电阻和沟道长度为L1+L2时的沟道电阻之和。
值得一提的是，测试的数据越多，所得的测量结果就越精确。举例而言，本实施例可以再测量掺杂区201与掺杂区204之间的总电阻值，此时，测量出的总电阻Rtotal3为接触电阻和沟道长度为L1+L2+L3时的沟道电阻之和。
此外，还可以选择掺杂区202以及掺杂区203，和/或者掺杂区202以及掺杂区204，和/或掺杂区203以及掺杂区204，因此最多可以测出六组数据。
S103，根据至少两次的测量数据做出沟道长度与总电阻的关系图，并根据关系图获得接触电阻。
具体而言，沟道长度与总电阻的关系图是根据以下公式做出：Rtotal＝RC+RL和RL＝kL，其中，RC为接触电阻，RL为沟道电阻，k为常数，L为沟道长度，由该公式可知，当L＝0时，RL＝0，此时Rtotal＝RC。
举例而言，沟道长度与总电阻的关系图中，以沟道长度作为横坐标，总电阻作为纵坐标。当选择了掺杂区201和掺杂区202作为一个测试点组时，Rtotal1的值由Rtotal＝Vds/Ids可得，从而可以在沟道长度与总电阻的关系图中描出一个点(L1，Rtotal1)。同理，当选择了掺杂区201和掺杂区203作为一个测试点组时，可以描出(L1+L2，Rtotal2)，该两点可以确定总电阻与沟道长度的关系的直线。该直线与纵坐标的交点(L0，Rtotal0)，即沟道长度L0＝0的时候的总电阻值，即接触电阻RC。
描出两个点即可确定总电阻与沟道长度的关系的直线，当然，描出的点数越多，所做出的直线就越精确。
例如，本实施例还可以描出(L1+L2+L3，Rtotal3)、(L2，Rtotal4)、(L2+L3， Rtotal5)和(L3，Rtotal6)等六个点，再根据该六个点绘出总电阻与沟道长度的关系的直线，该直线与纵轴的交点的值即接触电阻的值。
本发明可以在一个TFT器件上获取多组测量数据，而无需制作多个TFT器件，由于在一个TFT可以最大限度地将不同沟道长度的器件整合在同一位置，均一性好，使其制程、成膜质量以及界面性质最大程度的相似，所以能提高测量准确性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种用于测量接触电阻的TFT，其中，包括：
    有源层，所述有源层上设有沟道和四个掺杂区，两个所述掺杂区之间通过沟道连接，在测量接触电阻时，以其中两个所述掺杂区作为测试点进行测量，所述有源层由有机半导体材料制成，掺杂区为通过离子注入法形成的N型掺杂区或者P型掺杂区；
    栅极，与所述沟道对应设置；
    栅极绝缘层，用于隔离所述有源层和所述栅极。
  2. 根据权利要求1所述的TFT，其中，所述掺杂区为所述TFT的电极，两个所述电极之间的距离为沟道长度。
  3. 根据权利要求2所述的TFT，其中，其中两个所述掺杂区位于所述有源层的两端。
  4. 根据权利要求3所述的TFT，其中，每两个相邻的所述掺杂区之间的沟道长度均相异。
  5. 一种用于测量接触电阻的TFT，其中，包括：
    有源层，所述有源层上设有沟道和至少三个掺杂区，两个所述掺杂区之间通过沟道连接，在测量接触电阻时，以其中两个所述掺杂区作为测试点进行测量；
    栅极，与所述沟道对应设置；
    栅极绝缘层，用于隔离所述有源层和所述栅极。
  6. 根据权利要求5所述的TFT，其中，所述掺杂区为所述TFT的电极，两个所述电极之间的距离为沟道长度。
  7. 根据权利要求6所述的TFT，其中，其中两个所述掺杂区位于所述有源层的两端。
  8. 根据权利要求7所述的TFT，其中，所述有源层上设有四个掺杂区。
  9. 根据权利要求8所述的TFT，其中，每两个相邻的所述掺杂区之间的沟道长度均相异。
  10. 根据权利要求9所述的TFT，其中，所述有源层由有机半导体材料制成，所述掺杂区为N型掺杂区或者P型掺杂区。
  11. 一种TFT的接触电阻的测量方法，其中，包括以下步骤：
    被测量的TFT的有源层上设有沟道和至少三个掺杂区，两个所述掺杂区之间通过沟道连接，以其中两个所述掺杂区作为测试点进行测量，以获取该两个测试点之间的总电阻；
    在被测量的所述TFT上，更换测试点以改变沟道长度，测量并获取更换后的两个测试点之间的总电阻，其中，所述沟道长度为两个所述掺杂区之间的距离；
    根据至少两次的测量数据做出沟道长度与所述总电阻的关系图，并根据所述关系图获得接触电阻。
  12. 根据权利要求11所述的测量方法，其中，以其中两个所述掺杂区作为测试点进行测量，以获取该两个测试点之间的总电阻，的步骤中，测量的是该两个测试点之间的电压值和电流值，通过公式：Rtotal＝Vds/Ids获取所述总电阻，其中，Rtotal为总电阻，Vds为所述两个测试点之间的电压值，Ids为该两个测试点之间的电流值。
  13. 根据权利要求12所述的测量方法，其中，在所述被测量的TFT上，更换测试点以改变沟道长度，测量并获取更换后的两个测试点之间的总电阻的步骤中，更换测试点为更换其中一个测试点，或者同时更换两个测试点。
  14. 根据权利要求13所述的测量方法，其中，根据至少两次的测量数据做出沟道长度与所述总电阻的关系图，并根据所述关系图获得接触电阻的步骤中，根据公式：Rtotal＝RC+RL和RL＝kL做出所述沟道长度与所述总电阻的关系图，其中，RC为接触电阻，RL为沟道电阻，k为常数，L为沟道长度。
PCT/CN2015/091441 2015-09-28 2015-10-08 用于测量接触电阻的tft及接触电阻的测量方法 WO2017054251A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/896,741 US9903904B2 (en) 2015-09-28 2015-10-08 TFT device for measuring contact resistance and measurement method for contact resistance

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510629332.0A CN105223420B (zh) 2015-09-28 2015-09-28 用于测量接触电阻的tft及接触电阻的测量方法
CN201510629332.0 2015-09-28

Publications (1)

Publication Number Publication Date
WO2017054251A1 true WO2017054251A1 (zh) 2017-04-06

Family

ID=54992486

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/091441 WO2017054251A1 (zh) 2015-09-28 2015-10-08 用于测量接触电阻的tft及接触电阻的测量方法

Country Status (3)

Country Link
US (2) US9903904B2 (zh)
CN (1) CN105223420B (zh)
WO (1) WO2017054251A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10739389B2 (en) * 2018-03-16 2020-08-11 The Boeing Company Systems and methods for measuring the electrical contact resistance at an interface
CN109637944B (zh) * 2018-10-31 2020-10-30 深圳市华星光电半导体显示技术有限公司 薄膜晶体管结构及沟道电阻和接触电阻的测量方法
CN109300799B (zh) * 2018-11-19 2024-02-02 北京燕东微电子科技有限公司 半导体结构、测试系统、测试方法及半导体结构的制作方法
CN109540971A (zh) * 2018-12-29 2019-03-29 宁波石墨烯创新中心有限公司 导电膜均匀性检测装置、系统以及方法
CN109887933B (zh) * 2019-02-27 2021-08-03 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN110057862A (zh) * 2019-04-24 2019-07-26 苏州浪潮智能科技有限公司 一种使用一元线性回归方程测试接触热阻的方法与系统
CN114384322B (zh) * 2020-10-16 2023-07-18 长鑫存储技术有限公司 晶体管测试器件的接触电阻的测量方法与计算机可读介质
US11867745B2 (en) 2020-10-16 2024-01-09 Changxin Memory Technologies, Inc. Parasitic capacitance detection method, memory and readable storage medium
CN113253089B (zh) * 2021-07-15 2021-09-14 广东省大湾区集成电路与系统应用研究院 一种鳍式场效应晶体管源漏寄生电阻萃取方法
CN117517786A (zh) * 2022-07-28 2024-02-06 清华大学 场效应晶体管的接触电阻的测量方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859720A (zh) * 2010-04-15 2010-10-13 中山大学 一种测量晶体硅太阳能电池表面接触电阻率的方法
CN102735939A (zh) * 2012-07-11 2012-10-17 电子科技大学 一种测量黑硅材料与金属电极之间欧姆接触电阻率的方法
CN103426865A (zh) * 2012-05-16 2013-12-04 上海华虹Nec电子有限公司 半导体制品钨槽接触电阻测试结构及测试方法
CN103995182A (zh) * 2014-05-21 2014-08-20 奥特斯维能源（太仓）有限公司 一种测试金属电极与硅基底之间接触电阻的方法
CN104407224A (zh) * 2014-11-27 2015-03-11 合肥京东方光电科技有限公司 半导体-金属接触电阻率检测方法、阵列基板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4100486A (en) * 1977-03-11 1978-07-11 International Business Machines Corporation Monitor for semiconductor diffusion operations
US7030633B1 (en) * 2004-12-03 2006-04-18 Chunong Qiu Four-terminal methods for resistivity measurement of semiconducting materials
KR101890749B1 (ko) * 2011-10-27 2018-08-23 삼성전자주식회사 전극구조체, 이를 포함하는 질화갈륨계 반도체소자 및 이들의 제조방법
KR20140099230A (ko) * 2011-12-02 2014-08-11 스미토모덴키고교가부시키가이샤 반도체 장치의 제조 방법
JP2014003252A (ja) * 2012-06-21 2014-01-09 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
US8937307B2 (en) * 2012-08-10 2015-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859720A (zh) * 2010-04-15 2010-10-13 中山大学 一种测量晶体硅太阳能电池表面接触电阻率的方法
CN103426865A (zh) * 2012-05-16 2013-12-04 上海华虹Nec电子有限公司 半导体制品钨槽接触电阻测试结构及测试方法
CN102735939A (zh) * 2012-07-11 2012-10-17 电子科技大学 一种测量黑硅材料与金属电极之间欧姆接触电阻率的方法
CN103995182A (zh) * 2014-05-21 2014-08-20 奥特斯维能源（太仓）有限公司 一种测试金属电极与硅基底之间接触电阻的方法
CN104407224A (zh) * 2014-11-27 2015-03-11 合肥京东方光电科技有限公司 半导体-金属接触电阻率检测方法、阵列基板

Also Published As

Publication number Publication date
US9970978B1 (en) 2018-05-15
US20170089973A1 (en) 2017-03-30
US9903904B2 (en) 2018-02-27
CN105223420A (zh) 2016-01-06
US20180120369A1 (en) 2018-05-03
CN105223420B (zh) 2017-07-07

Similar Documents

Publication Publication Date Title
WO2017054251A1 (zh) 用于测量接触电阻的tft及接触电阻的测量方法
US9349659B2 (en) Methods for probing semiconductor fins and determining carrier concentrations therein
EP1902282B1 (de) Sensor
CN105699463A (zh) 一种化学场效应晶体管气敏传感器及其制造方法
US10332811B2 (en) Film test structure and array substrate
CN104576750A (zh) 薄膜晶体管结构
US8900887B2 (en) Method for etching polysilicon gate
US7972912B2 (en) Method of fabricating semiconductor device
WO2018045514A1 (zh) 生物传感器及其制作方法
US8729668B2 (en) Adjustable resistor
US20080100311A1 (en) Electrical Measurement Of The Thickness Of A Semiconductor Layer
CN103426866B (zh) 围栏间隔的设计规则测试电路
KR20230144930A (ko) 표준 웨이퍼, 표준 웨이퍼 제조 방법 및 교정 방법
CN107505376B (zh) 一种基于场效应晶体管结构的pH值传感器件及其制造方法
US20140209906A1 (en) Method of Fabricating GOI Silicon Wafer, GOI Silicon Wafer and GOI Detection Method
CN111029329A (zh) 应用于FinFET工艺中监控EPI的测试结构及方法
Isogai et al. Advanced method for measuring ultra-low contact resistivity between silicide and silicon based on cross bridge Kelvin resistor
KR101202015B1 (ko) ＳＯＩ기판을 이용한 ｐＨ센서 및 그 제작방법
CN102701146B (zh) 一种磷硅玻璃和多晶硅厚度的在线同步测试装置
CN117524898A (zh) 热效应器件结构、其形成方法以及热电阻获取方法
JP5017946B2 (ja) Ｓｏｉウエーハの評価方法
JPH03208375A (ja) 半導体圧力センサ
CN115763292A (zh) 超级结器件结构的电性补偿方法
JPH0574908A (ja) 半導体装置におけるシリコン基板の評価方法
JPS6083345A (ja) 電界効果型トランジスタの特性測定方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14896741

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15905163

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15905163

Country of ref document: EP

Kind code of ref document: A1