WO2017049903A1 - 一种晶体管仿真系统及方法 - Google Patents

一种晶体管仿真系统及方法 Download PDF

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Publication number
WO2017049903A1
WO2017049903A1 PCT/CN2016/080922 CN2016080922W WO2017049903A1 WO 2017049903 A1 WO2017049903 A1 WO 2017049903A1 CN 2016080922 W CN2016080922 W CN 2016080922W WO 2017049903 A1 WO2017049903 A1 WO 2017049903A1
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Prior art keywords
transistor
tested
network
measurement
simulation
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PCT/CN2016/080922
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English (en)
French (fr)
Inventor
孙涵
李春阳
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中兴通讯股份有限公司
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Publication of WO2017049903A1 publication Critical patent/WO2017049903A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]

Definitions

  • the present application relates to, but is not limited to, the field of simulation technology, and in particular, a transistor simulation system and method.
  • the performance of base station products is the main focus of competition in the industry.
  • the improvement of the circuit development technology of power amplifier units is crucial to improve the competitiveness of products in the industry.
  • the transistor is the core device on the circuit.
  • the transistor simulation design needs to borrow the transistor model parameters provided by the device manufacturer.
  • the transistor simulation design needs to borrow the transistor model parameters provided by the device manufacturer.
  • the peripheral circuit of the transistor simulation design has a large simulation error.
  • the simulation design in the related art uses transistor model parameters to cause simulation errors, which is a technical problem to be solved by those skilled in the art.
  • This paper provides a transistor simulation system and method to solve the problem of simulation error caused by using transistor model parameters in simulation design in related art.
  • Embodiments of the present invention provide a transistor emulation system, including:
  • the transistor measuring device is configured to: perform network measurement on the transistor to be tested, and output operating parameters;
  • the transistor simulation device is configured to perform transistor simulation design using operating parameters.
  • the transistor measuring device comprises:
  • At least one transistor test socket configured to: mount a fixed transistor
  • Network analyzer set to: provide network analysis functions
  • the measurement module is connected to the transistor test socket and is also connected to the network analyzer, and is configured to perform network measurement on the transistor to be tested by using the network analyzer.
  • the transistor test socket includes a ground structure and an RF microstrip line
  • the grounding structure is set to: realize the grounding of the transistor to be tested;
  • the RF microstrip line is set to be connected to the input and output terminals of the transistor to be tested to form a measurement circuit.
  • the transistor test socket includes a first shield cavity configured to shield external signals from interference with the transistor to be tested.
  • the measurement module comprises at least one interface component
  • the interface component comprises an impedance conversion circuit board and a corresponding metal base
  • the impedance conversion circuit board is configured to convert the output impedance of the transistor to be tested into a reference impedance
  • the metal base is set to achieve the impedance The conversion board is grounded.
  • the measurement module further includes a bias supply circuit configured to electrically connect the impedance conversion circuit board and the external power supply.
  • the measurement module further includes a second shielding cavity configured to shield the external signal from interference to the impedance conversion circuit board.
  • the transistor measuring device further comprises at least one network calibration component, the different network calibration components being arranged to calibrate the measurement errors of the transistor measuring devices of different specifications.
  • Embodiments of the present invention also provide a transistor simulation method, including:
  • the transistor measuring device performs network measurement on the transistor to be tested, and outputs operating parameters
  • the transistor simulation device uses the operating parameters for transistor simulation design.
  • the transistor measuring device further includes at least one network calibration component
  • the transistor simulation method further includes:
  • Embodiments of the present invention provide a transistor simulation system and method to be tested, and the simulation system is configured There is a transistor measuring device and a simulation device.
  • the working parameter of the transistor to be tested is measured by the transistor measuring device, thereby obtaining the working parameters of the transistor in practical application, and then using the working parameter for simulation design,
  • the simulation result is the use effect of the transistor in normal operation, and the transistor model is more reduced than the application in the related art that the transistor simulation parameter needs to borrow the transistor model parameter provided by the device manufacturer and there is a large simulation error.
  • the simulation error caused by the error between the parameters and the actual working parameters improves the development efficiency of the board and the competitiveness of the performance indicators.
  • FIG. 1 is a schematic structural diagram of a transistor emulation system according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a transistor measuring device according to a second embodiment of the present invention.
  • FIG. 3 is a flowchart of a transistor emulation method according to a third embodiment of the present invention.
  • FIG. 4 is a flow chart of a method of using a transistor measuring device according to a fourth embodiment of the present invention.
  • the transistor emulation system 1 includes:
  • the transistor measuring device 11 is configured to: perform network measurement on the transistor to be tested, and output operating parameters to the transistor emulation device 12;
  • the transistor emulation device 12 is configured to perform transistor emulation design using operating parameters.
  • the transistor measuring device 11 includes:
  • the transistor test socket 111 is configured to: fix and fix the transistor to be tested;
  • the network analyzer 112 is configured to: provide a network analysis function
  • the measurement module 113 is connected to the transistor test socket 111 and is also connected to the network analyzer 112, and is configured to perform network measurement on the transistor to be tested by the network analyzer 112.
  • the transistor test socket 111 in the above embodiment may include a ground structure and an RF microstrip line; the ground structure may be configured to implement grounding of the transistor to be tested, and the RF microstrip line may be set to input and output with the transistor to be tested.
  • the terminals are connected to form a measuring circuit.
  • the transistor test socket 111 in the above embodiment may be provided with a first metal reed at the connection of the radio frequency microstrip line, and the radio frequency microstrip line may utilize the input and output of the first metal reed and the transistor to be tested.
  • the terminal is electrically connected.
  • the transistor test socket 111 in the above embodiment may include a first shield cavity configured to shield external signals from interference with the transistor to be tested.
  • the transistor test socket 111 in the above embodiment may further include a fixing screw configured to fix the input end and the output end (wings on both sides) of the transistor to be tested on the radio frequency microstrip line.
  • the material of the fixing screw in the above embodiment may include: a polyethylene PE plastic insulating material.
  • the measurement module 113 in the above embodiment may include at least one interface component, the interface component may include an impedance conversion circuit board and a corresponding metal base, and the impedance conversion circuit board is configured to transform the output impedance of the transistor to be tested.
  • the metal base is set to ground the impedance conversion board.
  • the impedance conversion circuit board in the above embodiment may be provided with a second metal reed connected to the transistor to be tested through the second metal reed.
  • the measurement module 113 in the above embodiment may further include a bias power supply circuit configured to electrically connect the impedance conversion circuit board with an external power supply.
  • the measurement module 113 in the above embodiment may include an input interface and an output interface, and the network analyzer 112 is connected through the input interface and the output interface.
  • the measurement module 113 in the above embodiment may include a second shielding cavity. It is set to shield the external signal from interference on the impedance conversion board.
  • the transistor measuring device 11 in the above embodiment may further include at least one network calibration component, and different network calibration components may be disposed to the transistor test socket 111 and the measurement module 113 in the transistor measuring device 11 of different specifications. The measurement error is calibrated.
  • the transistor measuring device 11 in the above embodiment may include a plurality of transistor test sockets 111, and different sizes of the transistors to be tested may correspond to different transistor test sockets 111.
  • FIG. 3 is a flowchart of a method for simulating a transistor according to a third embodiment of the present invention. As shown in FIG. 3, in the embodiment, the transistor emulation method includes the following steps:
  • the transistor measuring device performs network measurement on the transistor to be tested, and outputs operating parameters
  • the transistor simulation device performs transistor simulation design using operating parameters.
  • the transistor measurement device in the above embodiment may further include at least one network calibration component, and the transistor simulation method may further include:
  • the method of using the transistor measuring device may include:
  • Network measurements are made using the network analyzer to measure the transistor.
  • the method in the above embodiment may further include: selecting an impedance conversion circuit board of a corresponding specification according to the transistor to be tested.
  • the method in the above embodiments may further include:
  • the transistor test socket and measuring device select the corresponding network calibration component, and use the network calibration component to calibrate the measurement error.
  • the transistor measuring device in the embodiment of the present invention will be further explained in conjunction with a specific application scenario.
  • the transistor measuring device comprises: a transistor test socket, a measurement module (including an interface component, an input interface, an output interface), and a network analyzer.
  • a measurement module including an interface component, an input interface, an output interface
  • a network analyzer specifically,
  • the function of the transistor test socket can be to install the transistor to be tested thereon. While ensuring that the bottom of the transistor to be tested is well grounded, it is also necessary to ensure the input and output ends (wings on both sides) of the transistor to be tested and the micro on the test socket.
  • the strip line is well connected, and the printed circuit board is mounted on the connection structure to achieve measurement of the transistor to be tested.
  • the transistor test socket can include a transistor bottom ground structure and an RF microstrip line.
  • a metal reed of a special structure can be provided at the connection of the transistor to be tested and the RF microstrip line.
  • the interface assembly can include an impedance conversion circuit board and its corresponding metal base.
  • the output impedance of the transistor to be tested can be low impedance. Since the measuring devices in the related art are all measured for a 50 ohm system, it is necessary to design a corresponding impedance conversion circuit board, which is to convert the test port of the transistor to be tested to 50. ohm.
  • a corresponding metal base can be disposed under the impedance conversion circuit board, and the function is to make the ground of the impedance conversion circuit board continuous with the ground of the transistor test socket while ensuring good grounding of the impedance conversion circuit board.
  • a special structure of metal reed can be placed to ensure that the impedance conversion board and the transistor to be tested are tightly connected.
  • the transistor to be tested may be an active device, so a corresponding bias supply circuit may be disposed in the interface component, and the function is to connect the printed circuit board and the external power source outside the transistor test socket.
  • a PTFE (Polytetrafluoroethylene) screw may be disposed above the metal reed above the wing of the transistor to be tested and the impedance conversion circuit board and the circuit to be tested.
  • the function is to press the transistor wings and metal reeds to be tested on the network port of the circuit under test, thereby realizing the current continuity between the RF microstrip lines.
  • the transistor measuring device of the embodiment of the invention can be respectively provided with a corresponding metal cavity structure above the transistor test socket and the impedance conversion circuit board, and the function thereof is to ensure the space stability of the circuit to be measured and minimize external interference. It is necessary to ensure that the metal cavity structure and the metal base are well connected during installation to ensure the continuity of the metal cavity structure and the ground of the metal base.
  • the transistor measuring device of the embodiment of the present invention can be applied to the measurement of the transistor to be tested from 0 GHz to 6 GHz.
  • Corresponding network calibration components can be set for different packages of transistors to be tested and different impedance conversion circuits.
  • the measurement error caused by the transistor test socket, interface component, input interface, and output interface can be calibrated by the TRL (Through/Reflect/Line) calibration method using the network calibration component. After the calibration is completed, the parameter characteristics of the transistor pins to be tested can be accurately measured by the calibrated measuring device.
  • This embodiment adopts a new structure, and takes into account the stability of the test network connection port, the reusability of the test network connection port, the error caused by the PTFE screw material for the network test, and the network calibration theory and method.
  • the transistor to be tested of various packaging methods is designed to have a general measurement structure of the transistor to be tested, has an interconnect structure capable of quickly loading the circuit under test, and has high test stability.
  • the transistor measuring device provided by the embodiment has the advantages of being able to quickly load the interconnected structure of the circuit under test and having high reusability while realizing the measuring function of the transistor to be tested in various packaging modes.
  • the transistor measurement device provided by the embodiment through CST (Computer Simulation Technology), ADS (Advanced Design System) software modeling and simulation and actual measurement, shows that the stability of the test socket network itself is high, indicating The test error due to the instability of the network itself is very low.
  • the reusability of the embodiment of the invention is high, and the calibration error introduced by the test station's own network calibration is small.
  • the transistor measuring device presses the wings of the transistor to be tested and the metal reed at the circuit connection on the network port of the circuit under test through the PTFE screw above the bracket, thereby realizing the continuity of current between the circuits to be tested.
  • PE Polyethylene, polyethylene
  • These stable scattering characteristics can be removed by network calibration, thereby improving the test accuracy of the measured microstrip network.
  • the transistor test circuit and the impedance conversion circuit to be tested have the current consistency of the port.
  • a corresponding bias circuit is designed to achieve stable external power supply of the transistor to be tested.
  • corresponding metal cavity structures are respectively designed to ensure the space stability of the circuit to be measured and to minimize external interference.
  • the transistor measuring device of the embodiment of the invention is suitable for measuring the scattering parameter (S parameter) of the transistor to be tested in a plurality of package modes in the frequency range of 0 GHz to 6 GHz, as shown in FIG. 4 , the crystal
  • the method of using the body tube measuring device can include the following steps:
  • an appropriate transistor test stand and a gradient line impedance conversion circuit can be selected according to the package mode and port impedance of the transistor to be tested.
  • the input and output interfaces can be connected to a vector network analyzer. Define calibration network parameters and set up the network analyzer.
  • the corresponding TRL network calibration component can be designed for different types of packaged transistors to be tested and different impedance conversion circuits.
  • the network calibration component can be used to join the measurement system in turn, and the measurement system error of the scattering parameter (S parameter) is included by the TRL calibration method (including the network analyzer, the transistor test socket, the input interface, and the output interface). Measurement error) is calibrated. After the calibration is completed, the S-parameter data of the package package section of the transistor to be tested can be accurately measured by the calibrated measurement system.
  • This step can include the following substeps:
  • the wings of the transistor to be tested are pressed against the network port of the circuit under test by a PTFE screw;
  • the bias circuit is connected to the external power source, checking the power supply of the transistor to be tested is normal, and adjusting the gate voltage of the transistor to be tested to the rated quiescent current;
  • an embodiment of the present invention provides a transistor simulation system and method to be tested, and the simulation system A transistor measuring device and a transistor emulating device are provided, and in use, the working parameters of the transistor to be tested are measured by the transistor measuring device, thereby obtaining the operating parameters of the transistor in practical application, and then using the operating parameter for simulation
  • the simulation result is the use effect of the transistor during normal operation.
  • the transistor simulation design needs to borrow the transistor model parameters provided by the device manufacturer, and the simulation error is greatly reduced.
  • the simulation error caused by the error between the transistor model parameters and the actual operating parameters improves the development efficiency of the board and the competitiveness of the performance indicators;
  • the transistor measuring device realizes the network measurement function of the transistor to be tested by using a network analyzer, so that the user can obtain more accurate working parameters, and avoids the subsequent simulation effect due to the difference between the model parameters and the physical device parameters.
  • the appearance of a phenomenon
  • the transistor measuring device has a transistor test socket that quickly loads a plurality of transistor networks to be tested, and is suitable for measurement of a transistor to be tested in a plurality of package modes, and provides a measurement precision and a fast for the development of the power amplifying unit circuit. Loaded measurement tool.
  • Embodiments of the present invention provide a transistor simulation system and method for detecting a transistor.
  • the simulation system is provided with a transistor measurement device and a simulation device.
  • the transistor measurement device performs network measurement on the operating parameters of the transistor to be tested, which can be obtained.
  • the operating parameters of the transistor in practical application, and then use the working parameters for simulation design, the simulation result is the use effect of the transistor in normal operation, and the transistor simulation design needs to borrow the transistor model parameters provided by the device manufacturer.
  • the simulation error caused by the error between the transistor model parameters and the actual operating parameters is reduced to a greater extent, and the development efficiency of the circuit board and the competitiveness of the performance index are improved.

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Abstract

一种晶体管仿真系统包括：晶体管测量装置，设置为：对待测晶体管进行网络测量，输出工作参数；晶体管仿真装置，设置为：利用工作参数进行晶体管仿真设计。

Description

一种晶体管仿真系统及方法 技术领域
本申请涉及但不限于仿真技术领域，尤其一种晶体管仿真系统及方法。
背景技术
面对目前日益激烈的市场竞争，基站产品的性能高低是业内竞争的主要焦点，功率放大单元电路开发技术水平的提高，对于提高产品的业内竞争力是至关重要的。在功率放大单元电路开发中，晶体管是电路上的核心器件，通过在电路板的投板前期，精确进行晶体管仿真设计、从而设计出对应的匹配电路，可以检验模块电路的设计是否满足应用要求，这决定着电路板的开发效率和性能指标的竞争力，也可以提高模块电路的设计水平。
但是，在相关技术中，由于用户不能获取实体晶体管器件的工作参数，晶体管仿真设计需借用器件厂家提供的晶体管模型参数，在实际生产中，由于设计、制造工艺等外界不可控因素，比如导致晶体管模型参数和实体晶体管器件的工作参数之间存在差异，进而晶体管仿真设计的外围电路存在较大的仿真误差。
因此，相关技术中仿真设计使用晶体管模型参数导致仿真误差，是本领域技术人员亟待解决的技术问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本文提供了一种晶体管仿真系统及方法，以解决相关技术中仿真设计使用晶体管模型参数导致仿真误差的问题。
本发明实施例提供了一种晶体管仿真系统，包括：
晶体管测量装置，设置为：对待测晶体管进行网络测量，输出工作参数；
晶体管仿真装置，设置为：利用工作参数进行晶体管仿真设计。
可选地，晶体管测量装置包括：
至少一个晶体管测试座，设置为：安装固定晶体管；
网络分析仪，设置为：提供网络分析功能；
测量模块，与晶体管测试座连接，还与网络分析仪连接，设置为：利用网络分析仪对待测晶体管进行网络测量。
可选地，晶体管测试座包括接地结构及射频微带线；
接地结构设置为：实现待测晶体管接地；
射频微带线设置为：与待测晶体管的输入输出端连接，形成测量电路。
可选地，晶体管测试座包括第一屏蔽腔体，其设置为：屏蔽外部信号对待测晶体管的干扰。
可选地，测量模块包括至少一个接口组件，接口组件包括阻抗变换电路板及其对应的金属底座，阻抗变换电路板设置为将待测晶体管的输出阻抗变换为基准阻抗，金属底座设置为实现阻抗变换电路板接地。
可选地，测量模块还包括偏置供电电路，其设置为：电连接阻抗变换电路板与外部供电电源。
可选地，测量模块还包括第二屏蔽腔体，其设置为：屏蔽外部信号对阻抗变换电路板的干扰。
可选地，晶体管测量装置还包括至少一个网络校准组件，不同的网络校准组件设置为对不同规格的晶体管测量装置的测量误差进行校准。
本发明实施例还提供了一种晶体管仿真方法，包括：
晶体管测量装置对待测晶体管进行网络测量，输出工作参数；
晶体管仿真装置利用工作参数进行晶体管仿真设计。
可选地，晶体管测量装置还包括至少一个网络校准组件，晶体管仿真方法还包括：
采用不同的网络校准组件，对不同规格的晶体管测量装置的测量误差进行校准。
本发明实施例提供了一种待测晶体管仿真系统及方法，该仿真系统设置 有晶体管测量装置及仿真装置，在使用时，利用晶体管测量装置对待测晶体管的工作参数进行网络测量，这就可以得到该晶体管在实际应用时的工作参数，进而利用该工作参数进行仿真设计，其仿真结果就是该晶体管正常工作时的使用效果，与相关技术中因晶体管仿真设计需借用器件厂家提供的晶体管模型参数而存在较大的仿真误差的应用相比，更大程度地降低了由于晶体管模型参数与实际工作参数之间的误差所导致的仿真误差，提高了电路板的开发效率和性能指标的竞争力。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1为本发明第一实施例提供的晶体管仿真系统的结构示意图；
图2为本发明第二实施例提供的晶体管测量装置的结构示意图；
图3为本发明第三实施例提供的晶体管仿真方法的流程图；
图4为本发明第四实施例提供的晶体管测量装置使用方法的流程图。
本发明的较佳实施方式
下面结合附图对本发明的实施方式进行描述。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的各种方式可以相互组合。
第一实施例：
图1为本发明第一实施例提供的晶体管仿真系统的结构示意图，参见图1，在本实施例中，晶体管仿真系统1包括：
晶体管测量装置11，设置为：对待测晶体管进行网络测量，输出工作参数至晶体管仿真装置12；
晶体管仿真装置12，设置为：利用工作参数进行晶体管仿真设计。
第二实施例：
图2为本发明第二实施例提供的晶体管测量装置的结构示意图，参见图2，在本实施例中，晶体管测量装置11包括：
晶体管测试座111，设置为：安装固定待测晶体管；
网络分析仪112，设置为：提供网络分析功能；
测量模块113，与晶体管测试座111连接，还与网络分析仪112连接，设置为：利用网络分析仪112对待测晶体管进行网络测量。
在一些实施例中，上述实施例中的晶体管测试座111可包括接地结构及射频微带线；接地结构可设置为实现待测晶体管接地，射频微带线可设置为与待测晶体管的输入输出端连接，形成测量电路。
在一些实施例中，上述实施例中的晶体管测试座111可以在射频微带线的连接处设置有第一金属簧片，射频微带线可利用第一金属簧片与待测晶体管的输入输出端电连接。
在一些实施例中，上述实施例中的晶体管测试座111可包括第一屏蔽腔体，其设置为：屏蔽外部信号对待测晶体管的干扰。
在一些实施例中，上述实施例中的晶体管测试座111还可包括固定螺钉，固定螺钉设置为：将待测晶体管的输入端及输出端(两侧翅膀)固定在射频微带线上。
在一些实施例中，上述实施例中的固定螺钉的材料可包括：聚乙烯PE塑料绝缘材料。
在一些实施例中，上述实施例中的测量模块113可包括至少一个接口组件，接口组件可包括阻抗变换电路板及其对应的金属底座，阻抗变换电路板设置为将待测晶体管的输出阻抗变换为基准阻抗，金属底座设置为实现阻抗变换电路板接地。
在一些实施例中，上述实施例中的阻抗变换电路板可设置有第二金属簧片，通过第二金属簧片与待测晶体管连接。
在一些实施例中，上述实施例中的测量模块113还可包括偏置供电电路，其设置为：电连接阻抗变换电路板与外部供电电源。
在一些实施例中，上述实施例中的测量模块113可包括输入接口及输出接口，通过输入接口及输出接口连接网络分析仪112。
在一些实施例中，上述实施例中的测量模块113可包括第二屏蔽腔体， 其设置为：屏蔽外部信号对阻抗变换电路板的干扰。
在一些实施例中，上述实施例中的晶体管测量装置11还可包括至少一个网络校准组件，不同的网络校准组件可设置为对不同规格的晶体管测量装置11内的晶体管测试座111及测量模块113的测量误差进行校准。
在一些实施例中，上述实施例中的晶体管测量装置11可包括多个晶体管测试座111，不同尺寸规格的待测晶体管可对应不同的晶体管测试座111。
第三实施例：
图3为本发明第三实施例提供的晶体管仿真方法的流程图，由图3可知，在本实施例中，该晶体管仿真方法包括以下步骤：
S301：晶体管测量装置对待测晶体管进行网络测量，输出工作参数；
S302：晶体管仿真装置利用工作参数进行晶体管仿真设计。
在一些实施例中，上述实施例中的晶体管测量装置还可包括至少一个网络校准组件，该晶体管仿真方法还可包括：
采用不同的网络校准组件，对不同规格的晶体管测量装置的测量误差进行校准。
在实际使用中，晶体管测量装置的使用方法可包括：
根据待测晶体管选择晶体管测试座，并安装；
将晶体管测试座与测量模块连接；
利用网络分析仪对待测晶体管进行网络测量。
在一些实施例中，当测量模块包括至少一个接口组件时，上述实施例中的方法还可包括：根据待测晶体管选择对应规格的阻抗变换电路板。
在一些实施例中，当晶体管测量装置包括网络校准组件时，上述实施例中的方法还可包括：
根据不同规格的晶体管测试座及测量装置，选择对应的网络校准组件，利用网络校准组件进行测量误差的校准。
现结合具体应用场景对本发明实施例中的晶体管测量装置作进一步的诠释说明。
第四实施例：
在本实施例中，晶体管测量装置包括：晶体管测试座、测量模块(包括接口组件、输入接口、输出接口)及网络分析仪。具体地，
晶体管测试座的作用可以是将待测晶体管安装在其上，在保证待测晶体管底部接地良好的同时，还需保证待测晶体管的输入端及输出端(两侧翅膀)和测试座上的微带线连接良好，以及将印制电路板安装在连接结构上来实现待测晶体管的测量。
晶体管测试座可以包括：晶体管底部接地结构以及射频微带线。为了确保待测晶体管的翅膀和射频微带线连接紧密以及确保连接端口的稳定性，可以在待测晶体管和射频微带线的连接处设置特殊结构的金属簧片。
接口组件可以包括阻抗变换电路板及其对应的金属底座。待测晶体管的输出阻抗可呈低阻，由于相关技术中的测量设备都是针对50欧姆系统进行测量，所以需设计对应的阻抗变换电路板，其作用是将待测晶体管的测试端口转换到50欧姆。阻抗变换电路板下可以设置对应的金属底座，其作用是在保证阻抗变换电路板接地良好的同时，使阻抗变换电路板的地与晶体管测试座的地连续。阻抗变换电路板的低阻抗一侧，可以设置特殊结构的金属簧片，以确保阻抗变换电路板和待测晶体管紧密连接。
待测晶体管可以是有源器件，所以上述接口组件内，可设置对应的偏置供电电路，其作用是将印制电路板和晶体管测试座外的外部电源连通。
本发明实施例的晶体管测量装置，在被测待测晶体管的翅膀上方、阻抗变换电路板与被测电路连接的金属簧片的上方，可以设置有PTFE(Polytetrafluoroethylene，聚四氟乙烯)螺钉，它的作用是可以将待测晶体管翅膀、金属簧片紧压在被测电路的网络端口上，从而实现射频微带线间的电流连续性。
本发明实施例的晶体管测量装置，在晶体管测试座、阻抗变换电路板的上方，可以分别设置有对应的金属腔体结构，其作用是确保被测量电路的空间稳定性、尽量减小外界干扰。安装时需确保金属腔体结构和金属底座连接良好，确保金属腔体结构和金属底座的地的连续性。
本发明实施例的晶体管测量装置可应用在0GHz～6GHz的待测晶体管测量中。针对不同封装的待测晶体管和不同的阻抗变换电路，可以设置对应的网络校准组件。可以利用网络校准组件，通过TRL(Through/Reflect/Line，直通/反射/线)校准方法，将晶体管测试座、接口组件、输入接口、输出接口带来的测量误差进行校准。校准完成后，可通过校准后的测量装置准确地测量到待测晶体管引脚的参数特性。
本实施例采用新型的结构，在对测试网络连接端口的稳定性、测试网络连接端口的可重复使用性、PTFE螺钉材料对于网络测试带来的误差、网络校准理论与方法进行充分分析后，兼顾多种封装方式的待测晶体管，设计出通用的待测晶体管的测量结构，具有可快速载入被测电路的互连结构、测试稳定性高的优点。
采用本实施例提供的晶体管测量装置，在实现对于多种封装方式的待测晶体管的测量功能的同时，具有可快速载入被测电路的互连结构、重复利用性强的优点。本实施例提供的晶体管测量装置，通过CST(Computer Simulation Technology，计算机仿真技术)、ADS(Advanced Design System，高级设计系统)软件的建模仿真和实测表明，测试座网络本身的稳定性高，表明由于网络自身不稳定产生的测试误差很低。本发明实施例的可重复利用性高，并且测试座自身网络校准引入的校准误差小。该晶体管测量装置，通过支架上方的PTFE螺钉将待测晶体管的翅膀、电路连接处的金属簧片紧压在被测电路的网络端口上，实现了被测电路间的电流连续性。通过大量的实验得到PTFE螺钉使用PE(Polyethylene，聚乙烯)材料的波散射几乎可忽略，这些稳定的散射特性是可以通过网络校准去除掉的，从而提高被测微带网络的测试精度。并可以通过金属簧片的连接作用，使待测晶体管测试电路和阻抗变换电路具有端口的电流一致性。针对有源器件，设计了对应的偏置电路，实现待测晶体管的稳定外部供电。在晶体管测试座、阻抗变换电路板的上方，分别设计对应的金属腔体结构，确保被测量电路的空间稳定性、尽量减小外界干扰。
本发明实施例的晶体管测量装置，适用于对于0GHz～6GHz频段内、多种封装方式的待测晶体管的散射参数(S参数)的测量，如图4所示，该晶 体管测量装置的使用方法可包括以下步骤：
S401：选择构件，完成线路连接。
本步骤中，可根据待测晶体管的封装方式和端口阻抗，选择合适的晶体管测试座和渐变线阻抗变换电路。
可将输入接口、输出接口连接到矢量网络分析仪。定义校准网络参数，设置网络分析仪。
S402：进行系统校准。
本步骤中，可以针对不同种封装方式的待测晶体管和不同的阻抗变换电路，设计对应的TRL网络校准组件。可依次分别利用网络校准组件与测量系统对接(join together)，通过TRL校准方法，将散射参数(S参数)的测量系统误差(包括网络分析仪、晶体管测试座、输入接口、输出接口带来的测量误差)进行校准。校准完成后，可通过校准后的测量系统准确地测量到待测晶体管封装断面的S参数数据。
S403：安装待测晶体管，进行工作参数测试。
本步骤可包括以下子步骤：
将待测晶体管安装于晶体管测试座上，不需焊接；
将晶体管测试座与测量模块对接；
安装晶体管测试座、阻抗变换电路，检查连接处的金属簧片是否连接正确；
将晶体管测试座、阻抗变换电路对应的金属腔体安装正确，通过PTFE螺钉将电路连接处的金属簧片紧压在被测电路的网络端口上，使被测电路的网络端口与左、右底板上的微带网络端口接触良好；
通过PTFE螺钉将待测晶体管的翅膀压紧在被测电路的网络端口上；
偏置电路连接外部电源，检查待测晶体管的供电正常，调整待测晶体管的栅压至额定静态电流；
开始网络测量。
综上，本发明实施例提供了一种待测晶体管仿真系统及方法，该仿真系 统设置有晶体管测量装置及晶体管仿真装置，在使用时，利用晶体管测量装置对待测晶体管的工作参数进行网络测量，这就可以得到该晶体管在实际应用时的工作参数，进而利用该工作参数进行仿真设计，其仿真结果就是该晶体管正常工作时的使用效果，与相关技术中因晶体管仿真设计需借用器件厂家提供的晶体管模型参数而存在较大的仿真误差的应用相比，更大程度地降低了由于晶体管模型参数与实际工作参数之间的误差所导致的仿真误差，提高了电路板的开发效率和性能指标的竞争力；
进一步地，晶体管测量装置采用网络分析仪实现了待测晶体管的网络测量功能，这样用户就可以获取更准确的工作参数，避免了由于模型参数与实体器件参数之间的差异导致后续仿真效果较差现象的出现；
进一步地，晶体管测量装置具有快速载入多种待测晶体管网络的晶体管测试座，适用于对于多种封装方式的待测晶体管的测量，为功率放大单元电路的开发提供了一个测量精度高、快速载入的测量工具。
本领域的普通技术人员可以理解，可以对本申请的技术方案进行修改或者等同替换，而不脱离本申请技术方案的精神和范围。本申请的保护范围以权利要求所定义的范围为准。
工业实用性
本发明实施例提供了一种待测晶体管仿真系统及方法，该仿真系统设置有晶体管测量装置及仿真装置，在使用时，利用晶体管测量装置对待测晶体管的工作参数进行网络测量，这就可以得到该晶体管在实际应用时的工作参数，进而利用该工作参数进行仿真设计，其仿真结果就是该晶体管正常工作时的使用效果，与相关技术中因晶体管仿真设计需借用器件厂家提供的晶体管模型参数而存在较大的仿真误差的应用相比，更大程度地降低了由于晶体管模型参数与实际工作参数之间的误差所导致的仿真误差，提高了电路板的开发效率和性能指标的竞争力。

Claims (10)

  1. 一种晶体管仿真系统，包括：
    晶体管测量装置，设置为：对待测晶体管进行网络测量，输出工作参数；
    晶体管仿真装置，设置为：利用所述工作参数进行晶体管仿真设计。
  2. 如权利要求1所述的晶体管仿真系统，其中，所述晶体管测量装置包括：
    至少一个晶体管测试座，设置为：安装固定待测晶体管；
    网络分析仪，设置为：提供网络分析功能；
    测量模块，与所述晶体管测试座连接，还与所述网络分析仪连接，设置为：利用所述网络分析仪对所述待测晶体管进行网络测量。
  3. 如权利要求2所述的晶体管仿真系统，其中，
    所述晶体管测试座包括接地结构及射频微带线；所述接地结构设置为实现所述待测晶体管接地，所述射频微带线设置为与所述待测晶体管的输入输出端连接，形成测量电路。
  4. 如权利要求3所述的晶体管仿真系统，所述晶体管测试座包括第一屏蔽腔体，所述第一屏蔽腔体设置为：屏蔽外部信号对所述待测晶体管的干扰。
  5. 如权利要求2所述的晶体管仿真系统，其中，所述测量模块包括至少一个接口组件，所述接口组件包括阻抗变换电路板及所述阻抗变换电路板对应的金属底座，所述阻抗变换电路板设置为将所述待测晶体管的输出阻抗变换为基准阻抗，所述金属底座设置为实现所述阻抗变换电路板接地。
  6. 如权利要求5所述的晶体管仿真系统，所述测量模块还包括偏置供电电路，所述偏置供电电路设置为：电连接所述阻抗变换电路板与外部供电电源。
  7. 如权利要求5所述的晶体管仿真系统，所述测量模块还包括第二屏蔽腔体，所述第二屏蔽腔体设置为：屏蔽外部信号对所述阻抗变换电路板的干扰。
  8. 如权利要求1至7任一项所述的晶体管仿真系统，所述晶体管测量装 置还包括至少一个网络校准组件，不同的所述网络校准组件设置为对不同规格的所述晶体管测量装置的测量误差进行校准。
  9. 一种晶体管仿真方法，包括：
    晶体管测量装置对待测晶体管进行网络测量，输出工作参数；
    晶体管仿真装置利用所述工作参数进行晶体管仿真设计。
  10. 如权利要求9所述的晶体管仿真方法，所述晶体管测量装置还包括至少一个网络校准组件，所述晶体管仿真方法还包括：
    采用不同的所述网络校准组件，对不同规格的所述晶体管测量装置的测量误差进行校准。
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