WO2017031755A1 - 一种扫描驱动电路 - Google Patents

一种扫描驱动电路 Download PDF

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Publication number
WO2017031755A1
WO2017031755A1 PCT/CN2015/088262 CN2015088262W WO2017031755A1 WO 2017031755 A1 WO2017031755 A1 WO 2017031755A1 CN 2015088262 W CN2015088262 W CN 2015088262W WO 2017031755 A1 WO2017031755 A1 WO 2017031755A1
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WO
WIPO (PCT)
Prior art keywords
switch tube
scan
signal
module
pull
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/088262
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English (en)
French (fr)
Inventor
肖军城
赵莽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US14/783,863 priority Critical patent/US9858874B2/en
Publication of WO2017031755A1 publication Critical patent/WO2017031755A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display driving, and more particularly to a scan driving circuit.
  • Gate Driver On Array is a driving circuit for forming a scan driving circuit on an array substrate of an existing thin film transistor liquid crystal display to realize progressive scanning of a scanning line.
  • the existing scan driving circuit includes a pull-down control module, a pull-down module, a downlink module, a reset control module, a bootstrap capacitor, and a reset control module.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of a previous stage, and generate a scan level signal of a low level of the scan line according to the scan signal of the previous stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal
  • a reset control module configured to receive a clock signal of a next stage, and generate a corresponding reset signal of the scan line according to the clock signal of the next stage;
  • a reset module configured to pull up a scan signal of the corresponding scan line according to the reset signal
  • a downlink module configured to generate and send a clock signal of the current stage according to the scan signal of the scan line
  • a first bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • the reset module includes a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eleventh switch tube;
  • the control end of the fourth switch tube inputs the reset signal, the input end of the fourth switch tube is connected to the constant voltage low level source, and the output end of the fourth switch tube and the sixth switch The output of the tube is connected;
  • a control end of the fifth switch tube is connected to an output end of the sixth switch tube, an input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube Connected to the output of the pull-down module;
  • a control end of the sixth switch tube is connected to an output end of the eleventh switch tube, and an input end of the sixth switch tube is connected to the constant voltage high level source;
  • a control end of the seventh switch tube is connected to an output end of the sixth switch tube, an input end of the seventh switch tube is connected to the constant voltage high level source, and an output end of the seventh switch tube Connected to an output end of the scan signal of the scan line;
  • a control end of the eleventh switch tube is connected to the constant voltage low level source, an input end of the eleventh switch tube is connected to the pull-down module, and an output end of the eleventh switch tube is Connecting the control end of the sixth switch tube;
  • the reset module further includes a second bootstrap capacitor, one end of the second bootstrap capacitor is connected to the constant voltage high level source, and the other end of the second bootstrap capacitor and the fourth switch tube Output connection;
  • the scan driving circuit controls the pull-down control module, the pull-down module, the reset module, the reset control module, and the transistor using a P-type metal oxide semiconductor type transistor or an N-type metal oxide semiconductor type transistor Down module.
  • the pull-down control module is further configured to receive a scan signal of a next stage, and generate a scan of a low level of the corresponding scan line according to the scan signal of the next stage.
  • Level signal
  • the reset control module is configured to receive a clock signal of a previous stage, and generate a corresponding reset signal of the scan line according to the clock signal of the upper stage.
  • the pull-down control module includes a first switch tube and a second switch tube;
  • the control end of the first switch tube inputs a first scan signal, and the input end of the first switch tube inputs a scan signal of the upper stage; the output end of the first switch tube is connected to the pull-down module;
  • the control end of the second switch tube inputs a second scan signal, and the input end of the second switch tube inputs the scan signal of the next stage; the output end of the second switch tube is connected to the pull-down module.
  • the reset control module includes an eighth switch tube and a ninth switch tube;
  • the control end of the eighth switch tube inputs the first scan signal, the input end of the eighth switch tube inputs a clock signal of the next stage, and the output end of the eighth switch tube and the fourth Connecting the control end of the switch tube;
  • the control end of the ninth switch tube inputs the second scan signal
  • the input end of the ninth switch tube inputs the clock signal of the upper stage
  • the output end of the ninth switch tube and the fourth The control end of the switch tube is connected.
  • the pull-down module includes a third switch tube, the input end of the third switch tube is connected to the pull-down control module, and the control end of the third switch tube and the pull-down control The module is connected, and an output end of the third switch tube is connected to an output end of the fifth switch tube.
  • the downlink module includes a tenth switch tube, and the control end of the tenth switch tube is respectively connected to the reset module and the pull-down module, and the tenth switch tube The input end is connected to the output end of the seventh switch tube, and the output end of the tenth switch tube outputs the clock signal of the current stage.
  • the downlink module further includes a thirteenth switch tube, and the control end of the thirteenth switch tube is connected to the control end of the tenth switch tube, the tenth An input end of the third switch tube is connected to an output end of the tenth switch tube, and an output end of the thirteenth switch tube outputs a cascade signal of the current stage;
  • the reset module further includes a twelfth switch tube, wherein a control end of the twelfth switch tube inputs a cascade signal of a previous stage, and an input end of the twelfth switch tube and the constant voltage high level source Connecting, the output end of the twelfth switch tube is connected to the control end of the fifth switch tube;
  • the pull-down module includes a third switch tube, an input end of the third switch tube is connected to the pull-down control module, and a control end of the third switch tube inputs a cascade signal of the upper stage, where the The output end of the three switch tube is connected to the output end of the fifth switch tube.
  • the reset module further includes a twelfth switch tube, a control end of the twelfth switch tube is connected to the pull-down control module, and an input of the twelfth switch tube The terminal is connected to the constant voltage high level source, and the output end of the twelfth switch tube is connected to the control end of the fifth switch tube.
  • the embodiment of the present invention further provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of a previous stage, and generate a scan level signal of a low level of the scan line according to the scan signal of the previous stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal
  • a reset control module configured to receive a clock signal of a next stage, and generate a corresponding reset signal of the scan line according to the clock signal of the next stage;
  • a reset module configured to pull up a scan signal of the corresponding scan line according to the reset signal
  • a downlink module configured to generate and send a clock signal of the current stage according to the scan signal of the scan line
  • a first bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • the reset module includes a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eleventh switch tube;
  • the control end of the fourth switch tube inputs the reset signal, the input end of the fourth switch tube is connected to the constant voltage low level source, and the output end of the fourth switch tube and the sixth switch The output of the tube is connected;
  • a control end of the fifth switch tube is connected to an output end of the sixth switch tube, an input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube Connected to the output of the pull-down module;
  • a control end of the sixth switch tube is connected to an output end of the eleventh switch tube, and an input end of the sixth switch tube is connected to the constant voltage high level source;
  • a control end of the seventh switch tube is connected to an output end of the sixth switch tube, an input end of the seventh switch tube is connected to the constant voltage high level source, and an output end of the seventh switch tube Connected to an output end of the scan signal of the scan line;
  • a control end of the eleventh switch tube is connected to the constant voltage low level source, an input end of the eleventh switch tube is connected to the pull-down module, and an output end of the eleventh switch tube is The control end of the sixth switch tube is connected.
  • the pull-down control module is further configured to receive a scan signal of a next stage, and generate a scan of a low level of the corresponding scan line according to the scan signal of the next stage.
  • Level signal
  • the reset control module is configured to receive a clock signal of a previous stage, and generate a corresponding reset signal of the scan line according to the clock signal of the upper stage.
  • the pull-down control module includes a first switch tube and a second switch tube;
  • the control end of the first switch tube inputs a first scan signal, and the input end of the first switch tube inputs a scan signal of the upper stage; the output end of the first switch tube is connected to the pull-down module;
  • the control end of the second switch tube inputs a second scan signal, and the input end of the second switch tube inputs the scan signal of the next stage; the output end of the second switch tube is connected to the pull-down module.
  • the reset control module includes an eighth switch tube and a ninth switch tube;
  • the control end of the eighth switch tube inputs the first scan signal, the input end of the eighth switch tube inputs a clock signal of the next stage, and the output end of the eighth switch tube and the fourth Connecting the control end of the switch tube;
  • the control end of the ninth switch tube inputs the second scan signal
  • the input end of the ninth switch tube inputs the clock signal of the upper stage
  • the output end of the ninth switch tube and the fourth The control end of the switch tube is connected.
  • the pull-down module includes a third switch tube, the input end of the third switch tube is connected to the pull-down control module, and the control end of the third switch tube and the pull-down control The module is connected, and an output end of the third switch tube is connected to an output end of the fifth switch tube.
  • the downlink module includes a tenth switch tube, and the control end of the tenth switch tube is respectively connected to the reset module and the pull-down module, and the tenth switch tube The input end is connected to the output end of the seventh switch tube, and the output end of the tenth switch tube outputs the clock signal of the current stage.
  • the downlink module further includes a thirteenth switch tube, and the control end of the thirteenth switch tube is connected to the control end of the tenth switch tube, the tenth An input end of the third switch tube is connected to an output end of the tenth switch tube, and an output end of the thirteenth switch tube outputs a cascade signal of the current stage;
  • the reset module further includes a twelfth switch tube, wherein a control end of the twelfth switch tube inputs a cascade signal of a previous stage, and an input end of the twelfth switch tube and the constant voltage high level source Connecting, the output end of the twelfth switch tube is connected to the control end of the fifth switch tube;
  • the pull-down module includes a third switch tube, an input end of the third switch tube is connected to the pull-down control module, and a control end of the third switch tube inputs a cascade signal of the upper stage, where the The output end of the three switch tube is connected to the output end of the fifth switch tube.
  • the reset module further includes a twelfth switch tube, a control end of the twelfth switch tube is connected to the pull-down control module, and an input of the twelfth switch tube The terminal is connected to the constant voltage high level source, and the output end of the twelfth switch tube is connected to the control end of the fifth switch tube.
  • the reset module further includes a second bootstrap capacitor, one end of the second bootstrap capacitor is connected to the constant voltage high level source, and the second bootstrap capacitor The other end is connected to the output end of the fourth switch.
  • the scan driving circuit controls the pull-down control module, the pull-down module, the transistor using a P-type metal oxide semiconductor type transistor or an N-type metal oxide semiconductor type transistor a reset module, the reset control module, and the downlink module.
  • the scan driving circuit of the present invention improves the reliability of the scan driving circuit by the setting of the reset module, and the structure of the entire scan driving circuit is simple; the structure of the existing scan driving circuit is solved. Complex and low-reliability technical issues.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 2A is a schematic structural view of a second preferred embodiment of a scan driving circuit of the present invention.
  • 2B is a signal waveform diagram of a first preferred embodiment and a second preferred embodiment of the scan driving circuit of the present invention
  • FIG. 3 is a schematic structural view of a third preferred embodiment of a scan driving circuit of the present invention.
  • FIG. 4 is a schematic structural view of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of a scan driving circuit of the present invention.
  • the scan driving circuit of the preferred embodiment is for driving a cascade of scan lines.
  • the scan driving circuit 10 includes a pull-down control module 11, a pull-down module 12, a reset control module 13, a reset module 14, a downlink module 15, a first bootstrap capacitor C1, a constant-voltage low-level source VGL, and a constant-voltage high-level source. VGH.
  • the pull-down control module 11 is configured to receive the scan signal G_N-1 of the previous stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal G_N-1 of the previous stage; or receive the scan of the next stage.
  • the signal G_N+1 is generated, and a scan level signal of a low level of the corresponding scan line is generated according to the scan signal G_N+1 of the next stage.
  • the pull-down module 12 is configured to pull down the scan signal G_N of the corresponding scan line according to the scan level signal.
  • the reset control module 13 is configured to receive the clock signal CK_N+1 of the next stage, and generate a reset signal of the corresponding scan line according to the clock signal CK_N+1 of the next stage; or receive the clock signal CK_N-1 of the previous stage, And according to the clock signal CK_N-1 of the previous stage, a reset signal of the corresponding scan line is generated.
  • the reset module 14 is configured to pull up the scan signal G_N of the corresponding scan line according to the reset signal.
  • the downlink module 15 is configured to generate and transmit the clock signal CK_N of the current stage according to the scan signal G_N of the scan line.
  • the first bootstrap capacitor C1 is used to generate a low level or a high level of the scan level signal of the scan line.
  • the constant voltage low level source VGL is used to provide a low level signal.
  • the constant voltage high level source VGH is used to provide a high level signal.
  • the pull-down control module 11 of the scan driving circuit 10 of the preferred embodiment includes a first switching transistor PT1 and a second switching transistor PT2.
  • the control terminal of the first switching transistor PT1 inputs a first scanning signal U2D, and the input end of the first switching transistor PT1.
  • the scan signal G_N-1 of the previous stage is input, and the output end of the first switch tube PT1 is connected to the pull-down module 12.
  • the control end of the second switch PT2 inputs the second scan signal D2U, the input end of the second switch PT2 inputs the scan signal G_N+1 of the next stage, and the output end of the second switch PT2 is connected to the pull-down module 12.
  • the pull-down module 12 includes a third switch tube PT3, the input end of the third switch tube PT3 is connected to the pull-down control module 11, the control end of the third switch tube PT3 is connected to the pull-down control module 11, and the output end of the third switch tube PT3 is reset.
  • the output of the fifth switching transistor PT5 of the module 14 is connected.
  • the reset control module 13 includes an eighth switch tube PT8 and a ninth switch tube PT9.
  • the control end of the eighth switch tube PT8 inputs a first scan signal U2D, and the input end of the eighth switch tube PT8 inputs a clock signal CK_N+1 of the next stage.
  • the output end of the eighth switch tube PT8 is connected to the control end of the fourth switch tube PT4 of the reset module 14 to output a reset signal.
  • the control end of the ninth switch tube PT9 inputs the second scan signal D2U, the input end of the ninth switch tube PT9 inputs the clock signal CK_N-1 of the previous stage, the output end of the ninth switch tube PT9 and the fourth switch of the reset module 14
  • the control terminal of the tube PT4 is connected to output a reset signal.
  • the reset module 14 includes a fourth switch tube PT4, a fifth switch tube PT5, a sixth switch tube PT6, a seventh switch tube PT7, an eleventh switch tube PT11, and a second bootstrap capacitor C2.
  • the control end of the fourth switch tube PT4 inputs a reset signal, the input end of the fourth switch tube PT4 is connected to the constant voltage low level source VGL, and the output end of the fourth switch tube PT4 is connected to the output end of the sixth switch tube PT6.
  • the control end of the fifth switch tube PT5 is connected to the output end of the sixth switch tube PT6, the input end of the fifth switch tube PT5 is connected to the constant voltage high level source VGH, and the output end of the fifth switch tube PT5 is connected to the pull-down module 12
  • the output end of the third switch tube PT3 is connected.
  • the control end of the sixth switch tube PT6 is connected to the output end of the third switch tube PT3, and the input end of the sixth switch tube PT6 is connected to the constant voltage high level source VGH.
  • the control end of the seventh switch tube PT7 is connected to the output end of the sixth switch tube PT6, the input end of the seventh switch tube PT7 is connected to the constant voltage high level source VGH, and the output end of the seventh switch tube PT7 is scanned with the scan line. The output of the signal is connected.
  • the control end of the eleventh switch tube PT11 is connected to the constant voltage low level source VHL, the input end of the eleventh switch tube PT7 is connected to the output end of the third switch tube PT3 of the pull-down module 12, and the eleventh switch tube PT11
  • the output terminal outputs a scan signal of the current stage of the scan line through the first bootstrap capacitor C1.
  • One end of the second bootstrap capacitor C2 is connected to the constant voltage high level source VGH, and the other end of the second bootstrap capacitor C2 is connected to the output end of the fourth switch tube PT4.
  • the lower transmission module 15 includes a tenth switch tube PT10, the control end of the tenth switch tube PT10 is connected to the output end of the eleventh switch tube PT11, and the input end of the tenth switch tube PT10 is connected to the output end of the seventh switch tube PT7.
  • the output end of the tenth switch PT10 outputs the clock signal CK_N of the current stage.
  • the clock signal CK_N in the scan driving circuit 10 of the preferred embodiment is output in four groups, that is, the waveforms of CK_N and CK_N+4 are the same.
  • the scan signal G_N-1 of the previous stage outputs a low-level signal.
  • the first switch PT1 of the pull-down control module 11 is in an on state under the control of the low-level scan signal U2D; therefore, the first switch The output end of the tube PT1 inputs the scan signal G_N-1 of the previous stage to the input end of the third switch tube PT3 of the pull-down module 12.
  • the scanning signal D2U and the scanning signal U2D are opposite in phase, and at this time, the second switching tube PT2 is in an off state under the control of the high-level scanning signal U2D.
  • control end of the third switch tube PT3 of the pull-down module 12 also inputs the scan signal G_N-1 of the previous stage of the low level, so the third switch tube PT3 is in the on state, and the output end of the third switch tube PT3 is output.
  • the control end of the sixth switch tube PT6 of the reset module 14 receives the low level signal G_N-1 outputted from the output end of the third switch tube PT3, so the sixth switch tube PT6 is turned on, and the control end of the fifth switch tube PT5 is turned on. And the control end of the seventh switch tube PT7 is connected to the constant voltage high level source VGH through the sixth switch tube PT6, respectively, so the control end of the fifth switch tube PT5 and the seventh switch tube PT7 are disconnected.
  • the eleventh switch tube PT11 of the reset module 14 is turned on under the control of the constant voltage low level source VGL, and the low level signal G_N-1 outputted by the third switch tube PT3 of the pull-down module 12 passes through the eleventh switch tube PT11.
  • the potential of the Q point is lower, so that G_N also outputs a low-level signal, and at the same time, the tenth switch tube PT10 of the module 15 is turned on, and is also turned on under the control of the potential of the Q point.
  • the output terminal of the ten-switch PT10 outputs the low-level clock signal CK_N of the current stage to the drive circuit of the scan line of the previous stage.
  • the eighth switch tube PT8 of the reset control module 13 inputs the clock signal CK_N+1 of the next stage under the control of the first scan signal U2D.
  • the output end of the eighth switch PT8 outputs the clock signal CK_N+1, that is, the reset signal to the control end of the fourth switch PT4.
  • the fourth switch tube PT4 of the reset module 14 is turned on under the control of the reset signal, and the constant voltage low level source VGL is input to the control end of the fifth switch tube PT5 and the control end of the seventh switch tube PT7 through the fourth switch tube PT4.
  • the fifth switch tube PT5 and the seventh switch tube PT7 are turned on, and the high level signal of the constant voltage high level source VGH is input to the Q point through the fifth switch tube PT5, and the Q point potential is pulled high.
  • the high level signal of the constant voltage high level source VGH is input to G_N through the seventh switch tube PT7, and G_N is pulled high, and at the same time, the clock signal CK_N is also turned to the high level because the tenth switch tube PT10 is turned off.
  • the setting of the second bootstrap capacitor C2 in the reset module 14 can better pull up the potential of the control end of the fifth switch tube PT5 and the control end of the seventh switch tube PT7, thereby better ensuring the Q point. Low potential.
  • the reset control module 13 of the preferred embodiment further includes a ninth switch tube PT9, the control end of the ninth switch tube PT9 inputs a second scan signal D2U, and the input end of the ninth switch tube PT9 inputs a clock of the previous stage.
  • the signal CK_N-1, the output end of the fourth switch PT4 outputs a reset signal of the scan line to the sixth switch PT6.
  • the reset control module 13 can receive the clock signal CK_N-1 of the previous stage and generate a reset signal of the corresponding scan line according to the clock signal CK_N-1 of the previous stage.
  • the drive scan circuit 10 of the preferred embodiment can also implement the function of reverse scan through the second switch tube PT2 and the ninth switch tube PT9.
  • the scan driving circuit 10 of the preferred embodiment is a P-type metal oxide semiconductor type transistor controlled pull-down control module 11, a pull-down module 12, a reset control module 13, a reset module 14, and a downstream module 15.
  • the N-type metal oxide semiconductor type transistor can also be used here to control the pull-down control module 11, the pull-down module 12, the reset control module 13, the reset module 14, and the downstream module 15.
  • the scan driving circuit of the preferred embodiment improves the reliability of the scan driving circuit by the arrangement of each module, and the structure of the entire scan driving circuit is simple.
  • FIG. 2A is a schematic structural view of a second preferred embodiment of the scan driving circuit of the present invention
  • FIG. 2B is a signal of the first preferred embodiment and the second preferred embodiment of the scan driving circuit of the present invention.
  • the voltage division effect of the eleventh switching transistor PT11 of the reset module 14 of the scan driving circuit 10 may cause the Q point potential to be insufficiently pulled down, as shown in FIG. 2B.
  • the dotted line is shown. If the potential at the Q point is too high, the scan driving circuit 10 of the preferred embodiment may be disabled.
  • the reset module 24 of the scan driving circuit 20 of the preferred embodiment resets the position of the eleventh switch PT11.
  • the control end of the eleventh switch tube PT11 is connected to the constant voltage low level source VGL
  • the input end of the eleventh switch tube PT11 is connected to the output end of the third switch tube PT3 of the pull-down module 12, and the eleventh switch tube PT11
  • the output end is connected to the control end of the sixth switch tube PT6.
  • the output end of the third switching transistor PT3 directly outputs the scanning signal of the current stage of the scanning line through the first bootstrap capacitor C1.
  • the internal resistance of the eleventh switch tube PT11 does not pull up the potential of the Q point, thereby avoiding the virtual height of the Q point potential, and avoiding the voltage division and the limit of the eleventh switch tube PT11.
  • the flow action causes a defect that the effective charging (pull-down) of the Q point cannot be achieved. Specifically, as shown by the solid line in FIG. 2B, the reliability of the scan driving circuit 20 is improved.
  • the specific operation principle of the scan driving circuit 20 of the preferred embodiment is the same as or similar to that described in the first preferred embodiment of the scan driving circuit 10 described above. Please refer to the related description in the first preferred embodiment of the scan driving circuit 10 described above. .
  • the scan driving circuit of the preferred embodiment further improves the reliability of the scan driving circuit by setting the position of the eleventh switching tube of the reset module.
  • FIG. 3 is a schematic structural diagram of a third preferred embodiment of the scan driving circuit of the present invention.
  • the reset module 34 of the scan driving circuit 30 of the preferred embodiment further includes a twelfth switch tube PT12, and the control end of the twelfth switch tube PT12 is connected to the output of the pull-down control module 11. That is, the output end of the first switch tube PT1 and the output end of the second switch tube PT2 are connected.
  • the input end of the twelfth switch tube PT12 is connected to the constant voltage high level source VGH, and the output end of the twelfth switch tube PT12 is connected to the control end of the fifth switch tube PT5.
  • the scan signal G_N-1 of the twelfth switch tube PT12 is obtained by the pull-down control module 11 in order to ensure the off state of the fifth switch tube PT5 and the seventh switch tube PT7.
  • the control is turned on to ensure that the control terminal of the fifth switching transistor PT5 and the control terminal of the seventh switching transistor PT7 are respectively connected to the constant voltage high level source VGH.
  • the specific operation principle of the scan driving circuit 30 of the preferred embodiment is the same as or similar to that described in the second preferred embodiment of the scan driving circuit 20 described above. Please refer to the related description in the second preferred embodiment of the scan driving circuit 20 described above. .
  • the scan driving circuit of the preferred embodiment further improves the reliability of the scan driving circuit by the arrangement of the twelfth switching tube on the basis of the second preferred embodiment.
  • FIG. 4 is a schematic structural diagram of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • the downlink module 45 of the scan driving circuit 40 of the preferred embodiment further includes a thirteenth switch tube PT13, a control end of the thirteenth switch tube PT13 and a control of the tenth switch tube PT10.
  • the terminal is connected, the input end of the thirteenth switch tube PT13 is connected to the output end of the tenth switch tube PT10, and the output end of the thirteenth switch tube PT13 outputs the cascade signal S_N of the current stage.
  • the reset module 44 further includes a twelfth switch tube PT12.
  • the control end of the twelfth switch tube PT12 inputs the cascaded signal S_N-1 of the previous stage, and the input end of the twelfth switch tube PT12 and the constant voltage high level source VGH Connected, the output end of the twelfth switch tube PT12 is connected to the control end of the fifth switch tube PT5.
  • the pull-down module 42 includes a third switch tube PT3, the input end of the third switch tube PT3 is connected to the output of the pull-down control module 11, and the control end of the third switch tube PT3 inputs the cascade signal S_N-1 of the previous stage, the third switch The output of the tube PT3 is connected to the output of the fifth switch PT5.
  • the scan signal 40 of the preferred embodiment uses the cascaded signal S_N-1 of the previous stage to control the twelfth switch tube PT12 and the third switch.
  • the PT3 is turned on and off, and the downlink module 45 can also generate the cascaded signal S_N of the current stage to upload the cascaded signal S_N to the driving circuit of the scanning line of the previous stage, thereby avoiding the internal resistance of the switching tube.
  • the effects of the turn-on signal and the turn-off signal improve the stability and reliability of the scan drive circuit 40.
  • the specific operation principle of the scan driving circuit 40 of the preferred embodiment is the same as or similar to that described in the third preferred embodiment of the scan driving circuit 30 described above. Please refer to the related description in the third preferred embodiment of the scan driving circuit 30 described above. .
  • the scan driving circuit of the preferred embodiment further improves the reliability of the scan driving circuit by the setting of the cascade signal on the basis of the third preferred embodiment.
  • the scan driving circuit of the invention improves the reliability of the scan driving circuit by the setting of the reset module, and the structure of the whole scan driving circuit is simple; and the technical problem that the existing scan driving circuit has a complicated structure and low reliability is solved.

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Abstract

一种扫描驱动电路（10），用于对级联的扫描线进行驱动操作，其包括下拉控制模块（11）、下拉模块（12）、复位控制模块（13）、复位模块（14）、下传模块（15）、第一自举电容（C1）、恒压低电平源（VGL）以及恒压高电平源（VGH）。扫描驱动电路（10）通过复位模块（14）的设置，提高了扫描驱动电路（10）的可靠性，同时整个扫描驱动电路（10）的结构简单。

Description

一种扫描驱动电路 技术领域
本发明涉及显示驱动领域，特别是涉及一种扫描驱动电路。
 背景技术
Gate Driver On Array，简称GOA，即在现有薄膜晶体管液晶显示器的阵列基板上制作扫描驱动电路，实现对扫描线逐行扫描的驱动方式。现有扫描驱动电路包括下拉控制模块、下拉模块、下传模块、复位控制模块、自举电容以及复位控制模块。
该扫描驱动电路在高温状态下工作时，容易出现延时以及漏电的问题，从而影响该扫描驱动电路的可靠性。
故，有必要提供一种扫描驱动电路，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种结构简单且可靠性高的扫描驱动电路，以解决现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
 技术解决方案
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号，生成相应的所述扫描线的复位信号；
复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号；
第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号；
其中所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第十一开关管；
所述第四开关管的控制端输入所述复位信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第六开关管的输出端连接；
所述第五开关管的控制端与所述第六开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述下拉模块的输出连接；
所述第六开关管的控制端与所述第十一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
所述第七开关管的控制端与所述第六开关管的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述扫描线的扫描信号的输出端连接；
所述第十一开关管的控制端与所述恒压低电平源连接，所述第十一开关管的输入端与所述下拉模块连接，所述第十一开关管的输出端与所述第六开关管的控制端连接；
其中所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接；
所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管或N型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述复位模块、所述复位控制模块以及所述下传模块。
在本发明所述的扫描驱动电路中，所述下拉控制模块还用于接收下一级的扫描信号，并根据所述下一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
所述复位控制模块用于接收上一级的时钟信号，并根据所述上一级的时钟信号，生成相应的所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管和第二开关管；
所述第一开关管的控制端输入第一扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接；
所述第二开关管的控制端输入第二扫描信号，所述第二开关管的输入端输入所述下一级的扫描信号；所述第二开关管的输出端与所述下拉模块连接。
在本发明所述的扫描驱动电路中，所述复位控制模块包括第八开关管和第九开关管；
所述第八开关管的控制端输入所述第一扫描信号，所述第八开关管的输入端输入所述下一级的时钟信号，所述第八开关管的输出端与所述第四开关管的控制端连接；
所述第九开关管的控制端输入所述第二扫描信号，所述第九开关管的输入端输入所述上一级的时钟信号，所述第九开关管的输出端与所述第四开关管的控制端连接。
在本发明所述的扫描驱动电路中，下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端与所述下拉控制模块连接，所述第三开关管的输出端与所述第五开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下传模块包括第十开关管，所述第十开关管的控制端分别与所述复位模块和所述下拉模块连接，所述第十开关管的输入端与所述第七开关管的输出端连接，所述第十开关管的输出端输出所述本级的时钟信号。
在本发明所述的扫描驱动电路中，所述下传模块还包括第十三开关管，所述第十三开关管的控制端与所述第十开关管的控制端连接，所述第十三开关管的输入端与所述第十开关管的输出端连接，所述第十三开关管的输出端输出本级的级联信号；
所述复位模块还包括第十二开关管，所述第十二开关管的控制端输入上一级的级联信号，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接；
所述下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端输入所述上一级的级联信号，所述第三开关管的输出端与所述第五开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述复位模块还包括第十二开关管，所述第十二开关管的控制端与所述下拉控制模块连接，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接。
本发明实施例还提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号，生成相应的所述扫描线的复位信号；
复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号；
第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号；
其中所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第十一开关管；
所述第四开关管的控制端输入所述复位信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第六开关管的输出端连接；
所述第五开关管的控制端与所述第六开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述下拉模块的输出连接；
所述第六开关管的控制端与所述第十一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
所述第七开关管的控制端与所述第六开关管的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述扫描线的扫描信号的输出端连接；
所述第十一开关管的控制端与所述恒压低电平源连接，所述第十一开关管的输入端与所述下拉模块连接，所述第十一开关管的输出端与所述第六开关管的控制端连接。
在本发明所述的扫描驱动电路中，所述下拉控制模块还用于接收下一级的扫描信号，并根据所述下一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
所述复位控制模块用于接收上一级的时钟信号，并根据所述上一级的时钟信号，生成相应的所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管和第二开关管；
所述第一开关管的控制端输入第一扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接；
所述第二开关管的控制端输入第二扫描信号，所述第二开关管的输入端输入所述下一级的扫描信号；所述第二开关管的输出端与所述下拉模块连接。
在本发明所述的扫描驱动电路中，所述复位控制模块包括第八开关管和第九开关管；
所述第八开关管的控制端输入所述第一扫描信号，所述第八开关管的输入端输入所述下一级的时钟信号，所述第八开关管的输出端与所述第四开关管的控制端连接；
所述第九开关管的控制端输入所述第二扫描信号，所述第九开关管的输入端输入所述上一级的时钟信号，所述第九开关管的输出端与所述第四开关管的控制端连接。
在本发明所述的扫描驱动电路中，下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端与所述下拉控制模块连接，所述第三开关管的输出端与所述第五开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下传模块包括第十开关管，所述第十开关管的控制端分别与所述复位模块和所述下拉模块连接，所述第十开关管的输入端与所述第七开关管的输出端连接，所述第十开关管的输出端输出所述本级的时钟信号。
在本发明所述的扫描驱动电路中，所述下传模块还包括第十三开关管，所述第十三开关管的控制端与所述第十开关管的控制端连接，所述第十三开关管的输入端与所述第十开关管的输出端连接，所述第十三开关管的输出端输出本级的级联信号；
所述复位模块还包括第十二开关管，所述第十二开关管的控制端输入上一级的级联信号，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接；
所述下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端输入所述上一级的级联信号，所述第三开关管的输出端与所述第五开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述复位模块还包括第十二开关管，所述第十二开关管的控制端与所述下拉控制模块连接，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接。
在本发明所述的扫描驱动电路中，所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管或N型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述复位模块、所述复位控制模块以及所述下传模块。
 有益效果
相较于现有的扫描驱动电路，本发明的扫描驱动电路通过复位模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单；解决了现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
 附图说明
图1为本发明的扫描驱动电路的第一优选实施例的结构示意图；
图2A为本发明的扫描驱动电路的第二优选实施例的结构示意图；
图2B为本发明的扫描驱动电路的第一优选实施例和第二优选实施例的信号波形图；
图3为本发明的扫描驱动电路的第三优选实施例的结构示意图；
图4为本发明的扫描驱动电路的第四优选实施例的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的扫描驱动电路的第一优选施实施例的结构示意图。本优选实施例的扫描驱动电路用于对级联的扫描线进行驱动操作。该扫描驱动电路10包括下拉控制模块11、下拉模块12、复位控制模块13、复位模块14、下传模块15、第一自举电容C1、恒压低电平源VGL以及恒压高电平源VGH。
下拉控制模块11用于接收上一级的扫描信号G_N-1，并根据上一级的扫描信号G_N-1生成相应的扫描线的低电平的扫描电平信号；或接收下一级的扫描信号G_N+1，并根据下一级的扫描信号G_N+1生成相应的扫描线的低电平的扫描电平信号。下拉模块12用于根据扫描电平信号，拉低相应的扫描线的扫描信号G_N。复位控制模块13用于接收下一级的时钟信号CK_N+1，并根据下一级的时钟信号CK_N+1，生成相应的扫描线的复位信号；或接收上一级的时钟信号CK_N-1，并根据上一级的时钟信号CK_N-1，生成相应的扫描线的复位信号。复位模块14用于根据复位信号，拉升相应的扫描线的扫描信号G_N。下传模块15用于根据扫描线的扫描信号G_N，生成并发送本级的时钟信号CK_N。第一自举电容C1用于生成扫描线的扫描电平信号的低电平或高电平。恒压低电平源VGL用于提供低电平信号。恒压高电平源VGH用于提供高电平信号。
本优选实施例的扫描驱动电路10的下拉控制模块11包括第一开关管PT1和第二开关管PT2，第一开关管PT1的控制端输入第一扫描信号U2D，第一开关管PT1的输入端输入上一级的扫描信号G_N-1，第一开关管PT1的输出端与下拉模块12连接。第二开关管PT2的控制端输入第二扫描信号D2U，第二开关管PT2的输入端输入下一级的扫描信号G_N+1，第二开关管PT2的输出端与下拉模块12连接。
下拉模块12包括第三开关管PT3，第三开关管PT3的输入端与下拉控制模块11连接，第三开关管PT3的控制端与下拉控制模块11连接，第三开关管PT3的输出端与复位模块14的第五开关管PT5的输出连接。
复位控制模块13包括第八开关管PT8以及第九开关管PT9，第八开关管PT8的控制端输入第一扫描信号U2D，第八开关管PT8的输入端输入下一级的时钟信号CK_N+1，第八开关管PT8的输出端与复位模块14的第四开关管PT4的控制端连接，以输出复位信号。第九开关管PT9的控制端输入第二扫描信号D2U，第九开关管PT9的输入端输入上一级的时钟信号CK_N-1，第九开关管PT9的输出端与复位模块14的第四开关管PT4的控制端连接，以输出复位信号。
复位模块14包括第四开关管PT4、第五开关管PT5、第六开关管PT6、第七开关管PT7、第十一开关管PT11以及第二自举电容C2。
第四开关管PT4的控制端输入复位信号，第四开关管PT4的输入端与恒压低电平源VGL连接，第四开关管PT4的输出端与第六开关管PT6的输出端连接。
第五开关管PT5的控制端与第六开关管PT6的输出端连接，第五开关管PT5的输入端与恒压高电平源VGH连接，第五开关管PT5的输出端与下拉模块12的第三开关管PT3的输出端连接。
第六开关管PT6的控制端与第三开关管PT3的输出端连接，第六开关管PT6的输入端与恒压高电平源VGH连接。
第七开关管PT7的控制端与第六开关管PT6的输出端连接，第七开关管PT7的输入端与恒压高电平源VGH连接，第七开关管PT7的输出端与扫描线的扫描信号的输出端连接。
第十一开关管PT11的控制端与恒压低电平源VHL连接，第十一开关管PT7的输入端与下拉模块12的第三开关管PT3的输出端连接，第十一开关管PT11的输出端通过第一自举电容C1输出扫描线的本级的扫描信号。
第二自举电容C2的一端与恒压高电平源VGH连接，第二自举电容C2的另一端与第四开关管PT4的输出端连接。
下传模块15包括第十开关管PT10，第十开关管PT10的控制端与第十一开关管PT11的输出端连接，第十开关管PT10的输入端与第七开关管PT7的输出端连接，第十开关管PT10的输出端输出本级的时钟信号CK_N。
本优选实施例的扫描驱动电路10中的时钟信号CK_N以四组为循环输出，即CK_N和CK_N+4的波形是相同的。首先上一级的扫描信号G_N-1输出低电平信号，这时由于下拉控制模块11的第一开关管PT1在低电平的扫描信号U2D的控制下，处于导通状态；因此第一开关管PT1的输出端向下拉模块12的第三开关管PT3的输入端输入上一级的扫描信号G_N-1。同时扫描信号D2U和扫描信号U2D相位相反，这时第二开关管PT2在高电平的扫描信号U2D的控制下，处于断开状态。
此时下拉模块12的第三开关管PT3的控制端也输入低电平的上一级的扫描信号G_N-1，因此第三开关管PT3处于导通状态，第三开关管PT3的输出端输出低电平信号G_N-1。
同时复位模块14的第六开关管PT6的控制端接收到第三开关管PT3的输出端输出的低电平信号G_N-1，因此第六开关管PT6导通，第五开关管PT5的控制端和第七开关管PT7的控制端分别通过第六开关管PT6与恒压高电平源VGH连接，因此第五开关管PT5的控制端和第七开关管PT7断开。
复位模块14的第十一开关管PT11在恒压低电平源VGL的控制下导通，下拉模块12的第三开关管PT3输出的低电平信号G_N-1通过第十一开关管PT11作用于第一自举电容C1上，使得Q点的电位更低，这样G_N也输出低电平信号，同时下传模块15的第十开关管PT10，在Q点电位的控制下也导通，第十开关管PT10的输出端输出本级的低电平的时钟信号CK_N至上一级的扫描线的驱动电路。
当下一级的时钟信号CK_N+1转为低电平时，复位控制模块13的第八开关管PT8在第一扫描信号U2D的控制下输入下一级的时钟信号CK_N+1。第八开关管PT8的输出端输出该时钟信号CK_N+1，即复位信号至第四开关管PT4的控制端。
复位模块14的第四开关管PT4在复位信号的控制下导通，恒压低电平源VGL通过第四开关管PT4输入到第五开关管PT5的控制端以及第七开关管PT7的控制端，这时第五开关管PT5和第七开关管PT7导通，恒压高电平源VGH的高电平信号通过第五开关管PT5输入到Q点，将Q点电位拉高。同时恒压高电平源VGH的高电平信号通过第七开关管PT7输入到G_N，将G_N拉高，同时由于第十开关管PT10断开，时钟信号CK_N也转为高电平。
这样即完成了本优选实施例的扫描驱动电路10的扫描信号的级联输出过程。
优选的，复位模块14中的第二自举电容C2的设置，可以更好的拉高第五开关管PT5的控制端以及第七开关管PT7的控制端的电位，从而可较好的保证Q点的低电位。
优选的，本优选实施例的复位控制模块13还包括第九开关管PT9，该第九开关管PT9的控制端输入第二扫描信号D2U，第九开关管PT9的输入端输入上一级的时钟信号CK_N-1，第四开关管PT4的输出端输出扫描线的复位信号至第六开关管PT6。这样复位控制模块13可接收上一级的时钟信号CK_N-1，并根据上一级的时钟信号CK_N-1，生成相应的扫描线的复位信号。
这样本优选实施例的驱动扫描电路10还可通过第二开关管PT2和第九开关管PT9实现反向扫描的功能。
优选的，本优选实施例的扫描驱动电路10的是P型金属氧化物半导体类型的晶体管控制下拉控制模块11、下拉模块12、复位控制模块13、复位模块14以及下传模块15。当然这里还可使用N型金属氧化物半导体类型的晶体管控制下拉控制模块11、下拉模块12、复位控制模块13、复位模块14以及下传模块15。
本优选实施例的扫描驱动电路通过各模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单。
请参照图2A和图2B，图2A为本发明的扫描驱动电路的第二优选实施例的结构示意图，图2B为本发明的扫描驱动电路的第一优选实施例和第二优选实施例的信号波形图。在扫描驱动电路10的第一优选实施例中，扫描驱动电路10的复位模块14的第十一开关管PT11的分压作用可能会使得Q点电位不能实现充分的拉低，具体如图2B中的虚线所示。如Q点的电位过高时，可能会导致本优选实施例的扫描驱动电路10失效。
故在第一优选实施例的基础上，本优选实施例的扫描驱动电路20的复位模块24对第十一开关管PT11的位置进行了重新设置。第十一开关管PT11的控制端与恒压低电平源VGL连接，第十一开关管PT11的输入端与下拉模块12的第三开关管PT3的输出端连接，第十一开关管PT11的输出端与第六开关管PT6的控制端连接。
这样第三开关管PT3的输出端直接通过第一自举电容C1输出扫描线的本级的扫描信号。这样当Q点拉低时，第十一开关管PT11中的内阻不会拉高Q点的电位，从而避免了Q点电位的虚高，避免了第十一开关管PT11的分压和限流作用，导致不能实现Q点的有效充电（拉低）的缺陷。具体如图2B中的实线所示，从而提高了该扫描驱动电路20的可靠性。
本优选实施例的扫描驱动电路20的具体工作原理与上述的扫描驱动电路10的第一优选实施例中的描述相同或相似，请参见上述扫描驱动电路10的第一优选实施例中的相关描述。
本优选实施例的扫描驱动电路通过复位模块的第十一开关管的位置设置，进一步提高了扫描驱动电路的可靠性。
请参照图3，图3为本发明的扫描驱动电路的第三优选实施例的结构示意图。在第二优选实施例的基础上，本优选实施例的扫描驱动电路30的复位模块34还包括第十二开关管PT12，第十二开关管PT12的控制端与下拉控制模块11的输出连接，即第一开关管PT1的输出端以及第二开关管PT2的输出端连接。第十二开关管PT12的输入端与恒压高电平源VGH连接，第十二开关管PT12的输出端与第五开关管PT5的控制端连接。
本优选实施例的扫描驱动电路30为了保证第五开关管PT5和第七开关管PT7的断开状态，第十二开关管PT12在上一级的扫描信号G_N-1（由下拉控制模块11获取）的控制下导通，以保证第五开关管PT5的控制端和第七开关管PT7的控制端分别与恒压高电平源VGH连接。
本优选实施例的扫描驱动电路30的具体工作原理与上述的扫描驱动电路20的第二优选实施例中的描述相同或相似，请参见上述扫描驱动电路20的第二优选实施例中的相关描述。
本优选实施例的扫描驱动电路在第二优选实施例的基础上，通过第十二开关管的设置，进一步提高了扫描驱动电路的可靠性。
请参照图4，图4为本发明的扫描驱动电路的第四优选实施例的结构示意图。在第二优选实施例的基础上，本优选实施例的扫描驱动电路40的下传模块45还包括第十三开关管PT13，第十三开关管PT13的控制端与第十开关管PT10的控制端连接，第十三开关管PT13的输入端与第十开关管PT10的输出端连接，第十三开关管PT13的输出端输出本级的级联信号S_N。
复位模块44还包括第十二开关管PT12，第十二开关管PT12的控制端输入上一级的级联信号S_N-1，第十二开关管PT12的输入端与恒压高电平源VGH连接，第十二开关管PT12的输出端与第五开关管PT5的控制端连接。
下拉模块42包括第三开关管PT3，第三开关管PT3的输入端与下拉控制模块11的输出连接，第三开关管PT3的控制端输入上一级的级联信号S_N-1，第三开关管PT3的输出端与第五开关管PT5的输出端连接。
本优选实施例的扫描驱动电路40为了保证第十二开关管PT12以及第三开关管PT3的及时开启，使用上一级的级联信号S_N-1来控制第十二开关管PT12以及第三开关管PT3的开启以及关闭，同时下传模块45还可生成本级的级联信号S_N，以将该级联信号S_N上传至上一级的扫描线的驱动电路，因此避免的开关管的内阻对开启信号以及关闭信号的影响，提高了扫描驱动电路40的稳定性以及可靠性。
本优选实施例的扫描驱动电路40的具体工作原理与上述的扫描驱动电路30的第三优选实施例中的描述相同或相似，请参见上述扫描驱动电路30的第三优选实施例中的相关描述。
本优选实施例的扫描驱动电路在第三优选实施例的基础上，通过级联信号的设置，进一步提高了扫描驱动电路的可靠性。
本发明的扫描驱动电路通过复位模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单；解决了现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
    复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号，生成相应的所述扫描线的复位信号；
    复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
    下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号；
    第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号；
    其中所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第十一开关管；
    所述第四开关管的控制端输入所述复位信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第六开关管的输出端连接；
    所述第五开关管的控制端与所述第六开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述下拉模块的输出连接；
    所述第六开关管的控制端与所述第十一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
    所述第七开关管的控制端与所述第六开关管的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述扫描线的扫描信号的输出端连接；
    所述第十一开关管的控制端与所述恒压低电平源连接，所述第十一开关管的输入端与所述下拉模块连接，所述第十一开关管的输出端与所述第六开关管的控制端连接；
    其中所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接；
    所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管或N型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述复位模块、所述复位控制模块以及所述下传模块。
  2. 根据权利要求1所述的扫描驱动电路，其中所述下拉控制模块还用于接收下一级的扫描信号，并根据所述下一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    所述复位控制模块用于接收上一级的时钟信号，并根据所述上一级的时钟信号，生成相应的所述扫描线的复位信号。
  3. 根据权利要求2所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管和第二开关管；
    所述第一开关管的控制端输入第一扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接；
    所述第二开关管的控制端输入第二扫描信号，所述第二开关管的输入端输入所述下一级的扫描信号；所述第二开关管的输出端与所述下拉模块连接。
  4. 根据权利要求2所述的扫描驱动电路，其中所述复位控制模块包括第八开关管和第九开关管；
    所述第八开关管的控制端输入所述第一扫描信号，所述第八开关管的输入端输入所述下一级的时钟信号，所述第八开关管的输出端与所述第四开关管的控制端连接；
    所述第九开关管的控制端输入所述第二扫描信号，所述第九开关管的输入端输入所述上一级的时钟信号，所述第九开关管的输出端与所述第四开关管的控制端连接。
  5. 根据权利要求1所述的扫描驱动电路，其中下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端与所述下拉控制模块连接，所述第三开关管的输出端与所述第五开关管的输出端连接。
  6. 根据权利要求1所述的扫描驱动电路，其中所述下传模块包括第十开关管，所述第十开关管的控制端分别与所述复位模块和所述下拉模块连接，所述第十开关管的输入端与所述第七开关管的输出端连接，所述第十开关管的输出端输出所述本级的时钟信号。
  7. 根据权利要求6所述的扫描驱动电路，其中所述下传模块还包括第十三开关管，所述第十三开关管的控制端与所述第十开关管的控制端连接，所述第十三开关管的输入端与所述第十开关管的输出端连接，所述第十三开关管的输出端输出本级的级联信号；
    所述复位模块还包括第十二开关管，所述第十二开关管的控制端输入上一级的级联信号，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接；
    所述下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端输入所述上一级的级联信号，所述第三开关管的输出端与所述第五开关管的输出端连接。
  8. 根据权利要求1所述的扫描驱动电路，其中所述复位模块还包括第十二开关管，所述第十二开关管的控制端与所述下拉控制模块连接，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接。
  9. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
    复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号，生成相应的所述扫描线的复位信号；
    复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
    下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号；
    第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号；
    其中所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第十一开关管；
    所述第四开关管的控制端输入所述复位信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第六开关管的输出端连接；
    所述第五开关管的控制端与所述第六开关管的输出端连接，所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述下拉模块的输出连接；
    所述第六开关管的控制端与所述第十一开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
    所述第七开关管的控制端与所述第六开关管的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述扫描线的扫描信号的输出端连接；
    所述第十一开关管的控制端与所述恒压低电平源连接，所述第十一开关管的输入端与所述下拉模块连接，所述第十一开关管的输出端与所述第六开关管的控制端连接。
  10. 根据权利要求9所述的扫描驱动电路，其中所述下拉控制模块还用于接收下一级的扫描信号，并根据所述下一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    所述复位控制模块用于接收上一级的时钟信号，并根据所述上一级的时钟信号，生成相应的所述扫描线的复位信号。
  11. 根据权利要求10所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管和第二开关管；
    所述第一开关管的控制端输入第一扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接；
    所述第二开关管的控制端输入第二扫描信号，所述第二开关管的输入端输入所述下一级的扫描信号；所述第二开关管的输出端与所述下拉模块连接。
  12. 根据权利要求10所述的扫描驱动电路，其中所述复位控制模块包括第八开关管和第九开关管；
    所述第八开关管的控制端输入所述第一扫描信号，所述第八开关管的输入端输入所述下一级的时钟信号，所述第八开关管的输出端与所述第四开关管的控制端连接；
    所述第九开关管的控制端输入所述第二扫描信号，所述第九开关管的输入端输入所述上一级的时钟信号，所述第九开关管的输出端与所述第四开关管的控制端连接。
  13. 根据权利要求9所述的扫描驱动电路，其中下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端与所述下拉控制模块连接，所述第三开关管的输出端与所述第五开关管的输出端连接。
  14. 根据权利要求9所述的扫描驱动电路，其中所述下传模块包括第十开关管，所述第十开关管的控制端分别与所述复位模块和所述下拉模块连接，所述第十开关管的输入端与所述第七开关管的输出端连接，所述第十开关管的输出端输出所述本级的时钟信号。
  15. 根据权利要求14所述的扫描驱动电路，其中所述下传模块还包括第十三开关管，所述第十三开关管的控制端与所述第十开关管的控制端连接，所述第十三开关管的输入端与所述第十开关管的输出端连接，所述第十三开关管的输出端输出本级的级联信号；
    所述复位模块还包括第十二开关管，所述第十二开关管的控制端输入上一级的级联信号，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接；
    所述下拉模块包括第三开关管，所述第三开关管的输入端与所述下拉控制模块连接，所述第三开关管的控制端输入所述上一级的级联信号，所述第三开关管的输出端与所述第五开关管的输出端连接。
  16. 根据权利要求9所述的扫描驱动电路，其中所述复位模块还包括第十二开关管，所述第十二开关管的控制端与所述下拉控制模块连接，所述第十二开关管的输入端与所述恒压高电平源连接，所述第十二开关管的输出端与所述第五开关管的控制端连接。
  17. 根据权利要求9所述的扫描驱动电路，其中所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接。
  18. 根据权利要求9所述的扫描驱动电路，其中所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管或N型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述复位模块、所述复位控制模块以及所述下传模块。
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