WO2017028461A1 - 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置 - Google Patents

薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置 Download PDF

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Publication number
WO2017028461A1
WO2017028461A1 PCT/CN2015/100170 CN2015100170W WO2017028461A1 WO 2017028461 A1 WO2017028461 A1 WO 2017028461A1 CN 2015100170 W CN2015100170 W CN 2015100170W WO 2017028461 A1 WO2017028461 A1 WO 2017028461A1
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Prior art keywords
photoresist
pattern
thin film
film transistor
region
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English (en)
French (fr)
Inventor
叶路路
刘华锋
吕景萍
杨磊
杨盟
张凯
王超
孙超超
赵生伟
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/521,471 priority Critical patent/US10120256B2/en
Publication of WO2017028461A1 publication Critical patent/WO2017028461A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • At least one embodiment of the present invention relates to a method of fabricating a thin film transistor and an array substrate, an array substrate, and a display device.
  • TFT Thin Film Transistor
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • the TFT can be mainly classified into an amorphous silicon TFT, a polycrystalline silicon TFT, and an oxide TFT in accordance with the composition of the TFT semiconductor film layer.
  • polysilicon TFT-LCD For LCD and OLED, the mobility of polysilicon TFT can reach 50-200cm 2 /Vs, so polysilicon TFT-LCD has the advantages of higher resolution, faster reaction speed and higher aperture ratio.
  • the polysilicon TFT is a technology platform for developing an Active Matrix/Organic Light Emitting Diode (AMOLED).
  • AMOLED Active Matrix/Organic Light Emitting Diode
  • the polysilicon TFT can be used as a driving backplane of the AMOLED panel to reduce current consumption.
  • the lattice arrangement of the polysilicon TFTs is neat, the impedance of the electrons inside is small, resulting in a serious leakage current problem in the off state, affecting the normal use of the polysilicon TFT.
  • a method of lightly doping between the source and the drain of the TFT is generally employed.
  • the off-state leakage current of the pixel switch can be reduced.
  • the phenomenon of deterioration of the hot electrons in the peripheral circuit can be improved, and the reliability can be improved.
  • this will increase the preparation process of the TFT, increase the production time, and reduce the yield of the product.
  • the critical dimensions of the lightly doped regions of the source and drain are more difficult to control, the uniformity of the product is lowered.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor and an array substrate, an array substrate, and a display device.
  • the preparation method of the thin film transistor can accurately and efficiently control the source light doping
  • the critical dimensions of the light-doped region of the region and the drain ensure the production efficiency and ensure product uniformity and solve the problem of leakage current.
  • the more conventional process reduces the number of process steps, and it is easier to control the undesirable increase due to the increase of process steps and production time, thereby shortening the production time, reducing the production cost, and improving the product quality.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, including:
  • first photoresist pattern Forming a first photoresist pattern on the pattern of the semiconductor layer, the first photoresist pattern comprising a first thickness photoresist and a second thickness photoresist, wherein the first thickness photoresist corresponds to a region of the semiconductor layer in which a channel region is to be formed, wherein the second thickness photoresist corresponds to a region of the semiconductor layer in which a source lightly doped region and a drain lightly doped region are to be formed; a thickness of the photoresist is greater than a thickness of the second thickness photoresist;
  • the second photoresist pattern is removed.
  • the source lightly doped region and the source heavily doped region constitute a source of a thin film transistor
  • the drain lightly doped region and The drain heavily doped region constitutes a drain of a thin film transistor with a space between the source and the drain to define the channel region.
  • the second thickness photoresist is located on both sides of the first thickness photoresist.
  • an interlayer dielectric layer is further formed on a pattern of the semiconductor layer, wherein the first light is formed on the interlayer dielectric layer Engraved pattern.
  • forming the first photoresist pattern includes:
  • Forming a photoresist film exposing and developing the photoresist film using a multi-tone mask.
  • Forming a first photoresist pattern the first photoresist pattern including a photoresist completely reserved region and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to a pattern of the semiconductor layer A region where the channel region is formed, the photoresist semi-retained region corresponding to a region of the pattern of the semiconductor layer in which a source lightly doped region and a drain lightly doped region are to be formed.
  • the multi-tone mask includes any one of a halftone mask and a gray tone mask.
  • the method further includes the step of forming a pattern of a gate, wherein a pattern of the gate is formed before forming a pattern of the semiconductor layer.
  • the method further includes the step of forming a buffer layer, wherein the buffer layer is located between a pattern of the gate and a pattern of the semiconductor layer.
  • the material of the semiconductor layer comprises polysilicon.
  • n-type doping is performed in the heavily doped ion implantation process and the lightly doped ion implantation process.
  • the dopant ion is a phosphorus ion.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, including the method of fabricating the thin film transistor of any of the above.
  • At least one embodiment of the present invention also provides an array substrate fabricated by any of the above methods.
  • At least one embodiment of the present invention also provides a display device including any of the above array substrates.
  • the display device includes a liquid crystal display device or an organic electroluminescent diode display device.
  • FIG. 1a-1h illustrate a method of fabricating a thin film transistor in a substrate according to an embodiment of the invention.
  • FIGS. 2a-2f are schematic diagrams showing a process flow for forming a pattern of a source-drain heavily doped region, a source-drain light-doped region, and a channel region in a pattern of a semiconductor layer in a method of fabricating a thin film transistor according to an embodiment of the present invention
  • 3a-3I are schematic diagrams showing a process flow for forming a pattern of a gate of a p-type TFT and an n-type TFT, a buffer layer, a pattern of a semiconductor layer, and an interlayer dielectric layer on a substrate according to an embodiment of the present invention
  • 4a-4d are schematic diagrams showing a process flow for forming a pattern of source and drain and a channel region in a pattern of a semiconductor layer of a p-type TFT according to an embodiment of the present invention
  • 5a-5f are schematic diagrams showing a process flow for forming patterns of source-drain heavily doped regions, source-drain light-doped regions, and channel regions in a pattern of a semiconductor layer of an n-type TFT according to an embodiment of the present invention
  • 6a is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention.
  • 6b is a schematic cross-sectional view of another array substrate according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of an array substrate according to another embodiment of the present invention.
  • 101-substrate substrate 1020-gate metal film; 1021-resist pattern; 102-gate; 122-gate; 103-buffer layer; 1040-semiconductor film; 1041-resist pattern; Crystalline silicon film; amorphous silicon film of 1043-p type TFT; amorphous silicon film of 1243-n type TFT; semiconductor layer of 104-p type TFT; semiconductor layer of 124-n type TFT; 105-resist pattern Source of 106-p type TFT; 126-source heavily doped region; drain of 107-p type TFT; 127-drain heavily doped region; channel region of 108-p type TFT; 128-n Channel region of the TFT; 111-first photoresist pattern; 112-second photoresist pattern; 129-source lightly doped region; 120-drain lightly doped region; source of 1296-n TFT Pole; 1207-n type TFT drain; 131-interlayer dielectric layer; 132-flat layer;
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, including:
  • the first photoresist pattern comprising a first thickness photoresist and a second thickness photoresist, wherein the first thickness photoresist corresponds to the pattern of the semiconductor layer to form a trench a region of the gate region (the channel region may correspond to an active layer of the TFT), wherein the second thickness photoresist corresponds to a region of the semiconductor layer in which the source lightly doped region and the drain lightly doped region are to be formed; the first thickness The thickness of the photoresist is greater than the thickness of the second thickness photoresist;
  • the channel region can correspond to the active layer of the TFT
  • the source lightly doped region can correspond to the active layer of the TFT
  • the drain a pattern of lightly doped regions
  • the second photoresist pattern is removed.
  • the source-drain lightly doped region is a target region for providing a buffer for electron motion, and is a key factor for suppressing leakage of the N-type thin film transistor in the pixel region.
  • a thin film transistor manufacturing method provided by an embodiment of the present invention uses a first photoresist pattern including two different thickness photoresists as a blocking mask of a heavily doped process, and forms a second light by a photoresist ashing process. Engraved pattern as a resistance to light doping Block mask.
  • the critical dimension (CD) of each region of the thin film transistor (for example, source-drain lightly doped region and/or source-drain heavily doped region) can be controlled simply, accurately, and efficiently to improve product uniformity; Process steps can be simplified and costs reduced.
  • FIG. 1a-1h and FIG. 2a-2f are schematic diagrams showing the process flow of a method for fabricating a thin film transistor according to an embodiment of the present invention.
  • a base substrate 101 is provided.
  • the base substrate 101 may be a glass substrate, a quartz substrate or other substrate.
  • a gate metal thin film 1020 is formed on the base substrate 101.
  • the gate metal film 1020 can be formed by a chemical vapor deposition (CVD), a magnetron sputtering (Megnetron Sputtering), or a vacuum evaporation method.
  • the material of the gate metal film 1020 includes one or more selected from the group consisting of aluminum, titanium, tantalum, chromium, molybdenum, molybdenum tungsten, or an alloy of any of the above metals. But it is not limited to this.
  • the gate metal film may be a single layer or a multilayer structure. Accordingly, the gate electrode formed may be a single layer or a multilayer structure.
  • a photoresist pattern 1021 is formed on the gate metal film 1020 at a corresponding position where the gate electrode 122 is to be formed.
  • the gate metal film 1020 is etched using the photoresist pattern 1021 as a mask to form a pattern of the gate electrode 122, and the photoresist pattern 1021 is peeled off.
  • a buffer layer 103 is formed on the base substrate 101 and the gate electrode 122.
  • the buffer layer 103 may be formed by chemical vapor deposition (CVD), but is not limited thereto.
  • the material of the buffer layer 103 includes one or more selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy), but is not limited thereto.
  • the buffer layer 103 can serve as a shield on the substrate substrate 101, avoid various adverse effects caused by the substrate 101, and can also serve as a gate of the gate 122.
  • the insulating layer thus, the preparation of the gate insulating layer can be reduced, the preparation time can be shortened, the product cost can be reduced, and the product quality can be improved.
  • a semiconductor thin film 1040 is formed on a base substrate, for example, the material of the semiconductor thin film is polycrystalline silicon (p-Si).
  • the formation process of the semiconductor layer film may include the step of forming an amorphous silicon (a-Si) film on the buffer layer 103.
  • a-Si amorphous silicon
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the amorphous silicon (a-Si) film is subjected to a laser annealing process to convert amorphous silicon (a-Si) into polycrystalline silicon (p-Si).
  • the laser annealing process may employ an Excimer Laser Annealing (ELA) process.
  • ELA Excimer Laser Annealing
  • a photoresist pattern 1041 is formed at a corresponding position on the semiconductor film 1040 where the semiconductor layer 124 is to be formed.
  • the semiconductor film 1040 is etched using the photoresist pattern 1041 as a mask to obtain a pattern of the island-shaped semiconductor layer 124, and the photoresist pattern 1041 is peeled off.
  • the pattern of the semiconductor layer 124 is polysilicon.
  • a pattern of the semiconductor layer 124 is subjected to a threshold voltage (Vth) adjustment using a Doping process.
  • the threshold voltage adjustment doping process may be a doping implantation process of boron ions or phosphorus ions on the semiconductor layer 124.
  • a first photoresist pattern 111 is formed on the pattern of the semiconductor layer 124.
  • the first photoresist pattern 111 includes a first thickness photoresist 1111 and a second thickness photoresist 1112, a first thickness.
  • the photoresist 1111 corresponds to a region of the pattern of the semiconductor layer 124 in which the channel region 128 (not shown in the drawing, see FIG. 2d) is to be formed
  • the second thickness photoresist 1112 corresponds to the source of the semiconductor layer 124 in which the source is to be formed.
  • the lightly doped region 129 (not shown in the figure, see Fig. 2d) and the region of the drain lightly doped region 120 (not shown in the figure, see Fig. 2d).
  • the thickness of the first thickness photoresist 1111 is greater than the thickness of the second thickness photoresist 1112.
  • the second thickness of photoresist is on either side of the first thickness of photoresist.
  • the step of forming the first photoresist pattern 111 includes: forming a photoresist film on the pattern of the semiconductor layer 124, and exposing and developing the photoresist film by using a multi-tone mask to form a first photoresist pattern. 111.
  • the first photoresist pattern 111 includes a photoresist completely reserved region and a photoresist semi-reserved region, and the photoresist completely reserved region corresponds to a region of the semiconductor layer 124 where the channel region 128 is to be formed, and the photoresist is semi-reserved.
  • the region corresponds to a region of the semiconductor layer 124 where the source lightly doped region 129 and the drain lightly doped region 120 are to be formed.
  • a region other than the first photoresist pattern 111 on the pattern of the semiconductor layer 124 corresponds to a pattern of the source heavily doped region 126 to be formed and a pattern of the drain heavily doped region 127.
  • the drain heavily doped region can be used as an ohmic contact.
  • the multi-tone mask includes any one of a halftone mask and a gray tone mask.
  • the semiconductor layer 124 is formed by using the first photoresist pattern 111 as a blocking mask.
  • the pattern is subjected to an n-type heavily doped ion implantation process to form a pattern of source heavily doped regions 126 and drain heavily doped regions 127 on both sides.
  • the implanted ions may be phosphorus ions, but are not limited thereto.
  • the first photoresist pattern 111 is ashed by a photoresist ashing process to remove the second thickness photoresist 1112 and thin the first thickness photoresist 1111.
  • a second photoresist pattern 112 is obtained.
  • the second photoresist pattern 112 includes a region of the pattern corresponding to the semiconductor layer 124 in which the channel region 128 is to be formed. It should be noted that after the n-type heavily doped ion implantation process, the surface of the first photoresist pattern 111 is carbonized. In the above ashing process, the carbonized photoresist needs to be removed to avoid the subsequent stripping process. Carbonized photoresist is not easily peeled off.
  • the pattern of the semiconductor layer 124 is subjected to an n-type lightly doped ion implantation process using the second photoresist pattern 112 as a blocking mask to form a pattern of the source lightly doped region 129 and lightly doped with the drain.
  • the implanted ions may be phosphorus ions, but are not limited thereto.
  • the second photoresist pattern which is a blocking mask for forming the source-drain lightly doped region, is ashed by the first photoresist pattern 111, and does not require an additional process of forming a barrier layer, for example, saving
  • the steps of film formation, exposure, development, and the like of the barrier layer are formed, or steps of forming, exposing, developing, etching, etc. forming the barrier layer can be saved, thereby simplifying the process steps, shortening the production time, and reducing the cost.
  • the first photoresist pattern 111 is directly used as the blocking mask, the accuracy and uniformity of the critical dimensions of the regions to be doped, that is, the source heavily doped region 126 and the drain heavily doped region 127 are required. Better, which can improve the quality of the product.
  • the surface of the second photoresist pattern 112 subjected to the n-type lightly doped ion implantation process is carbonized, and the carbonized photoresist is removed by a photoresist ashing process.
  • the second photoresist pattern 112 is carbonized on the surface after the n-type lightly doped ion implantation process, it is not easy to be directly stripped, so it is necessary to remove the carbonized photoresist by a photoresist ashing process. . For example, after the carbonized photoresist is removed, the photoresist can be stripped.
  • the second photoresist pattern 112 is removed.
  • the second photoresist pattern 112 is stripped using a photoresist stripping process.
  • the source lightly doped region 129 and the source heavily doped region 126 constitute the source 1296 of the thin film transistor
  • the drain lightly doped region 120 and the drain heavily doped region 127 constitute a thin film transistor.
  • Drain 1207 has a spacing between source 1296 and drain 1207 to define channel region 128.
  • both sides of the channel region 128 are source lightly doped regions 129 and light drains, respectively.
  • the doped region 120, the source lightly doped region 129 and the drain lightly doped region 120 are respectively a source heavily doped region 126 and a drain heavily doped region 127.
  • a first photoresist pattern including two different thickness photoresists is formed as a blocking mask of a heavily doped process, and the first photoresist pattern 111 is grayed out.
  • the second photoresist pattern 112 is directly used as a blocking mask for the n-type lightly doped ion implantation process, which eliminates the need to form an additional barrier layer, simplifies the process steps, shortens production time, and reduces cost.
  • the source heavily doped region 126 and the drain heavily doped region 127 are formed in the n-type heavily doped ion implantation process and the n-type lightly doped ion implantation process.
  • the accuracy and uniformity of the critical dimensions of the source lightly doped region 129 and the drain lightly doped region 127 are better than the usual techniques, thereby improving the quality of the product.
  • This embodiment provides a method of fabricating a thin film transistor.
  • 3a-3i, 4a-4d, and 5a-5f are schematic diagrams showing the process flow of a method for fabricating a thin film transistor according to an embodiment.
  • a base substrate 101 is provided.
  • the base substrate 101 may be a glass substrate, a quartz substrate, or another substrate.
  • a gate metal thin film 1020 is formed on the base substrate 101.
  • the gate metal thin film 1020 may be formed by a vapor deposition method, a magnetron sputtering method, or a vacuum evaporation method, but is not limited thereto.
  • the material of the gate metal film 1020 includes one or more selected from the group consisting of aluminum, titanium, tantalum, chromium, molybdenum, tungsten molybdenum, or an alloy of any of the foregoing metals, but is not limited thereto. this.
  • a photoresist pattern 1021 is formed at a corresponding position on the gate metal film 1020 where the gate 102 of the p-type thin film transistor and the gate 122 of the n-type thin film transistor are to be formed.
  • the gate metal film 1020 is etched by using the photoresist pattern 1021 as a mask to form a pattern of the gate 102 of the p-type thin film transistor and the gate 122 of the n-type thin film transistor, and the pattern is peeled off. Photoresist pattern 1021.
  • a buffer layer 103 is formed on the base substrate 101, the gate electrode 102, and the gate electrode 122.
  • the buffer layer 103 may be formed by chemical vapor deposition (CVD), but is not limited thereto.
  • the material of the buffer layer 103 includes one or more selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy), but is not limited thereto.
  • the buffer layer 103 can serve as a shield on the substrate substrate 101 to avoid various adverse effects caused by the substrate 101, and can also serve as the gate 102.
  • a gate insulating layer of the gate 122 a gate insulating layer of the gate 122.
  • an amorphous silicon (a-Si) film 1042 is formed on a base substrate.
  • the amorphous silicon (a-Si) film may be formed by plasma enhanced chemical vapor deposition (PECVD), but is not limited thereto.
  • a semiconductor layer photoresist pattern 1041 is formed at a corresponding position of the semiconductor layer 104 of the p-type thin film transistor and the semiconductor layer 124 of the n-type thin film transistor on the amorphous silicon (a-Si) thin film 1042.
  • the amorphous silicon (a-Si) film 1042 is etched by using the semiconductor layer photoresist pattern 1041 as a mask to remove an amorphous silicon (a-Si) film not covered by the photoresist.
  • a pattern of island-shaped amorphous silicon (a-Si) layers 1043, 1243 is obtained, and the semiconductor photoresist pattern 1041 is peeled off.
  • an interlayer dielectric layer (ILD) 131 is formed on the pattern of the amorphous silicon (a-Si) layers 1043 and 1243 and the buffer layer 103.
  • an amorphous silicon (a-Si) pattern is subjected to an excimer laser annealing process to convert amorphous silicon (a-Si) into polysilicon (p-Si) to form a pattern of a semiconductor layer (polysilicon pattern). ) 104 and 124. Threshold voltage adjustment is then performed on the patterns 104 and 124 of the semiconductor layer.
  • the formed interlayer dielectric layer can protect the amorphous silicon (a-Si) layer during laser annealing.
  • the amorphous silicon (a-Si) may be converted into polycrystalline silicon (p-Si) by performing an excimer laser annealing process on the pattern of the amorphous silicon (a-Si) layer, and then patterning the amorphous silicon (a-Si).
  • the semiconductor layer pattern (polysilicon pattern) is formed, and then the threshold voltage is adjusted, and then the interlayer dielectric layer is formed, which is not limited herein.
  • a threshold voltage (Vth) adjustment can be performed on the pattern of the semiconductor layers 104, 124 using a Doping process.
  • the threshold voltage-adjusting Doping process may be a doping implantation process of boron ions or phosphorus ions on the patterns of the semiconductor layers 104, 124.
  • a photoresist pattern 105 for defining a source and a drain of a p-type thin film transistor to be formed is formed on the interlayer dielectric layer 131, and the photoresist pattern 105 is formed on a p-type to be formed.
  • a portion on the pattern of the semiconductor layer 104 of the thin film transistor that covers only a portion of the pattern of the semiconductor layer 104 in which the channel region 108 is to be formed (not shown in the drawing, see FIG. 4b); and is formed in the n to be formed
  • the portion of the photoresist pattern 105 that covers the pattern of the semiconductor layer 124 is used.
  • the protective semiconductor layer 124 is not affected by the subsequent p-type dopant ion implantation process.
  • a p-type dopant ion implantation process is performed using the photoresist pattern 105 as a blocking mask, and a source 106, a drain 107, and a source 106 and a drain 107 are formed in the semiconductor layer 104.
  • Channel region 108 For example, there is a spacing between source 106 and drain 107 to define channel region 108.
  • the implanted ions can be boron ions.
  • the p-type dopant is p-type heavily doped.
  • the photoresist pattern 105 is directly used as a mask, the accuracy and uniformity of the critical dimensions of the regions to be doped, that is, the source 106 and the drain 107 are better than the usual techniques, thereby improving the product. quality. This reduces one-step etching, increases throughput, saves costs, and reduces overall product manufacturing time to avoid undesirable increases over time.
  • the surface of the photoresist pattern 105 subjected to the p-type dopant ion implantation process is carbonized, the carbonized photoresist is removed by a photoresist ashing process, and the photoresist is stripped.
  • the surface of the photoresist pattern 105 is carbonized after the p-type dopant ion implantation process, it is not easy to directly peel off, so it is necessary to remove the carbonized photoresist by a photoresist ashing process.
  • the remaining photoresist pattern 105 is peeled off, and the gate electrode 102, the buffer layer 103, the source electrode 106, the drain electrode 107, and the channel region 108 constitute a p-type thin film transistor.
  • a first photoresist pattern 111 is formed on the interlayer dielectric layer 131, the first photoresist pattern 111 including a portion covering a pattern of the semiconductor layer 124 of the n-type thin film transistor to be formed, which The portion includes a first thickness photoresist 1111 and a second thickness photoresist 1112.
  • the first thickness photoresist 1111 corresponds to a pattern of the channel region 128 to be formed in the pattern of the semiconductor layer 124 (not shown in the drawing, see the figure)
  • the second thickness photoresist 1112 corresponds to a region of the pattern of the semiconductor layer 124 in which the source lightly doped region 129 and the drain lightly doped region 120 are to be formed.
  • the first photoresist pattern 111 further includes a portion covering the source 106, the drain 107, and the channel region 108 of the p-type thin film transistor, the portion completely covering the source 106, the drain 107, and the trench of the p-type thin film transistor.
  • the track region 108 has a width greater than the total width of the source 106, the drain 107, and the channel region 108 (semiconductor layer 104).
  • the step of forming the first photoresist 111 includes: forming a photoresist film on the pattern of the semiconductor layers 104, 124, and exposing and developing the photoresist film by using a multi-tone mask to form a first photoresist pattern 111, the first photoresist pattern 111 includes a photoresist completely reserved region and a photoresist semi-reserved region, and the photoresist completely reserved region corresponds to the p-type thin film transistor source 106, the drain 107, and The region of the channel region 108 and the region of the semiconductor layer 124 in which the channel region 128 is to be formed, the photoresist semi-reserved region corresponding to the pattern of the semiconductor layer 124 to be formed in the source lightly doped region 129 and the lightly doped drain The area of area 120.
  • the second thickness photoresist is located on both sides of the first thickness photore
  • the multi-tone mask includes any one of a halftone mask and a gray tone mask.
  • portions of the first photoresist pattern 111 covering the source 106, the drain 107, and the channel region 108 are used for the source 106, the drain 107, and the channel region 108 without being subjected to subsequent n-type weights. Doping ion implantation process effects.
  • the pattern of the semiconductor layer 124 is subjected to an n-type heavily doped ion implantation process using the first photoresist pattern 111 as a blocking mask to form a source heavily doped region 126 and a drain on both sides.
  • Heavy doped region 127 may be phosphorus ions, but are not limited thereto.
  • the first photoresist pattern 111 is directly used as the blocking mask, the accuracy and uniformity of the critical dimensions of the doped regions, that is, the source doping region 126 and the drain heavily doping region 127 are required. Better than the usual technology, which can improve the quality of the product.
  • the first photoresist pattern 111 is ashed by a photoresist ashing process, the second thickness photoresist 1112 is removed, and the first thickness photoresist 1111 is thinned to obtain a second photoresist.
  • the second photoresist pattern 112 includes a portion covering the source 106, the drain 107, and the channel region 108 of the p-type thin film transistor and a region in the pattern of the corresponding semiconductor layer 124 covering the n-type thin film transistor to be formed into the channel region 128. .
  • the surface of the first photoresist pattern 111 subjected to the n-type heavily doped ion implantation process is carbonized, and in the above ashing process, the carbonized photoresist is also removed.
  • the width of the portion of the first photoresist pattern 111 covering the p-type thin film transistor is larger than the width of the p-type thin film transistor, the second photoresist is formed even after the above ashing process.
  • the pattern 112 can still completely cover the p-type thin film transistor for protection purposes.
  • the pattern of the semiconductor layer 124 is subjected to an n-type lightly doped ion implantation process using the second photoresist pattern 112 as a blocking mask to form a source lightly doped region 129 and a drain lightly doped region. 120 and a pattern of channel regions 128 between the source lightly doped region 129 and the drain lightly doped region 120.
  • the implanted ions may be phosphorus ions, but are not limited thereto.
  • the surface of the second photoresist pattern 112 subjected to the n-type lightly doped ion implantation process is carbonized, and the carbonized photoresist is removed by a photoresist ashing process.
  • the second photoresist pattern 112 is carbonized on the surface after the n-type lightly doped ion implantation process, it is not easy to be directly stripped, so it is necessary to remove the carbonized photoresist by a photoresist ashing process. .
  • the remaining second photoresist pattern 112 is stripped, thereby removing the second photoresist pattern 112.
  • the interlayer dielectric layer is not provided.
  • the first photoresist pattern is directly formed on the pattern of the semiconductor layer.
  • the source lightly doped region 129 and the source heavily doped region 126 constitute the source 1296 of the thin film transistor
  • the drain lightly doped region 120 and the drain heavily doped region 127 constitute a thin film transistor.
  • Drain 1207 has a spacing between source 1296 and drain 1207 to define channel region 128.
  • the channel region 128 is respectively a source lightly doped region 129 and a drain lightly doped region 120, and the source lightly doped region 129 and the drain lightly doped region 120 are respectively The source heavily doped region 126 and the drain heavily doped region 127.
  • a first photoresist pattern including two different thickness photoresists is formed as a blocking mask of a heavily doped process, and the first photoresist pattern 111 is grayed out.
  • the second photoresist pattern 112 is directly used as a blocking mask for the n-type lightly doped ion implantation process, which eliminates the need to form an additional barrier layer, simplifies the process steps, shortens production time, and reduces cost.
  • an n-type thin film transistor and a p-type thin film transistor can be formed, and the preparation of the photoresist pattern can be reduced by at least one time by the ashing process, which simplifies the preparation process.
  • the source 106 and the drain 107 are formed in the p-type doping ion implantation process, the n-type heavily doped ion implantation process, and the n-type lightly doped ion implantation process.
  • the accuracy and uniformity of the critical dimensions of the source heavily doped region 126, the drain heavily doped region 127, the source lightly doped region 129, and the drain lightly doped region 127 are better than the conventional techniques, thereby improving Quality of products.
  • the embodiment provides a method for preparing an array substrate, which comprises the method for preparing a thin film transistor according to the first embodiment.
  • the method of preparing the thin film transistor will not be described here, please refer to the previous description.
  • 6a is a schematic cross-sectional view of an array substrate prepared by the method for preparing an array substrate provided in the embodiment.
  • the method for fabricating the array substrate provided in this embodiment may further include: forming a flat layer 132 on the buffer layer 103 and the n-type thin film transistor.
  • a common electrode 133 is formed on a region of the flat layer 132 corresponding to the display region.
  • An insulating layer 134 is formed on the flat layer 132 and the common electrode 133; a via hole is formed in the insulating layer 134 and the flat layer 132, the via hole penetrating the insulating layer 134 and the flat layer 132 to expose the drain heavily doped of the n-type thin film transistor District 127.
  • a pixel electrode 135 is formed on the insulating layer 134 corresponding to the display region, and the pixel electrode 135 is electrically connected to the drain heavily doped region 127 through the via.
  • the step of forming source/drain contact regions 136 may also be included.
  • the source/drain contact regions 136 may be made of a metal material, but are not limited thereto.
  • the source contact area may be a data line, but is not limited thereto.
  • the drain contact region may be a contact electrode, but is not limited thereto.
  • planar layer 132 can be a single layer structure or a multilayer structure.
  • the material of the flat layer 132 may include one or more selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy), but is not limited thereto.
  • the flat layer 132 may be fabricated by plasma enhanced chemical vapor deposition (PECVD), but is not limited thereto.
  • PECVD plasma enhanced chemical vapor deposition
  • the material of the common electrode 133 and the pixel electrode 135 may be a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the common electrode 133 and the pixel electrode 135 may be fabricated using a magnetron sputtering process, but are not limited thereto.
  • the order of forming the pixel electrode 135 and the common electrode 133 in the method for fabricating the array substrate provided in this embodiment may be reversed, that is, the common electrode is located above the pixel electrode.
  • the upper electrode is, for example, a slit electrode.
  • FIG. 7 is an array substrate prepared by using the method for preparing an array substrate provided by an embodiment of the invention.
  • the method for fabricating the array substrate provided in the example of the embodiment further includes: forming a plurality of via holes on the interlayer dielectric layer 131 , and the plurality of via holes respectively penetrate the interlayer dielectric layer 131 .
  • a via hole is formed in the planarization layer 132 such that the via hole penetrates the planarization layer 132 and exposes the source/drain contact region 136 connected to the drain heavily doped region 127 of the n-type thin film transistor; and is formed in the planarization layer 132
  • the upper pixel electrode 135 is connected via a via to the source/drain contact region 136 connected to the drain heavily doped region 127 of the n-type thin film transistor.
  • the source contact area may be a data line, but is not limited thereto.
  • the drain contact region may be a contact electrode, but is not limited thereto.
  • the step of forming the array substrate provided by the present example may not include the step of forming a drain contact region.
  • planar layer 132 can be a single layer structure or a multilayer structure.
  • the material of the flat layer 132 may include one or more selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy), but is not limited thereto.
  • the flat layer 132 may be fabricated by plasma enhanced chemical vapor deposition (PECVD), but is not limited thereto.
  • PECVD plasma enhanced chemical vapor deposition
  • the material of the pixel electrode 135 may be a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the pixel electrode 135 can be fabricated using a magnetron sputtering process, but is not limited thereto.
  • the method for preparing the array substrate can be used for preparing an array substrate of a liquid crystal display device, and can also be used for preparing an array substrate of an organic electroluminescent diode display device.
  • the pixel electrode 135 can serve as an anode of an organic electroluminescent diode display device.
  • the gate 122 is directly formed on the base substrate 101 by the bottom gate design, thereby reducing the preparation of the gate insulating layer, thereby shortening the production time and reducing the production time.
  • Product Cost In addition, in the method for fabricating the array substrate provided by the third and fourth embodiments of the present invention, the photoresist of different thickness is formed by using a multi-tone mask process, and the preparation of the photoresist pattern is reduced by the ashing process, thereby simplifying the preparation process. Reduce the defects caused by the complicated preparation process.
  • the second photoresist pattern 112 obtained by ashing the first photoresist pattern 111 is directly used as a blocking mask for the n-type lightly doped ion implantation process, and the barrier layer can be formed without additional steps, thereby simplifying the process steps and shortening the production. Time, reduce costs.
  • a source 106, a drain 107, a source heavily doped region 126 formed in the p-type dopant ion implantation process, the n-type heavily doped ion implantation process, and the n-type lightly doped ion implantation process Due to the direct use of photoresist as a resistance a mask, a source 106, a drain 107, a source heavily doped region 126 formed in the p-type dopant ion implantation process, the n-type heavily doped ion implantation process, and the n-type lightly doped ion implantation process, The critical dimensions of the drain heavily doped region 127, the source lightly doped region 129, and the drain lightly doped region 127 are more accurate and uniform than conventional techniques, thereby improving the quality of the product.
  • This embodiment provides an array substrate fabricated by the method for preparing an array substrate according to the third or fourth embodiment.
  • the array substrate provided in this embodiment has the same technical effects as the method for preparing the array substrate described in the above third or fourth embodiment, and details are not described herein again.
  • the display device includes a liquid crystal display device or an organic electroluminescent diode display device.
  • the display device may include a counter substrate, and a liquid crystal layer interposed between the array substrate and the counter substrate, in addition to any of the above-described array substrates.
  • the display device is an organic electroluminescent diode display device
  • the display device includes the array substrate prepared by the preparation method according to the fourth embodiment of the present invention, and a cathode, an organic light-emitting layer, and the like disposed on the array substrate.
  • the display device provided by the embodiment of the present invention has the same technical effects as the method for preparing the array substrate according to the third or fourth embodiment of the present invention, and details are not described herein again.

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Abstract

薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置。该薄膜晶体管的制备方法包括在半导体层（124）的图案上形成包括两种不同厚度的光刻胶的第一光刻胶图案（111），以其为阻挡掩模对半导体层的图案进行重掺杂离子注入工艺；对第一光刻胶图案（111）进行灰化处理，以去除第二厚度光刻胶（1112），并减薄第一厚度光刻胶（1111），形成第二光刻胶图案（112）；再以其为阻挡掩模对半导体层的图案进行轻掺杂离子注入工艺。该方法减少了工艺步骤，缩短生产时间，降低成本，提高产品质量。

Description

薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置 技术领域
本发明至少一实施例涉及一种薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)是一种薄膜型的半导体器件，其在显示技术、集成电路技术等领域中被广泛应用。通常，在液晶显示器(Liquid Crystal Display，LCD)或有机发光二极管(Organic Light Emitting Diode，OLED)显示器中，每个像素单元都是由集成在像素单元后面的TFT来驱动，从而可以做到高速度、高亮度、高对比度地显示画面信息。通常，按照TFT半导体膜层的组成，可以将TFT主要分为非晶硅TFT，多晶硅TFT，以及氧化物TFT。
对于LCD和OLED，多晶硅TFT的电子迁移率可达50-200cm2/Vs，因此多晶硅TFT-LCD具有分辨率更高，反应速度更快，开口率高等优点。此外，多晶硅TFT又是发展有源矩阵有机发光二极管面板(Active Matrix/Organic Light Emitting Diode，AMOLED)的技术平台，多晶硅TFT可以采用低工作电压，作为AMOLED面板的驱动背板，可以降低消耗电流。
然而，由于多晶硅TFT的晶格排列整齐，电子在其内部所受的阻抗较小，导致在关闭状态下具有严重的漏电流问题，影响多晶硅TFT的正常使用。为了抑制TFT的漏电流，一般采用在TFT的源、漏极间进行轻掺杂的方式。一方面，可以降低像素开关的关态漏电流。另一方面，可以改善周边设置电路的热电子恶化现象，提高信赖性。但是这样会使得TFT的制备工艺步骤增加，增加生产时间，降低产品良率。并且，由于源极和漏极的轻掺杂区的关键尺寸较难控制，导致产品的均一性降低。
发明内容
本发明至少一实施例提供一种薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置。该薄膜晶体管的制备方法可以精确高效地控制源极轻掺杂 区和漏极轻掺杂区的关键尺寸，既可保证生产效率，又可保证产品均一性，解决了漏电流的难题。并且，较通常的工艺减少了工艺步骤，更容易控制因工艺步骤和生产时间增加带来的不良的增加，从而可缩短生产时间，可降低生产成本，提高产品质量。
本发明至少一实施例提供一种薄膜晶体管的制备方法，包括：
在衬底基板上形成半导体层的图案；
在所述半导体层的图案上形成第一光刻胶图案，所述第一光刻胶图案包括第一厚度光刻胶和第二厚度光刻胶，所述第一厚度光刻胶对应所述半导体层的图案中待形成沟道区的区域，所述第二厚度光刻胶对应所述半导体层的图案中待形成源极轻掺杂区和漏极轻掺杂区的区域；所述第一厚度光刻胶的厚度大于所述第二厚度光刻胶的厚度；
以所述第一光刻胶图案为阻挡掩模对所述半导体层的图案进行重掺杂离子注入工艺，形成源极重掺杂区和漏极重掺杂区的图案；
对所述第一光刻胶图案进行灰化处理，以去除所述第二厚度光刻胶，并减薄所述第一厚度光刻胶，形成第二光刻胶图案；
以所述第二光刻胶图案为阻挡掩模对所述半导体层的图案进行轻掺杂离子注入工艺，形成沟道区、源极轻掺杂区和漏极轻掺杂区的图案；以及
去除所述第二光刻胶图案。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，所述源极轻掺杂区和所述源极重掺杂区构成薄膜晶体管的源极，所述漏极轻掺杂区和所述漏极重掺杂区构成薄膜晶体管的漏极，所述源极和漏极之间具有间隔以界定所述沟道区。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，所述第二厚度光刻胶位于所述第一厚度光刻胶的两侧。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，在所述半导体层的图案上还形成层间介电层，其中，在所述层间介电层上形成所述第一光刻胶图案。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，形成所述第一光刻胶图案包括：
形成光刻胶薄膜，采用多色调掩模板对所述光刻胶薄膜进行曝光和显影， 形成第一光刻胶图案，所述第一光刻胶图案包括光刻胶完全保留区域和光刻胶半保留区域，其中，所述光刻胶完全保留区域对应所述半导体层的图案中待形成沟道区的区域，所述光刻胶半保留区域对应所述半导体层的图案中待形成源极轻掺杂区和漏极轻掺杂区的区域。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，所述多色调掩模板包括半色调掩模板和灰色调掩模板中的任一种。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，还包括形成栅极的图案的步骤，其中，所述栅极的图案在形成所述半导体层的图案之前形成。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，还包括形成缓冲层的步骤，其中，所述缓冲层位于所述栅极的图案和所述半导体层的图案之间。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，所述半导体层的材质包括多晶硅。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，所述重掺杂离子注入工艺和所述轻掺杂离子注入工艺中进行n型掺杂。
例如，在本发明一实施例提供的薄膜晶体管的制备方法中，掺杂离子为磷离子。
本发明至少一实施例还提供一种阵列基板的制备方法，包括上述任一所述的薄膜晶体管的制备方法。
本发明至少一实施例还提供一种阵列基板，采用上述任一方法制成。
本发明至少一实施例还提供一种显示装置，包括上述任一阵列基板。
例如，在本发明一实施例提供的显示装置中，所述显示装置包括液晶显示装置或有机电致发光二极管显示装置。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a-图1h为本发明一实施例提供的薄膜晶体管制备方法中在衬底基板 上形成栅极的图案、缓冲层、以及半导体层的图案的工艺流程示意图；
图2a-图2f为本发明一实施例提供的薄膜晶体管制备方法中在半导体层的图案中形成源漏重掺杂区、源漏轻掺杂区以及沟道区的图案的工艺流程示意图；
图3a-图3i为本发明一实施例提供的在衬底基板上形成p型TFT和n型TFT的栅极的图案、缓冲层、半导体层的图案以及层间介电层的工艺流程示意图；
图4a-图4d为本发明一实施例提供的在p型TFT的半导体层的图案中形成源漏极以及沟道区的图案的工艺流程示意图；
图5a-图5f为本发明一实施例提供的在n型TFT的半导体层的图案中形成源漏重掺杂区、源漏轻掺杂区以及沟道区的图案的工艺流程示意图；
6a为本发明一实施例提供的阵列基板的剖面示意图；
6b为本发明一实施例提供的另一阵列基板的剖面示意图；以及
图7为本发明另一实施例提供的阵列基板的剖面示意图。
附图标记：
101-衬底基板；1020-栅极金属薄膜；1021-光刻胶图案；102-栅极；122-栅极；103-缓冲层；1040-半导体薄膜；1041-光刻胶图案；1042-非晶硅薄膜；1043-p型TFT的非晶硅薄膜；1243-n型TFT的非晶硅薄膜；104-p型TFT的半导体层；124-n型TFT的半导体层；105-光刻胶图案；106-p型TFT的源极；126-源极重掺杂区；107-p型TFT的漏极；127-漏极重掺杂区；108-p型TFT的沟道区；128-n型TFT的沟道区；111-第一光刻胶图案；112-第二光刻胶图案；129-源极轻掺杂区；120-漏极轻掺杂区；1296-n型TFT的源极；1207-n型TFT的漏极；131-层间介电层；132-平坦层；133-公共电极；134-绝缘层；135-像素电极；136-源/漏接触区或者源/漏接触部。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明至少一实施例提供一种薄膜晶体管的制备方法，包括：
在衬底基板上形成半导体层的图案；
在半导体层的图案上形成第一光刻胶图案，第一光刻胶图案包括第一厚度光刻胶和第二厚度光刻胶，第一厚度光刻胶对应半导体层的图案中待形成沟道区(沟道区可对应TFT的有源层)的区域，第二厚度光刻胶对应半导体层的图案中待形成源极轻掺杂区和漏极轻掺杂区的区域；第一厚度光刻胶的厚度大于第二厚度光刻胶的厚度；
以第一光刻胶图案为阻挡掩模对半导体层的图案进行重掺杂离子注入工艺，形成源极重掺杂区和漏极重掺杂区的图案；
对第一光刻胶图案进行灰化处理，以去除第二厚度光刻胶，并减薄第一厚度光刻胶，形成第二光刻胶图案；
以第二光刻胶图案为阻挡掩模对半导体层的图案进行轻掺杂离子注入工艺，形成沟道区(沟道区可对应TFT的有源层)、源极轻掺杂区和漏极轻掺杂区的图案；以及
去除第二光刻胶图案。
源漏极轻掺杂区是为电子运动提供缓冲区的目的区域，是像素区N型薄膜晶体管抑制漏电的关键因素。本发明的实施例提供的薄膜晶体管制备方法通过包括两种不同厚度光刻胶的第一光刻胶图案作为重掺杂工艺的阻挡掩模，并且通过光刻胶灰化工艺来形成第二光刻胶图案来作为轻掺杂工艺的阻 挡掩模。既可简单、准确、高效地控制薄膜晶体管各区域(例如，源漏极轻掺杂区和/或源漏极重掺杂区)的关键尺寸(Critical Dimension，CD)，提高产品均一性；还可简化工艺步骤，降低成本。
下面通过例举几个实施例作进一步的说明。
实施例一
本实施例提供一种薄膜晶体管的制备方法。图1a-图1h以及图2a-图2f为本实施例提供的一种薄膜晶体管制备方法的工艺流程示意图。
如图1a所示，提供一衬底基板101，例如，该衬底基板101可以为玻璃基板、石英基板或其他基板。接着，在衬底基板101上形成一层栅极金属薄膜1020。例如，该栅极金属薄膜1020可采用气相沉积法(Chemical Vapor Deposition，CVD)、磁控溅射法(Megnetron Sputtering)或真空蒸镀法形成。例如，该栅极金属薄膜1020的材料包括选自铝，钛，钽，铬，钼，钨化钼中的一种或多种，或上述金属所任意组成的合金中的一种或多种，但不限于此。例如，栅极金属薄膜可为单层或者多层结构。相应地，形成的栅极可为单层或者多层结构。
如图1b所示，在栅极金属薄膜1020上待形成栅极122的对应位置形成光刻胶图案1021。
如图1c所示，利用光刻胶图案1021为掩模对栅极金属薄膜1020进行刻蚀，形成栅极122的图案，并剥离光刻胶图案1021。
如图1d所示，在衬底基板101和栅极122上形成缓冲层103。例如，形成该缓冲层103可以采用化学气相沉积法(CVD)，但不限于此。例如，该缓冲层103的材料包括选自氮化硅(SiNx)，氧化硅(SiOx)，氮氧化硅(SiNxOy)中的一种或多种，但不限于此。
需要说明的是，在本实施例中，该缓冲层103既可以起到屏蔽衬底基板101上的缺陷，避免衬底基板101引起的各种不良的作用，还可以作为栅极122的栅极绝缘层；从而，可减少栅极绝缘层的制备，缩短制备时间，降低产品成本，提高产品质量。
例如，如图1e所示，在衬底基板上形成半导体薄膜1040，例如，该半导体层薄膜的材质为多晶硅(p-Si)。半导体层薄膜的形成过程可包括如下步骤：在缓冲层103上形成非晶硅(a-Si)薄膜。例如，可以采用等离子体增 强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)形成非晶硅(a-Si)薄膜。对非晶硅(a-Si)薄膜进行激光退火工艺使非晶硅(a-Si)转变为多晶硅(p-Si)。例如，该激光退火工艺可以采用准分子激光退火工艺(Excimer Laser Annealing，ELA)。
如图1f所示，在半导体薄膜1040上待形成半导体层124的对应位置处形成光刻胶图案1041。
如图1g所示，用光刻胶图案1041作为掩模对半导体薄膜1040进行刻蚀，得到岛状的半导体层124的图案，并剥离光刻胶图案1041。例如，半导体层124的图案为多晶硅。
如图1h所示，采用掺杂(Doping)工艺对半导体层124的图案进行阀值电压(threshold voltage，Vth)调整。例如，该阀值电压调整的掺杂工艺可以为对半导体层124进行硼离子或磷离子的掺杂注入工艺。
如图2a所示，在半导体层124的图案上形成第一光刻胶图案111，该第一光刻胶图案111包括第一厚度光刻胶1111和第二厚度光刻胶1112，第一厚度光刻胶1111对应半导体层124的图案中待形成沟道区128(图中未示出，请参见图2d)的区域，第二厚度光刻胶1112对应半导体层124的图案中待形成源极轻掺杂区129(图中未示出，请参见图2d)和漏极轻掺杂区120(图中未示出，请参见图2d)的区域。并且，第一厚度光刻胶1111的厚度大于第二厚度光刻胶1112的厚度。例如，第二厚度光刻胶位于第一厚度光刻胶的两侧。
例如，形成该第一光刻胶图案111的步骤包括：在半导体层124的图案上形成一光刻胶薄膜，采用多色调掩模板对光刻胶薄膜进行曝光显影，形成第一光刻胶图案111，该第一光刻胶图案111包括光刻胶完全保留区域和光刻胶半保留区域，光刻胶完全保留区域对应半导体层124中待形成沟道区128的区域，光刻胶半保留区域对应半导体层124中待形成源极轻掺杂区129和漏极轻掺杂区120的区域。半导体层124的图案上除了第一光刻胶图案111外的区域对应待形成的源极重掺杂区126的图案和漏极重掺杂区127的图案。例如，漏极重掺杂区可作为欧姆接触的用途。
例如，该多色调掩模板包括半色调掩模板和灰色调掩模板中的任一种。
如图2b所示，以该第一光刻胶图案111作为阻挡掩模对半导体层124 的图案进行n型重掺杂离子注入工艺，形成位于两侧的源极重掺杂区126和漏极重掺杂区127的图案。例如，注入的离子可以为磷离子，但不限于此。
如图2c所示，采用光刻胶灰化(photoresist ashing)工艺对第一光刻胶图案111进行灰化处理，以去除第二厚度光刻胶1112并减薄第一厚度光刻胶1111，得到第二光刻胶图案112。第二光刻胶图案112包括对应半导体层124的图案中待形成沟道区128的区域。需要说明的是，经过n型重掺杂离子注入工艺处理后，第一光刻胶图案111的表面发生炭化，在上述灰化工艺中，需去除炭化光刻胶，以避免在后续剥离工艺中炭化光刻胶不易剥离。
如图2d所示，以该第二光刻胶图案112作为阻挡掩模对半导体层124的图案进行n型轻掺杂离子注入工艺，形成源极轻掺杂区129的图案和漏极轻掺杂区120的图案，以及位于该源极轻掺杂区129和漏极轻掺杂区120之间的沟道区128。例如，注入的离子可以为磷离子，但不限于此。
需要说明的是，作为形成源漏轻掺杂区的阻挡掩模的第二光刻胶图案由第一光刻胶图案111灰化而来，不需要额外形成阻挡层的工艺，例如，可节省形成阻挡层的成膜、曝光、显影等步骤，或者可节省形成阻挡层的成膜、曝光、显影、刻蚀等步骤，从而可简化工艺步骤，缩短生产时间，降低成本。另外，因为直接使用第一光刻胶图案111作为阻挡掩模，所以需要掺杂的区域即源极重掺杂区126和漏极重掺杂区127关键尺寸的准确性和均一性比通常技术更好，从而可提高产品的质量。
如图2e所示，经过n型轻掺杂离子注入工艺的第二光刻胶图案112的表面发生炭化，采用光刻胶灰化工艺对炭化的光刻胶进行去除。
需要说明的是，由于第二光刻胶图案112经过n型轻掺杂离子注入工艺后，表面发生炭化，不容易直接剥离，所以需要利用光刻胶灰化工艺将炭化的光刻胶进行去除。例如，炭化的光刻胶进行去除后，可进行光刻胶的剥离。
如图2f所示，去除第二光刻胶图案112。例如，将第二光刻胶图案112采用光刻胶的剥离工艺进行剥离。
例如，如图2f所示，源极轻掺杂区129和源极重掺杂区126构成薄膜晶体管的源极1296，漏极轻掺杂区120和漏极重掺杂区127构成薄膜晶体管的漏极1207，源极1296和漏极1207之间具有间隔以界定沟道区128。
例如，如图2f所示，沟道区128两侧分别为源极轻掺杂区129和漏极轻 掺杂区120，源极轻掺杂区129和漏极轻掺杂区120外分别为源极重掺杂区126和漏极重掺杂区127。
本实施例提供的薄膜晶体管的制备方法中，形成包括两种不同厚度光刻胶的第一光刻胶图案作为重掺杂工艺的阻挡掩模，以第一光刻胶图案111灰化后得到的第二光刻胶图案112直接作为阻挡掩模进行n型轻掺杂离子注入工艺，可不用形成额外的阻挡层，可简化工艺步骤，缩短生产时间，降低成本。另外，由于直接使用光刻胶作为阻挡掩模，在上述n型重掺杂离子注入工艺和n型轻掺杂离子注入工艺中形成的源极重掺杂区126、漏极重掺杂区127、源极轻掺杂区129、以及漏极轻掺杂区127的关键尺寸的准确性和均一性比通常技术更好，从而可提高产品的质量。
实施例二
本实施例提供一种薄膜晶体管的制备方法。图3a-图3i、图4a-图4d以及图5a-图5f为本实施例提供的薄膜晶体管制备方法的工艺流程示意图。
如图3a所示，提供一衬底基板101。例如，该衬底基板101可以为玻璃基板、石英基板或其他基板。接着，在衬底基板101上形成一层栅极金属薄膜1020。例如，该栅极金属薄膜1020可采用气相沉积法、磁控溅射法或真空蒸镀法形成，但不限于此。该栅极金属薄膜1020的材料包括选自铝，钛，钽，铬，钼，钨化钼中的一种或多种，或上述金属所任意组成的合金的一种或多种，但不限于此。
如图3b所示，在栅极金属薄膜1020上待形成p型薄膜晶体管的栅极102和n型薄膜晶体管的栅极122的对应位置处形成光刻胶图案1021。
如图3c所示，利用该光刻胶图案1021作为掩模对栅极金属薄膜1020进行刻蚀，形成p型薄膜晶体管的栅极102、n型薄膜晶体管的栅极122的图案，并剥离该光刻胶图案1021。
如图3d所示，在衬底基板101、栅极102和栅极122上形成缓冲层103。例如，形成该缓冲层103可以采用化学气相沉积法(CVD)形成，但不限于此。例如，该缓冲层103的材料包括选自氮化硅(SiNx)，氧化硅(SiOx)，氮氧化硅(SiNxOy)中的一种或多种，但不限于此。
需要说明的是，在本实施例中，缓冲层103既可以起到屏蔽衬底基板101上的缺陷，避免衬底基板101引起的各种不良的作用，还可以作为栅极102 和栅极122的栅极绝缘层。从而，可减少栅极绝缘层的制备，可缩短制备时间，降低产品成本，提高产品质量。
例如，如图3e所示，在衬底基板上形成非晶硅(a-Si)薄膜1042。例如，该非晶硅(a-Si)薄膜可以采用等离子体增强化学气相沉积法(PECVD)形成，但不限于此。
如图3f所示，在非晶硅(a-Si)薄膜1042上待形成p型薄膜晶体管的半导体层104和n型薄膜晶体管的半导体层124的对应位置处形成半导体层光刻胶图案1041。
如图3g所示，用该半导体层光刻胶图案1041作为掩模对非晶硅(a-Si)薄膜1042进行刻蚀，去除未被光刻胶覆盖的非晶硅(a-Si)薄膜，得到岛状的非晶硅(a-Si)层1043、1243的图案，并剥离该半导体光刻胶图案1041。
如图3h所示，在非晶硅(a-Si)层1043、1243的图案以及缓冲层103上形成层间介电层(Inter Layer Dielectric，ILD)131。
如图3i所示，对非晶硅(a-Si)层的图案进行准分子激光退火工艺使非晶硅(a-Si)转变为多晶硅(p-Si)，形成半导体层的图案(多晶硅图案)104和124。再对半导体层的图案104和124进行阀值电压调整。形成的层间介电层在激光退火的时候能对非晶硅(a-Si)层进行一定的保护。需要说明的是，也可以先对非晶硅(a-Si)层的图案进行准分子激光退火工艺使非晶硅(a-Si)转变为多晶硅(p-Si)，再对其进行图案化形成半导体层图案(多晶硅图案)，然后进行阀值电压调整，之后再形成层间介电层，在此不作限定。例如，可采用掺杂(Doping)工艺对半导体层104、124的图案进行阀值电压(threshold voltage，Vth)调整。例如，该阀值电压调整的掺杂(Doping)工艺可以为对半导体层104、124的图案进行硼离子或磷离子的掺杂注入工艺。
如图4a所示，在层间介电层131上形成用于定义待形成的p型薄膜晶体管的源漏极的光刻胶图案105，该光刻胶图案105包括形成在待形成的p型薄膜晶体管的半导体层104的图案上的部分，该部分只覆盖半导体层104的图案中待形成沟道区108(图中未示出，请参见图4b)的部分；以及形成在待形成的n型薄膜晶体管的半导体层124上的部分，该部分覆盖整个半导体层124的图案。
需要说明的是，该光刻胶图案105中覆盖半导体层124的图案的部分用 于保护半导体层124不被后续的p型掺杂离子注入工艺影响。
如图4b所示，以上述光刻胶图案105为阻挡掩模进行p型掺杂离子注入工艺，在半导体层104中形成源极106、漏极107以及位于源极106和漏极107之间的沟道区108。例如，源极106和漏极107之间具有间隔以界定沟道区108。例如，注入的离子可以为硼离子。例如，所述的p型掺杂为p型重掺杂。
需要说明的是，因为直接使用光刻胶图案105作为掩模，所以需要掺杂的区域即源极106和漏极107关键尺寸的准确性和均一性比通常技术更好，从而可提高产品的质量。这样可减少一步刻蚀，可提升产能，节约成本，同时减少整体产品制成的时间而避免随时间增加而造成不良的增加。
如图4c所示，经过p型掺杂离子注入工艺处理的光刻胶图案105的表面发生炭化，采用光刻胶灰化工艺将炭化光刻胶去除，再进行光刻胶的剥离。
需要说明的是，由于光刻胶图案105经过p型掺杂离子注入工艺后，表面发生炭化，不容易直接剥离，所以需要利用光刻胶灰化工艺将炭化的光刻胶进行去除。
如图4d所示，将剩余的光刻胶图案105剥离，上述栅极102、缓冲层103、源极106、漏极107以及沟道区108构成一个p型薄膜晶体管。
如图5a所示，在层间介电层131上形成第一光刻胶图案111，该第一光刻胶图案111包括覆盖待形成的n型薄膜晶体管的半导体层124的图案的部分，该部分包括第一厚度光刻胶1111和第二厚度光刻胶1112，第一厚度光刻胶1111对应半导体层124的图案中待形成沟道区128的图案(图中未示出，请参见图5f)的区域，第二厚度光刻胶1112对应半导体层124的图案中待形成源极轻掺杂区129和漏极轻掺杂区120的区域。并且，第一厚度光刻胶1111的厚度大于第二厚度光刻胶1112的厚度。该第一光刻胶图案111还包括覆盖p型薄膜晶体管的源极106、漏极107以及沟道区108的部分，该部分完全覆盖上述p型薄膜晶体管的源极106、漏极107以及沟道区108，并且该部分的宽度大于源极106、漏极107以及沟道区108(半导体层104)的总宽度。
例如，形成该第一光刻胶111的步骤包括：在半导体层104、124的图案上形成一光刻胶薄膜，采用多色调掩模板对光刻胶薄膜进行曝光显影，形成 第一光刻胶图案111，该第一光刻胶图案111包括光刻胶完全保留区域和光刻胶半保留区域，光刻胶完全保留区域对应p型薄膜晶体管源极106、漏极107和沟道区108的区域以及半导体层124的图案中待形成沟道区128的区域，光刻胶半保留区域对应半导体层124的图案中待形成源极轻掺杂区129和漏极轻掺杂区120的区域。例如，对应半导体层124的图案的第一光刻胶图案111中，第二厚度光刻胶位于第一厚度光刻胶的两侧。
例如，该多色调掩模板包括半色调掩模板和灰色调掩模板中的任一种。
需要说明的是，该第一光刻胶图案111中覆盖源极106、漏极107以及沟道区108的部分用于源极106、漏极107以及沟道区108不被后续的n型重掺杂离子注入工艺影响。
如图5b所示，以该第一光刻胶图案111作为阻挡掩模对半导体层124的图案进行n型重掺杂离子注入工艺，形成位于两侧的源极重掺杂区126和漏极重掺杂区127。例如，注入的离子可以为磷离子，但不限于此。
需要说明的是，因为直接使用第一光刻胶图案111作为阻挡掩模，所以需要掺杂的区域即源极掺杂区126和漏极重掺杂区127的关键尺寸的准确性和均一性比通常技术更好，从而可提高产品的质量。
如图5c所示，采用光刻胶灰化工艺对第一光刻胶图案111进行灰化，去除第二厚度光刻胶1112并减薄第一厚度光刻胶1111，得到第二光刻胶图案112。第二光刻胶图案112包括覆盖p型薄膜晶体管的源极106、漏极107以及沟道区108的部分以及覆盖n型薄膜晶体管的对应半导体层124的图案中待形成沟道区128的区域。经过n型重掺杂离子注入工艺处理的第一光刻胶图案111的表面发生炭化，在上述灰化工艺中，炭化光刻胶同时也被去除。
值得注意的是，由于上述第一光刻胶图案111中覆盖p型薄膜晶体管的部分的宽度大于p型薄膜晶体管的宽度，所以，即使在上述灰化工艺之后，所形成的第二光刻胶图案112仍然可以完全覆盖该p型薄膜晶体管，以达到保护的目的。
如图5d所示，以该第二光刻胶图案112作为阻挡掩模对半导体层124的图案进行n型轻掺杂离子注入工艺，形成源极轻掺杂区129、漏极轻掺杂区120以及位于源极轻掺杂区129和漏极轻掺杂区120之间的沟道区128的图案。例如，注入的离子可以为磷离子，但不限于此。
如图5e所示，经过n型轻掺杂离子注入工艺的第二光刻胶图案112的表面发生炭化，采用光刻胶灰化工艺对炭化的光刻胶进行去除。
需要说明的是，由于第二光刻胶图案112经过n型轻掺杂离子注入工艺后，表面发生炭化，不容易直接剥离，所以需要利用光刻胶灰化工艺将炭化的光刻胶进行去除。
如图5f所示，将剩余的第二光刻胶图案112进行剥离，从而去除第二光刻胶图案112。
需要说明的是，本实施例亦可如实施例1那样，不设置层间介电层。从而，第一光刻胶图案直接形成在半导体层的图案上。
例如，如图5f所示，源极轻掺杂区129和源极重掺杂区126构成薄膜晶体管的源极1296，漏极轻掺杂区120和漏极重掺杂区127构成薄膜晶体管的漏极1207，源极1296和漏极1207之间具有间隔以界定沟道区128。
例如，如图5f所示，沟道区128两侧分别为源极轻掺杂区129和漏极轻掺杂区120，源极轻掺杂区129和漏极轻掺杂区120外分别为源极重掺杂区126和漏极重掺杂区127。
本实施例提供的薄膜晶体管的制备方法中，形成包括两种不同厚度光刻胶的第一光刻胶图案作为重掺杂工艺的阻挡掩模，以第一光刻胶图案111灰化后得到的第二光刻胶图案112直接作为阻挡掩模进行n型轻掺杂离子注入工艺，可不用形成额外的阻挡层，简化工艺步骤，缩短生产时间，降低成本。同时可以形成n型薄膜晶体管和p型薄膜晶体管，并且借助灰化工艺减少至少一次光刻胶图案的制备，可简化制备工艺。另外，由于直接使用光刻胶作为阻挡掩模，在上述p型掺杂离子注入工艺，n型重掺杂离子注入工艺和n型轻掺杂离子注入工艺中形成的源极106、漏极107、源极重掺杂区126、漏极重掺杂区127、源极轻掺杂区129以及漏极轻掺杂区127的关键尺寸的准确性和均一性比通常技术更好，从而可提高产品的质量。
实施例三
本实施例提供一种阵列基板的制备方法，包括实施例一所述的薄膜晶体管的制备方法。薄膜晶体管的制备方法在此不再赘述，请参见之前描述。6a为采用本实施例提供的阵列基板的制备方法制备的一种阵列基板的剖面示意图。
例如，如6a所示，本实施例提供的阵列基板的制备方法还可包括：在缓冲层103和n型薄膜晶体管上形成平坦层132。在平坦层132上对应显示区的区域形成公共电极133。在平坦层132和公共电极133上形成绝缘层134；在绝缘层134和平坦层132中形成过孔，该过孔贯穿绝缘层134和平坦层132，露出n型薄膜晶体管的漏极重掺杂区127。在绝缘层134上对应显示区的区域形成像素电极135，该像素电极135通过过孔与漏极重掺杂区127电性连接。
例如，如6b所示，还可包括形成源/漏极接触区136的步骤。例如，源/漏极接触区136可采用金属材质，但不限于此。例如，源极接触区可为数据线，但不限于此。例如，漏极接触区可为接触电极，但不限于此。
例如，该平坦层132可为单层结构或多层结构。
例如，该平坦层132的材料可包括选自氮化硅(SiNx)，氧化硅(SiOx)，氮氧化硅(SiNxOy)中的一种或多种，但不限于此。
例如，该平坦层132可以用等离子体增强化学气相沉积法(PECVD)制作，但不限于此。
例如，该公共电极133和像素电极135的材料可为氧化铟锡(ITO)或铟锌氧化物(IZO)等透明金属氧化物，但不限于此。
例如，该公共电极133和像素电极135可采用磁控溅射工艺制作，但不限于此。
需要说明的是，本实施例提供的阵列基板的制备方法中像素电极135和公共电极133的形成顺序可以调换，即公共电极位于像素电极之上。对此不作具体限定。在上的电极例如为狭缝状电极。
实施例四
本实施例提供一种阵列基板的制备方法，包括实施例二所述的薄膜晶体管的制备方法。该薄膜晶体管的制备方法在此不再赘述，请参见之前描述。图7为采用本发明实施例提供的阵列基板的制备方法制备的一种阵列基板。
例如，如图7所示，本实施例一示例提供的阵列基板的制备方法还包括：在层间介电层131上形成多个过孔，多个过孔分别贯穿该层间介电层131并且暴露p型薄膜晶体管的源极106和漏极107以及n型薄膜晶体管的源极重掺杂区126和漏极重掺杂区127；在上述形成有过孔的层间介电层131上形 成金属层，使该金属层填入上述多个过孔，并采用构图工艺形成多个分别与p型薄膜晶体管的源极106和漏极107以及n型薄膜晶体管的源极重掺杂区126和漏极重掺杂区127相连的源/漏极接触区136；在上述层间介电层131和多个源/漏极接触区136上形成平坦层132。在平坦层132中形成过孔，使该过孔贯穿该平坦层132并暴露与n型薄膜晶体管的漏极重掺杂区127相连的源/漏极接触区136；以及形成在平坦层132之上的像素电极135，该像素电极135通过过孔连接与n型薄膜晶体管的漏极重掺杂区127相连的源/漏极接触区136。例如，源极接触区可为数据线，但不限于此。例如，漏极接触区可为接触电极，但不限于此。例如，本示例提供的阵列基板的制备方法中可不包括形成漏极接触区的步骤。
例如，该平坦层132可为单层结构或多层结构。
例如，该平坦层132的材料可包括选自氮化硅(SiNx)，氧化硅(SiOx)，氮氧化硅(SiNxOy)中的一种或多种，但不限于此。
例如，该平坦层132可以用等离子体增强化学气相沉积法(PECVD)制作，但不限于此。
例如，该像素电极135的材料可为氧化铟锡(ITO)或铟锌氧化物(IZO)等透明金属氧化物，但不限于此。
例如，该像素电极135可采用磁控溅射工艺制作，但不限于此。
需要说明的是，本实施例提供的阵列基板的制备方法既可用于制备液晶显示装置的阵列基板，也可以用于制备有机电致发光二极管显示装置的阵列基板。当该阵列基板的制备方法用于制备有机电致发光二极管显示装置的阵列基板时，该像素电极135可以作为有机电致发光二极管显示装置的阳极。
本发明实施例三和四提供的阵列基板的制备方法中，通过底栅设计，将栅极122直接形成在衬底基板101上，减少了栅极绝缘层的制备，从而可缩短生产时间，降低产品成本。另外，本发明实施例三和四提供的阵列基板的制备方法中，利用多色调掩膜工艺形成不同厚度的光刻胶，借助灰化工艺减少至少一次光刻胶图案的制备，可简化制备工艺，降低因制备工艺复杂造成的不良。并且，灰化第一光刻胶图案111后得到的第二光刻胶图案112直接作为阻挡掩模进行n型轻掺杂离子注入工艺，可不用额外形成阻挡层，可简化工艺步骤，缩短生产时间，降低成本。另外，由于直接使用光刻胶作为阻 挡掩模，在上述p型掺杂离子注入工艺，n型重掺杂离子注入工艺和n型轻掺杂离子注入工艺中形成的源极106、漏极107、源极重掺杂区126、漏极重掺杂区127、源极轻掺杂区129以及漏极轻掺杂区127的关键尺寸的准确性和均一性比通常技术更好，从而可提高产品的质量。
实施例五
本实施例提供一种阵列基板，采用实施例三或四所述的阵列基板的制备方法制作。本实施例提供的阵列基板具有与上述实施例三或四所述阵列基板的制备方法相同的技术效果，在此不再赘述。
实施例六
本实施例提供一种显示装置。该显示装置包括液晶显示装置或有机电致发光二极管显示装置。
该显示装置为液晶显示装置的情况下，该显示装置除了包括上述任意一种阵基板之外，还可包括对置基板，和夹设在阵列基板和对置基板之间的液晶层。
该显示装置为有机电致发光二极管显示装置的情况下，该显示装置包括本发明实施例四所述制备方法制备的阵列基板以及设置在阵列基板上的阴极、有机发光层等。本发明实施例提供的显示装置具有与上述实施例三或四所述阵列基板的制备方法相同的技术效果，在此不再赘述。
有以下几点需要说明：
(1)本发明实施例未涉及之处，请参见通常设计。
(2)本发明实施例附图中，只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易 想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本专利申请要求于2015年8月14日递交的中国专利申请第201510502027.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种薄膜晶体管的制备方法，包括：
    在衬底基板上形成半导体层的图案；
    在所述半导体层的图案上形成第一光刻胶图案，所述第一光刻胶图案包括第一厚度光刻胶和第二厚度光刻胶，所述第一厚度光刻胶对应所述半导体层的图案中待形成沟道区的区域，所述第二厚度光刻胶对应所述半导体层的图案中待形成源极轻掺杂区和漏极轻掺杂区的区域；所述第一厚度光刻胶的厚度大于所述第二厚度光刻胶的厚度；
    以所述第一光刻胶图案为阻挡掩模对所述半导体层的图案进行重掺杂离子注入工艺，形成源极重掺杂区和漏极重掺杂区的图案；
    对所述第一光刻胶图案进行灰化处理，以去除所述第二厚度光刻胶，并减薄所述第一厚度光刻胶，形成第二光刻胶图案；
    以所述第二光刻胶图案为阻挡掩模对所述半导体层的图案进行轻掺杂离子注入工艺，形成沟道区、源极轻掺杂区和漏极轻掺杂区的图案；以及
    去除所述第二光刻胶图案。
  2. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述源极轻掺杂区和所述源极重掺杂区构成薄膜晶体管的源极，所述漏极轻掺杂区和所述漏极重掺杂区构成薄膜晶体管的漏极，所述源极和漏极之间具有间隔以界定所述沟道区。
  3. 根据权利要求1或2所述的薄膜晶体管的制备方法，其中，所述第二厚度光刻胶位于所述第一厚度光刻胶的两侧。
  4. 根据权利要求1-3任一项所述的薄膜晶体管的制备方法，在所述半导体层的图案上还形成层间介电层，其中，在所述层间介电层上形成所述第一光刻胶图案。
  5. 根据权利要求1-4任一项所述的薄膜晶体管的制备方法，其中，形成所述第一光刻胶图案包括：
    形成光刻胶薄膜，采用多色调掩模板对所述光刻胶薄膜进行曝光和显影，形成第一光刻胶图案，所述第一光刻胶图案包括光刻胶完全保留区域和光刻胶半保留区域，其中，所述光刻胶完全保留区域对应所述半导体层的图案中 待形成沟道区的区域，所述光刻胶半保留区域对应所述半导体层的图案中待形成源极轻掺杂区和漏极轻掺杂区的区域。
  6. 根据权利要求1-5任一项所述的薄膜晶体管的制备方法，其中，所述多色调掩模板包括半色调掩模板和灰色调掩模板中的任一种。
  7. 根据权利要求1-6任一项所述的薄膜晶体管的制备方法，还包括形成栅极的图案的步骤，其中，所述栅极的图案在形成所述半导体层的图案之前形成。
  8. 根据权利要求1-7任一项所述的薄膜晶体管的制备方法，还包括形成缓冲层的步骤，其中，所述缓冲层位于所述栅极的图案和所述半导体层的图案之间。
  9. 根据权利要求1-8任一项所述的薄膜晶体管的制备方法，其中，所述半导体层的材质包括多晶硅。
  10. 根据权利要求1-9任一项所述的薄膜晶体管的制备方法，其中，所述重掺杂离子注入工艺和所述轻掺杂离子注入工艺中进行n型掺杂。
  11. 根据权利要求10所述的薄膜晶体管的制备方法，其中，掺杂离子为磷离子。
  12. 一种阵列基板的制备方法，包括权利要求1-11任一项所述的薄膜晶体管的制备方法。
  13. 一种阵列基板，采用权利要求12所述的方法制成。
  14. 一种显示装置，包括权利要求13所述的阵列基板。
  15. 根据权利要求14所述的显示装置，其中，所述显示装置包括液晶显示装置或有机电致发光二极管显示装置。
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