WO2017024873A1 - 一种存储单元和处理系统 - Google Patents

一种存储单元和处理系统 Download PDF

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Publication number
WO2017024873A1
WO2017024873A1 PCT/CN2016/084533 CN2016084533W WO2017024873A1 WO 2017024873 A1 WO2017024873 A1 WO 2017024873A1 CN 2016084533 W CN2016084533 W CN 2016084533W WO 2017024873 A1 WO2017024873 A1 WO 2017024873A1
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Prior art keywords
ram
port
data
read
storage structure
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PCT/CN2016/084533
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English (en)
French (fr)
Inventor
马骞
张灵燕
张瑛
杨洁伟
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深圳市中兴微电子技术有限公司
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Publication of WO2017024873A1 publication Critical patent/WO2017024873A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • the present invention relates to memory technologies in the field of hardware, and more particularly to a memory unit and a processing system.
  • automation is inseparable from the processing system, which is usually composed of a processor, a memory, an instrumentation, and a human-computer interaction interface.
  • the data storage capacity can be increased by increasing the access bandwidth of Memory.
  • the commonly used method is multiplier, that is, the data access bandwidth is increased by increasing the number of accesses to Memory per unit time, assuming that the data can be stored N times per unit time.
  • the embodiments of the present invention are expected to provide a storage unit and a processing system, which can improve data storage capacity, meet the control requirements of the processing system, and expand the application of the processing system.
  • an embodiment of the present invention provides a storage unit, where the storage unit includes at least one single-bit storage structure;
  • Each of the single-bit memory structures includes four random access memory RAMs, which are a first RAM, a second RAM, a third RAM, and a fourth RAM, respectively; the two read ports are a first read port and a second Read port; two write ports are a first write port and a second write port, respectively;
  • the first read port is respectively connected to the first RAM and the second RAM, and configured to read data stored in the first RAM and the second RAM;
  • the second read port is respectively connected to the third RAM and the fourth RAM, and configured to read data stored in the third RAM and the fourth RAM;
  • the first write port is respectively connected to the first RAM and the third RAM, and configured to write data to the first RAM and the third RAM;
  • the second write port is connected to the second RAM and the fourth RAM, respectively, and configured to write data to the second RAM and the fourth RAM.
  • the storage unit further includes a first logical operation subunit and a second logical operation subunit; the first logical operation subunit is connected to the first readout port, and the second logical operation subunit Connected to the first write port;
  • the first logical operation subunit is configured to read the first RAM through the first read port when writing first data to the single bit storage structure through the first write port And storing the second data stored in the second RAM, and then acquiring an exclusive OR value of the second data and the third data;
  • the second logical operation subunit is configured to, when the first data is different from the exclusive OR value, invert the second data through the first write port and respectively write the first data into the first RAM and the third RAM.
  • the storage unit includes two single-bit storage structures, which are respectively the first single a bit storage structure and a second single bit storage structure;
  • the first write port of the first single-bit storage structure and the first write port of the second single-bit storage structure are connected to form a first input port of the storage unit;
  • a second write port of the first single-bit storage structure and a second write port of the second single-bit storage structure are connected to form a second input port of the storage unit;
  • the first read port of the second single-bit storage structure is a first output port of the storage unit
  • the second read port of the second single bit storage structure is a second output port of the storage unit.
  • the storage unit further includes a third logical operation subunit and a fourth logical operation subunit; the third logical operation subunit is connected to the first read port of the first single bit storage structure, The fourth logical operation subunit is connected to the first input port;
  • the third logical operation subunit is configured to read the first read port of the first single bit storage structure separately when writing the fourth data to the storage unit through the first input port And storing the fifth data stored in the first RAM of the first single-bit storage structure and the sixth data stored in the second RAM, and then acquiring an exclusive OR value of the fifth data and the sixth data;
  • the fourth logical operation subunit is configured to, when the fourth data is different from the exclusive OR value, invert the fifth data through the first input port, and then write the first data into the first single The first RAM and the third RAM of the bit storage structure, and the first RAM and the third RAM of the second single bit storage structure.
  • the storage unit further includes at least one flag bit memory, and each of the flag bit memories corresponds to a single bit storage structure, and the flag bit memory is configured to store the first RAM and the second RAM of the corresponding single bit storage structure. The flags of the third RAM and the fourth RAM.
  • the storage unit includes a single-bit storage structure, and is a third single-bit storage structure, and the flag bit memory corresponding to the third single-bit storage structure is a fourth single-bit storage structure;
  • the flag bit memory is configured to, by the data read by the first read port of the fourth single-bit memory structure, instruct the first read port of the third single-bit memory structure to read the third single-bit memory Data stored in the first RAM of the structure or the second RAM of the third single bit storage structure;
  • the flag bit memory is specifically configured to: when the first read port of the fourth single-bit memory structure reads the seventh data, instruct the first read port of the third single-bit memory structure to read out Data stored in the first RAM;
  • the storage unit further includes a fifth logical operation subunit and a sixth logical operation subunit; the fifth logical operation subunit is connected to the first readout port of the fourth single bit storage structure, the sixth logic An operation subunit is connected to the first write port of the fourth single bit storage structure;
  • the fifth logical operation subunit is configured to pass the fourth data after writing new data to the first RAM of the third single-bit storage structure through the first write port of the third single-bit storage structure
  • the first read port of the single bit storage structure respectively reads the eighth data stored in the first RAM of the fourth single bit storage structure and the ninth data stored in the second RAM, and then acquires the eighth data and the The exclusive value of the ninth data;
  • the sixth logical operation subunit is configured to invert the eighth data by using a first write port of the fourth single bit storage structure when the XOR value is different from the seventh data
  • the first RAM and the third RAM of the fourth single-bit memory structure are then written.
  • the storage unit includes a single-bit storage structure, which is a fifth single-bit storage structure, and the flag bit memory corresponding to the fifth single-bit storage structure includes two single-bit storage structures, which are respectively the sixth single a bit storage structure and a seventh single bit storage structure;
  • the first write port of the sixth single-bit storage structure and the first write port of the seventh single-bit storage structure are connected to form a first write total port of the flag bit memory;
  • a second write port of the sixth single-bit storage structure and a second write port of the seventh single-bit storage structure are connected to form a second write total port of the flag bit memory;
  • the first read port of the seventh single bit storage structure is a first read total port of the flag bit memory
  • the second read port of the seventh single bit storage structure is a second read total port of the flag bit memory
  • the flag bit memory is configured to, by the data read by the first read total port, instruct the first read port of the fifth single bit storage structure to read out the fifth single bit storage structure.
  • an embodiment of the present invention provides a processing system, including any one of the foregoing storage units.
  • Embodiments of the present invention provide a storage unit and a processing system, including at least one single-bit storage structure; each of the single-bit storage structures includes four random access memory RAMs, which are respectively a first RAM, a second RAM, and a first a third RAM and a fourth RAM; the two read ports are a first read port and a second read port; respectively, two write ports, respectively a first write port and a second write port; wherein a first read port respectively connected to the first RAM and the second RAM, configured to read data stored in the first RAM and the second RAM; The second read port is respectively connected to the third RAM and the fourth RAM, configured to read data stored in the third RAM and the fourth RAM; the first write port respectively Connected to the first RAM and the third RAM, configured to write data to the first RAM and the third RAM; the second write port and the second RAM and the first A four RAM connection configured to write data to the second RAM and the fourth RAM.
  • each of the single-bit storage structures includes four random access memory RAMs, which are respectively a first RAM,
  • RAMs are used to form a single bit storage structure, so that the single bit storage structure has two read ports and two write ports, so that the single bit storage structure can be simultaneously Performing two read operations and two write operations improves the access bandwidth of the single-bit storage structure, thereby improving the data storage capacity of the storage unit including the single-bit storage structure, satisfying the control requirements of the processing system, and expanding the processing system.
  • FIG. 1 is a schematic structural diagram of a first storage unit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a second storage unit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a third storage unit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a fourth storage unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a fifth storage unit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a sixth storage unit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a seventh storage unit according to an embodiment of the present invention.
  • An embodiment of the present invention provides a storage unit, where the storage unit includes at least one single-bit storage structure 101, as shown in FIG.
  • Each of the single bit storage structures 101 includes four random access memories (Random-Access Memory, RAM), respectively, is a first RAM 1011, a second RAM 1012, a third RAM 1013, and a fourth RAM 1014; two read ports, respectively a first read port 101i and a second read port 101j; The write ports are the first write port 101p and the second write port 101q, respectively.
  • RAM Random-Access Memory
  • the first read port 101i is connected to the first RAM 1011 and the second RAM 1012, respectively, and configured to read data stored in the first RAM 1011 and the second RAM 1012;
  • the second read The output port 101j is connected to the third RAM 1013 and the fourth RAM 1014, respectively, and configured to read data stored in the third RAM 1013 and the fourth RAM 1014;
  • the first write port 101p and the The first RAM 1011 is connected to the third RAM 1013 and configured to write data to the first RAM 1011 and the third RAM 1013;
  • the second write port 101q is associated with the second RAM 1012 and the fourth RAM 1014, respectively. Connected, configured to write data to the second RAM 1012 and the fourth RAM 1014.
  • the ports 101q are connected to each other such that the first RAM 1011, the second RAM 1012, the third RAM 1013, and the fourth RAM 1014 constitute a single-bit memory structure 101 having two read ports and two writes.
  • the port and only corresponds to a set of address space, equivalent to two-bit two-write single-bit memory.
  • four RAMs are used to form a single-bit memory structure, so that the single-bit memory structure has two read ports and two write ports, so that the single-bit memory structure can be read twice at the same time.
  • the two write operations improve the access bandwidth of the single-bit storage structure, thereby improving the data storage capacity of the storage unit, satisfying the control requirements of the processing system, and expanding the application of the processing system.
  • the storage unit further includes a first logical operation subunit 102 and a second logic.
  • the second logical operation subunit 103 is configured to And when the first data is different from the XOR value, the second data is inverted by the first write port 101p and then written into the first RAM 1011 and the third RAM 1012, respectively.
  • the correspondence between the first read port 101i, the second read port 101j, the first write port 101p, and the second write port 101q may be set according to a specific situation.
  • the first read port 101i corresponds to the first write port 101p
  • the second read port 101j corresponds to the second write port 101q, that is, when writing data through the first write port 101p, it is first necessary to pass the first A read port 101i reads data, and when data is written through the second write port 101q, it is first necessary to read data through the second read port 101j.
  • the address space of the single-bit storage structure 101 includes a plurality of addresses, each of the addresses can store different data, that is, the first data can be written to any one of the addresses of the single-bit storage structure 101 through the first write port 101p.
  • the RAM is a single bit memory
  • the data stored in each RAM is 0 or 1
  • the first data is also 0 or 1.
  • the second logical operation sub-unit 103 may invert the second data 0 stored in the first RAM 1011 and write the first through the first write port 101p.
  • the RAM 1011 and the third RAM 1013 are 1 after the second data 0 is inverted, that is, the second logical operation sub-unit writes 1 to the first RAM 1011 and the third RAM 1013, respectively.
  • the second data stored in the first RAM 1011 becomes 1, and the data in the second RAM 1012 is still 1, and the XOR value of the second data and the third data is 0, which is the same as the first data.
  • the XOR value of the second data and the third data is 1, and the XOR value is the same as the first data, that is, the data currently read from the first read port is the same as the first data, so the current data may not be performed at this time.
  • Write operation is
  • the storage unit 10 may include two single-bit storage structures, respectively a first single-bit storage structure 101A and a second single-bit storage structure 101B; wherein the first The first write port of the single bit storage structure 101A is connected to the first write port of the second single bit storage structure 101B to constitute the first input port 10p of the storage unit 10; the first single bit storage structure 101A The second write port is connected to the second write port of the second single-bit storage structure to form a second input port 10q of the storage unit 10; the first read port of the second single-bit storage structure 101B The first output port 10i of the storage unit 10; the second read port of the second single-bit storage structure 101B is the second output port 10j of the storage unit.
  • the storage unit further includes a third logical operation subunit 104 and a fourth logical operation subunit 105; the third logical operation subunit 104 and the first single bit storage structure 101A a first read port 101iA connected, the fourth logical operation subunit 105 is connected to the first input port 10p; the third logical operation subunit 104 is configured to pass through the first input port 10p
  • the first read port 101iA of the first single-bit memory structure 101A reads the fifth data stored in the first RAM 1011A of the first single-bit memory structure 101A and the sixth data stored in the second RAM 1012A, respectively, and then acquires An XOR value of the fifth data and the sixth data; the fourth logical operation subunit 105 is configured to pass the first input port when the fourth data is different from the XOR value 10p inverts the fifth data into the first RAM 1011A and the third RAM 1013A of the first single-bit memory structure 101A, and the first RAM 1011B
  • the fifth data stored in the first RAM 1011A of the first single-bit storage structure 101A is 0, and the second RAM 1012A is stored in the sixth. If the data is 0, the XOR value of the fifth data and the sixth data acquired by the third logical operation sub-unit 104 is 0, which is different from the fourth data, and the fourth logical operation sub-unit 105 can pass the time.
  • the first input port 10p inverts the fifth data 0 and writes the first RAM 1011A and the third RAM 1013A of the first single-bit memory structure 101A, and the first RAM 1011B and the third RAM 1013B of the second single-bit memory structure 101B, After the fifth data is inverted, the fourth logical operation sub-unit 105 writes 1 to the first RAM 1011A and the third RAM 1013A of the first single-bit memory structure 101A, and the first RAM 1011B of the second single-bit memory structure 101B.
  • the third RAM 1013B is the third RAM 1013B.
  • the fifth data in the first RAM 1011A of the first single-bit storage structure 101A is 1, and the sixth data is still 0, and the XOR value of the fifth data and the sixth data is 1, which is the same as the fourth data.
  • the first single-bit storage structure 101A The fifth data stored in the first RAM 1011A is 1, the sixth data stored in the second RAM 1012A is 0, and the XOR value of the fifth data and the sixth data acquired by the third logical operation sub-unit 104 is 1, and the fourth data The same, you can not write at this time.
  • the first single bit storage is assumed.
  • the data stored in the third RAM 1013A of the structure 101A is 0, and the data stored in the fourth RAM 1014A is 0, and the exclusive value of the data stored in the third RAM 1013A and the data stored in the fourth RAM 1014A is 0, which is currently required.
  • the written data is different, and then the data 0 stored in the fourth RAM 1013A can be inverted and written into the second RAM 1012A and the fourth RAM 1014A of the first single-bit memory structure 101A, and the second RAM 1012B of the second single-bit memory structure 101B.
  • the fourth RAM 1014B since data 0 is inverted, it is 1, that is, 1 is written into the second RAM 1012A and the fourth RAM 1014A of the first single-bit memory structure 101A, and the second RAM 1012B and the fourth RAM 1014B of the second single-bit memory structure 101B. .
  • the data in the fourth RAM 1014A of the first single-bit memory structure 101A is 1, and the data stored in the third RAM 1013A is still 0, and the XOR value of the two data is 1, which is the same as the data currently required to be written.
  • the storage unit 10 may further include other logical sub-units configured to perform the above specific operations, and the specific processes and the operations of the third logical operation sub-unit 104 and the fourth logical operation sub-unit 105 described in the foregoing embodiments. The process is similar, and the embodiments of the present invention are not described herein.
  • the data of the first RAM 1011A and the third RAM 1013A written in the first single-bit memory structure 101A in the memory unit 10 are the same as the first RAM 1011B and the third RAM 1013B written in the second single-bit memory structure 101B, and are written.
  • the data of the second RAM 1012A and the fourth RAM 1014A of the first single-bit memory structure 101A are the same as the second RAM 1012B and the fourth RAM 1014B written in the second single-bit memory structure 101B, and thus the number read from the first output port 10i and the number
  • the number read by the first read port 101iA of a single bit memory structure 101A is the same, the number read from the second output port 10j and the second readout of the first single bit memory structure 101A
  • the number read by port 101jA is the same. Therefore, the data stored in the storage unit 10 can be read through the first output port 10i and the second output port 10j, and the write operation is not required after the read operation is completed, and is written through the first input port 10p and the second input port 10q.
  • the memory unit 10 of this type has no order limitation of reading and writing, and can satisfy various single-bit storage read/write applications. Scenes.
  • the storage unit 10 further includes at least one flag bit memory, each flag bit memory corresponding to a single bit storage structure, the flag bit memory being configured to be stored separately from the first RAM, the first A flag corresponding to the second RAM, the third RAM, and the fourth RAM.
  • the flag bit memory may preset two flag bits, respectively a first flag bit, a second flag bit, a third flag bit, and a fourth flag bit, respectively, in the first RAM, the second RAM, the first The third RAM corresponds to the fourth RAM. For example, when the first flag bit is 1, it indicates that the data of the first RAM should be read, and at this time, the first read of the single bit storage structure corresponding to the flag bit memory can be passed.
  • the out port reads the data stored in the first RAM of the single bit storage structure.
  • the corresponding flag bit memory may be read first, it is determined that the new data is stored in the specific location of the single-bit storage structure, and then the information in the position is read as a single-bit storage. Structure stored data.
  • the storage unit 10 includes a single-bit storage structure, which is a third single-bit storage structure 101C, and a flag bit memory corresponding to the third single-bit storage structure 101C.
  • a four-bit memory structure 101D the flag bit memory configured to indicate the first readout of the third single-bit memory structure 101C by data read by the first read port 101iD of the fourth single-bit memory structure 101D
  • Port 101iC reads out data stored in first RAM 1011C of said third single-bit memory structure 101C or second RAM 1012C of said third single-bit memory structure 101C; also configured to pass through said fourth single-bit memory structure 101D
  • Data read by the second read port 101jD indicating the second of the third single bit storage structure 101C
  • the read port 101jC reads out the data stored in the third RAM 1013C of the third single-bit memory structure 101C or the fourth RAM 1014C of the third single-bit memory structure 101C.
  • the port of the flag bit memory is not embodied, and the port external to the package has only the first read port 101iC of the third single-bit memory structure 101C, the second read port 101jC, the first write Port 101pC, the second write port 101qC, so that a two-bit two-write single-bit memory can be obtained.
  • the flag bit memory may be specifically configured to indicate a first readout of the third single bit memory structure 101C when the first read port 101iD of the fourth single bit memory structure 101D reads out the seventh data.
  • the port 101iC reads out the data stored in the first RAM 1011C; when the first read port 101iD of the fourth single-bit memory structure 101D reads out the tenth data, the first read port 101iC indicating the third single-bit memory structure 101C
  • the data stored in the second RAM 1012C is read. Assuming that new data is written into the first RAM 1011C of the third single-bit memory structure 101C through the first write port 101pC of the third single-bit memory structure 101C, the processor reads the newly stored data in the memory unit 10 next time.
  • the fourth single-bit memory structure 101D When the fourth single-bit memory structure 101D is required to indicate that the flag bit of the first RAM 1011C is valid, that is, the first RAM 1011C indicating the new data storage, so that the processor cannot distinguish the storage location of the new data, resulting in reading the third single bit.
  • the old data stored in the other RAM of the storage structure 101C causes system disorder.
  • the storage unit 10 further includes a fifth logical operation subunit 106 and a sixth logical operation subunit 107; the fifth logical operation subunit 106 and the fourth single bit storage structure a first read port 101iD of 101D is connected, the sixth logical operation subunit 107 is connected to a first write port 101pD of the fourth single bit storage structure 101D; and the fifth logical operation subunit 106 is configured to After writing new data to the first RAM 1011C of the third single-bit memory structure 101C through the first write port 101pC of the third single-bit memory structure 101C, passing through the first of the fourth single-bit memory structure 101D The read port 101iD reads the eighth data and the first stored in the first RAM 1011D of the fourth single-bit memory structure 101D, respectively.
  • the sixth logical operation subunit 107 is configured to when the exclusive OR value and the seventh
  • the eighth data is inverted by the first write port 101pD of the fourth single-bit storage structure 101D, and then written into the first RAM 1011D and the third RAM 1013D of the fourth single-bit storage structure 101D.
  • the fifth logic operation sub-unit 106 may pass the fourth single bit.
  • the first read port 101iD of the memory structure 101D reads the eighth data stored in the first RAM 1011D of the fourth single-bit memory structure 101D, the data is 0, and the ninth data stored in the second RAM 1012D is 1, At this time, the XOR value of the eighth data and the ninth data may be obtained, and the XOR value is not the same as the seventh data 0, indicating that the flag bit memory does not indicate that the new data is stored in the third single bit.
  • the storage unit 101C is in the first RAM 1011C, so the sixth logical operation sub-unit 107 can invert the eighth data and write the fourth through the first write port 101pD of the fourth single-bit storage structure 101D.
  • the first RAM 1011D and the third RAM 1013D of the single-bit memory structure 101D are 1 after the eighth data is inverted, that is, the sixth logic operation sub-unit 107 writes 1 to the first RAM 1011D and the third RAM 1013D, at this time in the first RAM 1011D.
  • the stored data is 1
  • the data stored in the second RAM 1012D is still 1, so the XOR value of the two data is 0, indicating that the new data is stored in the first RAM 1011C of the third single-bit memory structure 101C, that is, the third single-bit memory structure 101C.
  • the first read port 101iC reads out the data stored in the first RAM 1011C.
  • the second read port 101jD of the fourth single bit memory structure 101D When 0 is output, the second read port 101jC indicating the third single bit memory structure 101C reads out the data stored in the third RAM 1013C; when the second read port 101jD of the fourth single bit memory structure 101D reads 1 out, The second read port 101jC indicating the third single bit memory structure 101C reads out the data stored in the fourth RAM 1014C.
  • the second readout through the fourth single-bit memory structure 101D The data stored in the third RAM 1013D of the fourth single-bit memory structure 101D read by the port 101jD is 0, and the data stored in the fourth RAM 1014D is 1, and the XOR value of the two data is 1, indicating that the flag bit memory has now indicated that new data is stored in the fourth RAM 1014C, and the data of the flag bit memory may not be changed.
  • the storage unit 10 may further include other logic sub-units for performing the above specific operations, and the specific processes and the operations of the fifth logical operation sub-unit 106 and the sixth logical operation sub-unit 107 described in the foregoing embodiments. The process is similar, and the embodiments of the present invention are not described herein.
  • the analysis process of the data that does not need to change the flag bit memory is the same as the process of the data that does not need to change the flag bit memory; after the fourth RAM 1014C stores the new data, it needs to be changed.
  • the process of analyzing the data of the flag bit memory is the same as the process of changing the data of the flag bit memory in the first RAM 1011C as described above, and the present invention will not be described herein.
  • the storage unit 10 includes a single-bit storage structure, which is a fifth single-bit storage structure 101E, and a flag bit memory corresponding to the fifth single-bit storage structure 101E includes two
  • the single-bit storage structures are a sixth single-bit storage structure 101F and a seventh single-bit storage structure 101G, respectively.
  • the first write port of the sixth single-bit storage structure 101F and the first write port of the seventh single-bit storage structure 101G are connected to form a first write total port 1002p of the flag bit memory;
  • the second write port of the sixth single bit storage structure 101F is connected to the second write port of the seventh single bit storage structure 101G a second write total port 1002q constituting the flag bit memory;
  • a first read port of the seventh single bit memory structure 101G is a first read total port 1002i of the flag bit memory;
  • the second read port of the single bit memory structure 101G is the second read total port 1002j of the flag bit memory;
  • the flag bit memory is specifically configured to read data through the first read total port 1002i,
  • the first read port 101iE indicating the fifth single bit storage structure 101E reads out data stored in the first RAM 1011E of the fifth single bit storage structure 101E or the second RAM 1012E of the fifth single bit storage structure 101E;
  • the flag bit memory is further configured to, by the data read by the second read
  • the port of the flag bit memory is not embodied, and the port external to the package has only the first read port 101iE of the fifth single-bit memory structure 101E, the second read port 101jE, the first write Port 101pE, the second write port 101qE, so that a two-bit two-write single-bit memory can be obtained.
  • the first read port 101iE of the fifth single-bit storage structure 101E is instructed to read the fifth single.
  • the data of the first RAM 1011E in the bit storage structure 101E when the data read by the first read total port 1002i of the flag memory is 1, indicates the first read port of the fifth single bit storage structure 101E.
  • the 101iE reads out the data of the second RAM 1012E in the fifth single-bit memory structure 101E.
  • the first write port 101pE of the fifth single-bit memory structure 101E writes new data to the first RAM 1011E in the fifth single-bit memory structure 101E
  • the first read through the sixth single-bit memory structure 101F The output port 101iF reads the data stored in the first RAM 1011F of the sixth single-bit storage structure 101F and the data stored in the second RAM 1012F, respectively, and takes an exclusive-OR value output of the two data; if the exclusive-OR value is not 0 , indicating that the new data is not stored in the fifth single-bit storage structure 101E at this time.
  • the data of the flag bit memory needs to be changed.
  • the data stored in the first RAM 1011F can be inverted by the first write total port 1002p of the flag bit memory, and then written into the sixth single-bit storage.
  • the read port 101iF reads the data stored in the first RAM 1011F of the sixth single-bit memory structure 101F, the data is 0, and the data stored in the second RAM 1012D, the data is 1, and then the XOR value of the two data is acquired.
  • the exclusive OR value is not the same as 0, indicating that the flag bit memory does not indicate that new data is stored in the first RAM 1011E in the fifth single bit memory structure 101E, and the first write through the flag bit memory can be
  • the total port 1002p inverts the data stored in the first RAM 1011F of the sixth single-bit memory structure 101F, and writes the first RAM 1011F and the third RAM 1013F of the sixth single-bit memory structure 101F, and the seventh single-bit memory structure 101G.
  • the first RAM 1011G and the third RAM 1013G which are inverted by 0, are 1 written into the first RAM 1011F and the third RAM 1013F of the sixth single-bit memory structure 101F, and the first RAM of the seventh single-bit memory structure 101G.
  • the memory data in the first RAM 1011F of the sixth single-bit memory structure 101F is 1, and the data stored in the second RAM 1012F of the sixth single-bit memory structure 101F is still 1, so two data.
  • the XOR value is 0. Since the sixth single bit storage structure 101F and the seventh single bit storage structure 101G share the first write total port 1002p and the second write total port 1002q, the sixth single bit storage structure 101F and the seventh single bit storage structure 101G The same number is stored in each RAM, and therefore, the data read from the first read total port 1002i of the flag bit memory is 0, indicating that new data is stored in the fifth single bit storage structure 101E.
  • the first read port 101iE of the fifth single-bit memory structure 101E reads data stored in the first RAM 1011E when data is read. Since the data is not read when the data is read from the first read total port 1002i or the second read total port 1002j of the flag bit memory, when the data of the memory unit 10 is read, the first readout can be performed.
  • the total port 1002i or the second readout total port 1002j determines the flag bit information; and after storing the new data to the storage unit 10, since the data of the RAM in the flag bit memory may be changed, the sixth single bit storage structure 101F may be The first read port 101iF or the second read port 101jF reads the data of the RAM in the sixth single-bit memory structure 101F, and when the data in the flag bit memory needs to be changed, is changed by a write operation, so that The access bandwidth of the flag bit memory is improved, and the read/write operation sequence of the flag bit memory is not limited, and the applicable range is wide.
  • the foregoing operations may be performed by using the logical sub-units included in the storage unit. For the specific process, reference may be made to the specific description in the foregoing embodiments, and details are not described herein.
  • the third RAM 1013F and the fourth RAM 1014F may be first read through the second read port 101jF of the sixth single-bit memory structure 101F.
  • the specific method is the same as the above method, and the above may be referred to The method operates, and the embodiments of the present invention are not described herein.
  • the storage unit 10 may set other logical sub-units according to specific situations.
  • other logical sub-units may acquire the sum of the data stored by the first RAM 1011 and the data stored by the second RAM 1012 through the first read port 101i. Value, or can also obtain the product of the data stored in the first RAM 1011 and the data stored in the second RAM 1012;
  • the sum of the data stored in the third RAM 1013 and the data stored in the fourth RAM 1014 is obtained by the second read port 101j, or the product of the data stored in the third RAM 1013 and the data stored in the fourth RAM 1014 may be acquired, which is in the embodiment of the present invention. This is not limited.
  • Embodiments of the present invention provide a storage unit, which can adopt four RAMs to form a single-bit storage structure, such that the single-bit storage structure has two read ports and two write ports, so that the single bit can be simultaneously
  • the storage structure performs two read operations and two write operations, thereby improving the access bandwidth of the single-bit storage structure, thereby improving the data storage capacity of the storage unit composed of the single-bit storage structure, satisfying the control requirements of the processing system, and expanding.
  • the application of the processing system is a storage unit, which can adopt four RAMs to form a single-bit storage structure, such that the single-bit storage structure has two read ports and two write ports, so that the single bit can be simultaneously
  • the storage structure performs two read operations and two write operations, thereby improving the access bandwidth of the single-bit storage structure, thereby improving the data storage capacity of the storage unit composed of the single-bit storage structure, satisfying the control requirements of the processing system, and expanding.
  • An embodiment of the present invention provides a processing system, including the foregoing storage unit 10 of any of the above embodiments. Since the storage unit 10 is used as the storage unit of the processing unit, the access bandwidth of the storage device is increased, thereby increasing the data storage capacity of the processing system, so that the processing system can meet the control requirements of the large-scale automation device.
  • four RAMs are used to form a single bit storage structure, so that the single-bit storage structure has two read ports and two write ports, so that the single-bit storage structure can be simultaneously performed.
  • the two read operations and the two write operations improve the access bandwidth of the single-bit storage structure, thereby improving the data storage capacity of the storage unit including the single-bit storage structure, satisfying the control requirements of the processing system, and expanding the processing system. should.

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Abstract

一种存储单元及处理系统，所述存储单元包括至少一个单比特存储结构（101）；每个单比特存储结构（101）包括四个随机存取存储器RAM，分别为第一RAM（1011）、第二RAM（1012）、第三RAM（1013）和第四RAM（1014）；两个读出端口分别为第一读出端口（101i）和第二读出端口（101j）；两个写入端口，分别为第一写入端口（101p）和第二写入端口（101q）；其中，第一读出端口（101i）分别与第一RAM（1011）和第二RAM（1012）连接，配置为读取第一RAM（1011）和第二RAM（1012）中存储的数据；第二读出端口（101j）分别与第三RAM（1013）和第四RAM（1014）连接，配置为读取第三RAM（1013）和第四RAM（1014）中存储的数据；第一写入端口（101p）分别与第一RAM（1011）和第三RAM（1013）连接，配置为向第一RAM（1011）和第三RAM（1013）写入数据；第二写入端口（101q）分别与第二RAM（1012）和第四RAM（1014）连接，配置为向第二RAM（1012）和第四RAM（1014）写入数据。

Description

一种存储单元和处理系统 技术领域
本发明涉及硬件领域的存储器技术，尤其涉及一种存储单元和处理系统。
背景技术
随着电子技术的发展，自动化的应用越来越广泛，通常自动化的实现离不开处理系统，所述处理系统通常由处理器，存储器(Memory)，仪器仪表以及人机交互接口等构成。
现有技术中，为了减少人力资本，自动化设备越来越大型化，而对大型自动化设备的控制涉及海量数据的存储和读取，因此为了满足处理系统控制需求，必须提高处理系统中Memory的数据存储容量。实际应用中通常可以通过提高Memory的访问带宽提高数据存储容量，常用的方法是倍频，即通过提高单位时间内对Memory的访问次数来提高数据访问带宽，假设原来单位时间内可以存储N次数据，倍频之后单位时间内可以存储2N或3N次数据，因此可以提高Memory的数据存储容量，但是由于单位时间可以提高的访问次数有限，使得通过倍频方法能够提高的数据存储容量也有限，很多情况下无法满足处理系统的控制需求，限制了处理系统的应用。
发明内容
为解决上述技术问题，本发明实施例期望提供一种存储单元和处理系统，能够提高数据存储容量，满足处理系统的控制需求，扩展了处理系统的应用。
本发明的技术方案是这样实现的：
第一方面，本发明实施例提供一种存储单元，所述存储单元包括至少一个单比特存储结构；
每个所述单比特存储结构包括四个随机存取存储器RAM，分别为第一RAM、第二RAM、第三RAM和第四RAM；两个读出端口分别为第一读出端口和第二读出端口；两个写入端口分别为第一写入端口和第二写入端口；
其中，所述第一读出端口分别与所述第一RAM和所述第二RAM连接，配置为读取所述第一RAM和所述第二RAM中存储的数据；
所述第二读出端口分别与所述第三RAM和所述第四RAM连接，配置为读取所述第三RAM和所述第四RAM中存储的数据；
所述第一写入端口分别与所述第一RAM和所述第三RAM连接，配置为向所述第一RAM和所述第三RAM写入数据；
所述第二写入端口分别与所述第二RAM和所述第四RAM连接，配置为向所述第二RAM和所述第四RAM写入数据。
上述方案中，所述存储单元还包括第一逻辑运算子单元和第二逻辑运算子单元；所述第一逻辑运算子单元与所述第一读出端口连接，所述第二逻辑运算子单元与所述第一写入端口连接；
所述第一逻辑运算子单元配置为，在通过所述第一写入端口向所述单比特存储结构写入第一数据时，通过所述第一读出端口分别读取所述第一RAM中存储的第二数据和所述第二RAM中存储的第三数据，然后获取所述第二数据与所述第三数据的异或值；
所述第二逻辑运算子单元配置为，当所述第一数据与所述异或值不同时，通过所述第一写入端口将所述第二数据取反后分别写入所述第一RAM和所述第三RAM。
上述方案中，所述存储单元包括两个单比特存储结构，分别为第一单 比特存储结构和第二单比特存储结构；
其中，所述第一单比特存储结构的第一写入端口与所述第二单比特存储结构的第一写入端口连接组成所述存储单元的第一输入端口；
所述第一单比特存储结构的第二写入端口与所述第二单比特存储结构的第二写入端口连接组成所述存储单元的第二输入端口；
所述第二单比特存储结构的第一读出端口为所述存储单元的第一输出端口；
所述第二单比特存储结构的第二读出端口为所述存储单元的第二输出端口。
上述方案中，所述存储单元还包括第三逻辑运算子单元和第四逻辑运算子单元；所述第三逻辑运算子单元与所述第一单比特存储结构的第一读出端口连接，所述第四逻辑运算子单元与所述第一输入端口连接；
所述第三逻辑运算子单元配置为，在通过所述第一输入端口向所述存储单元写入第四数据时，通过所述第一单比特存储结构的第一读出端口分别读取所述第一单比特存储结构的第一RAM中存储的第五数据和第二RAM中存储的第六数据，然后获取所述第五数据与所述第六数据的异或值；
所述第四逻辑运算子单元配置为，当所述第四数据与所述异或值不同时，通过所述第一输入端口将所述第五数据取反后分别写入所述第一单比特存储结构的第一RAM和第三RAM，以及第二单比特存储结构的第一RAM和第三RAM。
上述方案中，所述存储单元还包括至少一个标志位存储器，每个标志位存储器对应一个单比特存储结构，所述标志位存储器配置为存储对应的单比特存储结构的第一RAM、第二RAM、第三RAM和第四RAM的标志位。
上述方案中，所述存储单元包括一个单比特存储结构，为第三单比特存储结构，与所述第三单比特存储结构对应的标志位存储器为第四单比特存储结构；
所述标志位存储器配置为，通过所述第四单比特存储结构的第一读出端口读出的数据，指示第三单比特存储结构的第一读出端口读出所述第三单比特存储结构的第一RAM或所述第三单比特存储结构的第二RAM中存储的数据；
通过所述第四单比特存储结构的第二读出端口读出的数据，指示第三单比特存储结构的第二读出端口读出所述第三单比特存储结构的第三RAM或所述第三单比特存储结构的第四RAM中存储的数据。
上述方案中，所述标志位存储器具体配置为，当所述第四单比特存储结构的第一读出端口读出第七数据时，指示第三单比特存储结构的第一读出端口读出第一RAM存储的数据；
所述存储单元还包括第五逻辑运算子单元和第六逻辑运算子单元；所述第五逻辑运算子单元与所述第四单比特存储结构的第一读出端口连接，所述第六逻辑运算子单元与所述第四单比特存储结构的第一写入端口连接；
所述第五逻辑运算子单元配置为，在通过所述第三单比特存储结构的第一写入端口向所述第三单比特存储结构的第一RAM写入新的数据后，通过第四单比特存储结构的第一读出端口分别读取第四单比特存储结构的第一RAM中存储的第八数据和第二RAM中存储的第九数据，然后获取所述第八数据与所述第九数据的异或值；
所述第六逻辑运算子单元配置为，当所述异或值与所述第七数据不相同时，通过所述第四单比特存储结构的第一写入端口将所述第八数据取反后写入所述第四单比特存储结构的第一RAM和第三RAM。
上述方案中，所述存储单元包括一个单比特存储结构，为第五单比特存储结构，与所述第五单比特存储结构对应的标志位存储器包括两个单比特存储结构，分别为第六单比特存储结构和第七单比特存储结构；
其中，所述第六单比特存储结构的第一写入端口与所述第七单比特存储结构的第一写入端口连接组成所述标志位存储器的第一写入总端口；
所述第六单比特存储结构的第二写入端口与所述第七单比特存储结构的第二写入端口连接组成所述标志位存储器的第二写入总端口；
所述第七单比特存储结构的第一读出端口为所述标志位存储器的第一读出总端口；
所述第七单比特存储结构的第二读出端口为所述标志位存储器的第二读出总端口；
所述标志位存储器具体配置为，通过所述第一读出总端口读出的数据，指示所述第五单比特存储结构的第一读出端口读出所述第五单比特存储结构中第一RAM或所述第五单比特存储结构中第二RAM中存储的数据；
通过所述第二读出总端口读出的数据，指示所述第五单比特存储结构的第二读出端口读出所述第五单比特存储结构的第三RAM或所述第五单比特存储结构的第四RAM中存储的数据。
第二方面，本发明实施例提供一种处理系统，包括上述任意一种存储单元。
本发明实施例提供了一种存储单元和处理系统，包括至少一个单比特存储结构；每个所述单比特存储结构包括四个随机存取存储器RAM，分别为第一RAM、第二RAM、第三RAM和第四RAM；两个读出端口分别为第一读出端口和第二读出端口；两个写入端口，分别为第一写入端口和第二写入端口；其中，所述第一读出端口分别与所述第一RAM和所述第二RAM连接，配置为读取所述第一RAM和所述第二RAM中存储的数据； 所述第二读出端口分别与所述第三RAM和所述第四RAM连接，配置为读取所述第三RAM和所述第四RAM中存储的数据；所述第一写入端口分别与所述第一RAM和所述第三RAM连接，配置为向所述第一RAM和所述第三RAM写入数据；所述第二写入端口分别与所述第二RAM和所述第四RAM连接，配置为向所述第二RAM和所述第四RAM写入数据。相较于现有技术，采用四个RAM组成一个单比特(bit)存储结构，使得该单比特存储结构具有两个读出端口和两个写入端口，因此可以同时对所述单比特存储结构进行两次读操作和两次写操作，提高了该单比特存储结构的访问带宽，进而提高了包括该单比特存储结构的存储单元的数据存储容量，满足处理系统的控制需求，扩展了处理系统的应用。
附图说明
图1为本发明实施例提供的第一种存储单元的结构示意图；
图2为本发明实施例提供的第二种存储单元的结构示意图；
图3为本发明实施例提供的第三种存储单元的结构示意图；
图4为本发明实施例提供的第四种存储单元的结构示意图；
图5为本发明实施例提供的第五种存储单元的结构示意图；
图6为本发明实施例提供的第六种存储单元的结构示意图；
图7为本发明实施例提供的第七种存储单元的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例提供一种存储单元，所述存储单元包括至少一个单比特存储结构101，如图1所示。
每个所述单比特存储结构101包括四个随机存取存储器 (Random-Access Memory，RAM)，分别为第一RAM1011、第二RAM1012、第三RAM1013和第四RAM1014；两个读出端口，分别为第一读出端口101i和第二读出端口101j；两个写入端口，分别为第一写入端口101p和第二写入端口101q。
其中，所述第一读出端口101i分别与所述第一RAM1011和所述第二RAM1012连接，配置为读取所述第一RAM1011和所述第二RAM1012中存储的数据；所述第二读出端口101j分别与所述第三RAM1013和所述第四RAM1014连接，配置为读取所述第三RAM1013和所述第四RAM1014中存储的数据；所述第一写入端口101p分别与所述第一RAM1011和所述第三RAM1013连接，配置为向所述第一RAM1011和所述第三RAM1013写入数据；所述第二写入端口101q分别与所述第二RAM1012和所述第四RAM1014连接，配置为向所述第二RAM1012和所述第四RAM1014写入数据。
由于第一RAM1011、第二RAM1012、第三RAM1013和第四RAM1014并非是完全独立的，而是通过第一读出端口101i、第二读出端口101j、第一写入端口101p和第二写入端口101q相互连接，这样可以使得所述第一RAM1011、第二RAM1012、第三RAM1013和第四RAM1014组成一个单比特存储结构101，该单比特存储结构101具有两个读出端口，两个写入端口，且仅对应一套地址空间，相当于两读两写的单比特存储器。
这样一来，采用四个RAM组成一个单比特存储结构，使得该单比特存储结构具有两个读出端口和两个写入端口，因此可以同时对所述单比特存储结构进行两次读操作和两次写操作，提高了该单比特存储结构的访问带宽，进而提高了存储单元的数据存储容量，满足处理系统的控制需求，扩展了处理系统的应用。
如图2所示，所述存储单元还包括第一逻辑运算子单元102和第二逻 辑运算子单元103；所述第一逻辑运算子单元102与所述第一读出端口101i连接，所述第二逻辑运算子单元103与所述第一写入端口101p连接；所述第一逻辑运算子单元102配置为，在通过所述第一写入端口101p向所述单比特存储结构101写入第一数据时，可以首先通过所述第一读出端口101i分别读取所述第一RAM1011中存储的第二数据和所述第二RAM1012中存储的第三数据，然后获取所述第二数据与所述第三数据的异或值；所述第二逻辑运算子单元103配置为，当所述第一数据与所述异或值不同时，通过所述第一写入端口101p将所述第二数据取反后分别写入所述第一RAM1011和所述第三RAM1012。
示例地，现有技术在使用单比特存储器时通常会遇到如下情况，即对单比特存储器的读操作和写操作成对出现，即有读必有写，且读在前，写在后，读写操作之间存在一定的时间间隔。所以在实际应用中，可以首先根据具体情况设定第一读出端口101i、第二读出端口101j、第一写入端口101p和第二写入端口101q之间的对应关系，本发明实施例中假设第一读出端口101i与第一写入端口101p对应，第二读出端口101j与第二写入端口101q对应，即在通过第一写入端口101p写入数据时，首先需要通过第一读出端口101i读取数据，在通过第二写入端口101q写入数据时，首先需要通过第二读出端口101j读取数据。并且，由于单比特存储结构101的地址空间中包括多个地址，每个地址可以存储不同的数据，即可以通过第一写入端口101p向单比特存储结构101的任意一个地址写入第一数据。同时由于RAM为单比特存储器，因此每个RAM中存储的数据为0或1，第一数据也为0或1。
示例地，假设第一数据为0，第一读出端口101i读取的第一RAM1011中存储的第二数据为0，第二RAM1012中存储的第三数据为1，第二数据与第三数据的异或值为1，即第一逻辑运算子单元102获取的异或值为1， 由于需要写入的第一数据与该异或值不同，因此所述第二逻辑运算子单元103可以将第一RAM1011存储的第二数据0取反后通过第一写入端口101p写入第一RAM1011和第三RAM1013，由于第二数据0取反后为1，即所述第二逻辑运算子单元将1分别写入第一RAM1011和第三RAM1013。这样一来，第一RAM1011中存储的第二数据变为1，而第二RAM1012中的数据仍然为1，此时第二数据与第三数据的异或值为0，与第一数据相同，表示已经通过第一写入端口101p将第一数据写入存储单元10；假设第一数据为1，第一RAM1011中存储的第二数据为0，第二RAM1012中存储的第三数据为1，第二数据与第三数据的异或值为1，此时该异或值与第一数据相同，即当前从第一读出端口读出的数据与第一数据相同，所以此时可以不进行写操作。
作为一种实施方式，如图3所示，所述存储单元10可以包括两个单比特存储结构，分别为第一单比特存储结构101A和第二单比特存储结构101B；其中，所述第一单比特存储结构101A的第一写入端口与所述第二单比特存储结构101B的第一写入端口连接组成所述存储单元10的第一输入端口10p；所述第一单比特存储结构101A的第二写入端口与所述第二单比特存储结构的第二写入端口连接组成所述存储单元10的第二输入端口10q；所述第二单比特存储结构101B的第一读出端口为所述存储单元10的第一输出端口10i；所述第二单比特存储结构101B的第二读出端口为所述存储单元的第二输出端口10j。
示例地，如图4所示，所述存储单元还包括第三逻辑运算子单元104和第四逻辑运算子单元105；所述第三逻辑运算子单元104与所述第一单比特存储结构101A的第一读出端口101iA连接，所述第四逻辑运算子单元105与所述第一输入端口10p连接；所述第三逻辑运算子单元104配置为，在通过所述第一输入端口10p向所述存储单元10写入第四数据时，通过所 述第一单比特存储结构101A的第一读出端口101iA分别读取所述第一单比特存储结构101A的第一RAM1011A中存储的第五数据和第二RAM1012A中存储的第六数据，然后获取所述第五数据与所述第六数据的异或值；所述第四逻辑运算子单元105配置为，当所述第四数据与所述异或值不同时，通过所述第一输入端口10p将所述第五数据取反后分别写入所述第一单比特存储结构101A的第一RAM1011A和第三RAM1013A，以及第二单比特存储结构101B的第一RAM1011B和第三RAM1013B。
假设当前需要通过所述第一输入端口10p向所述存储单元10写入第四数据1，第一单比特存储结构101A的第一RAM1011A存储的第五数据为0，第二RAM1012A存储的第六数据为0，则所述第三逻辑运算子单元104获取的第五数据与第六数据的异或值为0，与第四数据不相同，此时所述第四逻辑运算子单元105可以通过第一输入端口10p将第五数据0取反后将写入第一单比特存储结构101A的第一RAM1011A和第三RAM1013A，以及第二单比特存储结构101B的第一RAM1011B和第三RAM1013B，由于第五数据取反后为1，即第四逻辑运算子单元105将1写入第一单比特存储结构101A的第一RAM1011A和第三RAM1013A，以及第二单比特存储结构101B的第一RAM1011B和第三RAM1013B。此时，第一单比特存储结构101A的第一RAM1011A中的第五数据为1，而第六数据仍然为0，则第五数据与第六数据的异或值为1，与第四数据相同，表示已经通过第一输入端口10p将第四数据写入存储单元10；假设当前需要通过所述第一输入端口10p向所述存储单元10写入第四数据1，第一单比特存储结构101A的第一RAM1011A存储的第五数据为1，第二RAM1012A存储的第六数据为0，第三逻辑运算子单元104获取的第五数据与第六数据的异或值为1，与第四数据相同，此时可以不进行写操作。
同理，当通过第二输入端口10q写入数据1时，假设第一单比特存储 结构101A的第三RAM1013A存储的数据为0，第四RAM1014A存储的数据为0，则第三RAM1013A存储的数据与第四RAM1014A存储的数据的异或值，该异或值为0，与当前需要写入的数据不相同，然后可以将第四RAM1013A存储的数据0取反后写入第一单比特存储结构101A的第二RAM1012A和第四RAM1014A，以及第二单比特存储结构101B的第二RAM1012B和第四RAM1014B，由于数据0取反后为1，即将1写入第一单比特存储结构101A的第二RAM1012A和第四RAM1014A，以及第二单比特存储结构101B的第二RAM1012B和第四RAM1014B。此时，第一单比特存储结构101A的第四RAM1014A中的数据为1，而第三RAM1013A存储的数据仍然为0，则两个数据的异或值为1，与当前需要写入的数据相同，表示已经通过第二输入端口10p将数据写入存储单元10；假设当前需要通过所述第二输入端口10q向所述存储单元10写入第四数据1，第一单比特存储结构101A的第三RAM1013A存储的第五数据为1，第四RAM1014A存储的第六数据为0，两个数据的异或值为1，与需要存储的数据1相同，此时可以不进行写操作。需要说明的是，存储单元10还可以包括其他逻辑子单元，配置为完成上述具体操作，具体的过程与前述实施例中描述的第三逻辑运算子单元104和第四逻辑运算子单元105的工作过程类似，本发明实施例在此不做赘述。
由上述描述可知，存储单元10中写入第一单比特存储结构101A的第一RAM1011A和第三RAM1013A的数据与写入第二单比特存储结构101B的第一RAM1011B和第三RAM1013B相同，写入第一单比特存储结构101A的第二RAM1012A和第四RAM1014A的数据与写入第二单比特存储结构101B的第二RAM1012B和第四RAM1014B相同，因此从第一输出端口10i读出的数与第一单比特存储结构101A的第一读出端口101iA读出的数相同，从第二输出端口10j读出的数与第一单比特存储结构101A的第二读出 端口101jA读出的数相同。因此可以通过第一输出端口10i和第二输出端口10j读取存储单元10中存储的数据，并且读操作完成之后不要求必须进行写操作，在通过第一输入端口10p和第二输入端口10q写入数据时，也不需要首先通过第一输出端口10i或第二输出端口10j读取数据，因此该类型的存储单元10没有读写造作的顺序限制，可以满足各种单比特存储的读写应用场景。
作为一种实施方式，所述存储单元10还包括至少一个标志位存储器，每个标志位存储器对应一个单比特存储结构，所述标志位存储器配置为存储分别与所述第一RAM、所述第二RAM、所述第三RAM和所述第四RAM对应的标志位。示例地，标志位存储器可以预设两个标志位，分别第一标志位、第二标志位、第三标志位和第四标志位，分别于第一RAM、所述第二RAM、所述第三RAM和所述第四RAM对应，例如，当第一标志位为1时，表示应该读取第一RAM的数据，此时可以通过与该标志位存储器对应的单比特存储结构的第一读出端口读取该单比特存储结构的第一RAM存储的数据。在读取单比特存储结构存储的数据时，可以首先读取与其对应的标志位存储器，确定新的数据存储在该单比特存储结构的具体位置，然后在读取该位置的信息作为单比特存储结构存储的数据。
作为一种实施方式，如图5所示，所述存储单元10包括一个单比特存储结构，为第三单比特存储结构101C，与所述第三单比特存储结构101C对应的标志位存储器为第四单比特存储结构101D；所述标志位存储器配置为，通过所述第四单比特存储结构101D的第一读出端口101iD读出的数据，指示第三单比特存储结构101C的第一读出端口101iC读出所述第三单比特存储结构101C的第一RAM1011C或所述第三单比特存储结构101C的第二RAM1012C中存储的数据；还配置为通过所述第四单比特存储结构101D的第二读出端口101jD读出的数据，指示第三单比特存储结构101C的第二 读出端口101jC读出所述第三单比特存储结构101C的第三RAM1013C或所述第三单比特存储结构101C的第四RAM1014C中存储的数据。将存储单元10封装之后，不体现标志位存储器的端口，体现在封装体外部的端口仅有第三单比特存储结构101C的第一读出端口101iC，第二读出端口101jC，第一写入端口101pC，第二写入端口101qC，所以可以得到两读两写的单比特存储器。
示例地，所述标志位存储器可以具体配置为，当所述第四单比特存储结构101D的第一读出端口101iD读出第七数据时，表示第三单比特存储结构101C的第一读出端口101iC读出第一RAM1011C存储的数据；当所述第四单比特存储结构101D的第一读出端口101iD读出第十数据时，表示第三单比特存储结构101C的第一读出端口101iC读出第二RAM1012C存储的数据。假设通过第三单比特存储结构101C的第一写入端口101pC向第三单比特存储结构101C的第一RAM1011C中写入新的数据，则处理器下一次读取存储单元10中新存储的数据时，需要第四单比特存储结构101D指示第一RAM1011C的标志位有效，即指示新的数据存储的第一RAM1011C中，以免处理器无法分辨新数据的存储位置，导致读取到第三单比特存储结构101C其他RAM中存储的旧数据，引起系统紊乱。
具体的，如图6所示，所述存储单元10还包括第五逻辑运算子单元106和第六逻辑运算子单元107；所述第五逻辑运算子单元106与所述第四单比特存储结构101D的第一读出端口101iD连接，所述第六逻辑运算子单元107与所述第四单比特存储结构101D的第一写入端口101pD连接；所述第五逻辑运算子单元106配置为，在通过所述第三单比特存储结构101C的第一写入端口101pC向所述第三单比特存储结构101C的第一RAM1011C写入新的数据后，通过第四单比特存储结构101D的第一读出端口101iD分别读取第四单比特存储结构101D的第一RAM1011D中存储的第八数据和第 二RAM1012D中存储的第九数据，然后获取所述第八数据与所述第九数据的异或值；所述第六逻辑运算子单元107配置为，当所述异或值与所述第七数据不相同时，通过所述第四单比特存储结构101D的第一写入端口101pD将所述第八数据取反后写入所述第四单比特存储结构101D的第一RAM1011D和第三RAM1013D。假设当第四单比特存储结构101D的第一读出端口101iD读出0时，表示第三单比特存储结构101C的第一读出端口101iC读出第一RAM1011C存储的数据；当所述第四单比特存储结构101D的第一读出端口101iD读出1时，表示第三单比特存储结构101C的第一读出端口101iC读出第二RAM1012C存储的数据。在通过所述第三单比特存储结构101C的第一写入端口101pC向所述第三单比特存储结构101C的第一RAM1011C写入1后，第五逻辑运算子单元106可以通过第四单比特存储结构101D的第一读出端口101iD读取第四单比特存储结构101D的第一RAM1011D中存储的第八数据，该数据为0，第二RAM1012D中存储的第九数据，该数据为1，此时可以获取到第八数据与所述第九数据的异或值为1，该异或值与第七数据0并不相同，表示标志位存储器并没有指示新的数据存储在第三单比特存储结构101C的第一RAM1011C中，所以第六逻辑运算子单元107可以通过所述第四单比特存储结构101D的第一写入端口101pD将所述第八数据取反后写入所述第四单比特存储结构101D的第一RAM1011D和第三RAM1013D，由于第八数据取反后为1，即第六逻辑运算子单元107将1写入第一RAM1011D和第三RAM1013D，此时第一RAM1011D中的存数数据为1，而第二RAM1012D中存储的数据仍然为1，所以两个数据的异或值为0，表示新的数据存储在第三单比特存储结构101C第一RAM1011C中，即第三单比特存储结构101C的第一读出端口101iC读出第一RAM1011C存储的数据。
进一步的，假设当第四单比特存储结构101D的第二读出端口101jD读 出0时，表示第三单比特存储结构101C的第二读出端口101jC读出第三RAM1013C存储的数据；当所述第四单比特存储结构101D的第二读出端口101jD读出1时，表示第三单比特存储结构101C的第二读出端口101jC读出第四RAM1014C存储的数据。在通过所述第三单比特存储结构101C的第二写入端口101qC向所述第三单比特存储结构101C的第四RAM1014C写入1后，通过第四单比特存储结构101D的第二读出端口101jD读取到的第四单比特存储结构101D的第三RAM1013D中存储的数据，该数据为0，第四RAM1014D中存储的数据，该数据为1，此时两个数据的异或值为1，表示标志位存储器此时已经指示新的数据存储在第四RAM1014C中，可以不对标志位存储器的数据进行更改。需要说明的是，存储单元10还可以包括其他逻辑子单元，用于完成上述具体操作，具体的过程与前述实施例中描述的第五逻辑运算子单元106和第六逻辑运算子单元107的工作过程类似，本发明实施例在此不做赘述。
需要说明的是，在第一RAM1011C存储新数据后，不需要改变标志位存储器的数据的分析过程与上述不需要改变标志位存储器的数据的过程相同；在第四RAM1014C存储新数据后，需要改变标志位存储器的数据的分析过程与上述新数据存储在第一RAM1011C中改变标志位存储器的数据的过程相同，本发明在此不做赘述。
作为一种实施方式，如图7所示，所述存储单元10包括一个单比特存储结构，为第五单比特存储结构101E，与所述第五单比特存储结构101E对应的标志位存储器包括两个单比特存储结构，分别为第六单比特存储结构101F和第七单比特存储结构101G。其中，所述第六单比特存储结构101F的第一写入端口与所述第七单比特存储结构101G的第一写入端口连接组成所述标志位存储器的第一写入总端口1002p；所述第六单比特存储结构101F的第二写入端口与所述第七单比特存储结构101G的第二写入端口连 接组成所述标志位存储器的第二写入总端口1002q；所述第七单比特存储结构101G的第一读出端口为所述标志位存储器的第一读出总端口1002i；所述第七单比特存储结构101G的第二读出端口为所述标志位存储器的第二读出总端口1002j；所述标志位存储器具体配置为，通过所述第一读出总端口1002i读出的数据，指示所述第五单比特存储结构101E的第一读出端口101iE读出所述第五单比特存储结构101E中第一RAM1011E或所述第五单比特存储结构101E中第二RAM1012E存储的数据；所述标志位存储器还具体配置为，通过所述第二读出总端口1002j读出的数据，指示所述第五单比特存储结构的第二读出端口101jE读出所述第五单比特存储结构的第三RAM1013E或所述第五单比特存储结构101E的第四RAM1014E中存储的数据。将存储单元10封装之后，不体现标志位存储器的端口，体现在封装体外部的端口仅有第五单比特存储结构101E的第一读出端口101iE，第二读出端口101jE，第一写入端口101pE，第二写入端口101qE，所以可以得到两读两写的单比特存储器。
具体的，假设，所述标志位存储器的第一读出总端口1002i读出的数据为0时，指示所述第五单比特存储结构101E的第一读出端口101iE读出所述第五单比特存储结构101E中第一RAM1011E存数的数据，所述标志位存储器的第一读出总端口1002i读出的数据为1时，指示所述第五单比特存储结构101E的第一读出端口101iE读出所述第五单比特存储结构101E中第二RAM1012E存数的数据。在所述第五单比特存储结构101E的第一写入端口101pE向所述第五单比特存储结构101E中第一RAM1011E写入新的数据后，通过第六单比特存储结构101F的第一读出端口101iF分别读取第六单比特存储结构101F的第一RAM1011F中存储的数据和第二RAM1012F中存储的数据，并取两个数据的异或值输出；若所述异或值不为0，表示此时并没有指示新的数据存储在第五单比特存储结构101E中第 一RAM1011E中，需要改变标志位存储器的数据，具体的，可以通过所述标志位存储器的第一写入总端口1002p将所述第一RAM1011F中存储的数据取反后写入第六单比特存储结构101F的第一RAM1011F和第三RAM1013F，以及第七单比特存储结构101G的第一RAM1011G和第三RAM1013G，使得标志位存储器指示新的数据存储在第五单比特存储结构101E的第一RAM1011E中。
例如，在通过所述第五单比特存储结构101E的第一写入端口101pE向所述第五单比特存储结构101E中第一RAM1011E写入1后，通过第六单比特存储结构101F的第一读出端口101iF读取第六单比特存储结构101F的第一RAM1011F中存储的数据，该数据为0，以及第二RAM1012D中存储的数据，该数据为1，然后获取两个数据的异或值为1，该异或值与0并不相同，表示标志位存储器并没有指示新的数据存储在第五单比特存储结构101E中第一RAM1011E中，可以通过所述标志位存储器的第一写入总端口1002p将所述第六单比特存储结构101F的第一RAM1011F中存储的数据取反后写入第六单比特存储结构101F的第一RAM1011F和第三RAM1013F，以及第七单比特存储结构101G的第一RAM1011G和第三RAM1013G，由于0取反后为1，即将1写入第六单比特存储结构101F的第一RAM1011F和第三RAM1013F，以及第七单比特存储结构101G的第一RAM1011G和第三RAM1013G，此时第六单比特存储结构101F的第一RAM1011F中的存数数据为1，第六单比特存储结构101F的第二RAM1012F中存储的数据仍然为1，所以两个数据的异或值为0。由于第六单比特存储结构101F和第七单比特存储结构101G公用第一写入总端口1002p和第二写入总端口1002q，因此第六单比特存储结构101F与第七单比特存储结构101G的各个RAM中存储相同的数，因此，从标志位存储器第一读出总端口1002i读出的数据为0，表示新的数据存储在第五单比特存储结构101E 第一RAM1011E中，即在读取数据时第五单比特存储结构101E的第一读出端口101iE读出第一RAM1011E存储的数据。由于从标志位存储器的第一读出总端口1002i或第二读出总端口1002j读取数据时，不需要进行写入操作，所以在读取存储单元10的数据时，可以通过第一读出总端口1002i或第二读出总端口1002j确定标志位信息；而在向存储单元10存储新的数据后，由于可能会改变标志位存储器中RAM的数据，因此可以从第六单比特存储结构101F的第一读出端口101iF或第二读出端口101jF读取第六单比特存储结构101F中RAM的数据，并在需要改变标志位存储器中的数据时，通过写操作进行改变，这样一来，提高了标志位存储器的访问带宽，同时不限定标志位存储器的读写操作顺序，适用的范围较广。上述操作均可通过存储单元中包括的逻辑子单元完成，具体的过程可以参考前述实施例中的具体描述，本发明实施例在此不做赘述。
需要说明的是，如果第六单比特存储结构101F的第一读出端口101iF读出的数为0，此时已经指示新的数据存储在第五单比特存储结构101E中第一RAM1011E，可以不改变标志位存储器的数据，本发明实施例在此不做赘述。同时通过第二写入端口101qE向第五单比特存储结构101E的第四RAM1014E存储数据后，可以首先通过第六单比特存储结构101F的第二读出端口101jF读取第三RAM1013F与第四RAM1014F的数据，并根据该两个数据判断是否需要改变第六单比特存储结构101F的第四RAM1014F和第七单比特存储结构101G的第四RAM1014G的数据，具体的方法与上述方法相同，可以参照上述方法进行操作，本发明实施例在此不做赘述。
需要说明的是，存储单元10可以根据具体情况在设置其他逻辑子单元，示例地，其他逻辑子单元可以通过第一读出端口101i获取第一RAM1011存储的数据与第二RAM1012存储的数据的和值，或者还可以获取第一RAM1011存储的数据与第二RAM1012存储的数据的乘积；同理还可以通 过第二读出端口101j获取第三RAM1013存储的数据与第四RAM1014存储的数据的和值，或者还可以获取第三RAM1013存储的数据与第四RAM1014存储的数据的乘积，本发明实施例对此不做限定。
本发明实施例提供了一种存储单元，可以采用四个RAM组成一个单比特存储结构，使得该单比特存储结构具有两个读出端口和两个写入端口，因此可以同时对所述单比特存储结构进行两次读操作和两次写操作，提高了该单比特存储结构的访问带宽，进而提高了由该单比特存储结构组成的存储单元的数据存储容量，满足处理系统的控制需求，扩展了处理系统的应用。
本发明实施例提供一种处理系统，包括上述任一实施例上述的存储单元10。由于采用存储单元10作为处理单元的存储装置，使得存储装置的访问带宽增加，进而增加了处理系统的数据存储容量，使得处理系统能够满足大型自动化设备的控制需求。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明实施例中，采用四个RAM组成一个单比特(bit)存储结构，使得该单比特存储结构具有两个读出端口和两个写入端口，因此可以同时对所述单比特存储结构进行两次读操作和两次写操作，提高了该单比特存储结构的访问带宽，进而提高了包括该单比特存储结构的存储单元的数据存储容量，满足处理系统的控制需求，扩展了处理系统的应。

Claims (9)

  1. 一种存储单元，所述存储单元包括至少一个单比特存储结构；
    每个所述单比特存储结构包括四个随机存取存储器RAM，分别为第一RAM、第二RAM、第三RAM和第四RAM；两个读出端口分别为第一读出端口和第二读出端口；两个写入端口分别为第一写入端口和第二写入端口；
    其中，所述第一读出端口分别与所述第一RAM和所述第二RAM连接，配置为读取所述第一RAM和所述第二RAM中存储的数据；
    所述第二读出端口分别与所述第三RAM和所述第四RAM连接，配置为读取所述第三RAM和所述第四RAM中存储的数据；
    所述第一写入端口分别与所述第一RAM和所述第三RAM连接，配置为向所述第一RAM和所述第三RAM写入数据；
    所述第二写入端口分别与所述第二RAM和所述第四RAM连接，配置为向所述第二RAM和所述第四RAM写入数据。
  2. 根据权利要求1所述的存储单元，其中，所述存储单元还包括第一逻辑运算子单元和第二逻辑运算子单元；所述第一逻辑运算子单元与所述第一读出端口连接，所述第二逻辑运算子单元与所述第一写入端口连接；
    所述第一逻辑运算子单元配置为，在通过所述第一写入端口向所述单比特存储结构写入第一数据时，通过所述第一读出端口分别读取所述第一RAM中存储的第二数据和所述第二RAM中存储的第三数据，然后获取所述第二数据与所述第三数据的异或值；
    所述第二逻辑运算子单元配置为，当所述第一数据与所述异或值不同时，通过所述第一写入端口将所述第二数据取反后分别写入所述第一RAM和所述第三RAM。
  3. 根据权利要求1所述的存储单元，其中，所述存储单元包括两个单 比特存储结构，分别为第一单比特存储结构和第二单比特存储结构；
    其中，所述第一单比特存储结构的第一写入端口与所述第二单比特存储结构的第一写入端口连接组成所述存储单元的第一输入端口；
    所述第一单比特存储结构的第二写入端口与所述第二单比特存储结构的第二写入端口连接组成所述存储单元的第二输入端口；
    所述第二单比特存储结构的第一读出端口为所述存储单元的第一输出端口；
    所述第二单比特存储结构的第二读出端口为所述存储单元的第二输出端口。
  4. 根据权利要求3所述的存储单元，其中，所述存储单元还包括第三逻辑运算子单元和第四逻辑运算子单元；所述第三逻辑运算子单元与所述第一单比特存储结构的第一读出端口连接，所述第四逻辑运算子单元与所述第一输入端口连接；
    所述第三逻辑运算子单元配置为，在通过所述第一输入端口向所述存储单元写入第四数据时，通过所述第一单比特存储结构的第一读出端口分别读取所述第一单比特存储结构的第一RAM中存储的第五数据和第二RAM中存储的第六数据，然后获取所述第五数据与所述第六数据的异或值；
    所述第四逻辑运算子单元配置为，当所述第四数据与所述异或值不同时，通过所述第一输入端口将所述第五数据取反后分别写入所述第一单比特存储结构的第一RAM和第三RAM，以及第二单比特存储结构的第一RAM和第三RAM。
  5. 根据权利要求1所述的存储单元，其中，
    所述存储单元还包括至少一个标志位存储器，每个标志位存储器对应一个单比特存储结构，所述标志位存储器配置为存储对应的单比特存储结 构的第一RAM、第二RAM、第三RAM和第四RAM的标志位。
  6. 根据权利要求5所述的存储单元，其中，所述存储单元包括一个单比特存储结构，为第三单比特存储结构，与所述第三单比特存储结构对应的标志位存储器为第四单比特存储结构；
    所述标志位存储器配置为，通过所述第四单比特存储结构的第一读出端口读出的数据，指示第三单比特存储结构的第一读出端口读出所述第三单比特存储结构的第一RAM或所述第三单比特存储结构的第二RAM中存储的数据；
    通过所述第四单比特存储结构的第二读出端口读出的数据，指示第三单比特存储结构的第二读出端口读出所述第三单比特存储结构的第三RAM或所述第三单比特存储结构的第四RAM中存储的数据。
  7. 根据权利要求6所述的存储单元，其中，
    所述标志位存储器具体配置为，当所述第四单比特存储结构的第一读出端口读出第七数据时，指示第三单比特存储结构的第一读出端口读出第一RAM存储的数据；
    所述存储单元还包括第五逻辑运算子单元和第六逻辑运算子单元；所述第五逻辑运算子单元与所述第四单比特存储结构的第一读出端口连接，所述第六逻辑运算子单元与所述第四单比特存储结构的第一写入端口连接；
    所述第五逻辑运算子单元配置为，在通过所述第三单比特存储结构的第一写入端口向所述第三单比特存储结构的第一RAM写入新的数据后，通过第四单比特存储结构的第一读出端口分别读取第四单比特存储结构的第一RAM中存储的第八数据和第二RAM中存储的第九数据，然后获取所述第八数据与所述第九数据的异或值；
    所述第六逻辑运算子单元配置为，当所述异或值与所述第七数据不相 同时，通过所述第四单比特存储结构的第一写入端口将所述第八数据取反后写入所述第四单比特存储结构的第一RAM和第三RAM。
  8. 根据权利要求5所述的存储单元，其中，所述存储单元包括一个单比特存储结构，为第五单比特存储结构，与所述第五单比特存储结构对应的标志位存储器包括两个单比特存储结构，分别为第六单比特存储结构和第七单比特存储结构；
    其中，所述第六单比特存储结构的第一写入端口与所述第七单比特存储结构的第一写入端口连接组成所述标志位存储器的第一写入总端口；
    所述第六单比特存储结构的第二写入端口与所述第七单比特存储结构的第二写入端口连接组成所述标志位存储器的第二写入总端口；
    所述第七单比特存储结构的第一读出端口为所述标志位存储器的第一读出总端口；
    所述第七单比特存储结构的第二读出端口为所述标志位存储器的第二读出总端口；
    所述标志位存储器具体配置为，通过所述第一读出总端口读出的数据，指示所述第五单比特存储结构的第一读出端口读出所述第五单比特存储结构中第一RAM或所述第五单比特存储结构中第二RAM中存储的数据；
    通过所述第二读出总端口读出的数据，指示所述第五单比特存储结构的第二读出端口读出所述第五单比特存储结构的第三RAM或所述第五单比特存储结构的第四RAM中存储的数据。
  9. 一种处理系统，包括权利要求1至权利要求8任意一项权利要求所述的存储单元。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
CN112669895A (zh) * 2019-10-16 2021-04-16 长鑫存储技术有限公司 测试电路及采用该测试电路的存储芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101529521A (zh) * 2006-11-17 2009-09-09 飞思卡尔半导体公司 具有改善的写入操作的二端口sram
CN102385916A (zh) * 2011-09-21 2012-03-21 清华大学 一种具有读写分离的双端口sram单元6t结构
CN102844814A (zh) * 2010-04-14 2012-12-26 飞思卡尔半导体公司 具有可变数量的使用写端口的多端口存储器
US20140269019A1 (en) * 2013-03-15 2014-09-18 Pramod Kolar Dual-port static random access memory (sram)
CN104425007A (zh) * 2013-08-30 2015-03-18 台湾积体电路制造股份有限公司 三维交叉存取双端口位单元设计

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745374B1 (ko) * 2006-02-21 2007-08-02 삼성전자주식회사 멀티포트 반도체 메모리 장치 및 그에 따른 신호 입출력방법
KR101414774B1 (ko) * 2007-08-29 2014-08-07 삼성전자주식회사 멀티포트 반도체 메모리 장치
US8775744B2 (en) * 2009-08-31 2014-07-08 Chung Kuang Chin Simultaneous switching of multiple time slots in an optical network node
CN103309626A (zh) * 2013-07-03 2013-09-18 盛科网络（苏州）有限公司 实现网络芯片多读写端口存储器的方法及相应存储器
CN104484128A (zh) * 2014-11-27 2015-04-01 盛科网络（苏州）有限公司 基于一读一写存储器的多读多写存储器及其实现方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101529521A (zh) * 2006-11-17 2009-09-09 飞思卡尔半导体公司 具有改善的写入操作的二端口sram
CN102844814A (zh) * 2010-04-14 2012-12-26 飞思卡尔半导体公司 具有可变数量的使用写端口的多端口存储器
CN102385916A (zh) * 2011-09-21 2012-03-21 清华大学 一种具有读写分离的双端口sram单元6t结构
US20140269019A1 (en) * 2013-03-15 2014-09-18 Pramod Kolar Dual-port static random access memory (sram)
CN104425007A (zh) * 2013-08-30 2015-03-18 台湾积体电路制造股份有限公司 三维交叉存取双端口位单元设计

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