WO2022247195A1 - 数据存储器、数据存储、读取方法、芯片及计算机设备 - Google Patents

数据存储器、数据存储、读取方法、芯片及计算机设备 Download PDF

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Publication number
WO2022247195A1
WO2022247195A1 PCT/CN2021/134304 CN2021134304W WO2022247195A1 WO 2022247195 A1 WO2022247195 A1 WO 2022247195A1 CN 2021134304 W CN2021134304 W CN 2021134304W WO 2022247195 A1 WO2022247195 A1 WO 2022247195A1
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data
storage
bit
storage bit
current
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PCT/CN2021/134304
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English (en)
French (fr)
Inventor
王文强
霍冠廷
徐宁仪
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上海阵量智能科技有限公司
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Publication of WO2022247195A1 publication Critical patent/WO2022247195A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of computer hardware, in particular, to a data storage, data storage, reading method, chip and computer equipment.
  • Image processing technology has important applications in many scenarios. In fields such as surveillance and automatic driving, it is often necessary to process continuous multi-frame images or video streams.
  • the pipeline architecture is usually used to realize high-speed processing of multi-frame images; in the process of image processing, the image processing system needs to store each frame of image in the data memory in sequence, and the processing unit in the image processing system needs to read from the data memory image data, and process the read image data.
  • the current data memory has the problem of high power consumption.
  • Embodiments of the present disclosure at least provide a data memory, a data storage, a reading method, a chip, and a computer device, which can reduce power consumption of an image processing system.
  • an embodiment of the present disclosure provides a data storage, including: a first storage bank and a second storage bank; the first storage bank includes a plurality of first storage bits; the second storage bank includes a plurality of the second storage bits corresponding to the first storage bits respectively; , storing the first data in the current first storage bit, and setting the indicator in the second storage bit corresponding to the current first storage bit to a first value; wherein, the indicator is used Indicates whether the first data is the same as the second data.
  • the first data to be stored in the current first storage position corresponds to the previous first storage position.
  • the first data is stored, and the indicator in the corresponding second storage bit is set to the first value, and the indicator is used to indicate whether the first data is the same as the second data; when the data is read, If the indicator indicates that the first data is the same as the second data, the first data will not be obtained by accessing the first storage bank, and then in the case of duplicate data in the image data to be stored, the data writing process will reduce The access to the first storage bank reduces the access to the first storage bank during the data reading process, and reduces the power consumption during the data writing and reading process.
  • the data memory is further configured to respond to the fact that the first data to be stored in the current first storage bit is the same as the second data stored in the previous first storage bit, and will be the same as the current first storage bit.
  • the indicator in the second storage bit corresponding to a storage bit is set to the second value.
  • it further includes: a comparator; the output terminals of the comparator are respectively connected to the first memory bank and the second memory bank; compare the first data corresponding to the bit with the second data corresponding to the previous first storage bit; in response to the difference between the first data and the second data, transmit the the first data, and control the indicator in the second storage bit corresponding to the current first storage bit to be set to the first value.
  • the first data and the second data are compared by the comparator, so that when the first data and the second data are different, the first data will be stored in the current first storage bank by accessing the first storage bank. bits, thereby reducing the access to the first storage bank during the data storage process, and reducing the power consumption during the data storage process.
  • the comparator is further configured to, in response to the fact that the first data is the same as the second data, control the setting of the indicator in the second storage bit corresponding to the first storage bit. is the second value.
  • it further includes: a first register; the first register is connected to the comparator; the first register is used to store the second data corresponding to the previous first storage bit;
  • the comparator when comparing the first data corresponding to the current first storage bit with the second data corresponding to the previous first storage bit, is used to: acquire the first data transmitted by the data writing end one data, and read the second data corresponding to the previous first storage bit from the first register; write the data into the first data transmitted by the terminal and read from the first register Take the second data for comparison.
  • the comparator is further configured to control the second data stored in the first register to be updated to the first data in response to the difference between the first data and the second data .
  • it further includes: a first processing circuit; the input terminal of the first processing circuit is connected to the output terminal of the comparator, and the output terminal of the first processing circuit is connected to the first storage body connection; the first processing circuit is configured to, after receiving the write enable signal for the current first storage bit transmitted by the data write terminal and the first data transmitted by the comparator, based on the The write enable signal writes the first data into the current first storage bit.
  • it further includes: a data selector; the input terminals of the data selector are respectively connected to the first memory bank and the second memory bank; A second storage bit corresponding to a storage bit reads an indicator; based on the indicator, transmits to the data reading end the first data stored in the current first storage bit from the current first storage bit, or The second data corresponding to the previous first storage bit is transmitted to the data reading end.
  • it further includes: a second processing circuit; the second processing circuit is respectively connected to the first storage bank and the second storage bank; the second processing circuit is configured to receive After the read enable signal for the current first storage bit is transmitted to the data reading end, read the current first storage bit corresponding to the current first storage bit from the second storage bit corresponding to the current first storage bit , and in response to the indication indicating that the first data is read from the current first storage bit, sending a data read request to the first storage bank; the first data storage bank also and transmitting the first data stored in the current first storage bit to the data selector based on the data read request.
  • the access to the first memory bank is triggered by the second processing circuit, and it is possible to select whether to access the first memory bank according to the indicator, so as to realize the data reading process.
  • it further includes: a second register; the second register is connected to the data selector; the second register is used to store the second data corresponding to the previous first storage bit
  • the data selector based on the indication, transmits to the data reading end the first data obtained from the current first storage position and stored in the current first storage position, or reads to the data
  • the terminal corresponds to the second data corresponding to the previous first storage bit
  • it is used to: read the indicator; in response to the indicator being the first value, transmit the data stored in the data reading terminal to the data reading terminal.
  • the first data first data of the current first storage bit; in response to the indication being identified as a second value, reading the second data corresponding to the previous first storage bit from the second register, and transmitting the second data to the data reading end.
  • the second register is also connected to the first storage bank; the first storage bank transmits the first stored in the current first storage bit to the data selector. data, it is also used to: transmit the first data to the second register; the second register is also used to store the second data after receiving the first data transmitted by the first memory bank The data is updated to the first data.
  • an embodiment of the present disclosure further provides a data storage, including: a first storage bank and a second storage bank;
  • the first storage bank includes a plurality of first storage bits;
  • the second storage bank includes second storage bits respectively corresponding to the plurality of first storage bits;
  • the data memory is used for responding to the indication mark stored in the second storage bit corresponding to the current first storage bit to be read, representing that the first data stored in the current first storage bit is different from that stored in the previous first storage bit.
  • the second data is different, and the first data is determined as the data to be read and read.
  • the data memory is further configured to identify the first data stored in the current first storage bit in response to an indication stored in the second storage bit corresponding to the current first storage bit to be read. The same as the second data stored in the previous first storage bit, the second data is determined as the data to be read and read.
  • an embodiment of the present disclosure further provides a data storage method applied to a data storage
  • the data storage includes: a first storage bank and a second storage bank
  • the first storage bank includes a plurality of first storage bits
  • the second storage bank includes a plurality of second storage bits respectively corresponding to the first storage bits
  • the data storage method includes: responding to the first data to be stored in the current first storage bit and the previous first storage
  • the second data stored in each bit is different, the first data is stored in the current first storage bit, and the indicator in the second storage bit corresponding to the current first storage bit is set as the first value;
  • the indicator is used to indicate whether the first data is the same as the second data.
  • the data memory is configured to store the second data corresponding to the current first storage bit in response to the same first data to be stored in the current first storage bit as the second data stored in the previous first storage bit.
  • the indicator in the bit is set to the second value.
  • the data storage further includes: a comparator; output terminals of the comparator are respectively connected to the first memory bank and the second memory bank; the data storage method further includes: The comparator compares the first data corresponding to the current first storage bit with the second data corresponding to the previous first storage bit; in response to the difference between the first data and the second data , transmitting the first data to the current first storage bit, and controlling the indicator in the second storage bit corresponding to the current first storage bit to be set to a first value.
  • the method further includes: the comparator controlling the indicator in the second storage bit corresponding to the first storage bit to be set to the second value.
  • the data memory further includes: a first register; the first register is connected to the comparator; the data storage method further includes: the first register stores the previous first The second data corresponding to a storage bit; the comparator compares the first data corresponding to the current first storage bit with the second data corresponding to the previous first storage bit, including: obtaining data write The first data transmitted by the input terminal, and the second data corresponding to the previous first storage bit is read from the first register; the first data transmitted by the write terminal and the first data transmitted from the The second data read in the first register is compared.
  • the method further includes: the comparator controlling the second data stored in the first register to be updated to the first data in response to the difference between the first data and the second data.
  • the data memory further includes: a first processing circuit; an input terminal of the first processing circuit is connected to an output terminal of the comparator, and an output terminal of the first processing circuit is connected to the output terminal of the comparator.
  • the first storage bank is connected; the data storage method further includes: the first processing circuit receives the write enable signal for the current first storage bit transmitted by the data write terminal, and the comparator transmits After receiving the first data, write the first data into the current first storage bit based on the write enable signal.
  • an embodiment of the present disclosure further provides a data reading method applied to a data storage
  • the data storage includes: a first storage bank and a second storage bank;
  • the first storage bank includes a plurality of first storage bit;
  • the second storage bank includes second storage bits respectively corresponding to a plurality of the first storage bits;
  • the data storage method includes:
  • the The first data is determined as the data to be read and read.
  • the method further includes: responding to the indication stored in the second storage bit corresponding to the current first storage bit to be read, indicating that the first data stored in the current first storage bit is different from the previous The second data stored in a first storage bit is the same, and the second data is determined as the data to be read and read.
  • an embodiment of the present disclosure further provides a chip, including the data storage according to any one of the first aspect, and/or the data storage according to the second aspect.
  • an embodiment of the present disclosure further provides a computer device, including: a processor, a memory, and the data storage according to any one of the first aspect, or including the data storage according to any two items of the second aspect , or include the chip as described in the fifth aspect.
  • the embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a computer device, the computer device executes the method described in the third aspect.
  • FIG. 1 shows a schematic diagram of a data storage provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of another data storage provided by an embodiment of the present disclosure
  • Fig. 3 shows a flow chart of a data storage method provided by an embodiment of the present disclosure
  • Fig. 4 shows a flowchart of a data reading method provided by an embodiment of the present disclosure.
  • the pixel information corresponding to each pixel point in the image data is usually stored in each storage location of the storage device in sequence according to the position of each pixel point in the image data.
  • This data storage method makes it necessary to sequentially access the storage bits used to store the pixel information corresponding to multiple pixel points each time the image data is written or read when storing image data, resulting in data writing And the problem of high power consumption in the reading process.
  • the present disclosure provides a data memory, in which a first storage bank and a second storage bank are provided, the first storage bank includes a plurality of first storage bits, and the second storage bank includes a plurality of first storage bits.
  • the second storage bits respectively corresponding to the storage bits store the first data in the current first storage bit when the first data to be stored in the current first storage bit is different from the second data corresponding to the previous first storage bit, And store a corresponding indicator in the second storage bit corresponding to the current first storage bit, where the indicator can indicate whether to read the first data from the corresponding first storage bit.
  • the data storage provided in the embodiments of the present disclosure can be applied to computer equipment, and the computer equipment includes, for example: terminal equipment or servers or other
  • the processing device, the terminal device may be user equipment (User Equipment, UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (Personal Digital Assistant, PDA), handheld device, computing device, vehicle-mounted device, wearable devices etc.
  • This kind of data storage can be used to store various data, such as image data, audio data, text data, data in other formats, and the like.
  • FIG. 1 it is a schematic structural diagram of a data storage provided by an embodiment of the present disclosure, including: a first storage bank 10 and a second storage bank 20 .
  • the first storage bank 10 includes a plurality of first storage bits;
  • the second storage bank 20 includes second storage bits respectively corresponding to the plurality of first storage bits;
  • the data memory is configured to store the first data in the current first memory bit in response to the fact that the first data to be stored in the current first memory bit is different from the second data stored in the previous first memory bit. data, and setting the indicator in the second storage bit corresponding to the current first storage bit as the first value;
  • the indicator is used to indicate whether the first data is the same as the second data.
  • the data memory is further configured to store the first data to be stored in the current first storage bit is the same as the second data stored in the previous first storage bit, and will be the same as the current
  • the indicator in the second storage bit corresponding to the first storage bit is set to the second value.
  • the data memory may further include at least one of the following: a first register 30, a comparator 40, a first processing circuit 50, a second register 60, a data selector 70, a first Two processing circuits 80 .
  • the first storage bank 10 includes, for example: any one of a static random-access memory (Static Random-Access Memory, SRAM), a random access memory (random access memory, RAM), and the like.
  • SRAM static random-access memory
  • RAM random access memory
  • a plurality of first storage bits are included in the first memory bank 10; each first storage bit corresponds to a data storage space; each data storage space corresponds to at least one data storage address; specifically, according to actual data storage requirements, for Each storage bit determines the size of the data storage space.
  • the first storage bank 10 includes, for example, N first storage bits, and each first storage bit can be used as the current first storage bit; for example, it is assumed that the current first storage bit is Nth For the ith first storage bit in one storage bit, the corresponding previous first storage bit is the i-1 first storage bit. If the current first storage bit is the first first storage bit in the first memory bank 10 , then there is no previous first storage bit.
  • each first storage bit is used to store a sub-data in the data to be stored; for example, if the data to be stored is image data, each sub-data It includes pixel data corresponding to a pixel in the image data, such as the pixel value of the pixel.
  • the second storage bank 20 includes registers, for example; Exemplarily, the second storage bank 20 is a register file composed of a plurality of registers; each register corresponds to a second storage bit, and each second storage bit is associated with a first storage bit corresponding. Each register can store a preset number of bits of data, and the data is an indicator corresponding to the first storage bit.
  • the number of registers in the register file constituting the second memory bank 20 is, for example, the same as the number of the first storage bits; each register in the register file and the corresponding first storage bits can be made to use the same data storage address , through the same data storage address, the first storage bit in the first memory bank 10 is accessed, and the second storage bit corresponding to the first storage bit is accessed.
  • the first data is read by accessing the first memory bank 10 .
  • the indication flag indicates that the first data is the same as the second data
  • the read second data of the previous first storage bit may be copied.
  • the data corresponding to the previous first storage bit may be stored in a separate register, and the data in the register may be It is constantly updated according to the change of the current first storage bit.
  • the second data corresponding to the previous first storage bit may be read from the register.
  • the register is the second register 60 described in the embodiment of the present disclosure. For a specific reading method, refer to the description of the second register 60 in the following embodiments, which will not be repeated here.
  • the data memory may further include: a comparator 40 .
  • the output terminals of the comparator 40 are respectively connected with the first memory bank 10 and the second memory bank 20; Compare the two data, and in response to the difference between the first data and the second data, transmit the first data to the current first storage bit, and control the indicator in the second storage bit corresponding to the current first storage bit set to the first value.
  • the comparator 40 is further configured to control the indicator in the second storage bit corresponding to the first storage bit to be set to a second value in response to the first data being the same as the second data.
  • the first value is 1, that is, if the indication is 1, it means that data is stored in the first storage bit corresponding to the second storage bit;
  • the second value is 0, that is, if the indication is 0, it means that the first storage bit corresponding to the second storage bit has no data stored (the storage space corresponding to the first storage bit can be empty, or store other data except the data to be stored), in this
  • the first data corresponding to the current first storage bit is the same as the second data corresponding to the previous first storage bit
  • the second data corresponding to the previous first storage bit can be directly used as the current first storage bit. data.
  • the data storage further includes: a first register 30 .
  • the first register 30 is connected to a comparator 40 .
  • the first register 30 is used to store the second data corresponding to the previous first storage bit
  • the comparator 40 when comparing the first data corresponding to the current first storage bit with the second data corresponding to the previous first storage bit, is used to: first data, and read the second data corresponding to the previous first storage bit from the first register 30; The second data read in 30 is compared.
  • the comparator 40 is further configured to control the second data stored in the first register 30 to be updated to the first data in response to the difference between the first data and the second data.
  • a plurality of first storage bits are sequentially used as the current first storage bit, and if the first data to be written into the current first storage bit corresponds to its previous first storage bit If the second data is different, the first data is written into the current first storage position, and the data stored in the first register 30 is controlled to be updated to the first data, so as to use the next first storage position as the current storage position data writing; if the first data to be written into the current first storage bit is the same as the second data corresponding to the previous first storage bit, the first data will not be written into the current first storage bit; The first data is the same as the second data, and the data stored in the first register 30 does not need to be updated. Furthermore, in this way, when the data to be stored includes repeated data, access to the first memory bank 10 can be reduced, and power consumption when data is written into the first memory bank 10 can be reduced.
  • the data storage further includes: a first processing circuit 50;
  • the input end of the first processing circuit 50 is connected to the output end of the comparator 40, and the output end of the first processing circuit 50 is connected to the first storage bank 10;
  • the first processing circuit 50 is configured to, after receiving the write enable signal for the current first storage bit transmitted by the data write terminal and the first data transmitted by the comparator 40, based on the write The enable signal writes the first data into the current first storage bit.
  • the write enable signal carries, for example, the data storage address of the current first storage bit; after the first processing circuit 50 receives the write enable signal, if it receives the first data transmitted by the comparator 40, it can The data storage address carried in the enable signal accesses the current first storage bit, and stores the first data in the current first storage bit.
  • an embodiment of the present disclosure provides a specific process of writing data to a data storage, where the first storage bank 10 in the data storage includes N (N>1) first storage bits, and the second storage bank 20 includes N second storage bits, and the first storage bits correspond to the second storage bits one-to-one.
  • the data corresponding to the N first storage bits respectively include: a1 ⁇ aN, and the data reading process is as follows:
  • the data writing end transmits the data a1 corresponding to the first first storage bit to the comparator 40 .
  • the data in the first register 30 is empty or is preset data, for example, the preset data is data composed of m (m>1) 1s, or data composed of m 0s.
  • the comparator 40 compares the data a1 with the preset data, and if the two are inconsistent, the data a1 is transmitted to the first processing circuit 50; or, the data read by the comparator 40 from the first register 30 is empty, The data a1 is transmitted to the first processing circuit 50 .
  • the first processing circuit 50 receives the write enable signal transmitted by the data write end, and writes the data a1 into the first first storage bit according to the data storage address corresponding to the first first storage bit carried in the write enable signal. storage bit; the comparator 40 also sets the indicator in the first second storage bit corresponding to the first first storage bit in the second storage bank 20 as the first value; in addition, the comparator 40 also sets the data a1 written into the first register 30.
  • the data writing end transmits the data a2 corresponding to the second first storage bit to the comparator 40 .
  • data a1 is stored in the first register 30 .
  • the comparator 40 reads the data a1 from the first register 30 and compares the data a1 with the data a2.
  • the first processing circuit 50 receives the write enable signal transmitted by the data write end, and writes the data a2 into the second first storage bit according to the data storage address corresponding to the second first storage bit carried in the write enable signal. memory bits.
  • the comparator 40 also sets the indicator in the second second storage bit corresponding to the second first storage bit in the second memory bank 20 to the first value.
  • the comparator 40 also writes the data a2 into the first register 30, replacing the data a1 in the first register 30 with a2.
  • the data writing end transmits the data a3 corresponding to the third first storage bit to the comparator 40 .
  • data a2 is stored in the first register 30 .
  • the comparator 40 reads the data a2 from the first register 30 and compares the data a2 with the data a3.
  • the indicator of the third second storage bit corresponding to the third first storage bit in the second memory bank 20 is set to the second value.
  • the data writing end transmits the data a4 corresponding to the fourth first storage bit to the comparator 40 .
  • data a2 is stored in the first register 30 , and since a2 and a3 are the same, a2 is considered to be a3, that is, data corresponding to the third first storage bit is stored in the first register 30 .
  • the comparator 40 reads the data a2 from the first register 30 and compares the data a2 with the data a4.
  • the indicator of the 4th second storage bit corresponding to the 4th first storage bit in the second memory bank 20 is set to the second value.
  • the data writing end transmits the data a5 corresponding to the fifth first storage bit to the comparator 40 .
  • data a2 is stored in the first register 30 , and since a2 and a4 are the same, a2 is considered to be a4, that is, data corresponding to the fourth first storage bit is stored in the first register 30 .
  • the comparator 40 reads the data a2 from the first register 30 and compares the data a2 with the data a5.
  • the data a5 is transmitted to the first processing circuit 50 .
  • the first processing circuit 50 receives the write enable signal transmitted by the data write end, and writes the data a5 into the fifth first storage bit according to the data storage address corresponding to the fifth first storage bit carried in the write enable signal. memory bits.
  • the comparator 40 also sets the indicator in the fifth second storage bit corresponding to the fifth first storage bit to the first value.
  • the comparator 40 also writes the data a5 into the first register 30, replacing the data a2 in the first register 30 with a5.
  • the data to be stored can be stored in the data memory, and in this process, the power consumption in the data storage process can be reduced by reducing the access to the first storage bank 10 based on repeated data.
  • the data storage further includes: a data selector 70 .
  • the input ends of the data selector 70 are respectively connected to the first memory bank 10 and the second memory bank 20;
  • the data selector 70 is used to read the indicator from the second storage bit corresponding to the current first storage bit; based on the indicator, transmit the stored data obtained from the current first storage bit to the data reading end.
  • the first data of the current first storage bit, or the second data corresponding to the previous first storage bit is transmitted to the data reading end.
  • the data selector 70 when reading data from the data memory, can determine to transmit the first data obtained from the first storage bit to the data reading end according to the indicator stored in the second storage bit, Or transmit the second data corresponding to the previous first storage bit to the data reading end; here, since the data is stored in the process, if the current first storage bit is the same as the data corresponding to the previous first storage bit, it will not The first data corresponding to the current first storage bit will be stored in the first storage bit, therefore, when the first data corresponding to the current first storage bit needs to be read, the first data corresponding to the previous first storage bit will be directly stored The data is used as the data corresponding to the current first storage bit. If the data corresponding to the current first storage bit and the previous first storage bit are different, then by accessing the first storage bank 10, the first data stored in the current first storage bit is obtained, and the first data is transmitted to the data reading end. data.
  • a second processing circuit 80 is also included in the data memory.
  • the second processing circuit 80 is connected to the first memory bank 10 and the second memory bank 20 respectively;
  • the second processing circuit 80 is configured to, after receiving the read enable signal for the current first storage bit transmitted by the data reading end, from the second storage corresponding to the current first storage bit Read the indicator corresponding to the current first storage bit in the bit, and send data to the first storage bank 10 in response to the indicator indicating that the first data is read from the current first storage bit read request;
  • the first data storage body 10 is further configured to transmit the first data stored in the current first storage location to the data selector 70 based on the data read request.
  • the read enable signal transmitted from the data reading end to the second processing circuit 80 carries the data storage address of the current first storage bit to be read; the second storage bit corresponding to the current first storage bit has The same data storage address, therefore, the second processing circuit 80 can access the second storage bank 20 according to the data storage address, and obtain the indication stored in the second storage bit corresponding to the current first storage bit from the second storage bank 20 logo.
  • a data read request is sent to the first storage bank 10 .
  • the data storage address of the current first storage bit is carried; after the first storage bank 10 receives the data read request, based on the data storage address, the first data stored in the current first storage bit is Send to data selector 70.
  • the second memory bank 20 when the second memory bank 20 transmits the indication to the second processing circuit 80, it will also transmit the indication to the data selector 70, and the indication serves as a trigger for the data selector 70 signal, so that the data selector 70 triggers the work of the data selector 70 after receiving the indication mark, so as to transmit to the data reading end the first data obtained from the current first storage position and stored in the current first storage position. data, or transmit second data corresponding to the previous first storage bit to the data reading end.
  • the data memory further includes: a second register 60 .
  • the second register 60 is connected to the data selector 70 .
  • the second register 60 is used for storing the second data corresponding to the previous first storage bit.
  • the data selector 70 based on the indication, transmits the first data obtained from the current first storage position and stored in the current first storage position to the data reading end, or reads the data to the data read terminal.
  • the fetching end transmits the second data corresponding to the previous first storage bit, it is used to: read the indication mark; The first data acquired by the first storage bank 10; in response to the indication being identified as a second value, read the second data corresponding to the previous first storage bit from the second register 60 , and transmit the second data to the data reading end.
  • the data selector 70 has two data input terminals, respectively the first input terminal and the second input terminal; the first input terminal is connected to the first memory bank 10; the second input terminal is connected to the second register 60 .
  • the data selector 70 receives the first data through the first input terminal, and gates the first input terminal and the first input terminal of the data selector 70.
  • the data transmission path between the data output terminals transmits the first data to the data reading terminal.
  • the data selector 70 receives the second data transmitted by the second register 60 through the second input terminal, and gates the second input The data transmission path between the terminal and the data output terminal of the data selector 70 transmits the second data to the data reading terminal.
  • the second register 60 is also connected to the first memory bank 10;
  • the first memory bank 10 is further configured to: transmit the first data to the second register 60 when transmitting the first data stored in the current first storage bit to the data selector 70 ;
  • the second register 60 is further configured to update the stored second data to the first data after receiving the first data transmitted by the first memory bank 10 .
  • the data stored in the second register 60 can be constantly updated, so that the second data can be acquired by accessing the second register 60 . Since the energy consumption required for accessing the register is far less than the energy consumption for accessing the first memory bank 10, the energy consumption required during the data reading process can be reduced.
  • an embodiment of the present disclosure provides a specific process of reading data from a data storage.
  • the first storage bank 10 in the data storage includes N first storage bits
  • the second storage bank 20 includes N second storage bits, and there is a one-to-one correspondence between the first storage bits and the second storage bits.
  • the data corresponding to the N first storage bits respectively include: a1 ⁇ aN
  • the data reading process is as follows:
  • the data reading terminal sends a read enable signal for the 1st first storage bit to the second processing circuit 80; From the first second storage bit in the second memory bank 20, read the indicator corresponding to the first first storage bit.
  • the indication is identified as a first value, indicating that the data a1 is to be read from the first first storage bit.
  • the second processing circuit 80 sends a data read request to the first memory bank 10 .
  • the data storage address of the first first storage bit is carried in the data read request.
  • the first storage bank 10 After receiving the data read request, the first storage bank 10 transmits the data a1 stored in the first first data storage bit to the first input end of the data selector 70 according to the data storage address.
  • the second memory bank 20 also sends the indicator corresponding to the first first memory bit to the data selector 70 .
  • the data selector 70 gates the data transmission path between the first input terminal and the data output terminal according to the indication, and transmits the data a1 to the data reading terminal.
  • the first memory bank 10 also transfers the data a1 to the second register 60, and the second register 60 stores the data a1.
  • the data read terminal sends a read enable signal for the second first storage bit to the second processing circuit 80;
  • the data storage address reads the indicator corresponding to the second first storage bit from the second second storage bit in the second memory bank 20 .
  • the indication is identified as a first value, indicating that the data a2 is to be read from the second first storage bit.
  • the second processing circuit 80 sends a data read request to the first memory bank 10 .
  • the data storage address of the second first storage bit is carried in the data read request.
  • the first storage bank 10 After receiving the data read request, the first storage bank 10 transmits the data a2 stored in the second first data storage bit to the first input terminal of the data selector 70 according to the data storage address.
  • the second memory bank 20 also sends the indicator corresponding to the second first memory bit to the data selector 70 .
  • the data selector 70 gates the data transmission path between the first input terminal and the data output terminal according to the indication, and transmits the data a2 to the data reading terminal.
  • the first memory bank 10 also transfers the data a2 to the second register 60, and the second register 60 replaces the saved data a1 with the data a2.
  • the data reading end sends the read enable signal for the 3rd first storage bit to the second processing circuit 80;
  • the data storage address reads the indicator corresponding to the third first storage bit from the third second storage bit in the second memory bank 20 .
  • the indication is marked as the second value, indicating to read the previous first storage bit, that is, the data a2 corresponding to the second first storage bit, and the second processing circuit 80 ends the work of this data reading cycle, and no longer accesses the first storage bit.
  • a memory bank 10 .
  • the second memory bank 20 also sends the indicator corresponding to the third first memory bit to the data selector 70 .
  • the data selector 70 gates the data transmission path between the second input terminal and the data output terminal according to the indication, and transmits the data a2 stored in the second register 60 as the data corresponding to the third first storage bit to the data read end.
  • the data read terminal sends the read enable signal for the 4th first storage bit to the second processing circuit 80;
  • the data storage address reads the indicator corresponding to the fourth first storage bit from the fourth second storage bit in the second storage bank 20 .
  • the indication is marked as the second value, indicating to read the previous first storage bit, that is, the data a3 corresponding to the third first storage bit, and the second processing circuit 80 ends the work of this data reading cycle, and no longer accesses the first storage bit.
  • a memory bank 10 .
  • the second storage bank 20 also sends the indicator of the fourth first storage bit to the data selector 70 .
  • the data selector 70 gates the data transmission path between the second input terminal and the data output terminal according to the indication mark, and since a2 and a3 are the same, the data a2 stored in the second register 60 is used as the fourth first storage The data corresponding to the bit is transmitted to the data reading end.
  • the data reading end sends the read enable signal for the 5th first storage bit to the second processing circuit 80;
  • the data storage address reads the indicator corresponding to the fifth first storage bit from the fifth second storage bit in the second memory bank 20 .
  • the indication is identified as a first value, indicating that data a5 is to be read from the fifth first storage bit.
  • the second processing circuit 80 sends a data read request to the first memory bank 10 .
  • the data storage address of the fifth first storage bit is carried in the data read request.
  • the first storage bank 10 After receiving the data read request, the first storage bank 10 transmits the data a5 stored in the fifth first data storage bit to the first input terminal of the data selector 70 according to the data storage address.
  • the second memory bank 20 also sends the indicator of the fifth first memory bit to the data selector 70 .
  • the data selector 70 gates the data transmission path between the first input terminal and the data output terminal according to the indication, and transmits the data a5 to the data reading terminal.
  • the first memory bank 10 also transfers the data a5 to the second register 60, and the second register 60 replaces the saved data a2 with the data a5.
  • the power consumption in the data reading process can be reduced by reducing the access to the first memory bank when reading repeated data.
  • connection relationship and respective functions of each component do not constitute any limitation on the structure of the data storage provided by the embodiment of the present disclosure, and the specific structure of the data storage should be based on its Functionality and possible internal logic determined.
  • Another embodiment of the present disclosure also provides another data storage, including: a first storage bank and a second storage bank;
  • the first storage bank includes a plurality of first storage bits;
  • the second storage bank includes second storage bits respectively corresponding to the plurality of first storage bits;
  • the data memory is used for responding to the indication mark stored in the second storage bit corresponding to the current first storage bit to be read, representing that the first data stored in the current first storage bit is different from that stored in the previous first storage bit.
  • the second data is different, and the first data is determined as the data to be read and read.
  • the data memory is further configured to identify the first data stored in the current first storage bit in response to an indication stored in the second storage bit corresponding to the current first storage bit to be read. The same as the second data stored in the previous first storage bit, the second data is determined as the data to be read and read.
  • the embodiments of the present disclosure also provide a data storage method and a data reading method corresponding to the data memory. Since the problem-solving principle of the method in the embodiment of the present disclosure is similar to that of the above-mentioned data memory in the embodiment of the present disclosure, therefore For the implementation of the method, reference may be made to the implementation of the data storage, and repeated descriptions will not be repeated.
  • FIG. 3 it is a schematic diagram of a data storage method provided by an embodiment of the present disclosure, including:
  • the data memory includes: a first memory bank and a second memory bank; the first memory bank includes a plurality of first storage bits; the second memory bank includes a plurality of memory bits corresponding to the first memory bits The second storage bit; the data storage method includes:
  • the data memory stores the first data in the current first storage bit in response to the fact that the first data to be stored in the current first storage bit is different from the second data stored in the previous first storage bit;
  • the data memory is configured such that, in response to the first data to be stored in the current first storage bit is the same as the second data stored in the previous first storage bit, the second storage bit corresponding to the current first storage bit The indicator in is set to the second value.
  • the data storage further includes: a comparator; output terminals of the comparator are respectively connected to the first memory bank and the second memory bank; the data storage method further includes: The comparator compares the first data corresponding to the current first storage bit with the second data corresponding to the previous first storage bit; in response to the difference between the first data and the second data , transmitting the first data to the current first storage bit, and controlling the indicator in the second storage bit corresponding to the current first storage bit to be set to a first value.
  • the method further includes: the comparator controlling the indicator in the second storage bit corresponding to the first storage bit to be set to the second value.
  • the data memory further includes: a first register; the first register is connected to the comparator; the data storage method further includes: the first register stores the previous first The second data corresponding to a storage bit; the comparator compares the first data corresponding to the current first storage bit with the second data corresponding to the previous first storage bit, including: obtaining data write The first data transmitted by the input terminal, and the second data corresponding to the previous first storage bit is read from the first register; the first data transmitted by the write terminal and the first data transmitted from the The second data read in the first register is compared.
  • the method further includes: the comparator controlling the second data stored in the first register to be updated to the first data in response to the difference between the first data and the second data.
  • the data memory further includes: a first processing circuit; an input terminal of the first processing circuit is connected to an output terminal of the comparator, and an output terminal of the first processing circuit is connected to the output terminal of the comparator.
  • the first storage bank is connected; the data storage method further includes: the first processing circuit receives the write enable signal for the current first storage bit transmitted by the data write terminal, and the comparator transmits After receiving the first data, write the first data into the current first storage bit based on the write enable signal.
  • the data reading method provided by the embodiment of the present disclosure is applied to a data storage, and the data storage includes: a first storage bank and a second storage bank; the first storage bank includes a plurality of first storage banks bit; the second storage bank includes second storage bits respectively corresponding to a plurality of the first storage bits; the data storage method includes:
  • the method further includes: responding to the indication stored in the second storage bit corresponding to the current first storage bit to be read, indicating that the first data stored in the current first storage bit is different from the previous The second data stored in a first storage bit is the same, and the second data is determined as the data to be read and read.
  • the data storage further includes: a second processing circuit; the second processing circuit is respectively connected to the first memory bank and the second memory bank; the data reading method further includes: The second processing circuit reads from the second storage bit corresponding to the current first storage bit after receiving the read enable signal transmitted by the data reading terminal for the current first storage bit. An indicator corresponding to the current first storage bit, and in response to the indicator indicating that the first data is read from the current first storage bit, sending a data read request to the first storage bank; The first data storage bank transmits the first data stored in the current first storage position to the data selector based on the data read request.
  • the data memory further includes: a second register; the second register is connected to the data selector; the second register stores the second data corresponding to the previous first storage bit
  • the data reading method further includes: the data selector transmits to the data reading end the first data obtained from the current first storage position and stored in the current first storage position based on the indication mark, Or sending the second data corresponding to the previous first storage bit to the data reading end, comprising: reading the indication mark; in response to the indication being a first value, sending to the data reading end transmitting the first memory bank to transmit the first data; in response to the indication being identified as a second value, reading the second data corresponding to the previous first memory bit from the second register, And transmit the second data to the data reading end.
  • the second register is also connected to the first memory bank; the data reading method further includes: the first memory bank transmits the data stored in the data selector to the data selector.
  • the first data is transmitted to the second register; after the second register receives the first data transmitted by the first memory bank, the stored first data The second data is updated to the first data.
  • An embodiment of the present disclosure further provides a chip, including the data memory according to any one of the embodiments of the present disclosure.
  • An embodiment of the present disclosure further provides a computer device, including: a processor, a memory, and the data storage according to any embodiment of the present disclosure, or includes the chip provided by the embodiment of the present disclosure.
  • An embodiment of the present disclosure also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is run by a computer device, the computer device executes the method described in any embodiment of the present disclosure. Steps of the data storage method described above, or execute the steps of the data reading method described in any embodiment of the present disclosure.
  • An embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the data storage method or the data reading method described in the above method embodiments, For details, reference may be made to the foregoing method embodiments, and details are not repeated here.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. Wait.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本公开提供了一种数据存储器、数据存储、读取方法、芯片及计算机设备，其中数据存储器包括：所述第一存储体包括多个第一存储位；所述第二存储体包括与多个所述第一存储位分别对应的第二存储位；所述数据存储器被构造为，响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据不同，在所述当前第一存储位中存储所述第一数据，并将与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值；其中，所述指示标识用于指示所述第一数据与所述第二数据是否相同。

Description

数据存储器、数据存储、读取方法、芯片及计算机设备
相关申请的交叉引用
本公开要求于2021年5月22日提交的、申请号为202110561399.0、发明名称为“数据存储器、数据存储、读取方法、芯片及计算机设备”的中国专利申请的优先权，该中国专利申请公开的全部内容以引用的方式并入本文中。
技术领域
本公开涉及计算机硬件技术领域，具体而言，涉及一种数据存储器、数据存储、读取方法、芯片及计算机设备。
背景技术
图像处理技术在很多场景下具有重要应用。在例如监控领域、自动驾驶领域等这些领域中，往往需要对连续的多帧图像或者视频流进行处理。当前通常采用流水架构来实现对多帧图像的高速处理；在图像处理过程中，图像处理系统需要将各帧图像依次存储至数据存储器，且图像处理系统中的处理单元需要从数据存储器中读取图像数据，并对读取的图像数据进行处理。当前的数据存储器存在功耗大的问题。
发明内容
本公开实施例至少提供一种数据存储器、数据存储、读取方法、芯片及计算机设备，能够降低图像处理系统的功耗。
第一方面，本公开实施例提供了一种数据存储器，包括：第一存储体以及第二存储体；所述第一存储体包括多个第一存储位；所述第二存储体包括与多个所述第一存储位分别对应的第二存储位；所述数据存储器被构造为，响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据不同，在所述当前第一存储位中存储所述第一数据，并将与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值；其中，所述指示标识用于指示所述第一数据与所述第二数据是否相同。
这样，通过设置第一存储体和第二存储体，在第一存储体的各第一存储位中，在要存储至当前第一存储位的第一数据与前一第一存储位对应的第二数据不同时，存储第 一数据，并将对应第二存储位中的指示标识置为第一数值，该指示标识用于指示第一数据与第二数据是否相同；在进行数据读取时，若指示标识指示第一数据与第二数据相同，则不会通过访问第一存储体来获取第一数据，进而在待存储的图像数据中存在重复数据的情况下，减少数据写入过程中对第一存储体的访问，同时减少数据读取过程中对第一存储体的访问，降低数据写入和读取过程中的功耗。
一种可能的实施方式中，所述数据存储器，还用于响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据相同，将与所述当前第一存储位对应的第二存储位中的指示标识置为第二数值。
一种可能的实施方式中，还包括：比较器；所述比较器的输出端分别与所述第一存储体和所述第二存储体连接；所述比较器用于将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对；响应于所述第一数据和所述第二数据不同，向所述当前第一存储位传输所述第一数据，并控制与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值。
这样，通过比较器将第一数据和第二数据进行比对，以实现在第一数据和第二数据不同的情况下，才会通过访问第一存储体将第一数据存储至当前第一存储位，进而减少在数据存储过程中对第一存储体的访问，降低数据存储过程中的功耗。
一种可能的实施方式中，所述比较器，还用于响应于所述第一数据和所述第二数据相同，控制与所述第一存储位对应的第二存储位中的指示标识置为第二数值。
这样，能够标识出当前第一存储位的数据存储具体情况，方便后续数据的读取。
一种可能的实施方式中，还包括：第一寄存器；所述第一寄存器与所述比较器连接；所述第一寄存器，用于存储所述前一第一存储位对应的第二数据；所述比较器，在将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对时，用于：获取数据写入端传输的第一数据，以及从所述第一寄存器中读取所述前一第一存储位对应的第二数据；将所述数据写入端传输的所述第一数据和从所述第一寄存器中读取的第二数据进行比对。
这样，通过设置第一寄存器，利用第一寄存器暂存第二数据，方便比较器快速获取第二数据。
一种可能的实施方式中，所述比较器，还用于响应于所述第一数据和所述第二数据不同，控制所述第一寄存器中存储的第二数据更新为所述第一数据。
这样，实现对第一寄存器中数据的动态更新。
一种可能的实施方式中，还包括：第一处理电路；所述第一处理电路的输入端和所述比较器的输出端连接，所述第一处理电路的输出端和所述第一存储体连接；所述第一处理电路，用于在接收到数据写入端传输的针对所述当前第一存储位的写使能信号、以及所述比较器传输的第一数据后，基于所述写使能信号将所述第一数据写入所述当前第一存储位。
这样，通过第一处理电路来实现对第一存储体的访问。
一种可能的实施方式中，还包括：数据选择器；所述数据选择器的输入端分别与所述第一存储体和所述第二存储体连接；所述数据选择器用于从与当前第一存储位对应的第二存储位读取指示标识；基于所述指示标识，向数据读取端传输从所述当前第一存储位获取存储至所述当前第一存储位的第一数据，或者向所述数据读取端传输与所述前一第一存储位对应的第二数据。
这样，通过数据选择器选择输出第一数据或者第二数据，减少数据读取过程中对第一存储体的访问，降低数据读取过程中的功耗。
一种可能的实施方式中，还包括：第二处理电路；所述第二处理电路分别与所述第一存储体和所述第二存储体连接；所述第二处理电路，用于在接收到所述数据读取端传输的针对所述当前第一存储位的读使能信号后，从与所述当前第一存储位对应的第二存储位中读取所述当前第一存储位对应的指示标识，并响应于所述指示标识指示从所述当前第一存储位读取所述第一数据，向所述第一存储体发送数据读取请求；所述第一数据存储体，还用于基于所述数据读取请求，向所述数据选择器传输存储在所述当前第一存储位的第一数据。
这样，通过第二处理电路来触发对第一存储体的访问，可以根据指示标识选择是否要访问第一存储体，实现数据的读取过程。
一种可能的实施方式中，还包括：第二寄存器；所述第二寄存器与所述数据选择器连接；所述第二寄存器，用于存储所述前一第一存储位对应的第二数据；所述数据选择器，在基于所述指示标识，向数据读取端传输从所述当前第一存储位获取存储至所述当前第一存储位的第一数据，或者向所述数据读取端与所述前一第一存储位对应的第二数据时，用于：读取所述指示标识；响应于所述指示标识为第一数值，向所述数据读取端传输存储在所述当前第一存储位的第一数据第一数据；响应于所述指示标识为第二数 值，从所述第二寄存器读取与所述前一第一存储位对应的所述第二数据，并向所述数据读取端传输所述第二数据。
一种可能的实施方式中，所述第二寄存器还与所述第一存储体连接；所述第一存储体，在向所述数据选择器传输存储在所述当前第一存储位的第一数据时，还用于：向所述第二寄存器传输所述第一数据；所述第二寄存器，还用于在接收到所述第一存储体传输的第一数据后，将存储的第二数据更新为所述第一数据。
第二方面，本公开实施例还提供一种数据存储器，包括：第一存储体以及第二存储体；
所述第一存储体包括多个第一存储位；所述第二存储体包括与多个所述第一存储位分别对应的第二存储位；
所述数据存储器，用于响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据不同，将所述第一数据确定为待读取数据并读取。
一种可能的实施方式中，所述数据存储器，还用于响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据相同，将所述第二数据确定为待读取数据并读取。
第三方面，本公开实施例还提供一种数据存储方法，应用于数据存储器，所述数据存储器包括：第一存储体和第二存储体；所述第一存储体包括多个第一存储位；第二存储体包括多个与所述第一存储位分别对应的第二存储位；所述数据存储方法包括：响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据不同，在所述当前第一存储位中存储所述第一数据，并将与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值；其中，所述指示标识用于指示所述第一数据与所述第二数据是否相同。
一种可能的实施方式中，还包括：
所述数据存储器被构造为，响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据相同，将与所述当前第一存储位对应的第二存储位中的指示标识置为第二数值。
一种可能的实施方式中，所述数据存储器还包括：比较器；所述比较器的输出端分别与所述第一存储体和所述第二存储体连接；所述数据存储方法还包括：所述比较器 将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对；响应于所述第一数据和所述第二数据不同，向所述当前第一存储位传输所述第一数据，并控制与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值。
一种可能的实施方式中，还包括：所述比较器响应于所述第一数据和所述第二数据相同，控制与所述第一存储位对应的第二存储位中的指示标识置为第二数值。
一种可能的实施方式中，所述数据存储器还包括：第一寄存器；所述第一寄存器与所述比较器连接；所述数据存储方法还包括：所述第一寄存器存储所述前一第一存储位对应的第二数据；所述比较器将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对，包括：获取数据写入端传输的第一数据，以及从所述第一寄存器中读取所述前一第一存储位对应的第二数据；将所述数据写入端传输的所述第一数据和从所述第一寄存器中读取的第二数据进行比对。
一种可能的实施方式中，还包括：所述比较器响应于所述第一数据和所述第二数据不同，控制所述第一寄存器中存储的第二数据更新为所述第一数据。
一种可能的实施方式中，所述数据存储器还包括：第一处理电路；所述第一处理电路的输入端和所述比较器的输出端连接，所述第一处理电路的输出端和所述第一存储体连接；所述数据存储方法还包括：所述第一处理电路在接收到数据写入端传输的针对所述当前第一存储位的写使能信号、以及所述比较器传输的第一数据后，基于所述写使能信号将所述第一数据写入所述当前第一存储位。
第四方面，本公开实施例还提供一种数据读取方法，应用于数据存储器，所述数据存储器包括：第一存储体和第二存储体；所述第一存储体包括多个第一存储位；所述第二存储体包括与多个所述第一存储位分别对应的第二存储位；所述数据存储方法包括：
响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据不同，将所述第一数据确定为待读取数据并进行读取。
一种可能的实施方式中，所述方法还包括：响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据相同，将所述第二数据确定为待读取数据并读取。
第五方面，本公开实施例还提供一种芯片，包括如第一方面任一项所述的数据存储器、和/或第二方面所述的数据存储器。
第六方面，本公开实施例还提供一种计算机设备，包括：处理器、存储器，及如第一方面任一项所述的数据存储器，或者包括如第二方面任二项所述的数据存储器，或者包括如第五方面所述的芯片。
第七方面，本公开实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时，所述计算机设备执行如第三方面任一项所述的数据存储方法的步骤，或执行如第四方面任一项所述的数据读取方法的步骤。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，此处的附图被并入说明书中并构成本说明书中的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种数据存储器的示意图；
图2示出了本公开实施例所提供的另一种数据存储器的示意图；
图3示出了本公开实施例所提供的一种数据存储方法的流程图；
图4示出了本公开实施例所提供的一种数据读取方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实 施例，都属于本公开保护的范围。
经研究发现，在对图像数据进行存储的时候，通常会按照图像数据中各个像素点在图像中的位置，将各个像素点分别对应的像素信息依次存储至存储设备的各个存储位。这种数据存储方式使得在进行图像数据的存储时，图像数据的每次写入或读取，都需要依次访问用于存储多个像素点分别对应的像素信息的存储位，导致数据的写入和读取过程功耗较大的问题。
基于上述研究，本公开提供了一种数据存储器，其中设置有第一存储体和第二存储体，第一存储体包括多个第一存储位，第二存储体包括与多个所述第一存储位分别对应的第二存储位，在要存储至当前第一存储位的第一数据与前一第一存储位对应的第二数据不同时，在当前第一存储位中存储第一数据，并在与该当前第一存储位对应的第二存储位中存储对应的指示标识，该指示标识能够指示是否要从对应的第一存储位读取第一数据。以这种方式，在待存储的图像数据中存在重复数据的情况下，能够减少数据写入过程中对第一存储体的访问，同时减少数据读取过程中对第一存储体的访问，降低数据写入和读取过程中的功耗。
针对现有技术所存在的缺陷，是发明人在经过实践并仔细研究后得出的结果，因此，上述问题的发现过程以及本公开针对上述问题所提出的解决方案，都应该是发明人对本公开做出的贡献。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
为便于对本实施例进行理解，首先对本公开实施例所公开的一种数据存储器进行详细介绍，本公开实施例提供的数据存储器可以应用于计算机设备中，计算机设备例如包括：终端设备或服务器或其它处理设备，终端设备可以为用户设备(User Equipment，UE)、移动设备、用户终端、终端、蜂窝电话、无绳电话、个人数字助理(Personal Digital Assistant，PDA)、手持设备、计算设备、车载设备、可穿戴设备等。该种数据存储器可以用于对各种数据的存储，如图像数据、音频数据、文本数据、其他格式的数据等。
参见图1所示，为本公开实施例提供的数据存储器的结构示意图，包括：第一存储体10以及第二存储体20。所述第一存储体10包括多个第一存储位；所述第二存储体20包括与多个所述第一存储位分别对应的第二存储位；
所述数据存储器被构造为，响应于待存储至当前第一存储位的第一数据与前一第 一存储位存储的第二数据不同，在所述当前第一存储位中存储所述第一数据，并将与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值；
其中，所述指示标识用于指示所述第一数据与所述第二数据是否相同。
在本公开另一实施例中，所述数据存储器，还用于响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据相同，将与所述当前第一存储位对应的第二存储位中的指示标识置为第二数值。
参见图2所示，本公开其他实施例中，数据存储器还可以包括下述至少一种：第一寄存器30、比较器40、第一处理电路50、第二寄存器60、数据选择器70、第二处理电路80。
下面对本公开实施例提供的数据存储器中的各部件(包括上述第一存储体10、第二存储体20、第一寄存器30、比较器40、第一处理电路50、第二寄存器60、数据选择器70、第二处理电路80)之间的连接关系、以及各部件的功能加以详细说明。
本公开实施例提供的第一存储体10例如包括：静态随机存取存储器(Static Random-Access Memory，SRAM)、随机存取存储器(random access memory，RAM)等中任一种。在第一存储体10中包括多个第一存储位；每个第一存储位对应一数据存储空间；每个数据存储空间对应至少一个数据存储地址；具体的可以根据实际的数据存储需求，为每个存储位确定数据存储空间的大小。
本公开各个实施例中，第一存储体10例如包括N个第一存储位，每个第一存储位均可以作为当前第一存储位；示例性的，假设当前第一存储位为N个第一存储位中的第i个第一存储位，则对应的前一第一存储位为第i-1个第一存储位。若当前第一存储位为第一存储体10中的首个第一存储位，则其不存在前一第一存储位。
在向第一存储体10写入待存储数据时，每个第一存储位用于存储该待存储数据中的一子数据；示例性的，若待存储数据为图像数据，则每一子数据包括图像数据中一个像素点对应的像素数据，如像素点的像素值等。
第二存储体20例如包括寄存器；示例性的，第二存储体20是由多个寄存器构成的寄存器堆；每个寄存器即对应一个第二存储位，每个第二存储位与一个第一存储位对应。每个寄存器能够存储预设数量比特位的数据，该数据即为对应第一存储位的指示标识。
在具体实施中，构成第二存储体20的寄存器堆中寄存器的数量，例如和第一存储 位的数量相同；可以使寄存器堆中的各个寄存器与对应的第一存储位采用相同的数据存储地址，通过同一数据存储地址，访问第一存储体10中的第一存储位、并访问与该第一存储位对应的第二存储位。
此处，指示标识指示第一数据与第二数据不相同的情况下，通过访问第一存储体10读取第一数据。在指示标识指示第一数据与第二数据相同时，例如可以是对已经读取到的前一第一存储位的第二数据进行复制。在其他示例中，也可以在连续对多个第一存储位对应的数据进行读取的过程中，将前一第一存储位对应的数据存储在一个单独的寄存器中，该寄存器中的数据随着当前第一存储位的变化而不断更新。在该种情况下，在指示标识指示第一数据与第二数据相同时，可以从该寄存器中读取前一第一存储位对应的第二数据。该寄存器即本公开实施例所述的第二寄存器60，具体的读取方式可以参见下述实施例对第二寄存器60的描述，在此不再赘述。
在本公开另一实施例中，数据存储器还可以包括：比较器40。其中，比较器40的输出端分别与第一存储体10和第二存储体20连接；比较器40用于将当前第一存储位对应的第一数据、和前一第一存储位对应的第二数据进行比对，响应于所述第一数据和所述第二数据不同，向当前第一存储位传输第一数据，并控制与当前第一存储位对应的第二存储位中的指示标识置为第一数值。
比较器40，还用于响应于所述第一数据和所述第二数据相同，控制与所述第一存储位对应的第二存储位中的指示标识置为第二数值。
示例性的，第一数值为1，也即若该指示标识为1，表征与该第二存储位对应的第一存储位中存储有数据；第二数值为0，也即若该指示标识为0，则表征与该第二存储位对应的第一存储位未存储数据(该第一存储位对应的存储空间可以为空，也可以是存储除待存储数据外的其他数据)，在该种情况下，由于当前第一存储位对应的第一数据与前一第一存储位对应的第二数据相同，因此可以直接将前一第一存储位对应的第二数据作为当前第一存储位的数据。
另外，本公开另一实施例中，数据存储器还包括：第一寄存器30。该第一寄存器30与比较器40连接。
所述第一寄存器30，用于存储所述前一第一存储位对应的第二数据；
所述比较器40，在将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对时，用于：获取数据写入端传输的第一数据，以及从所述第 一寄存器30中读取所述前一第一存储位对应的第二数据；将所述数据写入端传输的所述第一数据和从所述第一寄存器30中读取的第二数据进行比对。
所述比较器40，还用于响应于第一数据和所述第二数据不同，控制所述第一寄存器30中存储的第二数据更新为所述第一数据。
这样，在将待存储的数据写入的过程中，将多个第一存储位依次作为当前第一存储位，若要写入当前第一存储位的第一数据与其前一第一存储位对应的第二数据不同，则将第一数据写入到当前第一存储位，并控制第一寄存器30中存储的数据更新为该第一数据，用于将下一第一存储位作为当前存储位时进行数据写入；若要写入当前第一存储位的第一数据与前一第一存储位对应的第二数据相同，则不将第一数据写入当前第一存储位，同时由于第一数据和第二数据相同，也不需要对第一寄存器30中存储的数据进行更新。进而通过该种方式，在待存储数据中包括重复数据的情况下，能够减少对第一存储体10的访问，降低数据写入第一存储体10时的功耗。
在本公开另一实施例中，数据存储器还包括：第一处理电路50；
所述第一处理电路50的输入端和所述比较器40的输出端连接，所述第一处理电路50的输出端和所述第一存储体10连接；
所述第一处理电路50，用于在接收到数据写入端传输的针对所述当前第一存储位的写使能信号、以及所述比较器40传输的第一数据后，基于所述写使能信号将所述第一数据写入所述当前第一存储位。
此处，写使能信号中例如携带有当前第一存储位的数据存储地址；第一处理电路50在接收到写使能信号后，若接收到比较器40传输的第一数据，能够根据写使能信号中携带的数据存储地址访问当前第一存储位，并将第一数据存储至当前第一存储位。
示例性的，本公开实施例提供一种向数据存储器写入数据的具体过程，在数据存储器中的第一存储体10中包括N(N＞1)个第一存储位，第二存储体20中包括N个第二存储位，第一存储位和第二存储位一一对应。其中，与N个第一存储位分别对应的数据包括：a1～aN，数据的读入过程例如下：
(1)：针对第1个第一存储位：数据写入端将第1个第一存储位对应的数据a1传输给比较器40。此时第一寄存器30中的数据为空或者为预设数据，该预设数据例如为由m(m＞1)个1构成的数据，或者由m个0构成的数据。比较器40将数据a1与该预设数据进行比对，两者不一致，将数据a1传输给第一处理电路50；或者，比较器40 在从第一寄存器30中读取到的数据为空，将数据a1传输给第一处理电路50。第一处理电路50接收到数据写入端传输的写使能信号，根据写使能信号中携带的第1个第一存储位对应的数据存储地址，将数据a1写入到第1个第一存储位；比较器40还将第二存储体20中与第1个第一存储位对应的第1个第二存储位中的指示标识置为第一数值；另外，比较器40还将数据a1写入到第一寄存器30中。
(2)：针对第2个第一存储位：
数据写入端将第2个第一存储位对应的数据a2传输给比较器40。此时，第一寄存器30中存储有数据a1。比较器40会从第一寄存器30中读取数据a1，并将数据a1和数据a2进行比对。
若a1和a2不同，将数据a2传输给第一处理电路50。第一处理电路50接收到数据写入端传输的写使能信号，根据写使能信号中携带的第2个第一存储位对应的数据存储地址，将数据a2写入到第2个第一存储位。比较器40还会将第二存储体20中与第2个第一存储位对应的第2个第二存储位中的指示标识置为第一数值。另外，比较器40还将数据a2写入到第一寄存器30中，将第一寄存器30中的数据a1替换为a2。
(3)：针对第3个第一存储位：
数据写入端将第3个第一存储位对应的数据a3传输给比较器40。此时，第一寄存器30中存储有数据a2。比较器40会从第一寄存器30中读取数据a2，并将数据a2和数据a3进行比对。
若a2和a3相同，则将第二存储体20中与第3个第一存储位对应的第3个第二存储位的指示标识置为第二数值。
(4)针对第4个第一存储位：
数据写入端将第4个第一存储位对应的数据a4传输给比较器40。此时，第一寄存器30中存储有数据a2，由于a2和a3相同，认为a2即为a3，也即第一寄存器30中存储了第3个第一存储位对应的数据。比较器40会从第一寄存器30中读取数据a2，并将数据a2和数据a4进行比对。
若a2和a4相同，则将第二存储体20中与第4个第一存储位对应的第4个第二存储位的指示标识置为第二数值。
(5)：针对第5个第一存储位：
数据写入端将第5个第一存储位对应的数据a5传输给比较器40。此时，第一寄存器30中存储有数据a2，由于a2和a4相同，认为a2即为a4，也即第一寄存器30中存储了第4个第一存储位对应的数据。比较器40会从第一寄存器30中读取数据a2，并将数据a2和数据a5进行比对。
若a2和a5不同，则将数据a5传输给第一处理电路50。第一处理电路50接收到数据写入端传输的写使能信号，根据写使能信号中携带的第5个第一存储位对应的数据存储地址，将数据a5写入到第5个第一存储位。比较器40还会将与第5个第一存储位对应的第5个第二存储位中的指示标识置为第一数值。另外，比较器40还将数据a5写入到第一寄存器30中，将第一寄存器30中的数据a2替换为a5。
以此类推，向后续的第一存储位写入数据的方式与以上相同。
通过上述过程，可以实现将待存储数据存储至数据存储器中，并在该过程中，通过减少基于重复数据而产生的对第一存储体10的访问，来降低数据存储过程中的功耗。
在本公开另一实施例中，数据存储器还包括：数据选择器70。其中，所述数据选择器70的输入端分别与所述第一存储体10和所述第二存储体20连接；
所述数据选择器70用于从与当前第一存储位对应的第二存储位读取指示标识；基于所述指示标识，向数据读取端传输从所述当前第一存储位获取的存储至所述当前第一存储位的第一数据，或者向所述数据读取端传输与所述前一第一存储位对应的第二数据。
在具体实施中，在从数据存储器中读取数据的时候，数据选择器70能够根据第二存储位中存储的指示标识，确定向数据读取端传输从第一存储位获取的第一数据，或者向数据读取端传输与前一第一存储位对应的第二数据；此处，由于数据在存储的过程中，若当前第一存储位和前一第一存储位对应的数据相同，不会将当前第一存储位对应的第一数据存储至第一存储位中，因而，在需要读取与当前第一存储位对应的第一数据时，会直接将前一第一存储位对应的数据作为当前第一存储位对应的数据。若当前第一存储位和前一第一存储位对应的数据不同，则通过访问第一存储体10，获取当前第一存储位中存储的第一数据，并向数据读取端传输该第一数据。
在另一实施例中，在数据存储器中还包括第二处理电路80。
所述第二处理电路80分别与所述第一存储体10和所述第二存储体20连接；
所述第二处理电路80，用于在接收到所述数据读取端传输的针对所述当前第一存储位的读使能信号后，从与所述当前第一存储位对应的第二存储位中读取所述当前第一 存储位对应的指示标识，并响应于所述指示标识指示从所述当前第一存储位读取所述第一数据，向所述第一存储体10发送数据读取请求；
所述第一数据存储体10，还用于基于所述数据读取请求，向所述数据选择器70传输存储在所述当前第一存储位的第一数据。
此处，数据读取端向第二处理电路80传输的读使能信号中，携带有要读取的当前第一存储位的数据存储地址；与当前第一存储位对应的第二存储位具有相同的数据存储地址，因此，第二处理电路80能够根据该数据存储地址，访问第二存储体20，从第二存储体20中获取当前第一存储位对应的第二存储位中存储的指示标识。
若该指示标识指示从当前第一存储位读取第一数据，则向第一存储体10发送数据读取请求。该数据读取请求中，携带了当前第一存储位的数据存储地址；第一存储体10在接收到数据读取请求后，基于该数据存储地址，将当前第一存储位存储的第一数据发送给数据选择器70。
在一种可能的实施方式中，第二存储体20在向第二处理电路80传输指示标识的时候，还会将指示标识传输给数据选择器70，该指示标识作为对数据选择器70的触发信号，使得数据选择器70在接收到指示标识后，触发数据选择器70的工作，以向数据读取端传输从所述当前第一存储位获取的存储至所述当前第一存储位的第一数据，或者向所述数据读取端传输与所述前一第一存储位对应的第二数据。
在本公开另一实施例中，数据存储器还包括：第二寄存器60。
所述第二寄存器60与所述数据选择器70连接。
所述第二寄存器60，用于存储所述前一第一存储位对应的第二数据。
所述数据选择器70，在基于所述指示标识，向数据读取端传输从所述当前第一存储位获取的存储至所述当前第一存储位的第一数据，或者向所述数据读取端传输与所述前一第一存储位对应的第二数据时，用于：读取所述指示标识；响应于所述指示标识为第一数值，向所述数据读取端传输从所述第一存储体10获取的所述第一数据；响应于所述指示标识为第二数值，从所述第二寄存器60读取与所述前一第一存储位对应的所述第二数据，并向所述数据读取端传输所述第二数据。
在具体实施中，数据选择器70有两个数据输入端，分别为第一输入端和第二输入端；第一输入端和第一存储体10连接；第二输入端和第二寄存器60连接。
其中，在指示标识指示从当前第一存储位读取所述第一数据的情况下，数据选择器70通过第一输入端接收第一数据，并选通第一输入端和数据选择器70的数据输出端之间的数据传输通路，将第一数据传输给数据读取端。
在指示标识指示读取与所述前一第一存储位对应的第二数据的情况下，数据选择器70通过第二输入端接收第二寄存器60传输的第二数据，并选通第二输入端和数据选择器70的数据输出端之间的数据传输通路，将第二数据传输给数据读取端。
这样，若当前第一存储位对应的第一数据与前一第一存储位对应的第二数据相同，则不需要通过访问第一存储体10来获取与当前第一存储位对应的数据，从而能够减少数据读取过程中的功耗。
另一实施例中，所述第二寄存器60还与所述第一存储体10连接；
所述第一存储体10，在向所述数据选择器70传输存储在所述当前第一存储位的第一数据时，还用于：向所述第二寄存器60传输所述第一数据；
所述第二寄存器60，还用于在接收到所述第一存储体10传输的第一数据后，将存储的第二数据更新为所述第一数据。
这样，可以实现对第二寄存器60中存储数据的不断更新，以能够通过访问第二寄存器60来获取第二数据。由于访问寄存器所需要的能耗远远小于访问第一存储体10的能耗，因而可以减少数据读取过程中所需要的功耗。
示例性的，本公开实施例提供一种从数据存储器中读取数据的具体过程，与上述示例类似，在数据存储器中的第一存储体10中包括N个第一存储位，第二存储体20中包括N个第二存储位，第一存储位和第二存储位一一对应。其中，与N个第一存储位分别对应的数据包括：a1～aN，数据的读取过程例如下：
(1)：针对第1个第一存储位：数据读取端向第二处理电路80发送针对第1个第一存储位的读使能信号；第二处理电路80根据读使能信号中携带的数据存储地址，从第二存储体20中的第1个第二存储位中，读取与第1个第一存储位对应的指示标识。该指示标识为第一数值，指示要从第1个第一存储位中读取数据a1。第二处理电路80向第一存储体10发送数据读取请求。在该数据读取请求中携带了第1个第一存储位的数据存储地址。
第一存储体10在接收到数据读取请求后，根据数据存储地址，将第1个第一数据存储位中存储的数据a1传输给数据选择器70的第一输入端。
第二存储体20还将第1个第一存储位对应的指示标识发送给数据选择器70。数据选择器70根据该指示标识，选通第一输入端和数据输出端之间的数据传输通路，将数据a1传输给数据读取端。
第一存储体10还将数据a1传输给第二寄存器60，第二寄存器60保存数据a1。
(2)针对第2个第一存储位：数据读取端向第二处理电路80发送针对第2个第一存储位的读使能信号；第二处理电路80根据读使能信号中携带的数据存储地址，从第二存储体20中的第2个第二存储位中，读取与第2个第一存储位对应的指示标识。该指示标识为第一数值，指示要从第2个第一存储位中读取数据a2。第二处理电路80向第一存储体10发送数据读取请求。在该数据读取请求中携带了第2个第一存储位的数据存储地址。
第一存储体10在接收到数据读取请求后，根据数据存储地址，将第2个第一数据存储位中存储的数据a2传输给数据选择器70的第一输入端。
第二存储体20还将第2个第一存储位对应的指示标识发送给数据选择器70。数据选择器70根据该指示标识，选通第一输入端和数据输出端之间的数据传输通路，将数据a2传输给数据读取端。
第一存储体10还将数据a2传输给第二寄存器60，第二寄存器60将保存的数据a1替换为数据a2。
(3)针对第3个第一存储位：数据读取端向第二处理电路80发送针对第3个第一存储位的读使能信号；第二处理电路80根据读使能信号中携带的数据存储地址，从第二存储体20中的第3个第二存储位中，读取与第3个第一存储位对应的指示标识。该指示标识为第二数值，指示读取前一第一存储位，也即第2个第一存储位对应的数据a2，第二处理电路80结束本数据读取周期的工作，不再访问第一存储体10。
第二存储体20还将第3个第一存储位对应的指示标识发送给数据选择器70。数据选择器70根据该指示标识，选通第二输入端和数据输出端之间的数据传输通路，将第二寄存器60中存储的数据a2作为第3个第一存储位对应的数据传输给数据读取端。
(4)针对第4个第一存储位：数据读取端向第二处理电路80发送针对第4个第一存储位的读使能信号；第二处理电路80根据读使能信号中携带的数据存储地址，从第二存储体20中的第4个第二存储位中，读取与第4个第一存储位对应的指示标识。该指示标识为第二数值，指示读取前一第一存储位，也即第3个第一存储位对应的数据 a3，第二处理电路80结束本数据读取周期的工作，不再访问第一存储体10。
第二存储体20还将第4个第一存储位的指示标识发送给数据选择器70。数据选择器70根据该指示标识，选通第二输入端和数据输出端之间的数据传输通路，由于a2和a3相同，因此将第二寄存器60中存储的数据a2作为第4个第一存储位对应的数据传输给数据读取端。
(5)针对第5个第一存储位：数据读取端向第二处理电路80发送针对第5个第一存储位的读使能信号；第二处理电路80根据读使能信号中携带的数据存储地址，从第二存储体20中的第5个第二存储位中，读取与第5个第一存储位对应的指示标识。该指示标识为第一数值，指示要从第5个第一存储位中读取数据a5。第二处理电路80向第一存储体10发送数据读取请求。在该数据读取请求中携带了第5个第一存储位的数据存储地址。
第一存储体10在接收到数据读取请求后，根据数据存储地址，将第5个第一数据存储位中存储的数据a5传输给数据选择器70的第一输入端。
第二存储体20还将第5个第一存储位的指示标识发送给数据选择器70。数据选择器70根据该指示标识，选通第一输入端和数据输出端之间的数据传输通路，将数据a5传输给数据读取端。
第一存储体10还将数据a5传输给第二寄存器60，第二寄存器60将保存的数据a2替换为数据a5。
以此类推，从后续的第一存储位读取数据的方式与以上相同。
通过上述过程，可以在从存储数据中读取数据时，通过减少在读取重复数据时对第一存储体的访问，来降低数据读取过程中的功耗。
本领域技术人员可以理解，在具体实施方式的上述数据存储器中，各部件的连接关系和各自的功能并不对本公开实施例提供的数据存储器的结构构成任何限定，数据存储器的具体结构应当以其功能和可能的内在逻辑确定。
本公开另一实施例还提供另外一种数据存储器，包括：第一存储体以及第二存储体；
所述第一存储体包括多个第一存储位；所述第二存储体包括与多个所述第一存储位分别对应的第二存储位；
所述数据存储器，用于响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据不同，将所述第一数据确定为待读取数据并读取。
一种可能的实施方式中，所述数据存储器，还用于响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据相同，将所述第二数据确定为待读取数据并读取。
上述数据存储器的结构、以及具体逻辑功能可以参见上述图1至图2对应的实施例，在此不再赘述。
基于同一发明构思，本公开实施例中还提供了与数据存储器对应的数据存储方法和数据读取方法，由于本公开实施例中的方法解决问题的原理与本公开实施例上述数据存储器相似，因此方法的实施可以参见数据存储器的实施，重复之处不再赘述。
参照图3所示，为本公开实施例提供的一种数据存储方法的示意图，包括：
应用于数据存储器，所述数据存储器包括：第一存储体和第二存储体；所述第一存储体包括多个第一存储位；第二存储体包括多个与所述第一存储位对应的第二存储位；所述数据存储方法包括：
S301：所述数据存储器响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据不同，在所述当前第一存储位中存储所述第一数据；
S302：将对应第二存储位中的指示标识置为第一数值。
一种可能的实施方式中，还包括：
所述数据存储器被构造为响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据相同，将与所述当前第一存储位对应的第二存储位中的指示标识置为第二数值。
一种可能的实施方式中，所述数据存储器还包括：比较器；所述比较器的输出端分别与所述第一存储体和所述第二存储体连接；所述数据存储方法还包括：所述比较器将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对；响应于所述第一数据和所述第二数据不同，向所述当前第一存储位传输所述第一数据，并控制与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值。
一种可能的实施方式中，还包括：所述比较器响应于所述第一数据和所述第二 数据相同，控制与所述第一存储位对应的第二存储位中的指示标识置为第二数值。
一种可能的实施方式中，所述数据存储器还包括：第一寄存器；所述第一寄存器与所述比较器连接；所述数据存储方法还包括：所述第一寄存器存储所述前一第一存储位对应的第二数据；所述比较器将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对，包括：获取数据写入端传输的第一数据，以及从所述第一寄存器中读取所述前一第一存储位对应的第二数据；将所述数据写入端传输的所述第一数据和从所述第一寄存器中读取的第二数据进行比对。
一种可能的实施方式中，还包括：所述比较器响应于所述第一数据和所述第二数据不同，控制所述第一寄存器中存储的第二数据更新为所述第一数据。
一种可能的实施方式中，所述数据存储器还包括：第一处理电路；所述第一处理电路的输入端和所述比较器的输出端连接，所述第一处理电路的输出端和所述第一存储体连接；所述数据存储方法还包括：所述第一处理电路在接收到数据写入端传输的针对所述当前第一存储位的写使能信号、以及所述比较器传输的第一数据后，基于所述写使能信号将所述第一数据写入所述当前第一存储位。
如图4所示，本公开实施例提供的数据读取方法，应用于数据存储器，所述数据存储器包括：第一存储体和第二存储体；所述第一存储体包括多个第一存储位；所述第二存储体包括与多个所述第一存储位分别对应的第二存储位；所述数据存储方法包括：
S401：响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据不同，将所述第一数据确定为待读取数据。
S402：进行待读取数据的读取。
一种可能的实施方式中，所述方法还包括：响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据相同，将所述第二数据确定为待读取数据并读取。
一种可能的实施方式中，数据存储器还包括：第二处理电路；所述第二处理电路分别与所述第一存储体和所述第二存储体连接；所述数据读取方法还包括：所述第二处理电路在接收到所述数据读取端传输的针对所述当前第一存储位的读使能信号后，从与所述当前第一存储位对应的第二存储位中读取所述当前第一存储位对应的指示标识，并响应于所述指示标识指示从所述当前第一存储位读取所述第一数据，向所述第一存储 体发送数据读取请求；所述第一数据存储体基于所述数据读取请求，向所述数据选择器传输存储在所述当前第一存储位的第一数据。
一种可能的实施方式中，数据存储器还包括：第二寄存器；所述第二寄存器与所述数据选择器连接；所述第二寄存器存储有所述前一第一存储位对应的第二数据；所述数据读取方法还包括：所述数据选择器基于所述指示标识，向数据读取端传输从所述当前第一存储位获取存储至所述当前第一存储位的第一数据，或者向所述数据读取端与所述前一第一存储位对应的第二数据，包括：读取所述指示标识；响应于所述指示标识为第一数值，向所述数据读取端传输所述第一存储体传输所述第一数据；响应于所述指示标识为第二数值，从所述第二寄存器读取与所述前一第一存储位对应的所述第二数据，并向所述数据读取端传输所述第二数据。
一种可能的实施方式中，所述第二寄存器还与所述第一存储体连接；所述数据读取方法还包括：所述第一存储体，在向所述数据选择器传输存储在所述当前第一存储位的第一数据时，向所述第二寄存器传输所述第一数据；所述第二寄存器在接收到所述第一存储体传输的第一数据后，将存储的第二数据更新为所述第一数据。
本公开实施例还提供一种芯片，包括如本公开任一实施例所述的数据存储器。
本公开实施例还提供一种计算机设备，包括：处理器、存储器，及本公开任一实施例所述的数据存储器，或者包括如本公开实施例提供的芯片。
本公开实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时，所述计算机设备执行如本公开任一实施例所述的数据存储方法的步骤，或执行如本公开任一实施例所述的数据读取方法的步骤。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的数据存储方法或者数据读取方法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系 统和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上所述实施例，仅为本公开的具体实施方式，用以说明本公开的技术方案，而非对其限制，本公开的保护范围并不局限于此，尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本公开实施例技术方案的精神和范围，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (18)

  1. 一种数据存储器，其特征在于，包括：
    第一存储体，其包括多个第一存储位；
    第二存储体，其包括与多个所述第一存储位分别对应的第二存储位；
    其中，所述数据存储器被构造为，响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据不同，在所述当前第一存储位中存储所述第一数据，并将与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值；
    其中，所述指示标识用于指示所述第一数据与所述第二数据是否相同。
  2. 根据权利要求1所述的数据存储器，其特征在于，所述数据存储器，还用于响应于待存储至所述当前第一存储位的所述第一数据与所述前一第一存储位存储的所述第二数据相同，将与所述当前第一存储位对应的第二存储位中的指示标识置为第二数值。
  3. 根据权利要求1或2所述的数据存储器，其特征在于，还包括：比较器；
    所述比较器的输出端分别与所述第一存储体和所述第二存储体连接；
    所述比较器用于将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对；
    响应于所述第一数据和所述第二数据不同，向所述当前第一存储位传输所述第一数据，并控制与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值。
  4. 根据权利要求3所述的数据存储器，其特征在于，所述比较器，还用于响应于所述第一数据和所述第二数据相同，控制与所述第一存储位对应的第二存储位中的指示标识置为第二数值。
  5. 根据权利要求4所述的数据存储器，其特征在于，还包括：第一寄存器；
    所述第一寄存器与所述比较器连接；
    所述第一寄存器，用于存储所述前一第一存储位对应的第二数据；
    所述比较器，在将所述当前第一存储位对应的第一数据、和所述前一第一存储位对应的第二数据进行比对时，用于：获取数据写入端传输的第一数据，以及从所述第一寄 存器中读取所述前一第一存储位对应的第二数据；
    将所述数据写入端传输的所述第一数据和从所述第一寄存器中读取的所述第二数据进行比对。
  6. 根据权利要求5所述的数据存储器，其特征在于，所述比较器，还用于响应于所述第一数据和所述第二数据不同，控制所述第一寄存器中存储的第二数据更新为所述第一数据。
  7. 根据权利要求2-6任一项所述的数据存储器，其特征在于，还包括：第一处理电路；
    所述第一处理电路的输入端和所述比较器的输出端连接，所述第一处理电路的输出端和所述第一存储体连接；
    所述第一处理电路，用于在接收到所述数据写入端传输的针对所述当前第一存储位的写使能信号、以及所述比较器传输的第一数据后，基于所述写使能信号将所述第一数据写入所述当前第一存储位。
  8. 根据权利要求1-7任一项所述的数据存储器，其特征在于，还包括：数据选择器；
    所述数据选择器的输入端分别与所述第一存储体和所述第二存储体连接；
    所述数据选择器用于从与所述当前第一存储位对应的第二存储位读取所述指示标识；基于所述指示标识，向数据读取端传输从所述当前第一存储位获取的存储至所述当前第一存储位的第一数据，或者向所述数据读取端传输与所述前一第一存储位对应的第二数据。
  9. 根据权利要求8所述的数据存储器，其特征在于，还包括：第二处理电路；
    所述第二处理电路分别与所述第一存储体和所述第二存储体连接；
    所述第二处理电路，用于在接收到所述数据读取端传输的针对所述当前第一存储位的读使能信号后，从与所述当前第一存储位对应的第二存储位中读取所述当前第一存储位对应的指示标识，并响应于所述指示标识指示从所述当前第一存储位读取所述第一数据，向所述第一存储体发送数据读取请求；
    所述第一数据存储体，还用于基于所述数据读取请求，向所述数据选择器传输存储在所述当前第一存储位的第一数据。
  10. 根据权利要求9所述的数据存储器，其特征在于，还包括：第二寄存器；
    所述第二寄存器与所述数据选择器连接；
    所述第二寄存器，用于存储所述前一第一存储位对应的第二数据；
    所述数据选择器，在基于所述指示标识，向所述数据读取端传输从所述当前第一存储位获取的存储至所述当前第一存储位的第一数据，或者向所述数据读取端传输与所述前一第一存储位对应的第二数据时，用于：读取所述指示标识；响应于所述指示标识为第一数值，向所述数据读取端传输存储在所述当前第一存储位的第一数据；响应于所述指示标识为第二数值，从所述第二寄存器读取与所述前一第一存储位对应的所述第二数据，并向所述数据读取端传输所述第二数据。
  11. 根据权利要求10所述的数据存储器，其特征在于，所述第二寄存器还与所述第一存储体连接；
    所述第一存储体，在向所述数据选择器传输存储在所述当前第一存储位的第一数据时，还用于：向所述第二寄存器传输所述第一数据；
    所述第二寄存器，还用于在接收到所述第一存储体传输的所述第一数据后，将存储的所述第二数据更新为所述第一数据。
  12. 一种数据存储器，其特征在于，包括：
    第一存储体，其包括多个第一存储位；
    第二存储体，其包括与多个所述第一存储位分别对应的第二存储位；
    所述数据存储器，用于响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据不同，将所述第一数据确定为待读取数据并读取。
  13. 根据权利要求12所述的数据存储器，其特征在于，所述数据存储器，还用于响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据相同，将所述第二数据确定为 待读取数据并读取。
  14. 一种数据存储方法，其特征在于，应用于数据存储器，所述数据存储器包括：第一存储体和第二存储体；所述第一存储体包括多个第一存储位；第二存储体包括多个与所述第一存储位分别对应的第二存储位；所述数据存储方法包括：
    响应于待存储至当前第一存储位的第一数据与前一第一存储位存储的第二数据不同，在所述当前第一存储位中存储所述第一数据，并将与所述当前第一存储位对应的第二存储位中的指示标识置为第一数值；
    其中，所述指示标识用于指示所述第一数据与所述第二数据是否相同。
  15. 一种数据读取方法，其特征在于，应用于数据存储器，所述数据存储器包括：第一存储体和第二存储体；所述第一存储体包括多个第一存储位；所述第二存储体包括与多个所述第一存储位分别对应的第二存储位；所述数据存储方法包括：
    响应于待读取的当前第一存储位对应的第二存储位存储的指示标识表征所述当前第一存储位存储的第一数据与前一第一存储位存储的第二数据不同，将所述第一数据确定为待读取数据并进行读取。
  16. 一种芯片，其特征在于，包括如权利要求1至11或者12至13任一项所述的数据存储器。
  17. 一种计算机设备，其特征在于，包括：处理器、存储器，及如权利要求1至11任一项所述的数据存储器，或者包括如权利要求16所述的芯片。
  18. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时，所述计算机设备执行如权利要求14所述的数据存储方法的步骤，或执行如权利要求15所述的数据读取方法的步骤。
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Publication number Priority date Publication date Assignee Title
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040184328A1 (en) * 2003-03-18 2004-09-23 Renesas Technology Corp. Semiconductor integrated circuit capable of testing with small scale circuit configuration
CN102166886A (zh) * 2011-05-05 2011-08-31 珠海天威技术开发有限公司 耗材芯片及其数据读写方法、耗材容器
CN102831930A (zh) * 2012-08-20 2012-12-19 珠海天威技术开发有限公司 耗材芯片及耗材容器、耗材芯片的数据写入方法
CN111159061A (zh) * 2018-11-08 2020-05-15 三星电子株式会社 存储设备、存储设备的操作方法和控制存储设备的主机的操作方法
CN111312309A (zh) * 2020-01-10 2020-06-19 电子科技大学 一种提升铁电存储器读写次数的电路结构
CN111971660A (zh) * 2018-06-05 2020-11-20 拉姆伯斯公司 高速缓存动态随机存取存储器
CN113222807A (zh) * 2021-05-22 2021-08-06 上海阵量智能科技有限公司 数据存储器、数据存储、读取方法、芯片及计算机设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111596863B (zh) * 2020-05-20 2023-04-07 歌尔科技有限公司 一种数据读取方法、装置、设备及可读存储介质
CN112804532A (zh) * 2021-01-07 2021-05-14 苏州浪潮智能科技有限公司 一种图像数据获取方法、系统及相关装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040184328A1 (en) * 2003-03-18 2004-09-23 Renesas Technology Corp. Semiconductor integrated circuit capable of testing with small scale circuit configuration
CN102166886A (zh) * 2011-05-05 2011-08-31 珠海天威技术开发有限公司 耗材芯片及其数据读写方法、耗材容器
CN102831930A (zh) * 2012-08-20 2012-12-19 珠海天威技术开发有限公司 耗材芯片及耗材容器、耗材芯片的数据写入方法
CN111971660A (zh) * 2018-06-05 2020-11-20 拉姆伯斯公司 高速缓存动态随机存取存储器
CN111159061A (zh) * 2018-11-08 2020-05-15 三星电子株式会社 存储设备、存储设备的操作方法和控制存储设备的主机的操作方法
CN111312309A (zh) * 2020-01-10 2020-06-19 电子科技大学 一种提升铁电存储器读写次数的电路结构
CN113222807A (zh) * 2021-05-22 2021-08-06 上海阵量智能科技有限公司 数据存储器、数据存储、读取方法、芯片及计算机设备

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