WO2017024612A1 - 氧化物半导体tft基板的制作方法及其结构 - Google Patents

氧化物半导体tft基板的制作方法及其结构 Download PDF

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WO2017024612A1
WO2017024612A1 PCT/CN2015/087889 CN2015087889W WO2017024612A1 WO 2017024612 A1 WO2017024612 A1 WO 2017024612A1 CN 2015087889 W CN2015087889 W CN 2015087889W WO 2017024612 A1 WO2017024612 A1 WO 2017024612A1
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layer
island
oxide semiconductor
shaped
barrier layer
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French (fr)
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曹尚操
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an oxide semiconductor TFT substrate and a structure thereof.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • TFTs Thin Film Transistors
  • Oxide semiconductor TFT technology is currently a popular technology.
  • Oxide semiconductors have higher electron mobility, and compared to low temperature polysilicon (LTPS), oxide semiconductors have simple process and high compatibility with amorphous silicon processes, and can be applied to LCDs, OLEDs, and Flexible display (Flexible) and other fields, and compatible with high-generation production lines, can be applied to large, medium and small size display, with good application development prospects.
  • LTPS low temperature polysilicon
  • Oxide semiconductors have simple process and high compatibility with amorphous silicon processes, and can be applied to LCDs, OLEDs, and Flexible display (Flexible) and other fields, and compatible with high-generation production lines, can be applied to large, medium and small size display, with good application development prospects.
  • the structure of the existing mature oxide semiconductor TFT substrate is a structure having an etch-stopper layer (ESL).
  • ESL etch-stopper layer 1 to 5 illustrate the process flow of a conventional method for fabricating an oxide semiconductor TFT substrate.
  • the first step is to deposit a first metal layer on the substrate 100, using the first photomask pair first.
  • the metal layer is patterned to form the gate electrode 200; the second step is to deposit the gate insulating layer 300; the third step is to deposit an oxide semiconductor film, and the oxide film is patterned by a second mask to form an oxide Fourth semiconductor layer 400; fourth step is to deposit an etch stop layer 500, using a third mask to pattern the etch barrier layer 500; the fifth step is to deposit a second metal layer, using a fourth mask to the second metal layer Patterning is performed to form source/drain 600.
  • each of the other layers needs to pass through a complete photolithography process (including yellow light, etching, and stripping).
  • the process of patterning is performed, the number of masks required is large, the process flow is long, the production efficiency is low, and the production cost is high;
  • the oxide semiconductor layer 400 and the gate insulating layer 300, the etching barrier layer The interface of 500 is easily contaminated by the etching solution and the stripping solution, and there is a risk of deteriorating the performance of the TFT;
  • Source/drain 600 and oxide The semiconductor layer 400 has a small contact area, a large contact resistance, and a low on-state current of the TFT.
  • An object of the present invention is to provide a method for fabricating an oxide semiconductor TFT substrate, which can reduce the number of masks, reduce production cost, improve production efficiency, and increase the contact area between the source/drain of the TFT and the oxide semiconductor layer, and reduce Contact resistance increases the on-state current of the TFT.
  • Another object of the present invention is to provide an oxide semiconductor TFT substrate structure which has low production cost and high production efficiency, and has a large contact area between a source/drain of the TFT and the oxide semiconductor layer, and a small contact resistance, and the TFT has a small contact resistance.
  • the on-state current is higher.
  • the present invention first provides a method for fabricating an oxide semiconductor TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer using a first photomask to form a gate;
  • Step 2 sequentially depositing a gate insulating layer, an oxide semiconductor layer, and an etch barrier layer on the gate and the substrate;
  • Step 3 patterning the oxide semiconductor layer and the etch barrier layer by using a second halftone mask or a slit diffractive ray to form a stacked island-shaped oxide on the gate insulating layer above the gate a semiconductor layer and an island-shaped etch barrier layer, and further forming blind holes respectively on both sides of the island-shaped oxide semiconductor layer and the island-shaped etch barrier layer;
  • the depth of the blind via is greater than the thickness of the island-shaped etch barrier layer, and is smaller than the sum of the thickness of the island-shaped etch barrier layer and the island-shaped oxide semiconductor layer;
  • Step 4 depositing a second metal layer on the island-shaped etch barrier layer and the gate insulating layer, and patterning the second metal layer using a third mask to form a source/drain;
  • the source/drain contacts the island-shaped oxide semiconductor layer via a bottom surface of the blind via and a portion of the via wall.
  • the step 3 specifically includes:
  • Step 31 applying a photoresist on the etching barrier layer, exposing and developing the photoresist using a halftone mask or a slit diffractive mask to obtain a photoresist layer directly above the gate.
  • Each of the two sides of the photoresist layer has a recessed region, and the thickness of the photoresist layer in the recessed region is smaller than the thickness of the photoresist layer outside the recessed region;
  • Step 32 using the entire photoresist layer as a shielding layer, dry etching the etching barrier layer, and performing wet etching on the oxide semiconductor layer to form a stacked island-shaped oxide semiconductor layer and an island-shaped etching barrier layer;
  • Step 33 removing the photoresist layer located in the recessed region, and remaining remaining outside the recessed region Photoresist layer
  • Step 34 using the remaining photoresist layer as a shielding layer, dry etching the island etching barrier layer, and performing wet etching on the island-shaped oxide semiconductor layer to form an island-shaped oxide semiconductor layer and an island-shaped etching barrier layer respectively. Blind holes on both sides;
  • Step 35 removing the remaining photoresist layer.
  • the material of the island-shaped oxide semiconductor layer is IGZO.
  • the material of the island-shaped etch barrier layer is silicon oxide, silicon nitride or a combination of the two.
  • the material of the gate insulating layer is silicon oxide, silicon nitride or a combination of the two.
  • the material of the gate and the source/drain is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the step 1 deposits a first metal layer by a physical vapor deposition process, and the first metal layer is patterned by wet etching.
  • the step 2 sequentially deposits a gate insulating layer by a chemical vapor deposition process, deposits an oxide semiconductor layer by a sputtering process, and deposits an etch barrier layer by a chemical vapor deposition process.
  • the step 4 deposits a second metal layer by a physical vapor deposition process, and the second metal layer is patterned by wet etching.
  • An oxide semiconductor TFT substrate structure includes a substrate, a gate electrode disposed on the substrate, a gate insulating layer covering the gate electrode and the substrate, and a gate electrode layer disposed above the gate electrode a stacked island-shaped oxide semiconductor layer and an island-shaped etch barrier layer on the gate insulating layer, and a source/drain;
  • Each of the island-shaped oxide semiconductor layer and the island-shaped etch barrier layer is respectively provided with a blind hole, the depth of the blind hole is larger than the thickness of the island-shaped etch barrier layer, and is smaller than the island-shaped etch barrier layer and the island-shaped oxide semiconductor a sum of thicknesses of the layers; the source/drain contacts the island-shaped oxide semiconductor layer via a bottom surface of the blind via and a portion of the via walls.
  • the invention also provides a method for fabricating an oxide semiconductor TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer using a first photomask to form a gate;
  • Step 2 sequentially depositing a gate insulating layer, an oxide semiconductor layer, and an etch barrier layer on the gate and the substrate;
  • Step 3 patterning the oxide semiconductor layer and the etch barrier layer by using a second halftone mask or a slit diffractive ray to form a stacked island-shaped oxide on the gate insulating layer above the gate a semiconductor layer and an island-shaped etch barrier layer, and further forming blind holes respectively on both sides of the island-shaped oxide semiconductor layer and the island-shaped etch barrier layer;
  • the depth of the blind hole is greater than the thickness of the island-shaped etch barrier layer, and is smaller than the island-shaped etch barrier layer The sum of the thicknesses of the island-shaped oxide semiconductor layers;
  • Step 4 depositing a second metal layer on the island-shaped etch barrier layer and the gate insulating layer, and patterning the second metal layer using a third mask to form a source/drain;
  • the source/drain contacts the island-shaped oxide semiconductor layer via a bottom surface of the blind via and a portion of the via wall;
  • the step 3 specifically includes:
  • Step 31 applying a photoresist on the etching barrier layer, exposing and developing the photoresist using a halftone mask or a slit diffractive mask to obtain a photoresist layer directly above the gate.
  • Each of the two sides of the photoresist layer has a recessed region, and the thickness of the photoresist layer in the recessed region is smaller than the thickness of the photoresist layer outside the recessed region;
  • Step 32 using the entire photoresist layer as a shielding layer, dry etching the etching barrier layer, and performing wet etching on the oxide semiconductor layer to form a stacked island-shaped oxide semiconductor layer and an island-shaped etching barrier layer;
  • Step 33 removing the photoresist layer located in the recessed region, leaving a photoresist layer outside the recessed region;
  • Step 34 using the remaining photoresist layer as a shielding layer, dry etching the island etching barrier layer, and performing wet etching on the island-shaped oxide semiconductor layer to form an island-shaped oxide semiconductor layer and an island-shaped etching barrier layer respectively. Blind holes on both sides;
  • Step 35 removing the remaining photoresist layer
  • step 1 deposits a first metal layer by a physical vapor deposition process, and the first metal layer is patterned by wet etching;
  • the step 2 sequentially deposits a gate insulating layer by a chemical vapor deposition process, deposits an oxide semiconductor layer by a sputtering process, and deposits an etch barrier layer by a chemical vapor deposition process;
  • the step 4 deposits a second metal layer by a physical vapor deposition process, and the second metal layer is patterned by wet etching.
  • the present invention provides a method for fabricating an oxide semiconductor TFT substrate by continuously forming a gate insulating layer, an oxide semiconductor layer, and an etch barrier layer, using a halftone mask or slit diffraction.
  • the mask performs patterning treatment on the oxide semiconductor layer and the etch barrier layer, and first forms a stacked island-shaped oxide semiconductor layer and an island-shaped etch barrier layer, and then forms an island-shaped oxide semiconductor layer and an island-shaped etch barrier respectively.
  • the blind holes on both sides of the layer can reduce the number of masks, reduce the production cost, and improve the production efficiency; and the depth of the blind holes is larger than the thickness of the island-shaped etching barrier layer, smaller than the island-shaped etching barrier layer and the island-shaped oxide semiconductor layer.
  • the sum of the thicknesses, the source/drain contacts the island-shaped oxide semiconductor layer via the bottom surface of the blind via and the partial hole wall, and the contact area between the source/drain and the island-shaped oxide semiconductor layer can be increased, and the contact area can be reduced.
  • Contact resistance Increase the on-state current of the TFT.
  • An oxide semiconductor TFT substrate structure provided by the present invention is provided with a stacked island-shaped oxide semiconductor layer and an island-shaped etch barrier layer, and the island-shaped oxide semiconductor layer and the island-shaped etch barrier layer are respectively provided with one side a blind hole having a depth greater than a thickness of the island-shaped etch barrier layer, smaller than a sum of a thickness of the island-shaped etch barrier layer and the island-shaped oxide semiconductor layer, the source/drain passing through the bottom surface and the partial hole of the blind hole
  • the wall contacts the island-shaped oxide semiconductor layer, so that the oxide semiconductor TFT substrate has low production cost, high production efficiency, large contact area between the source/drain and the oxide semiconductor layer, small contact resistance, and opening of the TFT.
  • the state current is higher.
  • FIG. 5 are schematic diagrams showing first to fifth steps of a conventional method for fabricating an oxide semiconductor TFT substrate
  • FIG. 6 is a flow chart showing a method of fabricating an oxide semiconductor TFT substrate of the present invention.
  • Figure 7 is a schematic view showing the first step of the method for fabricating the oxide semiconductor TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a step 2 of a method of fabricating an oxide semiconductor TFT substrate of the present invention.
  • FIG. 13 are schematic views showing a step 3 of a method of fabricating an oxide semiconductor TFT substrate of the present invention.
  • Fig. 14 is a schematic view showing the step 4 of the method for fabricating the oxide semiconductor TFT substrate of the present invention and a schematic view showing the structure of the oxide semiconductor TFT substrate of the present invention.
  • the present invention provides a method for fabricating an oxide semiconductor TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 7, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned using a first common photomask to form a gate 2.
  • the first metal layer is deposited by a physical vapor deposition (PVD) process, and then the photoresist is coated, the photoresist is exposed, developed, and the first metal layer is patterned by wet etching. deal with.
  • PVD physical vapor deposition
  • the substrate 1 is a glass substrate.
  • the material of the first metal layer is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Step 2 As shown in Fig. 8, a gate insulating layer 3, an oxide semiconductor layer 4', and an etch barrier layer 5' are successively deposited on the gate 2 and the substrate 1.
  • the etching liquid and the stripping liquid which are formed by etching and etching each layer separately can be avoided as compared with the prior art.
  • the contamination of the contact interface of each layer improves the quality of the contact surface, thereby helping to ensure the performance of the TFT.
  • the step 2 sequentially deposits the gate insulating layer 3 by a chemical vapor deposition (CVD) process, deposits the oxide semiconductor layer 4' by a sputtering process, and deposits the etching stopper layer 5' by a chemical vapor deposition process.
  • CVD chemical vapor deposition
  • the material of the gate insulating layer 3 and the etch barrier layer 5' is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of both.
  • the material of the oxide semiconductor layer 4' is Indium Gallium Zinc Oxide (IGZO).
  • Step 3 referring to FIG. 9 to FIG. 13, the oxide semiconductor layer 4' and the etch stop layer 5' are patterned by using a second halftone mask or a slit diffractive ray, above the gate 2.
  • a stacked island-shaped oxide semiconductor layer 4 and an island-shaped etch barrier layer 5 are formed on the gate insulating layer 3, and blind holes 54 respectively formed on both sides of the island-shaped oxide semiconductor layer 4 and the island-shaped etch barrier layer 5 are formed. .
  • the depth of the blind hole 54 is greater than the thickness of the island-shaped etch barrier layer 5, and is smaller than the sum of the thickness of the island-shaped etch barrier layer 5 and the island-shaped oxide semiconductor layer 4, that is, the blind hole 54 not only penetrates the island-shaped etch barrier layer. 5. Further, the inside of the island-shaped oxide semiconductor layer 4 is further advanced.
  • step 3 specifically includes:
  • Step 31 as shown in FIG. 9, coating a photoresist on the etching stopper layer 5', and exposing and developing the photoresist using a halftone mask or a slit diffractive mask to obtain a gate electrode.
  • each side of the photoresist layer 6 has a recessed region, and the thickness of the photoresist layer 6 in the recessed region is smaller than the thickness of the photoresist layer 6 outside the recessed region.
  • Step 32 as shown in FIG. 10, the entire photoresist layer 6 is used as a shielding layer, and the etching stopper layer 5' is dry-etched successively, and the oxide semiconductor layer 4' is wet-etched to form a stacked island-shaped oxide semiconductor layer. 4 and an island-shaped etching barrier layer 5.
  • Step 33 As shown in FIG. 11, the photoresist layer 6 located in the recessed region is removed, and the photoresist layer 6 outside the recessed region remains.
  • Step 34 as shown in FIG. 12, the remaining photoresist layer 6 is used as a shielding layer, and the island is etched successively.
  • the barrier layer 5 is dry etched, and the island-shaped oxide semiconductor layer 4 is wet-etched to form blind vias 54 respectively located on both sides of the island-shaped oxide semiconductor layer 4 and the island-shaped etch barrier layer 5.
  • Step 35 as shown in FIG. 13, the remaining photoresist layer 6 is removed.
  • the island-shaped etch barrier layer 5, the island-shaped oxide semiconductor layer 4, and the island-shaped oxide semiconductor layer 4 and the island-shaped etch barrier layer 5 are respectively formed using only one halftone mask or slit diffractive mask.
  • the blind holes 54 on both sides reduce the number of masks, reduce production costs, and increase production efficiency.
  • Step 4 as shown in FIG. 14, depositing a second metal layer on the island-shaped etch barrier layer 5 and the gate insulating layer 3, and patterning the second metal layer using a third common mask. Source/drain 7 is formed.
  • the source/drain 7 contacts the island-shaped oxide semiconductor layer 4 via the bottom surface of the blind via 54 and a portion of the via hole, thereby increasing the contact area between the source/drain 7 and the island-shaped oxide semiconductor layer 4.
  • the contact resistance is reduced, and the on-state current of the TFT can be increased.
  • a second metal layer is deposited by a PVD process, then a photoresist is applied, the photoresist is exposed, developed, and the second metal layer is patterned by wet etching.
  • the material of the second metal layer is a stack combination of one or more of Mo, Ti, Al, and Cu.
  • the present invention further provides an oxide semiconductor TFT substrate structure including a substrate 1, a gate electrode 2 provided on the substrate 1, and a cover The gate electrode 2 and the gate insulating layer 3 of the substrate 1 , the stacked island-shaped oxide semiconductor layer 4 and the island-shaped etching barrier layer 5 and the source provided on the gate insulating layer 3 above the gate 2 /Drain 7.
  • a blind hole 54 is defined in each of the two sides of the island-shaped oxide semiconductor layer 4 and the island-shaped etch barrier layer 5, and the depth of the blind hole 54 is greater than the thickness of the island-shaped etch barrier layer 5, which is smaller than the island-shaped etch barrier layer 5.
  • the sum of the thicknesses of the island-shaped oxide semiconductor layers 4; the source/drain electrodes 7 contact the island-shaped oxide semiconductor layer 4 via the bottom surface of the blind vias 54 and a portion of the via walls.
  • the stacked island-shaped oxide semiconductor layer 4 and the island-shaped etch barrier layer 5, and the blind vias 54 can be formed using a halftone mask or a slit diffractive mask, so that the production cost of the oxide semiconductor TFT substrate Low and high production efficiency.
  • the depth of the blind via 54 is greater than the thickness of the island-shaped etch barrier layer 5, and is smaller than the sum of the thickness of the island-shaped etch barrier layer 5 and the island-shaped oxide semiconductor layer 4, and the source/drain electrodes 7 pass through the bottom surface of the blind via 54 And a part of the hole wall contacts the island-shaped oxide semiconductor layer 4, so that the contact area of the source/drain 7 and the oxide semiconductor layer 4 is large, the contact resistance is small, and the on-state current of the TFT is high.
  • the oxide semiconductor TFT substrate of the present invention is fabricated by continuously forming a gate insulating layer, an oxide semiconductor layer, and an etch barrier layer, using a halftone mask or The slit diffractive ray patterning the oxide semiconductor layer and the etch barrier layer, first forming a stacked island-shaped oxide semiconductor layer and an island-shaped etch barrier layer, and then forming the island-shaped oxide semiconductor layer and the island respectively
  • the etching of the blind holes on both sides of the barrier layer can reduce the number of masks, reduce the production cost, and improve the production efficiency; and the depth of the blind holes is larger than the thickness of the island-shaped etching barrier layer, smaller than the island-shaped etching barrier layer and the island-shaped oxidation
  • the sum of the thicknesses of the semiconductor layers, the source/drain contacts the island-shaped oxide semiconductor layer via the bottom surface of the blind via and the partial hole walls, and the contact area between the source/drain and the island-shaped oxide semiconductor layer can be increased.
  • An oxide semiconductor TFT substrate structure provided by the present invention is provided with a stacked island-shaped oxide semiconductor layer and an island-shaped etch barrier layer, and the island-shaped oxide semiconductor layer and the island-shaped etch barrier layer are respectively provided with one side a blind hole having a depth greater than a thickness of the island-shaped etch barrier layer, smaller than a sum of a thickness of the island-shaped etch barrier layer and the island-shaped oxide semiconductor layer, the source/drain passing through the bottom surface and the partial hole of the blind hole
  • the wall contacts the island-shaped oxide semiconductor layer, so that the oxide semiconductor TFT substrate has low production cost, high production efficiency, large contact area between the source/drain and the oxide semiconductor layer, small contact resistance, and opening of the TFT.
  • the state current is higher.

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Abstract

本发明提供一种氧化物半导体TFT基板的制作方法及其结构。该方法连续成膜栅极绝缘层(3)、氧化物半导体层(4')、及蚀刻阻挡层(5')，使用一道半色调光罩或狭缝衍射光罩对氧化物半导体层(4')与蚀刻阻挡层(5')进行图案化处理，先形成层叠的岛状氧化物半导体层(4)与岛状蚀刻阻挡层(5)，再形成分别位于岛状氧化物半导体层(4)与岛状蚀刻阻挡层(5)两侧的盲孔(54)，能减少光罩数量，降低生产成本，提高生产效率；且盲孔(54)的深度大于岛状蚀刻阻挡层(5)的厚度，小于岛状蚀刻阻挡层(5)与岛状氧化物半导体层(4)的厚度之和，能增大源/漏极(7)与岛状氧化物半导体层(4)的接触面积，减小接触电阻，提高TFT的开态电流。

Description

氧化物半导体TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种氧化物半导体TFT基板的制作方法及其结构。
背景技术
平面显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。
薄膜晶体管(Thin Film Transistor，TFT)是平面显示装置的重要组成部分。由于TFT可形成在玻璃基板或塑料基板上，通常作为开关部件和驱动部件用在诸如LCD、OLED等平面显示装置上。
氧化物半导体TFT技术是当前的热门技术。由于氧化物半导体具有较高的电子迁移率，而且相比低温多晶硅(Low Temperature Poly Silicon，LTPS)，氧化物半导体制程简单，与非晶硅制程相容性较高，可以应用于LCD、OLED、柔性显示(Flexible)等领域，且与高世代生产线兼容，可应用于大中小尺寸显示，具有良好的应用发展前景。
现有的较为成熟的氧化物半导体TFT基板的结构是具有刻蚀阻挡层(etch-stopper layer，ESL)的结构。图1至图5按先后顺序示意出了现有常见的氧化物半导体TFT基板的制作方法的工艺流程：第一步是在基板100上沉积第一金属层，使用第一道光罩对第一金属层进行图案化处理，形成栅极200；第二步是沉积栅极绝缘层300；第三步是沉积氧化物半导体膜，使用第二道光罩对氧化物半导体膜进行图案化处理，形成氧化物半导体层400；第四步是沉积蚀刻阻挡层500，使用第三道光罩对蚀刻阻挡层500进行图案化处理；第五步是沉积第二金属层，使用第四道光罩对第二金属层进行图案化处理，形成源/漏极600。
上述现有常见的氧化物半导体TFT基板的制作方法存在以下几个问题：一、除基板100外，其它各层分别需要使用一道光罩通过一次完整的光刻制程(包括黄光、蚀刻、剥离等工序)来进行图案化处理，所需的光罩数量较多，工序流程较长，生产效率较低，生产成本较高；二、氧化物半导体层400与栅极绝缘层300、蚀刻阻挡层500的界面容易受到蚀刻液、剥离液的污染，存在造成TFT性能下降的风险；三、源/漏极600与氧化物 半导体层400的接触面积较小，接触电阻较大，TFT的开态电流较低。
发明内容
本发明的目的在于提供一种氧化物半导体TFT基板的制作方法，能够减少光罩数量，降低生产成本，提高生产效率，增大TFT的源/漏极与氧化物半导体层的接触面积，减小接触电阻，提高TFT的开态电流。
本发明的另一目的在于提供一种氧化物半导体TFT基板结构，其生产成本低、生产效率高，TFT的源/漏极与氧化物半导体层的接触面积较大，接触电阻较小，TFT的开态电流较高。
为实现上述目的，本发明首先提供一种氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积第一金属层，使用第一道光罩对所述第一金属层进行图案化处理，形成栅极；
步骤2、在所述栅极与基板上依次连续沉积栅极绝缘层、氧化物半导体层、及蚀刻阻挡层；
步骤3、使用第二道半色调光罩或狭缝衍射光罩对所述氧化物半导体层与蚀刻阻挡层进行图案化处理，于栅极上方的栅极绝缘层上先形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，再形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和；
步骤4、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积第二金属层，使用第三道光罩对所述第二金属层进行图案化处理，形成源/漏极；
所述源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层。
所述步骤3具体包括：
步骤31、在所述蚀刻阻挡层上涂布光阻，使用半色调光罩或狭缝衍射光罩对所述光阻进行曝光、显影，得到位于所述栅极正上方的光阻层，所述光阻层的两侧分别具有一凹陷区域，位于凹陷区域内的光阻层的厚度小于位于凹陷区域以外的光阻层的厚度；
步骤32、以整个光阻层为遮蔽层，先后对蚀刻阻挡层进行干蚀刻，对氧化物半导体层进行湿蚀刻，形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层；
步骤33、去除位于所述凹陷区域内的光阻层，剩余位于凹陷区域以外 的光阻层；
步骤34、以剩余的光阻层为遮蔽层，先后对岛状蚀刻阻挡层进行干蚀刻，对岛状氧化物半导体层进行湿蚀刻，形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
步骤35、去除剩余的光阻层。
所述岛状氧化物半导体层的材料为IGZO。
所述岛状蚀刻阻挡层的材料为氧化硅、氮化硅或二者的组合。
所述栅极绝缘层的材料为氧化硅、氮化硅或二者的组合。
所述栅极与源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述步骤1通过物理气相沉积工艺沉积第一金属层，通过湿蚀刻对第一金属层进行图案化处理。
所述步骤2依次通过化学气相沉积工艺沉积栅极绝缘层、通过溅射工艺沉积氧化物半导体层、通过化学气相沉积工艺沉积蚀刻阻挡层。
所述步骤4通过物理气相沉积工艺沉积第二金属层，通过湿蚀刻对第二金属层进行图案化处理。
本发明提供的一种氧化物半导体TFT基板结构，其特征在于，包括基板、设于所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设于栅极绝缘层上的层叠的岛状氧化物半导体层与岛状蚀刻阻挡层、及源/漏极；
所述岛状氧化物半导体层与岛状蚀刻阻挡层的两侧分别设有一盲孔，所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和；所述源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层。
本发明还提供一种氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积第一金属层，使用第一道光罩对所述第一金属层进行图案化处理，形成栅极；
步骤2、在所述栅极与基板上依次连续沉积栅极绝缘层、氧化物半导体层、及蚀刻阻挡层；
步骤3、使用第二道半色调光罩或狭缝衍射光罩对所述氧化物半导体层与蚀刻阻挡层进行图案化处理，于栅极上方的栅极绝缘层上先形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，再形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与 岛状氧化物半导体层的厚度之和；
步骤4、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积第二金属层，使用第三道光罩对所述第二金属层进行图案化处理，形成源/漏极；
所述源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层；
其中，所述步骤3具体包括：
步骤31、在所述蚀刻阻挡层上涂布光阻，使用半色调光罩或狭缝衍射光罩对所述光阻进行曝光、显影，得到位于所述栅极正上方的光阻层，所述光阻层的两侧分别具有一凹陷区域，位于凹陷区域内的光阻层的厚度小于位于凹陷区域以外的光阻层的厚度；
步骤32、以整个光阻层为遮蔽层，先后对蚀刻阻挡层进行干蚀刻，对氧化物半导体层进行湿蚀刻，形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层；
步骤33、去除位于所述凹陷区域内的光阻层，剩余位于凹陷区域以外的光阻层；
步骤34、以剩余的光阻层为遮蔽层，先后对岛状蚀刻阻挡层进行干蚀刻，对岛状氧化物半导体层进行湿蚀刻，形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
步骤35、去除剩余的光阻层；
其中，所述步骤1通过物理气相沉积工艺沉积第一金属层，通过湿蚀刻对第一金属层进行图案化处理；
其中，所述步骤2依次通过化学气相沉积工艺沉积栅极绝缘层、通过溅射工艺沉积氧化物半导体层、通过化学气相沉积工艺沉积蚀刻阻挡层；
其中，所述步骤4通过物理气相沉积工艺沉积第二金属层，通过湿蚀刻对第二金属层进行图案化处理。
本发明的有益效果：本发明提供的一种氧化物半导体TFT基板的制作方法，通过连续成膜栅极绝缘层、氧化物半导体层、及蚀刻阻挡层，使用一道半色调光罩或狭缝衍射光罩对所述氧化物半导体层与蚀刻阻挡层进行图案化处理，先形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，再形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔，能够减少光罩数量，降低生产成本，提高生产效率；且所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和，源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层，能够增大源/漏极与岛状氧化物半导体层的接触面积，减小接触电阻， 提高TFT的开态电流。本发明提供的一种氧化物半导体TFT基板结构，设有层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，所述岛状氧化物半导体层与岛状蚀刻阻挡层的两侧分别设有一盲孔，所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和，源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层，使得该氧化物半导体TFT基板的生产成本低、生产效率高，源/漏极与氧化物半导体层的接触面积较大，接触电阻较小，TFT的开态电流较高。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1至图5分别为现有常见的氧化物半导体TFT基板的制作方法的第一步至第五步的示意图；
图6为本发明的氧化物半导体TFT基板的制作方法的流程图；
图7为本发明的氧化物半导体TFT基板的制作方法的步骤1的示意图；
图8为本发明的氧化物半导体TFT基板的制作方法的步骤2的示意图；
图9至图13为本发明的氧化物半导体TFT基板的制作方法的步骤3的示意图；
图14为本发明的氧化物半导体TFT基板的制作方法的步骤4的示意图暨本发明的氧化物半导体TFT基板结构的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6，本发明提供一种氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、如图7所示，提供一基板1，在该基板1上沉积第一金属层，使用第一道普通光罩对所述第一金属层进行图案化处理，形成栅极2。
具体地，该步骤1通过物理气相沉积(Physical Vapor Deposition，PVD)工艺沉积第一金属层，然后涂布光阻、对光阻进行曝光、显影，再通过湿蚀刻对第一金属层进行图案化处理。
所述基板1为玻璃基板。
所述第一金属层的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
步骤2、如图8所示，在所述栅极2与基板1上依次连续沉积栅极绝缘层3、氧化物半导体层4’、及蚀刻阻挡层5’。
由于所述栅极绝缘层3、氧化物半导体层4’、及蚀刻阻挡层5’连续成膜，相比于现有技术，能够避免因各层单独成膜、蚀刻造成的蚀刻液、剥离液对各层接触界面的污染，提高接触面质量，从而有助于保证TFT的性能。
具体地，该步骤2依次通过化学气相沉积(Chemical Vapor Deposition，CVD)工艺沉积栅极绝缘层3、通过溅射工艺沉积氧化物半导体层4’、通过化学气相沉积工艺沉积蚀刻阻挡层5’。
所述栅极绝缘层3与蚀刻阻挡层5’的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。所述氧化物半导体层4’的材料为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
步骤3、请参阅图9至图13，使用第二道半色调光罩或狭缝衍射光罩对所述氧化物半导体层4’与蚀刻阻挡层5’进行图案化处理，于栅极2上方的栅极绝缘层3上先形成层叠的岛状氧化物半导体层4与岛状蚀刻阻挡层5，再形成分别位于岛状氧化物半导体层4与岛状蚀刻阻挡层5两侧的盲孔54。
所述盲孔54的深度大于岛状蚀刻阻挡层5的厚度，小于岛状蚀刻阻挡层5与岛状氧化物半导体层4的厚度之和，即所述盲孔54不仅贯穿岛状蚀刻阻挡层5，还继续深入岛状氧化物半导体层4内部。
进一步地，该步骤3具体包括：
步骤31、如图9所示，在所述蚀刻阻挡层5’上涂布光阻，使用半色调光罩或狭缝衍射光罩对所述光阻进行曝光、显影，得到位于所述栅极2正上方的光阻层6，所述光阻层6的两侧分别具有一凹陷区域，位于凹陷区域内的光阻层6的厚度小于位于凹陷区域以外的光阻层6的厚度。
步骤32、如图10所示，以整个光阻层6为遮蔽层，先后对蚀刻阻挡层5’进行干蚀刻，对氧化物半导体层4’进行湿蚀刻，形成层叠的岛状氧化物半导体层4与岛状蚀刻阻挡层5。
步骤33、如图11所示，去除位于所述凹陷区域内的光阻层6，剩余位于凹陷区域以外的光阻层6。
步骤34、如图12所示，以剩余的光阻层6为遮蔽层，先后对岛状蚀刻 阻挡层5进行干蚀刻，对岛状氧化物半导体层4进行湿蚀刻，形成分别位于岛状氧化物半导体层4与岛状蚀刻阻挡层5两侧的盲孔54。
步骤35、如图13所示，去除剩余的光阻层6。
该步骤3仅使用一道半色调光罩或狭缝衍射光罩制得岛状蚀刻阻挡层5、岛状氧化物半导体层4、及分别位于岛状氧化物半导体层4与岛状蚀刻阻挡层5两侧的盲孔54，减少了光罩数量，降低了生产成本，提高了生产效率。
步骤4、如图14所示，在所述岛状蚀刻阻挡层5与栅极绝缘层3上沉积第二金属层，使用第三道普通光罩对所述第二金属层进行图案化处理，形成源/漏极7。
所述源/漏极7经由所述盲孔54的底面及部分孔壁接触所述岛状氧化物半导体层4，增大了源/漏极7与岛状氧化物半导体层4的接触面积，减小了接触电阻，能够提高TFT的开态电流。
具体地，该步骤4通过PVD工艺沉积第二金属层，然后涂布光阻、对光阻进行曝光、显影，再通过湿蚀刻对第二金属层进行图案化处理。
所述第二金属层的材料为Mo、Ti、Al、Cu中的一种或多种的堆栈组合。
在上述氧化物半导体TFT基板的制作方法的基础上，如图14所示，本发明还提供一种氧化物半导体TFT基板结构，包括基板1、设于所述基板1上的栅极2、覆盖所述栅极2与基板1的栅极绝缘层3、于所述栅极2上方设于栅极绝缘层3上的层叠的岛状氧化物半导体层4与岛状蚀刻阻挡层5、及源/漏极7。所述岛状氧化物半导体层4与岛状蚀刻阻挡层5的两侧分别设有一盲孔54，所述盲孔54的深度大于岛状蚀刻阻挡层5的厚度，小于岛状蚀刻阻挡层5与岛状氧化物半导体层4的厚度之和；所述源/漏极7经由所述盲孔54的底面及部分孔壁接触所述岛状氧化物半导体层4。
所述层叠的岛状氧化物半导体层4与岛状蚀刻阻挡层5、及所述盲孔54可使用一道半色调光罩或狭缝衍射光罩制得，使得氧化物半导体TFT基板的生产成本低、生产效率高。所述盲孔54的深度大于岛状蚀刻阻挡层5的厚度，小于岛状蚀刻阻挡层5与岛状氧化物半导体层4的厚度之和，源/漏极7经由所述盲孔54的底面及部分孔壁接触所述岛状氧化物半导体层4，使得源/漏极7与氧化物半导体层4的接触面积较大，接触电阻较小，TFT的开态电流较高。
综上所述，本发明的氧化物半导体TFT基板的制作方法，通过连续成膜栅极绝缘层、氧化物半导体层、及蚀刻阻挡层，使用一道半色调光罩或 狭缝衍射光罩对所述氧化物半导体层与蚀刻阻挡层进行图案化处理，先形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，再形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔，能够减少光罩数量，降低生产成本，提高生产效率；且所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和，源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层，能够增大源/漏极与岛状氧化物半导体层的接触面积，减小接触电阻，提高TFT的开态电流。本发明提供的一种氧化物半导体TFT基板结构，设有层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，所述岛状氧化物半导体层与岛状蚀刻阻挡层的两侧分别设有一盲孔，所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和，源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层，使得该氧化物半导体TFT基板的生产成本低、生产效率高，源/漏极与氧化物半导体层的接触面积较大，接触电阻较小，TFT的开态电流较高。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (15)

  1. 一种氧化物半导体TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积第一金属层，使用第一道光罩对所述第一金属层进行图案化处理，形成栅极；
    步骤2、在所述栅极与基板上依次连续沉积栅极绝缘层、氧化物半导体层、及蚀刻阻挡层；
    步骤3、使用第二道半色调光罩或狭缝衍射光罩对所述氧化物半导体层与蚀刻阻挡层进行图案化处理，于栅极上方的栅极绝缘层上先形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，再形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
    所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和；
    步骤4、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积第二金属层，使用第三道光罩对所述第二金属层进行图案化处理，形成源/漏极；
    所述源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层。
  2. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述步骤3具体包括：
    步骤31、在所述蚀刻阻挡层上涂布光阻，使用半色调光罩或狭缝衍射光罩对所述光阻进行曝光、显影，得到位于所述栅极正上方的光阻层，所述光阻层的两侧分别具有一凹陷区域，位于凹陷区域内的光阻层的厚度小于位于凹陷区域以外的光阻层的厚度；
    步骤32、以整个光阻层为遮蔽层，先后对蚀刻阻挡层进行干蚀刻，对氧化物半导体层进行湿蚀刻，形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层；
    步骤33、去除位于所述凹陷区域内的光阻层，剩余位于凹陷区域以外的光阻层；
    步骤34、以剩余的光阻层为遮蔽层，先后对岛状蚀刻阻挡层进行干蚀刻，对岛状氧化物半导体层进行湿蚀刻，形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
    步骤35、去除剩余的光阻层。
  3. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中， 所述岛状氧化物半导体层的材料为IGZO。
  4. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述岛状蚀刻阻挡层的材料为氧化硅、氮化硅或二者的组合。
  5. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述栅极绝缘层的材料为氧化硅、氮化硅或二者的组合。
  6. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述栅极与源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  7. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述步骤1通过物理气相沉积工艺沉积第一金属层，通过湿蚀刻对第一金属层进行图案化处理。
  8. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述步骤2依次通过化学气相沉积工艺沉积栅极绝缘层、通过溅射工艺沉积氧化物半导体层、通过化学气相沉积工艺沉积蚀刻阻挡层。
  9. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述步骤4通过物理气相沉积工艺沉积第二金属层，通过湿蚀刻对第二金属层进行图案化处理。
  10. 一种氧化物半导体TFT基板结构，包括基板、设于所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设于栅极绝缘层上的层叠的岛状氧化物半导体层与岛状蚀刻阻挡层、及源/漏极；
    所述岛状氧化物半导体层与岛状蚀刻阻挡层的两侧分别设有一盲孔，所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和；所述源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层。
  11. 一种氧化物半导体TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积第一金属层，使用第一道光罩对所述第一金属层进行图案化处理，形成栅极；
    步骤2、在所述栅极与基板上依次连续沉积栅极绝缘层、氧化物半导体层、及蚀刻阻挡层；
    步骤3、使用第二道半色调光罩或狭缝衍射光罩对所述氧化物半导体层与蚀刻阻挡层进行图案化处理，于栅极上方的栅极绝缘层上先形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层，再形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
    所述盲孔的深度大于岛状蚀刻阻挡层的厚度，小于岛状蚀刻阻挡层与岛状氧化物半导体层的厚度之和；
    步骤4、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积第二金属层，使用第三道光罩对所述第二金属层进行图案化处理，形成源/漏极；
    所述源/漏极经由所述盲孔的底面及部分孔壁接触所述岛状氧化物半导体层；
    其中，所述步骤3具体包括：
    步骤31、在所述蚀刻阻挡层上涂布光阻，使用半色调光罩或狭缝衍射光罩对所述光阻进行曝光、显影，得到位于所述栅极正上方的光阻层，所述光阻层的两侧分别具有一凹陷区域，位于凹陷区域内的光阻层的厚度小于位于凹陷区域以外的光阻层的厚度；
    步骤32、以整个光阻层为遮蔽层，先后对蚀刻阻挡层进行干蚀刻，对氧化物半导体层进行湿蚀刻，形成层叠的岛状氧化物半导体层与岛状蚀刻阻挡层；
    步骤33、去除位于所述凹陷区域内的光阻层，剩余位于凹陷区域以外的光阻层；
    步骤34、以剩余的光阻层为遮蔽层，先后对岛状蚀刻阻挡层进行干蚀刻，对岛状氧化物半导体层进行湿蚀刻，形成分别位于岛状氧化物半导体层与岛状蚀刻阻挡层两侧的盲孔；
    步骤35、去除剩余的光阻层；
    其中，所述步骤1通过物理气相沉积工艺沉积第一金属层，通过湿蚀刻对第一金属层进行图案化处理；
    其中，所述步骤2依次通过化学气相沉积工艺沉积栅极绝缘层、通过溅射工艺沉积氧化物半导体层、通过化学气相沉积工艺沉积蚀刻阻挡层；
    其中，所述步骤4通过物理气相沉积工艺沉积第二金属层，通过湿蚀刻对第二金属层进行图案化处理。
  12. 如权利要求11所述的氧化物半导体TFT基板的制作方法，其中，所述岛状氧化物半导体层的材料为IGZO。
  13. 如权利要求11所述的氧化物半导体TFT基板的制作方法，其中，所述岛状蚀刻阻挡层的材料为氧化硅、氮化硅或二者的组合。
  14. 如权利要求11所述的氧化物半导体TFT基板的制作方法，其中，所述栅极绝缘层的材料为氧化硅、氮化硅或二者的组合。
  15. 如权利要求11所述的氧化物半导体TFT基板的制作方法，其中，所述栅极与源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105679675B (zh) * 2016-01-25 2019-01-15 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
CN108206137A (zh) * 2016-12-16 2018-06-26 中华映管股份有限公司 薄膜晶体管及其制造方法
CN107195659B (zh) * 2017-05-27 2020-07-24 京东方科技集团股份有限公司 阵列基板的制作方法、阵列基板及显示装置
CN107664889B (zh) * 2017-09-14 2020-05-22 深圳市华星光电半导体显示技术有限公司 一种tft器件及液晶显示面板的静电保护电路
US11335789B2 (en) 2018-09-26 2022-05-17 Intel Corporation Channel structures for thin-film transistors
CN109346526A (zh) * 2018-10-19 2019-02-15 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板及显示装置
CN114420762B (zh) * 2020-10-28 2026-02-10 京东方科技集团股份有限公司 一种氧化物薄膜晶体管及其制作方法和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921143A (zh) * 2005-08-23 2007-02-28 株式会社半导体能源研究所 晶体管及使用它的显示装置、电子设备及半导体装置
JP2009016469A (ja) * 2007-07-03 2009-01-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
US20100148155A1 (en) * 2008-12-16 2010-06-17 Sungkyunkwan University Foundation For Corporate Collaboration Thin film transistor, method of forming the same and flat panel display device having the same
CN104037090A (zh) * 2014-06-19 2014-09-10 深圳市华星光电技术有限公司 氧化物薄膜晶体管结构的制作方法及氧化物薄膜晶体管结构
CN104037126A (zh) * 2014-05-16 2014-09-10 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置
CN104300003A (zh) * 2013-07-19 2015-01-21 索尼公司 薄膜晶体管及其制造方法以及电子设备

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578984B (zh) * 2012-07-26 2016-10-26 瀚宇彩晶股份有限公司 半导体元件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921143A (zh) * 2005-08-23 2007-02-28 株式会社半导体能源研究所 晶体管及使用它的显示装置、电子设备及半导体装置
JP2009016469A (ja) * 2007-07-03 2009-01-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
US20100148155A1 (en) * 2008-12-16 2010-06-17 Sungkyunkwan University Foundation For Corporate Collaboration Thin film transistor, method of forming the same and flat panel display device having the same
CN104300003A (zh) * 2013-07-19 2015-01-21 索尼公司 薄膜晶体管及其制造方法以及电子设备
CN104037126A (zh) * 2014-05-16 2014-09-10 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置
CN104037090A (zh) * 2014-06-19 2014-09-10 深圳市华星光电技术有限公司 氧化物薄膜晶体管结构的制作方法及氧化物薄膜晶体管结构

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