WO2017020354A1 - 源驱动晶片驱动电路以及液晶显示面板 - Google Patents

源驱动晶片驱动电路以及液晶显示面板 Download PDF

Info

Publication number
WO2017020354A1
WO2017020354A1 PCT/CN2015/087784 CN2015087784W WO2017020354A1 WO 2017020354 A1 WO2017020354 A1 WO 2017020354A1 CN 2015087784 W CN2015087784 W CN 2015087784W WO 2017020354 A1 WO2017020354 A1 WO 2017020354A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch tube
power supply
level
switch
buffer amplifier
Prior art date
Application number
PCT/CN2015/087784
Other languages
English (en)
French (fr)
Inventor
吴晶晶
熊志
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/888,750 priority Critical patent/US9886923B2/en
Publication of WO2017020354A1 publication Critical patent/WO2017020354A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a source driven wafer driving circuit and a liquid crystal display panel.
  • the liquid crystal display screen drives each pixel for display by a source driving wafer and a gate driving wafer.
  • the gate driving chip inputs an on signal to the first row of pixels to make the first row of pixels in a conductive state, and at this time, the source driving chip inputs a data signal to the first row of pixels, thereby “pointing” Bright" the first line of pixels.
  • the second row of pixels is scanned in the above manner until all the pixels on the liquid crystal panel are scanned, that is, one frame of scanning is completed. It can be understood that there is a certain time gap before a line is scanned until the next line starts scanning, and this time gap is called line blanking.
  • the technical problem to be solved by the embodiments of the present invention is to provide a source driving chip driving circuit. And the liquid crystal display panel can effectively reduce power consumption.
  • the present invention provides a source driving chip driving circuit, comprising: a blanking timer, a switching unit, a buffer amplifier, a level shifting circuit, and a switching device, wherein an output end of the blanking timer is connected to the switching unit a control terminal, an input end of the switch unit is connected to a power supply, an output end of the switch unit is connected to a power supply end of the buffer amplifier, the switch unit and a buffer amplifier are integrated in the source drive chip; a timer for generating a control signal, wherein the control signal is at a first level when line blanking or frame blanking, the control signal being at a second level when non-line blanking and non-frame blanking; An input end of the level shifting circuit is connected to an output end of the blanking timer, an output end of the level converting circuit is connected to a control end of the switching device, and an input end of the switching device is connected to the power supply An output end of the switching device is connected to a power terminal of the buffer amplifier; the level converting circuit is configured to
  • the level conversion circuit includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube, wherein the switch device is a fifth switch tube, and the control end of the first switch tube
  • the switch device is a fifth switch tube
  • the control end of the first switch tube For inputting a control signal generated by the blanking timer, an input end of the first switch tube is respectively connected to an output end of the third switch tube and a control end of the fourth switch tube, the first switch The output end of the tube is connected to the power supply, the control end of the second switch is used to input a control signal generated by the blanking timer, and the second switch
  • the input end of the fourth switch tube is connected to the output end of the fourth switch tube, the output end of the second switch tube is grounded, and the input end of the fourth switch tube is connected to the power supply
  • the input end of the second switch tube is connected to the output end of the fourth switch tube and the control end of the third switch tube to the control end of the fifth switch tube, and the fifth switch tube
  • the input end of the second switch tube and the output end of the fourth switch tube and the common end of the control end of the third switch tube output a low voltage, thereby causing the
  • the five switch tubes are turned on, and the switch unit is in an on state, so that the power supply source supplies power to the power supply end of the buffer amplifier through the switch unit.
  • the fifth switch tube is a field effect tube.
  • the present invention also provides a source driving chip driving circuit comprising: a blanking timer, a switching unit, and a buffer amplifier, wherein a buffer amplifier is integrated in the source driving chip, and an output terminal of the blanking timer is connected a control end of the switch unit, the input end of the switch unit is connected to a power supply, and an output end of the switch unit is connected to a power end of the buffer amplifier;
  • the blanking timer is configured to generate a control signal, wherein the control signal is at a first level when line blanking or frame blanking, and the control signal is a second power when non-line blanking and non-frame blanking level;
  • the switch unit is configured to be in an off state when the control signal is at the first level, so that the power supply cannot supply power to a power supply end of the buffer amplifier through the switch unit;
  • the control signal is at the second level, it is in an on state, so that the power supply source supplies power to the power supply end of the buffer amplifier through the switch unit.
  • the switch unit includes: a level conversion circuit and an output device, an input end of the level conversion circuit is connected to an output end of the blanking timer, and an output end of the level conversion circuit is connected to the a control end of the switching device, the input end of the switching device is connected to the power supply, and an output end of the switching device is connected to a power end of the buffer amplifier;
  • the level shifting circuit is configured to level-convert a control signal output by the blanking timer to obtain a conversion level adapted to the switching device;
  • the switching device is configured to receive the conversion level, and when the conversion level is the first level, is in an off state, so that the power supply cannot pass through the switching unit to the buffer amplifier
  • the power supply terminal supplies power; and, when the conversion level is the second level, is in an on state, so that the power supply source supplies power to the power supply terminal of the buffer amplifier through the switching unit.
  • the level conversion circuit includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube, wherein the switch device is a fifth switch tube, and the control end of the first switch tube
  • the switch device is a fifth switch tube
  • the control end of the first switch tube For losing Entering a control signal generated by the blanking timer, an input end of the first switch tube is respectively connected to an output end of the third switch tube and a control end of the fourth switch tube, where the first switch tube The output end is grounded, the input end of the third switch tube is connected to the power supply, and the control end of the second switch tube is used to input a control signal generated by the blanking timer, and the input of the second switch tube
  • the end of the fourth switch tube is connected to the output end of the fourth switch tube, the output end of the second switch tube is grounded, and the input end of the fourth switch tube is connected to the power supply.
  • the input end of the second switch tube is connected to the output end of the fourth switch tube and the control end of the third switch tube to the control end of the fifth switch tube, and the input end of the fifth switch tube Connecting the power supply, the output end of the fifth switch is connected to the power end of the buffer amplifier;
  • the input end of the second switch tube and the output end of the fourth switch tube and the common end of the control end of the third switch tube output the high voltage, thereby causing
  • the fifth switch is turned off, and the switch unit is in an off state, so that the power supply cannot supply power to the power supply end of the buffer amplifier through the switch unit;
  • the input end of the second switch tube and the output end of the fourth switch tube and the common end of the control end of the third switch tube output a low voltage, thereby causing the
  • the five switch tubes are turned on, and the switch unit is in an on state, so that the power supply source supplies power to the power supply end of the buffer amplifier through the switch unit.
  • the fifth switch tube is a field effect tube.
  • the switching unit is integrated within the source drive wafer.
  • the present invention also provides a liquid crystal display panel comprising: a first substrate, a liquid crystal layer and a second substrate, wherein the second substrate is provided with an active driving wafer driving circuit, and the source driving wafer driving circuit comprises: blanking timing And a buffer amplifier, wherein a buffer amplifier is integrated in the source driving chip, an output end of the blanking timer is connected to a control end of the switching unit, and an input end of the switching unit is connected to a power supply. An output end of the switch unit is connected to a power terminal of the buffer amplifier;
  • the blanking timer is configured to generate a control signal, wherein the control signal is at a first level when line blanking or frame blanking, and the control signal is a second power when non-line blanking and non-frame blanking level;
  • the switching unit is configured to be in an off state when the control signal is at the first level, such that the power supply cannot pass through the switching unit to a power terminal of the buffer amplifier And supplying power; and, when the control signal is at the second level, in an on state, so that the power supply source supplies power to the power supply terminal of the buffer amplifier through the switching unit.
  • the switch unit includes: a level conversion circuit and an output device, an input end of the level conversion circuit is connected to an output end of the blanking timer, and an output end of the level conversion circuit is connected to the a control end of the switching device, the input end of the switching device is connected to the power supply, and an output end of the switching device is connected to a power end of the buffer amplifier;
  • the level shifting circuit is configured to level-convert a control signal output by the blanking timer to obtain a conversion level adapted to the switching device;
  • the switching device is configured to receive the conversion level, and when the conversion level is the first level, is in an off state, so that the power supply cannot pass through the switching unit to the buffer amplifier
  • the power supply terminal supplies power; and, when the conversion level is the second level, is in an on state, so that the power supply source supplies power to the power supply terminal of the buffer amplifier through the switching unit.
  • the level conversion circuit includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube, wherein the switch device is a fifth switch tube, and the control end of the first switch tube
  • the switch device is a fifth switch tube
  • the control end of the first switch tube For inputting a control signal generated by the blanking timer, an input end of the first switch tube is respectively connected to an output end of the third switch tube and a control end of the fourth switch tube, the first switch The output end of the tube is connected to the power supply, the control end of the second switch is used to input a control signal generated by the blanking timer, and the second switch
  • the input end of the fourth switch tube is connected to the output end of the fourth switch tube, the output end of the second switch tube is grounded, and the input end of the fourth switch tube is connected to the power supply
  • the input end of the second switch tube is connected to the output end of the fourth switch tube and the control end of the third switch tube to the control end of the fifth switch tube, and the fifth switch tube
  • the input end of the second switch tube and the output end of the fourth switch tube and the common end of the control end of the third switch tube output the high voltage, thereby causing
  • the fifth switch is turned off, and the switch unit is in an off state, so that the power supply cannot supply power to the power supply end of the buffer amplifier through the switch unit;
  • the input end of the second switch tube and the fourth switch tube The output terminal and the common terminal of the control terminal of the third switch transistor output a low voltage, thereby causing the fifth switch transistor to be turned on, and the switch unit is in an on state, thereby causing the power supply source to pass through the switch unit Power is supplied to the power supply terminal of the buffer amplifier.
  • the fifth switch tube is a field effect tube.
  • the switching unit is integrated within the source drive wafer.
  • the blanking timer and the switching unit are set, wherein the blanking timer generates a first level when line blanking or frame blanking, and generates a second when non-line blanking and non-frame blanking Level, and input to the switch unit, so that at the first level, the switch unit is in an off state, so that the power supply cannot supply power to the power supply end of the buffer amplifier through the switch unit, and when line blanking or frame blanking is performed There is no quiescent current flowing through the buffer amplifier resulting in unnecessary power consumption.
  • FIG. 1 is a circuit diagram of an embodiment of a liquid crystal driving circuit of the prior art
  • FIG. 2 is a circuit diagram of an embodiment of a source drive wafer drive circuit of the present invention.
  • FIG. 3 is a circuit diagram of an embodiment of a source drive wafer drive circuit of the present invention.
  • FIG. 4 is a timing diagram of a source driving chip driving circuit control signal, a level shifting circuit signal, and a switching unit output signal of the present invention
  • Fig. 5 is a circuit diagram showing still another embodiment of the source drive chip drive circuit of the present invention.
  • FIG. 2 is a circuit diagram of an embodiment of a source driven wafer driving circuit of the present invention.
  • the source driving chip driving circuit of the embodiment includes a blanking timer 210, a switching unit 221, and a buffer amplifier 222.
  • the switching unit 221 and the buffer amplifier 222 are integrated in the source driving wafer 220.
  • the switch unit 221 may not be integrated in the source drive wafer 220.
  • the output end of the blanking timer 210 is connected to the control end of the switch unit 221, the input end of the switch unit 221 is connected to the power supply VCC, and the output end of the switch unit 221 is connected to the power supply end of the buffer amplifier 222.
  • the blanking timer 210 can be set to generate a first level in line blanking or frame blanking, and a second in non-line blanking and non-frame blanking.
  • the level is output to the switching unit 221 as a control signal of the switching unit 221.
  • the first level is a high level
  • the second level is a low level.
  • the first level may be a low level
  • the second level may be a high level. level.
  • the power supply VCC cannot supply power to the buffer amplifier 222 through the switching unit 221, so that the buffer amplifier 222 does not have a quiescent current, and power consumption does not occur.
  • the switch unit 221 is in an on state.
  • the power supply VCC supplies power to the buffer amplifier 222 through the switching unit 221, and data can be input to the scanned pixel through the buffer amplifier 222, and the pixel is "lighted".
  • the blanking timer and the switching unit are set, wherein the blanking timer generates a first level when line blanking or frame blanking, and generates a second when non-line blanking and non-frame blanking Level, and input to the switch unit, so that at the first level, the switch unit is in an off state, so that the power supply cannot supply power to the power supply end of the buffer amplifier through the switch unit, and when line blanking or frame blanking is performed There is no quiescent current flowing through the buffer amplifier resulting in unnecessary power consumption.
  • FIG. 3 is a circuit diagram of another embodiment of the source driving chip driving circuit of the present invention.
  • the source driving chip driving circuit of the present embodiment includes a blanking timer 310, a switching unit 321, and a buffer amplifier 322.
  • the switching unit 321 and the buffer amplifier 322 are integrated in the source driving chip 320.
  • the switch unit 221 may not be integrated in the source drive wafer 220.
  • the switching unit 321 includes: a level converting circuit 3211 and a switching device 3212.
  • the input end of the level converting circuit 3211 is connected to the output end of the blanking timer 310, and the output end of the level converting circuit 3211 is connected to the control end of the switching device 3212.
  • the input end of the switching device 3212 is connected to the power supply.
  • the output of the switching device is connected to the power supply terminal of the buffer amplifier 322.
  • the blanking timer 310 can be set to generate the first level in line blanking or frame blanking, in the non-line blanking and non-line.
  • the second level is generated when the frame is blanked, thereby generating the control signal Vin as shown in FIG. 4, and outputting the controller signal Vin signal to the level converting circuit 3211.
  • the first level is a high level
  • the second level is a low level.
  • the first level may be a low level
  • the second level may be a high level. level.
  • the level converting circuit 3211 After receiving the control signal Vin output from the blanking timer 310, the level converting circuit 3211 performs level shifting so that the signal Vout output from the level converting circuit 3211 can be adapted to the switching device 3212. For example, if the high level of the control signal Vin is 3.3V and the low level is 0V, after the level shifting, the level of the signal Vout output by the level conversion circuit 3211 is 5V at a high level, and the low level is -5V, etc. .
  • the signal Vout output from the level conversion circuit 3211 is input to the switching device 3212.
  • the signal Vaa output by the switching device and the signal of the level converting circuit 3211 are inverted. That is, when the signal Vout output from the level conversion circuit 3211 is at a high level, the switching device 3212 is turned off. At this time, the power supply VCC cannot supply power to the buffer amplifier 322 through the switching device 3212. Therefore, the buffer amplifier 322 does not have a quiescent current. There is no power consumption.
  • the switching device 3212 is in an on state. At this time, the power supply VCC supplies power to the buffer amplifier 322 through the switching device 3212, and data can be input to the scanned portion through the buffer amplifier 322. Pixels and "lights up" the pixels.
  • the blanking timer and the switching unit are set, wherein the blanking timer generates a first level when line blanking or frame blanking, and generates a second when non-line blanking and non-frame blanking Level, and input to the switch unit, so that at the first level, the switch unit is in an off state, so that the power supply cannot supply power to the power supply end of the buffer amplifier through the switch unit, and when line blanking or frame blanking is performed There is no quiescent current flowing through the buffer amplifier resulting in unnecessary power consumption.
  • FIG. 5 is a circuit diagram of still another embodiment of the source driving chip driving circuit of the present invention.
  • the source driving chip driving circuit of the present embodiment includes a blanking timer 310, a switching unit 321, and a buffer amplifier 322.
  • the switching unit 321 and the buffer amplifier 322 are integrated in the source driving chip 320.
  • the switch unit 221 may not be integrated in the source drive.
  • the wafer 220 is moved.
  • the switching unit 321 includes a level converting circuit 3211 and a switching device 3212.
  • the level converting circuit 321 includes a first switching transistor Q1, a second switching transistor Q2, a third switching transistor Q3, and a fourth switching transistor Q4.
  • the switching device 3212 It is the fifth switch tube Q5, and the fifth switch tube is a field effect tube.
  • the control end of the first switch tube Q1 is used to input the control signal generated by the blanking timer 310.
  • the input end of the first switch tube Q1 is respectively connected to the output end of the third switch tube Q3 and the control end of the fourth switch tube Q4.
  • the output end of a switch tube Q1 is grounded, the input end of the third switch tube Q3 is connected to the power supply, the control end of the second switch tube Q2 is used to input the control signal generated by the blanking timer 310, and the input end of the second switch tube Q2 Connect the output end of the fourth switch tube Q4 and the control end of the third switch tube Q3, the output end of the second switch tube Q2 is grounded, the input end of the fourth switch tube Q4 is connected to the power supply, and the input end of the second switch tube Q2
  • the control end of the fifth switch tube Q5 is connected to the output end of the fourth switch tube Q4 and the control end of the third switch tube Q3.
  • the input end of the fifth switch tube Q5 is connected to the power supply, and the
  • the blanking timer 310 can be set to generate the first level in line blanking or frame blanking, in the non-line blanking and non-line.
  • the second level is generated when the frame is blanked, thereby generating the control signal Vin as shown in FIG. 4, and outputting the controller signal Vin signal to the level converting circuit 3211.
  • the first level is a high level and the second level is a low level.
  • the level converting circuit 3211 After receiving the control signal Vin output from the blanking timer 310, the level converting circuit 3211 performs level shifting so that the signal Vout output from the level converting circuit 3211 can be adapted to the switching device 3212. For example, if the high level of the control signal Vin is 3.3V and the low level is 0V, after the level shifting, the level of the signal Vout output by the level conversion circuit 3211 is 5V at a high level, and the low level is -5V, etc. . Specifically, when the blanking timer 310 outputs a high level (first level), the first switching transistor Q1 is turned off, the second switching transistor Q2 is turned off, the third switching transistor Q3 is turned on, and the fourth switching transistor Q4 is turned on. Therefore, the high level is output. At this time, the fifth switching transistor Q5 is turned off, and the power supply VCC cannot supply power to the buffer amplifier 322 through the fifth switching transistor Q5. Therefore, the buffer amplifier 322 does not have a quiescent current, and no work is generated
  • the blanking timer 310 When the blanking timer 310 outputs a low level (second level), the first switching transistor Q1 is turned on, the second switching transistor Q2 is turned on, the third switching transistor Q3 is turned off, and the fourth switching transistor Q4 is turned off, thereby outputting Low Level, at this time, the fifth switch Q5 is turned on, and the power supply VCC supplies power to the buffer amplifier 322 through the fifth switch, and data can be input to the scanned pixel through the buffer amplifier 322, and the pixel is "lighted up". .
  • the blanking timer and the switching unit are set, wherein the blanking timer generates a first level when line blanking or frame blanking, and generates a second when non-line blanking and non-frame blanking Level, and input to the switch unit, so that at the first level, the switch unit is in an off state, so that the power supply cannot supply power to the power supply end of the buffer amplifier through the switch unit, and when line blanking or frame blanking is performed There is no quiescent current flowing through the buffer amplifier resulting in unnecessary power consumption.
  • the present invention also provides a liquid crystal display panel comprising: a first substrate, a liquid crystal layer and a second substrate, wherein the second substrate is provided with an active driving wafer driving circuit.
  • the source driving chip driving circuit is the source driving chip driving circuit as described above with reference to FIGS. 2 to 4, and details are not repeated herein.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种源驱动晶片（220,320）驱动电路以及液晶显示面板。所述源驱动晶片（220,320）驱动电路中，消隐定时器（210,310）的输出端连接开关单元（221,321）的控制端，开关单元（221,321）的输入端连接供电电源（VCC），开关单元（221,321）的输出端连接缓冲放大器（222,322）的电源端；消隐定时器（210,310）用于产生控制信号（Vin），其中，控制信号（Vin）在行消隐或者帧消隐时为第一电平，控制信号（Vin）在非行消隐以及非帧消隐时为第二电平；开关单元（221,321）用于在控制信号（Vin）为第一电平时，处于断开状态，从而使得供电电源（VCC）不能通过开关单元（221,321）向缓冲放大器（222,322）的电源端进行供电；以及，在控制信号（Vin）为第二电平时，处于导通状态，从而使得供电电源（VCC）通过开关单元（221,321）向缓冲放大器（222,322）的电源端进行供电。所述源驱动晶片（220,320）驱动电路以及液晶显示面板能够有效地减少功耗。

Description

源驱动晶片驱动电路以及液晶显示面板
本发明要求2015年08月04日递交的发明名称为“源驱动晶片驱动电路以及液晶显示面板”的申请号201510470829.2的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，特别涉及一种源驱动晶片驱动电路以及液晶显示面板。
背景技术
随着技术的发展，用户对视觉体验的要求越来越高，各种高清晰、大屏幕的电子产品越来越受欢迎。对应液晶面板而言，屏幕越大，分辨率越高，则功耗也自然越大。但是，当功耗越大，液晶面板的温度也会越高，从而影响液晶面板的工作的稳定性，而且，也不符合一直倡导的节能减排要求。
如图1所示，液晶显示屏是通过源驱动晶片和门驱动晶片来驱动每个像素进行显示的。当对第一行像素进行扫描时，门驱动芯片向第一行像素输入开启信号以使得第一行像素处于导通状态，此时源驱动晶片则向第一行像素输入数据信号，从而“点亮”第一行像素。第一行像素扫描完毕后，继续以上述的方式对第二行像素进行扫描，直到液晶面板上所有的行像素都扫描完毕，即完成了一帧的扫描。可以理解的是，一行扫描完毕到下一行开始扫描之前都有一定的时间间隙，而这段时间间隙被称为行消隐，同样地，一帧扫描结束到下一帧开始扫描之前也同样有一定的时间间隙，而这段时间间隙被称为帧消隐。在行消隐和帧消隐期间，源驱动晶片中的缓冲放大器是没有数据输出的，但是，由于现时源驱动晶片的设计原因，缓冲放大器在没有数据输出时依然存在静态电流，从而导致不必要的功耗浪费。
发明内容
本发明实施例所要解决的技术问题在于，提供一种源驱动晶片驱动电路以 及液晶显示面板，能够有效地减少功耗。
本发明提供了一种源驱动晶片驱动电路，包括：消隐定时器、开关单元、缓冲放大器、电平转换电路以及开关器件，其中，所述消隐定时器的输出端连接所述开关单元的控制端，所述开关单元的输入端连接供电电源，所述开关单元的输出端连接所述缓冲放大器的电源端，所述开关单元以及缓冲放大器集成在所述源驱动晶片内；所述消隐定时器用于产生控制信号，其中，所述控制信号在行消隐或者帧消隐时为第一电平，所述控制信号在非行消隐以及非帧消隐时为第二电平；所述电平转换电路的输入端连接所述消隐定时器的输出端，所述电平转换电路的输出端连接所述开关器件的控制端，所述开关器件的输入端连接所述供电电源，所述开关器件的输出端连接所述缓冲放大器的电源端；所述电平转换电路用于将所述消隐定时器输出的控制信号进行电平转换，以得到与所述开关器件适配的转换电平；所述开关器件用于接收所述转换电平，在所述转换电平为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述转换电平为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述电平转换电路包括第一开关管、第二开关管、第三开关管以及第四开关管，所述开关器件为第五开关管，所述第一开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第一开关管的输入端分别连接所述第三开关管的输出端以及所述第四开关管的控制端，所述第一开关管的输出端接地，所述第三开关管的输入端连接所述供电电源，所述第二开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第二开关管的输入端分别连接所述第四开关管的输出端以及所述第三开关管的控制端，所述第二开关管的输出端接地，所述第四开关管的输入端连接所述供电电源，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端连接所述第五开关管的控制端，所述第五开关管的输入端连接所述供电电源，所述第五开关管的输出端连接所述缓冲放大器的电源端；
所述控制信号为第一电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出所述高电压，从而导致所述第五开关管截止，所述开关单元处于断开状态，从而使得所述供电电源不能 通过所述开关单元向所述缓冲放大器的电源端进行供电；
所述控制信号为第二电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出低电压，从而导致所述第五开关管导通，所述开关单元处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述第五开关管为场效应管。
本发明还提供了一种源驱动晶片驱动电路，包括：消隐定时器、开关单元以及缓冲放大器，其中，缓冲放大器集成在所述源驱动晶片中，所述消隐定时器的输出端连接所述开关单元的控制端，所述开关单元的输入端连接供电电源，所述开关单元的输出端连接所述缓冲放大器的电源端；
所述消隐定时器用于产生控制信号，其中，所述控制信号在行消隐或者帧消隐时为第一电平，所述控制信号在非行消隐以及非帧消隐时为第二电平；
所述开关单元用于在所述控制信号为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述控制信号为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述开关单元包括：电平转换电路以及开关器件，所述电平转换电路的输入端连接所述消隐定时器的输出端，所述电平转换电路的输出端连接所述开关器件的控制端，所述开关器件的输入端连接所述供电电源，所述开关器件的输出端连接所述缓冲放大器的电源端；
所述电平转换电路用于将所述消隐定时器输出的控制信号进行电平转换，以得到与所述开关器件适配的转换电平；
所述开关器件用于接收所述转换电平，在所述转换电平为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述转换电平为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述电平转换电路包括第一开关管、第二开关管、第三开关管以及第四开关管，所述开关器件为第五开关管，所述第一开关管的控制端用于输 入所述消隐定时器产生的控制信号，所述第一开关管的输入端分别连接所述第三开关管的输出端以及所述第四开关管的控制端，所述第一开关管的输出端接地，所述第三开关管的输入端连接所述供电电源，所述第二开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第二开关管的输入端分别连接所述第四开关管的输出端以及所述第三开关管的控制端，所述第二开关管的输出端接地，所述第四开关管的输入端连接所述供电电源，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端连接所述第五开关管的控制端，所述第五开关管的输入端连接所述供电电源，所述第五开关管的输出端连接所述缓冲放大器的电源端；
所述控制信号为第一电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出所述高电压，从而导致所述第五开关管截止，所述开关单元处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；
所述控制信号为第二电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出低电压，从而导致所述第五开关管导通，所述开关单元处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述第五开关管为场效应管。
可选地，所述开关单元集成在所述源驱动晶片内。
本发明还提供了一种液晶显示面板，包括：第一基板、液晶层以及第二基板，所述第二基板上设置有源驱动晶片驱动电路，所述源驱动晶片驱动电路包括：消隐定时器、开关单元以及缓冲放大器，其中，缓冲放大器集成在所述源驱动晶片中，所述消隐定时器的输出端连接所述开关单元的控制端，所述开关单元的输入端连接供电电源，所述开关单元的输出端连接所述缓冲放大器的电源端；
所述消隐定时器用于产生控制信号，其中，所述控制信号在行消隐或者帧消隐时为第一电平，所述控制信号在非行消隐以及非帧消隐时为第二电平；
所述开关单元用于在所述控制信号为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行 供电；以及，在所述控制信号为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述开关单元包括：电平转换电路以及开关器件，所述电平转换电路的输入端连接所述消隐定时器的输出端，所述电平转换电路的输出端连接所述开关器件的控制端，所述开关器件的输入端连接所述供电电源，所述开关器件的输出端连接所述缓冲放大器的电源端；
所述电平转换电路用于将所述消隐定时器输出的控制信号进行电平转换，以得到与所述开关器件适配的转换电平；
所述开关器件用于接收所述转换电平，在所述转换电平为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述转换电平为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述电平转换电路包括第一开关管、第二开关管、第三开关管以及第四开关管，所述开关器件为第五开关管，所述第一开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第一开关管的输入端分别连接所述第三开关管的输出端以及所述第四开关管的控制端，所述第一开关管的输出端接地，所述第三开关管的输入端连接所述供电电源，所述第二开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第二开关管的输入端分别连接所述第四开关管的输出端以及所述第三开关管的控制端，所述第二开关管的输出端接地，所述第四开关管的输入端连接所述供电电源，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端连接所述第五开关管的控制端，所述第五开关管的输入端连接所述供电电源，所述第五开关管的输出端连接所述缓冲放大器的电源端；
所述控制信号为第一电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出所述高电压，从而导致所述第五开关管截止，所述开关单元处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；
所述控制信号为第二电平时，所述第二开关管的输入端与所述第四开关管 的输出端以及所述第三开关管的控制端的公共端输出低电压，从而导致所述第五开关管导通，所述开关单元处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
可选地，所述第五开关管为场效应管。
可选地，所述开关单元集成在所述源驱动晶片内。
上述的实施方式中，通过设置消隐定时器以及开关单元，其中，消隐定时器在行消隐或者帧消隐时产生第一电平，在非行消隐以及非帧消隐时产生第二电平，并输入到开关单元，使得在第一电平时，开关单元处于断开状态，从而使得供电电源不能通过开关单元向缓冲放大器的电源端进行供电，则在行消隐或者帧消隐时，不会有静态电流流过缓冲放大器而导致不必要的功耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术的液晶驱动电路一实施方式的电路图；
图2是本发明源驱动晶片驱动电路一实施方式的电路图；
图3是本发明源驱动晶片驱动电路一实施方式的电路图；
图4是本发明源驱动晶片驱动电路控制信号、电平转换电路信号以及开关单元输出信号的时序图；
图5是本发明源驱动晶片驱动电路再一实施方式的电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图2，图2是本发明源驱动晶片驱动电路一实施方式的电路图。本 实施方式的源驱动晶片驱动电路包括：消隐定时器210、开关单元221以及缓冲放大器222。在本实施方式中，开关单元221以及缓冲放大器222集成在源驱动晶片220中。在其它的实施方式中，开关单元221也可以不集成在源驱动晶片220。消隐定时器210的输出端连接开关单元221的控制端，开关单元221的输入端连接供电电源VCC，开关单元221的输出端连接缓冲放大器222的电源端。
由于行消隐和帧消隐都是周期固定的，所以，可以设置消隐定时器210在行消隐或者帧消隐产生第一电平，在非行消隐以及非帧消隐时产生第二电平，并将信号输出到开关单元221以作为开关单元221的控制信号。在本实施方式中，第一电平为高电平，第二电平为低电平，在其它的实施方式中，也可以令第一电平为低电平，第二电平为高电平。当控制信号为第一电平时，开关单元221处于断开状态。此时，供电电源VCC无法通过开关单元221向缓冲放大器222供电，所以，缓冲放大器222的不存在静态电流，也就不会产生功耗。而当控制信号为第二电平时，开关单元221处于导通状态。此时，供电电源VCC通过开关单元221向缓冲放大器222供电，数据可以通过缓冲放大器222输入到被扫描的像素点，并将像素点“点亮”。
上述的实施方式中，通过设置消隐定时器以及开关单元，其中，消隐定时器在行消隐或者帧消隐时产生第一电平，在非行消隐以及非帧消隐时产生第二电平，并输入到开关单元，使得在第一电平时，开关单元处于断开状态，从而使得供电电源不能通过开关单元向缓冲放大器的电源端进行供电，则在行消隐或者帧消隐时，不会有静态电流流过缓冲放大器而导致不必要的功耗。
请参阅图3，图3是本发明源驱动晶片驱动电路另一实施方式的电路图。本实施方式的源驱动晶片驱动电路包括：消隐定时器310、开关单元321以及缓冲放大器322。在本实施方式中，开关单元321以及缓冲放大器322集成在源驱动晶片320中。在其它的实施方式中，开关单元221也可以不集成在源驱动晶片220。其中，开关单元321包括：电平转换电路3211以及开关器件3212，电平转换电路3211的输入端连接消隐定时器310的输出端，电平转换电路3211的输出端连接开关器件3212的控制端，开关器件3212的输入端连接供电电源， 开关器件的输出端连接缓冲放大器322的电源端。
请一并参阅图4，由于行消隐和帧消隐都是周期固定的，所以，可以设置消隐定时器310在行消隐或者帧消隐产生第一电平，在非行消隐以及非帧消隐时产生第二电平，从而产生如图4中所示的控制信号Vin，并将控制器信号Vin信号输出到电平转换电路3211。在本实施方式中，第一电平为高电平，第二电平为低电平，在其它的实施方式中，也可以令第一电平为低电平，第二电平为高电平。
电平转换电路3211接收到消隐定时器310输出的控制信号Vin后，进行电平转换，使得电平转换电路3211输出的信号Vout能够和开关器件3212适配。例如，如果控制信号Vin的高电平是3.3V，低电平是0V，则通过电平转换后，电平转换电路3211输出的信号Vout的高电平时5V，低电平是-5V等等。
电平转换电路3211输出的信号Vout输入到开关器件3212。其中，开关器件输出的信号Vaa和电平转换电路3211的信号反相。即，在电平转换电路3211输出的信号Vout为高电平时，开关器件3212截止，此时，供电电源VCC无法通过开关器件3212向缓冲放大器322供电，所以，缓冲放大器322不存在静态电流，也就不会产生功耗。而电平转换电路3211输出的信号Vout为低电平时，开关器件3212处于导通状态，此时，供电电源VCC通过开关器件3212向缓冲放大器322供电，数据可以通过缓冲放大器322输入到被扫描的像素点，并将像素点“点亮”。
上述的实施方式中，通过设置消隐定时器以及开关单元，其中，消隐定时器在行消隐或者帧消隐时产生第一电平，在非行消隐以及非帧消隐时产生第二电平，并输入到开关单元，使得在第一电平时，开关单元处于断开状态，从而使得供电电源不能通过开关单元向缓冲放大器的电源端进行供电，则在行消隐或者帧消隐时，不会有静态电流流过缓冲放大器而导致不必要的功耗。
请参阅图5，图5是本发明源驱动晶片驱动电路再一实施方式的电路图。本实施方式的源驱动晶片驱动电路包括：消隐定时器310、开关单元321以及缓冲放大器322。在本实施方式中，开关单元321以及缓冲放大器322集成在源驱动晶片320中。在其它的实施方式中，开关单元221也可以不集成在源驱 动晶片220。开关单元321包括：电平转换电路3211以及开关器件3212，其中，电平转换电路321包括第一开关管Q1、第二开关管Q2、第三开关管Q3以及第四开关管Q4，开关器件3212为第五开关管Q5，第五开关管为场效应管。
第一开关管Q1的控制端用于输入消隐定时器310产生的控制信号，第一开关管Q1的输入端分别连接第三开关管Q3的输出端以及第四开关管Q4的控制端，第一开关管Q1的输出端接地，第三开关管Q3的输入端连接供电电源，第二开关管Q2的控制端用于输入消隐定时器310产生的控制信号，第二开关管Q2的输入端分别连接第四开关管Q4的输出端以及第三开关管Q3的控制端，第二开关管Q2的输出端接地，第四开关管Q4的输入端连接供电电源，第二开关管Q2的输入端与第四开关管Q4的输出端以及第三开关管Q3的控制端的公共端连接第五开关管Q5的控制端，第五开关管Q5的输入端连接供电电源，第五开关管Q5的输出端连接缓冲放大器322的电源端。
请一并参阅图4，由于行消隐和帧消隐都是周期固定的，所以，可以设置消隐定时器310在行消隐或者帧消隐产生第一电平，在非行消隐以及非帧消隐时产生第二电平，从而产生如图4中所示的控制信号Vin，并将控制器信号Vin信号输出到电平转换电路3211。在本实施方式中，第一电平为高电平，第二电平为低电平。
电平转换电路3211接收到消隐定时器310输出的控制信号Vin后，进行电平转换，使得电平转换电路3211输出的信号Vout能够和开关器件3212适配。例如，如果控制信号Vin的高电平是3.3V，低电平是0V，则通过电平转换后，电平转换电路3211输出的信号Vout的高电平时5V，低电平是-5V等等。具体地，当消隐定时器310输出高电平(第一电平)时，第一开关管Q1截止，第二开关管Q2截止，第三开关管Q3导通，第四开关管Q4导通，从而输出高电平，此时，第五开关管Q5截止，供电电源VCC不能通过第五开关管Q5向缓存放大器322供电，所以，缓冲放大器322的不存在静态电流，也就不会产生功耗。
当消隐定时器310输出低电平(第二电平)时，第一开关管Q1导通，第二开关管Q2导通，第三开关管Q3截止，第四开关管Q4截止，从而输出低 电平，此时，第五开关管Q5导通，供电电源VCC通过第五开关管向缓存放大器322供电，数据可以通过缓冲放大器322输入到被扫描的像素点，并将像素点“点亮”。
上述的实施方式中，通过设置消隐定时器以及开关单元，其中，消隐定时器在行消隐或者帧消隐时产生第一电平，在非行消隐以及非帧消隐时产生第二电平，并输入到开关单元，使得在第一电平时，开关单元处于断开状态，从而使得供电电源不能通过开关单元向缓冲放大器的电源端进行供电，则在行消隐或者帧消隐时，不会有静态电流流过缓冲放大器而导致不必要的功耗。
本发明还提供了一种液晶显示面板，包括：第一基板、液晶层以及第二基板，其中，第二基板上设置有源驱动晶片驱动电路。源驱动晶片驱动电路为如上述图2至图4所述的源驱动晶片驱动电路，此处不再重复一一赘述。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (13)

  1. 一种源驱动晶片驱动电路，其特征在于，包括：消隐定时器、开关单元、缓冲放大器、电平转换电路以及开关器件，其中，所述消隐定时器的输出端连接所述开关单元的控制端，所述开关单元的输入端连接供电电源，所述开关单元的输出端连接所述缓冲放大器的电源端，所述开关单元以及缓冲放大器集成在所述源驱动晶片内；
    所述消隐定时器用于产生控制信号，其中，所述控制信号在行消隐或者帧消隐时为第一电平，所述控制信号在非行消隐以及非帧消隐时为第二电平；
    所述电平转换电路的输入端连接所述消隐定时器的输出端，所述电平转换电路的输出端连接所述开关器件的控制端，所述开关器件的输入端连接所述供电电源，所述开关器件的输出端连接所述缓冲放大器的电源端；
    所述电平转换电路用于将所述消隐定时器输出的控制信号进行电平转换，以得到与所述开关器件适配的转换电平；
    所述开关器件用于接收所述转换电平，在所述转换电平为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述转换电平为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  2. 根据权利要求1所述的电路，其特征在于，所述电平转换电路包括第一开关管、第二开关管、第三开关管以及第四开关管，所述开关器件为第五开关管，所述第一开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第一开关管的输入端分别连接所述第三开关管的输出端以及所述第四开关管的控制端，所述第一开关管的输出端接地，所述第三开关管的输入端连接所述供电电源，所述第二开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第二开关管的输入端分别连接所述第四开关管的输出端以及所述第三开关管的控制端，所述第二开关管的输出端接地，所述第四开关管的输入端连接所述供电电源，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端连接所述第五开关管的控制端，所述第五开关管的输入端连接所述供电电源，所述第五开关管的输出端连接所述缓冲放大器的电源端；
    所述控制信号为第一电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出所述高电压，从而导致所述第五开关管截止，所述开关单元处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；
    所述控制信号为第二电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出低电压，从而导致所述第五开关管导通，所述开关单元处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  3. 根据权利要求2所述的电路，其特征在于，所述第五开关管为场效应管。
  4. 一种源驱动晶片驱动电路，其特征在于，包括：消隐定时器、开关单元以及缓冲放大器，其中，缓冲放大器集成在所述源驱动晶片中，所述消隐定时器的输出端连接所述开关单元的控制端，所述开关单元的输入端连接供电电源，所述开关单元的输出端连接所述缓冲放大器的电源端；
    所述消隐定时器用于产生控制信号，其中，所述控制信号在行消隐或者帧消隐时为第一电平，所述控制信号在非行消隐以及非帧消隐时为第二电平；
    所述开关单元用于在所述控制信号为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述控制信号为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  5. 根据权利要求4所述的电路，其特征在于，所述开关单元包括：电平转换电路以及开关器件，所述电平转换电路的输入端连接所述消隐定时器的输出端，所述电平转换电路的输出端连接所述开关器件的控制端，所述开关器件的输入端连接所述供电电源，所述开关器件的输出端连接所述缓冲放大器的电源端；
    所述电平转换电路用于将所述消隐定时器输出的控制信号进行电平转换，以得到与所述开关器件适配的转换电平；
    所述开关器件用于接收所述转换电平，在所述转换电平为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述转换电平为所述第二电平时，处于导 通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  6. 根据权利要求5所述的电路，其特征在于，所述电平转换电路包括第一开关管、第二开关管、第三开关管以及第四开关管，所述开关器件为第五开关管，所述第一开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第一开关管的输入端分别连接所述第三开关管的输出端以及所述第四开关管的控制端，所述第一开关管的输出端接地，所述第三开关管的输入端连接所述供电电源，所述第二开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第二开关管的输入端分别连接所述第四开关管的输出端以及所述第三开关管的控制端，所述第二开关管的输出端接地，所述第四开关管的输入端连接所述供电电源，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端连接所述第五开关管的控制端，所述第五开关管的输入端连接所述供电电源，所述第五开关管的输出端连接所述缓冲放大器的电源端；
    所述控制信号为第一电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出所述高电压，从而导致所述第五开关管截止，所述开关单元处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；
    所述控制信号为第二电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出低电压，从而导致所述第五开关管导通，所述开关单元处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  7. 根据权利要求6所述的电路，其特征在于，所述第五开关管为场效应管。
  8. 根据权利要求4所述的电路，其特征在于，所述开关单元集成在所述源驱动晶片内。
  9. 一种液晶显示面板，其特征在于，包括：第一基板、液晶层以及第二基板，所述第二基板上设置有源驱动晶片驱动电路，所述源驱动晶片驱动电路包括：消隐定时器、开关单元以及缓冲放大器，其中，缓冲放大器集成在所述源驱动晶片中，所述消隐定时器的输出端连接所述开关单元的控制端，所述开 关单元的输入端连接供电电源，所述开关单元的输出端连接所述缓冲放大器的电源端；
    所述消隐定时器用于产生控制信号，其中，所述控制信号在行消隐或者帧消隐时为第一电平，所述控制信号在非行消隐以及非帧消隐时为第二电平；
    所述开关单元用于在所述控制信号为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述控制信号为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  10. 根据权利要求9所述的显示面板，其特征在于，所述开关单元包括：电平转换电路以及开关器件，所述电平转换电路的输入端连接所述消隐定时器的输出端，所述电平转换电路的输出端连接所述开关器件的控制端，所述开关器件的输入端连接所述供电电源，所述开关器件的输出端连接所述缓冲放大器的电源端；
    所述电平转换电路用于将所述消隐定时器输出的控制信号进行电平转换，以得到与所述开关器件适配的转换电平；
    所述开关器件用于接收所述转换电平，在所述转换电平为所述第一电平时，处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；以及，在所述转换电平为所述第二电平时，处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  11. 根据权利要求10所述的显示面板，其特征在于，所述电平转换电路包括第一开关管、第二开关管、第三开关管以及第四开关管，所述开关器件为第五开关管，所述第一开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第一开关管的输入端分别连接所述第三开关管的输出端以及所述第四开关管的控制端，所述第一开关管的输出端接地，所述第三开关管的输入端连接所述供电电源，所述第二开关管的控制端用于输入所述消隐定时器产生的控制信号，所述第二开关管的输入端分别连接所述第四开关管的输出端以及所述第三开关管的控制端，所述第二开关管的输出端接地，所述第四开关管的输入端连接所述供电电源，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端连接所述第五开关管的控制端，所述第五 开关管的输入端连接所述供电电源，所述第五开关管的输出端连接所述缓冲放大器的电源端；
    所述控制信号为第一电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出所述高电压，从而导致所述第五开关管截止，所述开关单元处于断开状态，从而使得所述供电电源不能通过所述开关单元向所述缓冲放大器的电源端进行供电；
    所述控制信号为第二电平时，所述第二开关管的输入端与所述第四开关管的输出端以及所述第三开关管的控制端的公共端输出低电压，从而导致所述第五开关管导通，所述开关单元处于导通状态，从而使得所述供电电源通过所述开关单元向所述缓冲放大器的电源端进行供电。
  12. 根据权利要求11所述的显示面板，其特征在于，所述第五开关管为场效应管。
  13. 根据权利要求9所述的显示面板，其特征在于，所述开关单元集成在所述源驱动晶片内。
PCT/CN2015/087784 2015-08-04 2015-08-21 源驱动晶片驱动电路以及液晶显示面板 WO2017020354A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/888,750 US9886923B2 (en) 2015-08-04 2015-08-21 Driving circuit for source driving chips and liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510470829.2A CN105096862B (zh) 2015-08-04 2015-08-04 源驱动晶片驱动电路以及液晶显示面板
CN201510470829.2 2015-08-04

Publications (1)

Publication Number Publication Date
WO2017020354A1 true WO2017020354A1 (zh) 2017-02-09

Family

ID=54577154

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/087784 WO2017020354A1 (zh) 2015-08-04 2015-08-21 源驱动晶片驱动电路以及液晶显示面板

Country Status (3)

Country Link
US (1) US9886923B2 (zh)
CN (1) CN105096862B (zh)
WO (1) WO2017020354A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107508455A (zh) * 2017-08-25 2017-12-22 惠科股份有限公司 缓冲电路及其显示装置
CN108539973B (zh) * 2018-05-18 2019-12-31 深圳市华星光电技术有限公司 Tft-lcd显示器及其驱动电路、开关电源
CN108665844B (zh) * 2018-05-21 2021-05-14 京东方科技集团股份有限公司 显示装置及其驱动方法、驱动装置
CN113851067B (zh) * 2020-06-28 2023-07-04 京东方科技集团股份有限公司 充电电路、显示装置、可穿戴设备及显示驱动方法、装置
KR20220144449A (ko) * 2021-04-19 2022-10-27 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN113315477A (zh) * 2021-05-13 2021-08-27 深圳市时代速信科技有限公司 一种射频放大器及其控制方法
CN113380210B (zh) * 2021-06-22 2023-03-28 昆山龙腾光电股份有限公司 一种快速掉电电路和显示装置
CN113571001B (zh) * 2021-09-24 2022-01-14 惠科股份有限公司 显示装置及显示系统
CN114566130A (zh) * 2022-03-14 2022-05-31 重庆惠科金渝光电科技有限公司 开关控制电路和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1437175A (zh) * 2002-02-08 2003-08-20 夏普株式会社 显示装置及其驱动电路和驱动方法
US20110115541A1 (en) * 2009-11-19 2011-05-19 Integrated Device Technology, Inc. Apparatuses and methods for a level shifter with reduced shoot-through current
US20120032935A1 (en) * 2010-08-05 2012-02-09 Himax Technologies Limited Driving device of flat panel display and driving method thereof
TW201207804A (en) * 2010-08-04 2012-02-16 Himax Tech Ltd Driving device of flat panel display and driving method thereof
CN102568413A (zh) * 2010-11-30 2012-07-11 乐金显示有限公司 液晶显示设备及其驱动方法
CN103856198A (zh) * 2012-11-28 2014-06-11 上海华虹宏力半导体制造有限公司 电平转换器
CN103871346A (zh) * 2012-12-12 2014-06-18 三星显示有限公司 显示装置及其驱动方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1564715A3 (en) * 2004-02-12 2006-11-08 Seiko Epson Corporation Driving circuit and driving method for electro-optical device
TW200721841A (en) * 2005-11-29 2007-06-01 Novatek Microelectronics Corp Method for displaying non-specified resolution frame on panel
JP4988258B2 (ja) * 2006-06-27 2012-08-01 三菱電機株式会社 液晶表示装置及びその駆動方法
CN101471048B (zh) * 2007-12-27 2011-04-20 比亚迪股份有限公司 一种tft-lcd驱动电路及液晶显示装置
US8957882B2 (en) * 2010-12-02 2015-02-17 Samsung Display Co., Ltd. Gate drive circuit and display apparatus having the same
KR101878976B1 (ko) * 2011-07-07 2018-07-17 삼성디스플레이 주식회사 터치 센싱 표시 패널의 구동 방법 및 이를 수행하는 표시 장치
TWI498876B (zh) * 2012-10-12 2015-09-01 Orise Technology Co Ltd 具有省電機制的源極驅動裝置及其所應用的平面顯示器
CN104538000B (zh) * 2015-01-08 2018-03-02 北京集创北方科技股份有限公司 一种面板显示系统的视频流数据传输方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1437175A (zh) * 2002-02-08 2003-08-20 夏普株式会社 显示装置及其驱动电路和驱动方法
US20110115541A1 (en) * 2009-11-19 2011-05-19 Integrated Device Technology, Inc. Apparatuses and methods for a level shifter with reduced shoot-through current
TW201207804A (en) * 2010-08-04 2012-02-16 Himax Tech Ltd Driving device of flat panel display and driving method thereof
US20120032935A1 (en) * 2010-08-05 2012-02-09 Himax Technologies Limited Driving device of flat panel display and driving method thereof
CN102568413A (zh) * 2010-11-30 2012-07-11 乐金显示有限公司 液晶显示设备及其驱动方法
CN103856198A (zh) * 2012-11-28 2014-06-11 上海华虹宏力半导体制造有限公司 电平转换器
CN103871346A (zh) * 2012-12-12 2014-06-18 三星显示有限公司 显示装置及其驱动方法

Also Published As

Publication number Publication date
US9886923B2 (en) 2018-02-06
CN105096862B (zh) 2017-11-17
US20170162142A1 (en) 2017-06-08
CN105096862A (zh) 2015-11-25

Similar Documents

Publication Publication Date Title
WO2017020354A1 (zh) 源驱动晶片驱动电路以及液晶显示面板
WO2018040711A1 (zh) 移位寄存器及其中的驱动方法、栅极驱动电路和显示装置
WO2017206542A1 (zh) 移位寄存器及其操作方法、栅极驱动电路和显示装置
WO2018171137A1 (zh) Goa单元及其驱动方法、goa电路、显示装置
KR20170096023A (ko) 액정 디스플레이 디바이스를 위한 goa 회로
US10796780B2 (en) Shift register unit and driving method thereof, gate driving circuit and display apparatus
US8466908B2 (en) Display device having a bias control unit for dynamically biasing a buffer and method thereof
WO2022089067A1 (zh) 栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置
WO2021253570A1 (zh) 显示面板及栅极驱动电路驱动方法、显示装置
TWI460702B (zh) 顯示裝置及其移位暫存電路
TW200828221A (en) Liquid crystal display and display method of same
JP6513447B2 (ja) 半導体装置、電子機器及び制御方法
TWI392226B (zh) 運算放大器、顯示器之源極驅動器及其相關控制該運算放大器之方法
TW201340057A (zh) 驅動控制方法及相關源極驅動器
TWI453719B (zh) 閘極驅動器
US20130293451A1 (en) Liquid crystal display apparatus and source driving circuit thereof
US10679580B2 (en) Pixel circuit, driving method thereof and display panel
JP2009124689A (ja) レベルシフタ、表示画面駆動回路及び映像表示系統
US9761191B2 (en) Method for driving display apparatus and display apparatus
JP2021504757A (ja) 液晶表示パネル及びそのｅｏａモジュール
CN210378428U (zh) 一种控制电路及显示装置
JP2005062484A (ja) 表示装置、及び表示装置の駆動方法
TWI409782B (zh) 驅動一顯示器之方法及其相關顯示裝置
JP2006018149A (ja) 液晶表示装置
TWI428880B (zh) 動態偏壓驅動裝置及其方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14888750

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15900128

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15900128

Country of ref document: EP

Kind code of ref document: A1