TW201207804A - Driving device of flat panel display and driving method thereof - Google Patents

Abstract

A driving device and a driving method of a flat panel display are provided. The driving device includes a driving circuit, an output buffer, and a buffer control module. The driving circuit outputs a pixel data during a valid data period, and an input terminal of the output buffer receives the output of the source driving module. The buffer control module turns off the output buffer during a blanking data period, and turns on the output buffer during the valid data period in order to reduce power consumption of the output buffer, and maintain the image quality of the flat panel display.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a flat panel display, and more particularly to a flat panel display driving device. [Prior Art] In today's society, a wide variety of electronic products (such as notebook computers, mobile phones, and televisions) have applications for display devices, providing users with viewing status, information, and the like. Due to the low power consumption and small size of the flat panel display (FPD), the conventional cathode ray tube display (CRT) has been replaced. A flat panel display is a general name for the shape of its display panel, including a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and field emission. Flat display (fldd emissi〇n display, FED) and so on. In various types of flat panel displays, a plurality of female (gate) signals are used to match the data (source) signals to display images. As the size and resolution of the flat panel display increase, the load of the driving device when driving the display panel increases and the charge and discharge time thereof relatively decreases. Therefore, when designing the driving device, it is necessary to consider that the driving ability of the driving device output signal is small to meet the demand for an increase in size and resolution of the display panel. However, when the driving device charges the pixel capacitance of the display panel, it only needs to be in the transition state of the pixel signal (that is, the pixel is being charged 201207804)

U29-TW 34329twf.doc/I During discharge, sufficient drive capability is provided to accelerate the charge and discharge speed. When the pixel is already in a steady state (i.e., during the period in which the pixel is completed and discharged), or when the blank data of the pixel data is not required to be updated, the excess power is consumed in the driving device, thereby wasting energy. SUMMARY OF THE INVENTION The present invention provides a driving device for a flat panel display. The driving device turns off an output buffer during a blank data period, and activates an output buffer during an active data period, thereby reducing power consumption of the output buffer and maintaining The display quality of the flat panel display. In another aspect, the present invention provides a method for driving a flat panel display. The method turns off an output buffer during a blank data period and activates an output buffer during a valid data period to maintain display quality while reducing an output buffer. Energy consumption. The invention provides a driving device for a flat panel display, the driving device comprising a driving circuit, an output buffer and a buffer control module. The drive circuit outputs pixel data during the active data period, and the input of the output buffer is used to receive the output of the drive circuit. The buffer control module is configured to turn off the output buffer during blank data, and the buffer control module activates the output buffer during the active data period. In an embodiment of the present invention, the driving device may further include a timing controller that generates a system clock signal, and the buffer control module "T samples the data enable signal according to the system clock signal. In order to discriminate between the blank data period and the valid data period. 201207804

In one embodiment of the present invention, the driving device may further include a timing controller that generates a vertical synchronization signal, and the buffer control module can be vertically synchronized, During the front porch period and the back porch period, the blank data period and the valid data period are calculated. In an embodiment of the invention, the buffer control module includes a buffer control unit and a first buffer switch unit. During the blank data period, the buffer control unit adjusts the buffer switch signal to the first potential, and adjusts the buffer switch signal to the second potential during the valid data period. The first buffer switch unit is coupled to the buffer control unit to turn off or enable the output buffer based on the first potential or the second potential of the buffer switch signal. In an embodiment of the invention, the first buffer switch unit includes a first transistor, a first switch, and a first current source. The first end of the first transistor receives the system voltage, and the control end of the first transistor is coupled to the second end of the first electrode, and thereby generates a first switch. The first end of the first switch is lightly connected to the second end of the first transistor, the second end of the first switch is connected to the system voltage ' and the control end of the first switch receives the buffer switch signal. The supply end of the first current source is coupled to the third end of the first switch. When the buffer switch signal is the first potential, the first-on_first terminal and the second terminal thereof are turned on 'so that the first-switch voltage is equal to the system voltage, and when the buffer switch signal is the second potential, the first switch The first end is electrically coupled to the third end thereof such that the first switching voltage is a first normal bias value. In an embodiment of the invention, the output buffer described above includes an operational amplifier and a first-to-power switch. The non-inverting terminal of the operational amplifier can be used as the input terminal of the output buffer, and the inverting terminal of the operational amplifier is connected.

201207804 Jw29-TW 34329twf.doc/I The wheel end of the instrument and the wheel end of the buffer. The control terminal of the first switch receives the first-switch voltage, and the first power switch is connected to the system voltage, and the second end of the first power switch is coupled to the first power terminal of the large power supply. The first power switch is powered according to the first switch, or the operational amplifier 启动 is activated. In detail, when the first switch county is pressed, the first power switch is used to turn off the operational amplifier, and when the first power is the first normal bias value, the first power switch is used to start the operation of the rose. In an embodiment of the invention, the buffer control module further includes a second buffer switch unit connected to the buffer control unit, and the second buffer switch unit is configured to be turned off or activated according to the buffer switch signal. Output Buffer In one embodiment of the invention, the second buffer switch unit 上述* includes a first electrical body, a first switch, and a second current source. The first end of the second transistor receives the ground voltage, and the control end thereof is coupled to the second end of the second transistor, thereby generating a second switching voltage. The first end of the second switch is coupled to the second end of the second transistor, and the second end of the second switch is coupled to the ground voltage, and the control end of the second switch receives the buffer switch signal. The supply end of the second current source is coupled to the third end of the second switch. When the buffer switch signal is at the first potential, the first end of the second switch is turned on with the second end thereof, so that the second switch voltage is equal to the ground voltage. Moreover, when the buffer switch signal is at the second potential, the first end of the first switch is electrically connected to the third end thereof, so that the second switch electric dust is the second normal bias value. 201207804

Rvi-^\j χ0-0029-TW 34329twf.doc/I In one embodiment of the present invention, the above-mentioned wheel-out key guard includes two power switches, and the control terminal receives the second switch power, and the second The first end of the electrical switch is terminated to the second power terminal of the operational amplifier, and the second power switch turns off or starts the operational amplifier according to the second switching voltage. When the first-switch voltage (four), the second power switch is turned off

When the second normal bias value of the electric county is switched, the second electric switch is used to start the operational amplifier. From another point of view, the present invention proposes a driving method of a flat panel display, 'comprising the following steps. The drive circuit outputs pixel data during the active data period, and the input of the output buffer receives the output of the drive circuit. Also, the output buffer is turned off during the blank data period, and the output buffer is activated during the active data period. In an embodiment of the invention, the driving method described above further comprises the following steps. The data enable signal is sampled according to the system clock signal, and the blank data period and the valid data period are discriminated. In an embodiment of the present invention, the driving method further comprises the following steps: calculating and obtaining a blank data period and a valid data period according to the vertical synchronization signal and the front corridor. Based on the above, the embodiment of the present invention uses the timing controller pulse number or the h-synchronization county to calculate or secret, and the valid data in the signal is called the empty data_. And in the blank data buffer control module, the output buffer "low output" is consumed, and the buffer is controlled.

20120780 (29-^ 34329twfdoc/I group starts and maintains the driving capability of the output buffer so that it can drive the display panel normally] to maintain the display quality of the flat panel display. To make the above features and advantages of the present invention more obvious and understandable DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following is a detailed description of the exemplary embodiments of the present invention Wherever possible, the same reference numerals in the drawings and the embodiments of the the the the the the the the the the the the the the the the the the the the the the the the the State (or startup state), so as to provide sufficient driving capability at any time to quickly charge and discharge the display panel 16〇, so that the source driver 120 can quickly update the pixel data of a plurality of pixel circuits (eg, 165) as shown in FIG. 1 and FIG. 2 is a block diagram of the flat panel display 10, and FIG. 2 is a vertical sync signal %, a data enable signal plus, and an output buffer 140 offset. Please refer to the figure 丨, the flat panel display ίο includes a timing controller 110, a source driving stomach 12 〇 and a display panel (Panel). The source driver g 12 〇 includes a driving circuit (four) spot 'O' and an output buffer The number of 140 depends on the number of pixels possessed by the display of the mother bar scan line, and an output buffer 140 is taken as an example. Further, the display panel 16A of this example also utilizes the pixel circuit 165 corresponding to the output buffer 14A as For example. 201207804

-------0-0029-TW 34329twf.doc/I In this example, the timing controller receives the data signal D and the data enable signal DE to be displayed on the display panel 160, and converts the received signal. For the vertical synchronization signal VS and other signals, and to provide these signals to the source, the device 12 and other device components. The driving circuit 13 transmits the corresponding pixel data PD to the output buffer 14 in sequence according to the data signal D and the related signal transmitted by the timing controller 110. In conjunction with the timing of the scan lines, the output buffer 140 writes the pixel data PD into a corresponding pixel φ circuit (e.g., pixel circuit 165). The output buffer 140 receives sufficient bias voltage in this example to cause the output buffer 140 to be in an activated state at any time, and charges and discharges the pixel load (not shown) of the pixel circuit 165 according to the pixel data PD, thereby allowing the display panel to be displayed. 16〇 shows the image, and its detailed waveform flow is shown in Figure 2. Referring to Fig. 2, a frame period VT of the vertical sync signal vs has a switching period vsw, a back porch period VBP, a valid data period T2, and a front p〇rch period vfp. The vertical synchronization signal VS informs the driving circuit 130 that the image signal transmission of the 昼 面 (frame) has ended during the switching period VSW, and is ready to transmit the image signal of the next picture. This embodiment uses a high level to go back and forth. The pulse of the level is the VSW during its switching. When the VBP during the back corridor and the VFP during the front porch are the same image signal transmitted by the same side, the flat-panel display requires a preparation time. The data signal D (not shown) and the data enable signal DE will sequentially carry the same video signal in the VBP during the vestibule of the vertical sync signal vs. The controller 110 receives the data signal 201207804 according to the data enable signal DE

029-TW

34329twf.doc/I D, and the pixel data D is transmitted to the drive circuit 13A. The driving circuit converts the digital pixel data D into the analog pixel data pd, and transmits the pixel data PD to the output buffer 140. Further, in the present embodiment, the switching period VSW, the back corridor period VBP, and the front porch period VFP are collectively referred to as the blank data period T1. It can be seen from the data enable signal 0 £ that there is no valid data for the data signal d of T1 during the blank data period. That is, the drive circuit 130 does not provide a valid pixel data pD to the output buffer 140 during the blank data period T1. In the example shown in Figures 1 and 2, the output buffer 14 is always in the active state during the frame period ντ. At the active data period T2, the output buffer 140 in the active state can provide sufficient driving capability to quickly transfer the pixel material PD into the pixel circuit 165. However, when 空1 during the blank data period, the pixel data PD does not need to be updated or driven at this time, and the electric power is consumed in the output buffer 14〇 having sufficient driving capability, thus causing waste of energy. Thereby, the buffer control module 310 according to the first embodiment of the present invention turns off the output buffer 14A during the blank data period T1, thereby saving power consumption. And during the active data period T2, the buffer control module 310 will activate the output buffer 140, thereby maintaining the image quality of the display panel 16A, as shown in FIG. Figure 3 is a block diagram of a flat panel display in accordance with a first embodiment of the present invention. Referring to FIG. 3, the flat panel display 30 includes a timing control 110, a source driver 120, and a display panel 160. This embodiment is similar to the above embodiment, and therefore the same description will not be repeated here. 201207804

χ^-^ν,.Ο-0029-TW 34329twf.doc/I In the present embodiment, the 'source driver 120 can define the switching period VSW and the vestibule period VBP according to the vertical synchronization signal VS provided by the timing controller 11〇. And VFP during the front porch. For example, the source driver 120 can use the counter (or timer) to define the vestibule period VBP, the valid data period T2, and the front porch period VFP according to the phase of the vertical sync signal VS. In other embodiments, the source driver 120 can define the valid data period T2 and the blank data period T1 by detecting the data enable signal DE. The source driver 120 (which may also be referred to as the driving device 120 in the present embodiment) includes a driving circuit 130 and an output buffer 14

And a buffer control module 310. The drive circuit 13 outputs the pixel data PD at the time of the valid data period T2. The input of the output buffer 14A receives the output of the drive circuit 130, while the output of the output buffer 14 turns the display panel 160. The buffer control module 31 can calculate or determine the blank data period and the valid data in the frame period ντ by using the vertical sync signal vs or the data enable signal DE provided by the timing controller 110. T2 'and during the blank data period n, the buffer control group turns off (or disables) the buffer 14 轮, and activates (or enables) the output buffer 14 在 during the active data period T2. In the embodiment, the flat panel display 3 is used. Except for the display panel 16A, it can be collectively referred to as a driving device. In addition, the buffer control module i is disposed in the source driver m. In other embodiments, the buffer control group 31G can also be set in the timing. In other words, the buffer side group 31G can determine the plane according to the design requirements.

201207804 丨 29-TW 34329twf.doc/I The location of the display 30 is not necessarily embedded in the source driver 120, and the invention should not be limited thereto. For details of the actuation method and principle of the damper control module 31A, please refer to FIG. 4 is a waveform diagram of the vertical sync signal VS, the data enable signal DE, and the output buffer bias voltage according to the first embodiment of the present invention. Specifically, the data enable signal DE of FIG. 4 carries the image signals of the same side in a valid data period T2, and each picture is composed of pixel data of a plurality of scan lines, so the horizontal scanning time HT is In the embodiment, it represents the time required to update the pixel-before each scan line in the picture. In this example, a detailed description will be given. It is assumed that the facet of the embodiment has 1024 x 768 pixels, that is, 768 scan lines in each picture and each scan line has 1 〇 24 pixels, so the effective data period T2 consists of 768 horizontal scanning times HT. In addition, the buffer control module 310 can determine the blank data period T1 and the valid data period according to design requirements and various signals of the timing controller 110 (for example, the system clock signal CLK, the vertical synchronization signal VS, or the data enable signal de, etc.). T2, the invention should not be limited thereto. Referring to FIG. 3 and FIG. 4 simultaneously, in the embodiment, the buffer control module 31 can determine the blank data period T1 and the valid data period T2 ' to enable or disable the output buffer 14 according to the data enable signal DE. . In detail, the buffer control module 31 samples the data enable signal DE according to each pulse in the system clock signal CLK. When the result of the sampling determines that the data enable signal DE is at a high level, that is, the drive When the circuit 130 is updating the pixel data PD according to the data signal D, the buffer control module 310 immediately starts 12 201207804

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34329twf.doc/I The output buffer 140 is used to transfer the pixel data pd to the display panel 160. When the result of the above sampling determines that the data enable signal de is at a low level, and the sampling result at such a low level maintains at least one horizontal scanning time HT, it represents that the valid data period T2 has ended, that is, has entered the front porch period. The VFP/blank data period T1, so the buffer control module 310 turns off the output buffer 140, thereby saving power consumption. In another embodiment, the buffer control module 31 can also calculate and discriminate the blank data period τι and the valid data period T2 ' according to the vertical synchronization signal VS to enable or disable the output buffer mo. The buffer control module 310 calculates the phase according to the pulse of the vertical synchronization signal vs (ie, the switching period vsw), and uses the system clock signal CLK to calculate when the VBP/blank data period T1 enters the valid data period T2 by the corridor period. The output buffer 140 is switched from the off state to the activated state to maintain the image quality of the display panel. In addition, the buffer control module 31 can also use the system clock signal CLK to calculate the length of the effective data period T2 (in this embodiment, 768 horizontal scanning time Ητ), thereby The state of each state is switched to the off state, and thus the 'low power' is consumed. 'b. As shown in FIG. 5, FIG. 5 is a block diagram of the buffer control module 310 according to the first embodiment of the present invention. Referring to Fig. 5, the buffer group 310 includes a buffer control unit 51 and a second buffer switch unit 520 in this embodiment. The buffer control unit 510 determines/calculates based on the data enable signal DE or the vertical sync signal VS. Blank data period gate η and valid data Gu Yu 2. When the blank data is T1, the buffer control sheet 13

201207804,9 34329twf.doc/I Element 510 adjusts the buffer switch signal as the first time (as shown in Figure 4) is the first potential (the same potential), and during the valid data period Τ 2, the buffer BB unit 510 will be slow =^SSW is adjusted to the second potential (for example, low potential). Punch (4)-:==5 'The first buffer switch unit 520 is connected to the buffer = 11 to turn off or start the output buffer (10) according to the high or low potential of the buffer switch signal. Moreover, in this embodiment, the m mode is controlled. The group 31 〇 may further include a second buffer switch unit = 〇, which is connected to the buffer control unit 51G. The second buffer switch unit 530 is activated by (10) according to the high or low potential of the buffering_number Ssw, and is turned off. Output buffer ϋ H In detail, #moderate the shutdown signal Ssw, the same potential 'the first buffer (four) off unit 52G and the second buffer switch unit / element 530 control the output buffer | | 14G to make it off, and When the buffer switch signal Ssw is low, the first buffer switch unit 52A and the first buffer II switch unit 53G control the output buffer 14A to be in an activated state. The buffer control unit 510 can be based on various methods. The data enable signal DE or the vertical sync signal vs. signals are used to calculate and generate the buffer switch signal Ssw, and the first buffer switch unit 52 () and the second buffer switch unit 530 are activated according to the buffer switch signal gsw or Close control The buffer 140. For example, a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a phase locked loop (PLL), a microchip ( Microchip), application specific integrated circuit (ASIC), etc.

201207804 -------0-0029-TW 34329twf.doc/I implements the buffer control unit 510, and thus the present invention should not be limited to the above-described manner. The circuit structure of the first buffer switch unit 520, the second buffer switch unit 53A, and the output buffer 14A according to the embodiment of the present invention is described in detail herein, as shown in FIG. Figure 6 is a circuit diagram of a buffer control module 310 in accordance with a first embodiment of the present invention. Referring to FIG. 6, the first buffer switch unit 520 includes a first transistor μb and a first current source 610. The first transistor M1 can be implemented in the present embodiment by using a p-ehannel metal Qxide semiconductor field-effect transistor (P-MOSFET). The first end (eg, the source terminal) of the first transistor M1 receives the system voltage V dd , and the control terminal (eg, the gate terminal) of the first transistor M1 is coupled to the second end of the first transistor M1 (eg, the 汲 terminal And, thereby generating a first switching voltage V1. The first end of the first switch SW1 is coupled to the 汲 terminal of the first transistor M1, the second end of the first switch SW1 is coupled to the voltage Vdd, and the control end of the first switch SW1 receives the buffer switch signal Ssw. In addition, the supply end of the first current source 610 is coupled to the third end of the _ switch SW1. The other end of the first current source 610 is coupled to the ground voltage Vss. The second buffer switch unit 530 includes a second transistor M2, a second switch SW2, and a second current source 62〇β. In this embodiment, the second transistor M2 can utilize a germanium channel MOSFET (N_channd metal). Oxide semiconductor field-effect transistor, N-MOSFET, referred to as N-channel transistor. The first end of the second transistor M2 (for example, 15 201207804

»u29-TW

The 34329twf.doc/I source terminal) receives the ground voltage Vss, and its control terminal (e.g., the gate terminal) is coupled to the second terminal (e.g., not extreme) of the second transistor M2, thereby generating a second switching voltage V2. The first end of the second switch SW2 is coupled to the first end ' of the second transistor M2 and the second end of the second switch SW2 is connected to the ground voltage vss, and the control end of the second switch SW2 receives the buffer switch signal Ssw. In addition, the supply end of the second current source 620 is coupled to the third end of the second switch SW2. The other end of the second current source 620 is coupled to the system voltage Vd (the output buffer 140 includes an operational amplifier (〇p_AMp) 63〇, a first power switch 640, and a second power switch 65. The operational amplifier 63 is non-reverse. The phase terminal can be used as an input terminal of the output buffer 140 to receive the pixel data PD. The operational amplifier 630 #inverting terminal is coupled to the output terminal of the operational amplifier 63. The output terminal of the operational amplifier 630 serves as an output buffer 14 The output terminal outputs the pixel data 〇PD to the display panel 16〇. The first power switch 640 is exemplified by the P-channel transistor M3#, and the control terminal (such as the gate terminal) receives the first-level switch v-di-wei switch The first end of _ (the source terminal of the transistor M3) receives the system voltage, and the first power source is turned on, and the second end of the 640 (the end of the transistor M3 is not extreme) is reduced to the first power terminal of the operational amplification benefit (4) The second power switch 650 here takes the N-through as an example 'its control terminal (such as the gate terminal) receives the first end of the second power switch (4) (the voltage of the transistor M4 ==%, and the second power switch) The second end of (4) is connected to the second power of the operational amplifier 630 The second power supply terminal and the second power supply terminal are used to supply power to the operational amplifier 6

201207804 -0029-TW 34329twf.doc/I By the first time, when the buffer switch signal "3^ SSW is the local potential (that is, the first potential), the first end of the first switch SW1 and the second switch SW2 The two terminals are turned on, whereby the first switching voltage VI is equal to the system voltage vdd, and the second switching voltage V2 is equal to the ground voltage Vss. At this time, the first power switch 640 and the first power switch 650 are pinned to supply power to the operational amplifier 630, thus leaving the operational amplifier 630 in the off state. Relatively when the buffer switch signal Ssw is low (ie, the second potential), the first end and the third end of the first switch SW1 and the second switch SW2 are turned on, that is, the transistors M1 and M2 are respectively connected to The current source 61〇 and 620 are such that the first switching voltage VI and the second switching voltage V2 are respectively a first normal bias value and a second normal bias value. At this time, the first power switch 640 and the second power switch 650 Sufficient power is supplied to the operational amplifier 630 to put the operational amplifier 630 in an active state. Another second embodiment consistent with the present invention is presented herein, as shown in Figure 7, which is a circuit diagram of a buffer control module in accordance with a second embodiment of the present invention. Referring to Fig. 7, the present embodiment is similar to the first embodiment of Fig. 6 described above. Therefore, the same operation modes and descriptions will not be repeated. The difference is that the operational amplifier 630 in FIG. 6 directly turns off/starts the power supply, and the embodiment of FIG. 7 directly pulls/pushes the signal transmitted in the operational amplifier 75A to the system voltage Vdd/ The ground voltage Vss is used to turn off the operational amplifier 750. DETAILED DESCRIPTION The output buffer 140 of the present embodiment includes a first power switch 701, a second power switch 702, and an operational amplifier 750, and the operational amplifier 750 includes an input stage amplifier 710 and an output stage amplifier 72A. 17

201207804,, 34329 twf.doc/I, the 710 can be utilized as an example in the present embodiment by rail-to-rail touch and core amplification, and the output stage amplifier 720 utilizes a push-pull (PUSh__) amplifier as the present embodiment. For example, but other types of input stage/input amplifiers are substituted, so the invention should not be limited thereto. The non-inverting terminal and the inverting terminal of the operational amplifier 750 respectively transmit the pixel data pD and the pixel data OPD to the input stage amplifier. The input stage amplifier 71 receives the pixel data PD and OPD and generates V3 and V4 accordingly. The output stage amplifier 720 is combined into a push-pull amplifier by a P-channel transistor M5 and an N-channel transistor M6, wherein the control terminal (eg, gate &) of the transistor milk receives the voltage V3' and its source terminal receives The system voltage is here, and the 汲 terminal of the transistor M5 is used as the output terminal of the operational amplifier 75A. In addition, the control terminal (eg, the gate terminal) of the transistor M6 receives the voltage V4, the source terminal thereof receives the grounded electric dust Vss, and the non-extreme terminal of the transistor M6 serves as the output terminal of the operational amplifier 750 and is coupled to the transistor M5. extreme. Therefore, when the buffer switch signal SSw is at a high potential (that is, the first potential), the first power switch 701 and the second power switch 7〇2 are turned on, so that the voltage V3 and the voltage V4 are forced to become the system voltage and Grounding "Electricity, Vss" is used to amplify n 75G. In contrast, when the buffering switch signal Ssw is low (ie, the second potential), the first power switch 7〇1 and the second power switch 702 are worn. In the state, the pixel data contained in the voltage V3 and the voltage V4 can be transmitted to the output and the amplifier 72A, thereby starting the operational amplifier 750. In summary, the embodiment of the present invention utilizes the system clock signal of the timing controller or Vertical sync signal to calculate or sample to report data

2〇i2〇m〇. · 34329twf.doc/I Valid data period and blank data period in the signal. The buffer control module then uses the shutdown output buffer to reduce the energy consumption of the output buffer during the blank data period, and during the active data period, the buffer control module activates and maintains the output buffer drive capability, The display panel can be driven normally to maintain the display quality of the flat panel display. Thereby, the present embodiment can save energy consumption while maintaining the display quality of the flat panel display. The present invention has been disclosed in the above embodiments, and it is not intended to limit the invention to those skilled in the art, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a flat panel display. Figure 2 is a waveform diagram of the vertical sync signal, the data enable signal, and the bias voltage of the output buffer. 3 is a block diagram of a flat panel display in accordance with an embodiment of the invention. 4 is a waveform diagram of a vertical sync signal, a data enable signal, and a bias voltage of an output buffer according to an embodiment of the invention. FIG. 5 is a block diagram of a buffer control module according to an embodiment of the invention. Figure 6 is a circuit diagram of a buffer control module in accordance with a first embodiment of the present invention. 201207804

34329twf.doc/I -------- Figure 7 is a circuit diagram of a buffer control module in accordance with a second embodiment of the present invention. [Main component symbol description] SW2: Second switch Vdd: System voltage Vss: Ground voltage VI: First switching voltage V2: Second switching voltage V3, V4: Voltage VS: Vertical synchronization signal D: Data signal DE: Data enable Signal CLK. System clock signal PD, OPD: Pixel data HT: Horizontal scan time Ssw: Buffer switch signal VSW: Switching period VBP: Veneer period VFP: Front porch period

10'30 I flat panel display 110: timing controller 120: source driver 130: drive circuit 140: output buffer 160: | page panel 165 = pixel circuit 310: buffer control module 51 〇: buffer control unit 520 The first buffer switch unit 530: the second buffer switch unit 610: the first current source 620: the second current source 630, 750: the operational amplifier 640'701: the first power switch 650, 702: the second power switch 710 : Input stage amplifier T1: blank data period 20 201207804

Ηινι*ζυ 10-0029-TW 34329twf.doc/I T2 : Valid data period VT : Frame period 720 : Output stage amplifier Ml ~ M6: Transistor SW1 : First switch

twenty one

Claims (1)

201207804 ........029*TW 34329twf.doc/I VII. Patent Application Range: L A driving device for a flat panel display, comprising: a driving circuit for outputting pixel data during an active data period; an output buffer The input end receives the output of the driving circuit, the output end of the output buffer drives a display panel; and the buffer control module closes the output buffer during a blank data period, and during the valid data period Start the output buffer. 2. The driving device of claim </ RTI>, further comprising: a timing controller for generating a system clock signal, and the output buffer control module is based on the system clock signal The data can be sampled to determine the period of the blank data and the period of the valid data. ~ 3 · The driving device described in claim 1 of the patent scope further includes: The timing controller is configured to generate a vertical synchronization signal, and the buffer control module calculates the blank data period and the valid data period according to the vertical synchronization signal, a front corridor period, and a back corridor period. 4. The driving device of claim 1, wherein the buffer control module comprises: 〃. a buffer control unit, during the blank data, the buffer control unit adjusts a buffer switch signal to a first potential, and adjusts the buffer switch signal to a second potential during the valid data period; and a first buffer The switch unit is connected to the buffer control unit for turning off or starting the output buffer according to the first potential or the second potential of the buffer switch signal. 5. The driving device of claim 4, wherein the first buffer switch unit comprises: - a first transistor, a first end receiving system thereof, - 00 00 00 00 00 00 00 00 a voltage, the control end of the first transistor is lightly connected to the second end of the first transistor to generate a first switching voltage; a f-switch 'the first end of the first to the second of the first transistor The first end of the switch is connected to the system, the control end of the first switch receives the buffer switch signal; and: the first current source, the supply end is coupled to the third end of the first switch, Wherein, when the buffer switch signal is the first potential, the second end of the first switch P(4) of the first switch is turned on '^ when the buffer switch signal is i. When the bit is the first end of the first switch and the third end of the first switch, as in the fifth item of the patent application system, the buffer includes: · He Liyi is the same as the zero-transfer two-amplifier' The inverting terminal serves as an inverting terminal of the output buffer of the output buffer. The output terminal of the operational amplifier is used as the output end of the gorge, and the flute is: the power switch, and the control terminal receives the first- Switching power: and lightly connecting a first power terminal of the operational amplifier, and turning off the power supply to the operational amplifier. The driving device of the fourth aspect of the invention, wherein the buffer control module further comprises: a second buffer switch unit connected to the driving device of the fourth aspect of the invention The buffer control unit is configured to turn off or start the output buffer according to the buffer switch signal. 8. The driving device of claim 7, wherein the second buffer switch unit comprises: ” a second transistor, the first end of which receives a ground voltage, and the control end of the second transistor And coupled to the second end of the second transistor to generate a second switching voltage; a second switch having a first end coupled to the second end of the second transistor, the second end of the second switch The terminal is coupled to the ground voltage, and the control end of the second switch receives the buffer switch signal; and a sweat and a second current source, the supply end of which is coupled to the second switch end, wherein when the buffer switch signal is At the first potential, the first end of the second switch is electrically connected to the second open second end, and when the buffer switch signal is the second potential, the first end and the second end of the second switch 9. The driving device is turned on. 9. The driving device of claim 8, wherein the output buffer comprises: - an operational amplification n 'the non-inverting terminal is used as the output buffer terminal, and the operation is amplified and corrected. Subtract the operation Α|| The output of the op amp is used as The output end of the output buffer is 1 24 2〇12〇7 _._ - the first thunder end receives the second open face, the = end of the power switch receives the grounding electric, the second power The second end is coupled to a second power terminal of the operational amplifier. 10. A method for driving a flat display, comprising: providing a driving circuit, wherein the driving circuit outputs a pixel data during an active data; providing an output buffer 'where the output of the output buffer is received The output of the driver circuit, the output of the output buffer H - the display panel; the output buffer is turned off during a blank data; and the output buffer is activated during the active data. 11. The driving method according to claim 10, further comprising: sampling a data enable signal according to a system clock signal to determine the blank data period and the valid data period. 12. The driving method as described in the scope of the patent application, further includes: 求 determining the blank data period and the valid data period according to a vertical sync signal, a front corridor period, and a post-maze period. 25