TWI415062B - Driving device of flat panel display and driving method thereof - Google Patents

Abstract

A driving device and a driving method of a flat panel display are provided. The driving device includes a driving circuit, an output buffer, and a buffer control module. The driving circuit outputs a pixel data during a valid data period, and an input terminal of the output buffer receives the output of the source driving module. The buffer control module turns off the output buffer during a blanking data period, and turns on the output buffer during the valid data period in order to reduce power consumption of the output buffer, and maintain the image quality of the flat panel display.

Description

Flat display display driving device and driving method

The present invention relates to a flat panel display, and more particularly to a drive device for a flat panel display.

In today's society, a wide variety of electronic products (such as notebook computers, mobile phones, and televisions) have applications for display devices, providing users with viewing status, information, and the like. Due to the low power consumption and small size of flat panel display (FPD), the traditional cathode ray tube (CRT) has been replaced. A flat panel display is a general name for the shape of its display panel, including: liquid crystal display (LCD), plasma display panel (PDP), organic light emitting display (OLED), field emission plane. Field emission display (FED), etc.

In various types of flat panel displays, a plurality of scan (gate) signals are used to match the data (source) signals to display images. As the size and resolution of the flat panel display increase, the load of the driving device when driving the display panel increases and the charging and discharging time thereof relatively decreases. Therefore, when designing the driving device, it is necessary to consider the driving ability of the output signal of the driving device to meet the demand for increasing the size and resolution of the display panel.

However, when the driving device charges and discharges the pixel capacitance of the display panel, it is often only required during the transition state of the pixel signal (that is, the pixel is being charged). During the discharge period, sufficient driving capability can be provided to accelerate the charging and discharging speed. When the pixel is already in a steady state (that is, during the period in which the pixel is completed and discharged), or during the blank data period in which the pixel data is not required to be updated, the excess electric power is consumed in the driving device, thereby causing waste of energy.

The invention provides a driving device for a flat panel display. The driving device turns off an output buffer during a blank data period, and activates an output buffer during an active data period, thereby reducing power consumption of the output buffer and maintaining display of the flat display. quality.

In another aspect, the present invention provides a method for driving a flat panel display. The method turns off an output buffer during a blank data period and activates an output buffer during a valid data period to maintain display quality while reducing an output buffer. Energy consumption.

The invention provides a driving device for a flat panel display, the driving device comprising a driving circuit, an output buffer and a buffer control module. The driver circuit outputs pixel data during the active data period, and the input of the output buffer is used to receive the output of the driver circuit. The buffer control module is configured to turn off the output buffer during blank data, and the buffer control module activates the output buffer during the active data period.

In an embodiment of the present invention, the driving device may further include a timing controller, which can generate a system clock signal, and the buffer control module can sample the data enable signal according to the system clock signal, thereby Discriminate the blank data period and the valid data period.

In an embodiment of the present invention, the driving device may further include a timing controller capable of generating a vertical synchronization signal, and the buffer control module may be configured by a vertical synchronization signal, a front porch period, and a back corridor. During the (back porch) period, the period of the blank data and the period of the valid data are calculated.

In an embodiment of the invention, the buffer control module includes a buffer control unit and a first buffer switch unit. During the blank data period, the buffer control unit adjusts the buffer switch signal to the first potential, and adjusts the buffer switch signal to the second potential during the valid data period. The first buffer switch unit is coupled to the buffer control unit to turn off or enable the output buffer based on the first potential or the second potential of the buffer switch signal.

In an embodiment of the invention, the first buffer switch unit includes a first transistor, a first switch, and a first current source. The first end of the first transistor receives the system voltage, and the control end of the first transistor is coupled to the second end of the first transistor, thereby generating a first switching voltage. The first end of the first switch is coupled to the second end of the first transistor, the second end of the first switch is coupled to the system voltage, and the control end of the first switch receives the buffer switch signal. The supply end of the first current source is coupled to the third end of the first switch. When the buffer switch signal is at the first potential, the first end of the first switch and the second end thereof are turned on, so that the first switch voltage is equal to the system voltage, and when the buffer switch signal is the second potential, the first switch The first end is electrically coupled to the third end thereof such that the first switching voltage is a first normal bias value.

In an embodiment of the invention, the output buffer includes an operational amplifier and a first power switch. The non-inverting terminal of the operational amplifier can be used as an input terminal of the output buffer, and the inverting terminal of the operational amplifier is coupled to the operational amplifier. The output of the amplifier and the output of the buffer. The control end of the first power switch receives the first switching voltage, and the first end of the first power switch receives the system voltage, and the second end of the first power switch is coupled to the first power end of the operational amplifier. The first power switch turns off or starts the operational amplifier according to the first switching voltage. In detail, when the first switching voltage is the system voltage, the first power switch is used to turn off the operational amplifier, and when the first switching voltage is the first normal bias value, the first power switch is used to start the operational amplifier.

In an embodiment of the invention, the buffer control module further includes a second buffer switch unit connected to the buffer control unit, and the second buffer switch unit is configured to be turned off or activated according to the buffer switch signal. Output buffer.

In an embodiment of the invention, the second buffer switch unit includes a second transistor, a second switch, and a second current source. The first end of the second transistor receives the ground voltage, and the control end thereof is coupled to the second end of the second transistor, thereby generating a second switching voltage. The first end of the second switch is coupled to the second end of the second transistor, and the second end of the second switch is coupled to the ground voltage, and the control end of the second switch receives the buffer switch signal. The supply end of the second current source is coupled to the third end of the second switch. When the buffer switch signal is at the first potential, the first end of the second switch is electrically connected to the second end thereof, so that the second switch voltage is equal to the ground voltage. Moreover, when the buffer switch signal is at the second potential, the first end of the second switch is turned on with the third end thereof, so that the second switch voltage is the second normal bias value.

In an embodiment of the invention, the output buffer further includes a second power switch, the control end of which receives the second switching voltage, and the first end of the second power switch receives the ground voltage. The second end of the second power switch is coupled to the second power terminal of the operational amplifier, and the second power switch turns off or starts the operational amplifier according to the second switching voltage. When the second switching voltage is the system voltage, the second power switch is used to turn off the operational amplifier, and when the second switching voltage is the second normal bias value, the second power switch is used to start the operational amplifier.

From another point of view, the present invention provides a method of driving a flat panel display comprising the following steps. The driving circuit outputs pixel data during the active data period, and the input end of the output buffer receives the output of the driving circuit. Also, the output buffer is turned off during the blank data period, and the output buffer is activated during the active data period.

In an embodiment of the invention, the driving method described above further comprises the following steps. The data enable signal is sampled according to the system clock signal, and the blank data period and the valid data period are discriminated.

In an embodiment of the invention, the driving method described above further comprises the following steps. According to the vertical sync signal, the front corridor period and the back corridor period, the blank data period and the valid data period are calculated and obtained.

Based on the above, the embodiment of the present invention uses the system clock signal of the timing controller or the vertical synchronization signal to calculate or sample to discriminate between the valid data period and the blank data period in the data enable signal. And during the blank data period, the buffer control module uses the output buffer to reduce the energy consumption of the output buffer, and during the valid data period, the buffer control mode The group activates and maintains the drive capability of the output buffer to enable it to properly drive the display panel, thereby maintaining the display quality of the flat panel display.

The above described features and advantages of the present invention will be more apparent from the following description.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the elements and/

At any time or state, each output buffer 140 of the flat panel display 10 is always maintained in an enabled state (or activated state) to provide sufficient drive capability to quickly charge and discharge the display panel 160 at any time. The pole driver 120 can quickly update the pixel data of a plurality of pixel circuits (eg, the pixel circuit 165) as shown in FIGS. 1 and 2. 1 is a block diagram of a flat panel display 10. FIG. 2 is a waveform diagram of bias voltages of a vertical sync signal VS, a data enable signal DE, and an output buffer 140. Referring to FIG. 1 , the flat panel display 10 includes a timing controller 110 , a source driver 120 , and a display panel 160 . The source driver 120 includes a driving circuit 130 and a plurality of output buffers 140, and the number of output buffers 140 depends on the number of pixels owned by each scanning line in the display panel 160, where an output buffer 140 is used. For example. Further, the display panel 160 of this example also utilizes the pixel circuit 165 corresponding to the output buffer 140 as an example.

In this example, the timing controller 110 receives the data signal D and the data enable signal DE to be displayed on the display panel 160, and converts the received signal into a plurality of signals such as the vertical synchronization signal VS, and supplies the signals to the source respectively. Device elements such as the driver 120 are used. The driving circuit 130 sequentially transmits the corresponding pixel data PD to the output buffer 140 according to the data signal D and the related signal transmitted by the timing controller 110. In conjunction with the timing of the scan lines, the output buffer 140 writes the pixel data PD into a corresponding pixel circuit (e.g., pixel circuit 165). The output buffer 140 receives sufficient bias voltage in this example to cause the output buffer 140 to be in an activated state at any time, and charges and discharges the pixel load (not shown) of the pixel circuit 165 according to the pixel data PD, thereby allowing the display panel to be displayed. 160 shows the image, and its detailed waveform flow is shown in Figure 2.

Referring to FIG. 2, a frame period VT of the vertical sync signal VS has a switching period VSW, a back porch period VBP, a valid data period T2, and a front porch period VFP. The vertical synchronization signal VS informs the driving circuit 130 that the image signal transmission of the previous frame (frame) has ended during the switching period VSW, and is ready to transmit the image signal of the next picture. This embodiment uses a high-level round-trip low level. The pulse is VSW during its switching. When the VBP during the back porch and the VFP during the front porch are the image signals transmitting the same picture, the flat display 10 requires the preparation time. The data signal D (not shown) and the data enable signal DE will sequentially carry the image signal of the same picture during the VBP period of the vertical synchronization signal VS and the effective data period T2 other than the VFP during the front corridor, and the timing control The device 110 receives the data signal according to the data enable signal DE D, and the pixel data D is transmitted to the drive circuit 130. The drive circuit 130 converts the digital pixel data D into an analog pixel data PD, and transmits the pixel data PD to the output buffer 140. Further, in the present embodiment, the switching period VSW, the back corridor period VBP, and the front porch period VFP are collectively referred to as a blank data period T1. It can be seen from the data enable signal DE that there is no valid data for the data signal D of T1 during the blank data period. That is, the drive circuit 130 does not provide a valid pixel data PD to the output buffer 140 during the blank data period T1.

In the example shown in Figures 1 and 2, the output buffer 140 is always active in the frame period VT. During the active data period T2, the output buffer 140 in the active state can provide sufficient driving capability to quickly transfer the pixel material PD into the pixel circuit 165. However, during the blank data period T1, the pixel data PD does not need to be updated or driven at this time, and the electric power is consumed in the output buffer 140 having sufficient driving capability, thereby causing waste of energy.

Thereby, the buffer control module 310 according to the first embodiment of the present invention turns off the output buffer 140 during the blank data period T1, thereby saving power consumption. And during the active data period T2, the buffer control module 310 will activate the output buffer 140, thereby maintaining the image quality of the display panel 160, as shown in FIG. Figure 3 is a block diagram of a flat panel display in accordance with a first embodiment of the present invention. Referring to FIG. 3, the flat panel display 30 includes a timing controller 110, a source driver 120, and a display panel 160. This embodiment is similar to the above embodiment, and therefore the same description will not be repeated herein.

In this embodiment, the source driver 120 can define the switching period VSW, the porch period VBP, and the front porch period VFP according to the vertical synchronization signal VS provided by the timing controller 110. For example, the source driver 120 may define a back corridor period VBP, a valid data period T2, and a front corridor period VFP according to the phase of the vertical synchronization signal VS using a counter (or timer). In other embodiments, the source driver 120 can define the valid data period T2 and the blank data period T1 by detecting the data enable signal DE.

The source driver 120 (the source driver 120 may also be referred to as the driving device 120 in this embodiment) includes a driving circuit 130, an output buffer 140, and a buffer control module 310. The drive circuit 130 outputs the pixel data PD at the valid data period T2. An input of the output buffer 140 receives the output of the drive circuit 130, and an output of the output buffer 140 drives the display panel 160. In the embodiment, the buffer control module 310 can calculate or determine the blank data period T1 and the valid data period in the frame period VT by using the vertical synchronization signal VS or the data enable signal DE provided by the timing controller 110. T2, and during the blank data period T1, the buffer control module 310 turns off (or disables) the output buffer 140, and activates (or enables) the output buffer 140 during the active data period T2.

In other embodiments, devices other than display panel 160 of flat panel display 30 may be collectively referred to as a drive device. In addition, the buffer control module 310 can be disposed in the source driver 120. In other embodiments, the buffer control module 310 can also be disposed in the timing controller 110. In other words, the buffer control module 310 can determine the plane according to its design requirements. The location of the display 30 is not necessarily embedded in the source driver 120, and the invention should not be limited thereto.

Here, in order to explain in detail the actuation mode and principle of the buffer control module 310, please refer to FIG. 4 is a waveform diagram of bias voltages of the vertical sync signal VS, the data enable signal DE, and the output buffer according to the first embodiment of the present invention. Specifically, the data enable signal DE of FIG. 4 carries the image signals of the same picture during a valid data period T2, and each picture is composed of pixel data of a plurality of scan lines, so the horizontal scan time HT is in this implementation. In the example, it represents the time required to update the pixel information for each scan line in the picture. In this example, a detailed description will be given. It is assumed that the picture of this embodiment has 1024×768 pixels, that is, 768 scanning lines in each picture, and each scanning line has 1024 pixels, so the effective data period T2 It consists of 768 horizontal scanning time HT.

In addition, the buffer control module 310 can determine the blank data period T1 and the valid data period according to design requirements and various signals of the timing controller 110 (for example, the system clock signal CLK, the vertical synchronization signal VS, or the data enable signal DE, etc.). T2, the invention should not be limited thereto. Referring to FIG. 3 and FIG. 4 simultaneously, in the embodiment, the buffer control module 310 can determine the blank data period T1 and the valid data period T2 according to the data enable signal DE, thereby starting or closing the output buffer 140. In detail, the buffer control module 310 samples the data enable signal DE according to each pulse in the system clock signal CLK. When the result of the sampling determines that the data enable signal DE is at a high level, that is, the driving circuit When the pixel data PD is being updated according to the data signal D, the buffer control module 310 immediately starts The output buffer 140 is moved to transfer the pixel material PD to the display panel 160. When the result of the above sampling judges that the data enable signal DE is at a low level, and the sampling result at such a low level maintains at least one horizontal scanning time HT, it represents that the valid data period T2 has ended, that is, has entered the front porch period. The VFP/blank data period T1, so the buffer control module 310 turns off the output buffer 140, thereby saving power consumption.

In another embodiment, the buffer control module 310 can also calculate and discriminate the blank data period T1 and the valid data period T2 according to the vertical synchronization signal VS, thereby starting or closing the output buffer 140. In detail, the buffer control module 310 calculates the phase according to the pulse of the vertical synchronization signal VS (ie, the switching period VSW), and uses the system clock signal CLK to calculate when the VBP/blank data period T1 is valid during the back corridor period. The data period T2 is to convert the output buffer 140 from the off state to the startup state to maintain the image quality of the display panel. In addition, the buffer control module 310 can also calculate the length of the valid data period T2 (in this embodiment, 768 horizontal scanning times HT) by using the system clock signal CLK, thereby converting the output buffer 140 from the startup state. It is turned off, thus reducing the consumption of electrical energy.

As shown in FIG. 5, FIG. 5 is a block diagram of a buffer control module 310 according to a first embodiment of the present invention. Referring to FIG. 5, the buffer control module 310 includes a buffer control unit 510 and a first buffer switch unit 520 in this embodiment. The buffer control unit 510 determines/calculates the blank data period T1 and the valid data period T2 according to the data enable signal DE or the vertical sync signal VS. Buffer control list during blank data period T1 The element 510 adjusts the buffer switch signal Ssw (shown in FIG. 4) to a first potential (eg, a high potential), and during the valid data period T2, the buffer control unit 510 adjusts the buffer switch signal Ssw to a second potential (eg, low). Potential).

Referring to FIG. 5, the first buffer switch unit 520 is coupled to the buffer control unit 510, which can turn off or enable the output buffer 140 according to the high or low potential of the buffer switch signal Ssw. Moreover, in the embodiment, the buffer control module 310 may further include a second buffer switch unit 530 connected to the buffer control unit 510. The second buffer switch unit 530 is configured to enable or disable the output buffer 140 according to the high or low potential of the buffer switch signal Ssw. In detail, when the buffer switch signal Ssw is high, the first buffer switch unit 520 and the second buffer switch unit 530 control the output buffer 140 to be in the off state, and when the buffer switch signal Ssw is low. At this time, the first buffer switch unit 520 and the second buffer switch unit 530 control the output buffer 140 to be in an activated state.

The buffer control unit 510 can calculate and generate the buffer switch signal Ssw according to the data enable signal DE or the vertical sync signal VS and the like by various methods, and let the first buffer switch unit 520 and the second buffer switch unit 530 The control buffer 140 can be turned on or off according to the buffer switch signal Ssw. For example, a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a phase locked loop (PLL), a microchip, a special Application specific integrated circuit (ASIC) The buffer control unit 510 is implemented, and thus the present invention should not be limited to the implementation described above.

The circuit structure of the first buffer switch unit 520, the second buffer switch unit 530, and the output buffer 140 according to the embodiment of the present invention is described in detail herein, as shown in FIG. 6. FIG. 6 is a circuit diagram of a buffer control module 310 in accordance with a first embodiment of the present invention. Referring to FIG. 6 , the first buffer switch unit 520 includes a first transistor M1 , a first switch SW1 , and a first current source 610 . The first transistor M1 can be implemented in the present embodiment by using a P-channel metal oxide semiconductor field-effect transistor (P-MOSFET). The first end (eg, the source terminal) of the first transistor M1 receives the system voltage Vdd, and the control end (eg, the gate terminal) of the first transistor M1 is coupled to the second end of the first transistor M1 (eg, the 汲 terminal) And thereby generating a first switching voltage V1. The first end of the first switch SW1 is coupled to the 汲 terminal of the first transistor M1, the second end of the first switch SW1 is coupled to the system voltage Vdd, and the control end of the first switch SW1 receives the buffer switch signal Ssw. In addition, the supply end of the first current source 610 is coupled to the third end of the first switch SW1. The other end of the first current source 610 is coupled to the ground voltage Vss.

The second buffer switch unit 530 includes a second transistor M2, a second switch SW2, and a second current source 620. In this embodiment, the second transistor M2 can be implemented by using an N-channel metal oxide semiconductor field-effect transistor (N-MOSFET). The first end of the second transistor M2 (eg The source terminal receives the ground voltage Vss, and its control terminal (eg, the gate terminal) is coupled to the second terminal (eg, the 汲 terminal) of the second transistor M2, and thereby generates the second switching voltage V2. The first end of the second switch SW2 is coupled to the second end of the second transistor M2, and the second end thereof is coupled to the ground voltage Vss, and the control end of the second switch SW2 receives the buffer switch signal Ssw. In addition, the supply end of the second current source 620 is coupled to the third end of the second switch SW2. The other end of the second current source 620 is coupled to the system voltage Vdd.

The output buffer 140 includes an operational amplifier (OP-AMP) 630, a first power switch 640, and a second power switch 650. The non-inverting terminal of operational amplifier 630 can serve as an input to output buffer 140 to receive pixel data PD. The inverting terminal of the operational amplifier 630 is coupled to the output of the operational amplifier 630. The output of the operational amplifier 630 serves as an output of the output buffer 140 to output the pixel data OPD to the display panel 160. The first power switch 640 is exemplified herein by a P-channel transistor M3 whose control terminal (eg, a gate terminal) receives the first switching voltage V1. The first end of the first power switch 640 (the source terminal of the transistor M3) receives the system voltage Vdd, and the second end of the first power switch 640 (the 汲 terminal of the transistor M3) is coupled to the first of the operational amplifier 630 Power terminal. The second power switch 650 is exemplified herein by an N-channel transistor M4 whose control terminal (eg, a gate terminal) receives the second switching voltage V2. The first end of the second power switch 650 (the source terminal of the transistor M4) receives the ground voltage Vss, and the second end of the second power switch 650 (the 汲 terminal of the transistor M4) is coupled to the second of the operational amplifier 630 Power terminal. The first power terminal and the second power terminal are used to supply power to the operational amplifier 630.

Therefore, when the buffer switch signal Ssw is at a high potential (ie, the first potential), the first end of the first switch SW1 and the second switch SW2 are electrically connected to the second end, so that the first switching voltage V1 is equal to the system voltage Vdd. And the second switching voltage V2 is equal to the ground voltage Vss. At this time, the first power switch 640 and the second power switch 650 are turned off to supply power to the operational amplifier 630, thus leaving the operational amplifier 630 in the off state. In contrast, when the buffer switch signal Ssw is low (ie, the second potential), the first end and the third end of the first switch SW1 and the second switch SW2 are turned on, that is, the transistors M1 and M2 are respectively connected to The current sources 610 and 620 are such that the first switching voltage V1 and the second switching voltage V2 are the first normal bias value and the second normal bias value, respectively. At this time, the first power switch 640 and the second power switch 650 can provide sufficient power to the operational amplifier 630 to put the operational amplifier 630 in an activated state.

Another second embodiment consistent with the present invention is proposed herein. As shown in FIG. 7, FIG. 7 is a circuit diagram of a buffer control module according to a second embodiment of the present invention. Referring to FIG. 7, this embodiment is similar to the first embodiment of FIG. 6 described above, and therefore the same operation manner and description will not be repeated. The difference is that the operational amplifier 630 in FIG. 6 directly turns off/starts the power supply, and the embodiment of FIG. 7 directly pulls/pushes the signal transmitted from the operational amplifier 750 to the system voltage Vdd/ground. The voltage Vss is used to turn off the operational amplifier 750.

In detail, the output buffer 140 of the present embodiment includes a first power switch 701, a second power switch 702, and an operational amplifier 750, and the operational amplifier 750 includes an input stage amplifier 710 and an output stage amplifier 720. The input stage amplifier 710 can be exemplified by a rail-to-rail amplifier in this embodiment, and the output stage amplifier 720 is exemplified by a push-pull amplifier in this embodiment. Other types of input stage/output stage amplifiers may be substituted, and thus the invention should not be limited thereto. The non-inverting terminal and the inverting terminal of the operational amplifier 750 respectively transmit the pixel data PD and the pixel data OPD to the input stage amplifier 710. The input stage amplifier 710 receives the pixel data PD and OPD and accordingly generates V3 and V4. The output stage amplifier 720 is combined into a push-pull amplifier by a P-channel transistor M5 and an N-channel transistor M6, wherein the control terminal (eg, the gate terminal) of the transistor M5 receives the voltage V3, and the source terminal thereof receives the system voltage. Vdd, the 汲 terminal of transistor M5 acts as the output of operational amplifier 750. In addition, the control terminal (eg, the gate terminal) of the transistor M6 receives the voltage V4, the source terminal thereof receives the ground voltage Vss, and the 汲 terminal of the transistor M6 serves as the output terminal of the operational amplifier 750 and is coupled to the 汲 terminal of the transistor M5. .

Therefore, when the buffer switch signal Ssw is at a high potential (ie, the first potential), the first power switch 701 and the second power switch 702 are turned on, so that the voltage V3 and the voltage V4 are forced to become the system voltage Vdd and the ground voltage. Vss, thereby turning off the operational amplifier 750. In contrast, when the buffer switch signal Ssw is at a low potential (ie, a second potential), the first power switch 701 and the second power switch 702 are turned off, and the pixel data included in the voltage V3 and the voltage V4 can be transmitted. To the output and amplifier 720, the operational amplifier 750 is enabled.

In summary, the embodiment of the present invention uses the system clock signal of the timing controller or the vertical synchronization signal to calculate or sample to determine the data. The valid data period and the blank data period in the signal. Then during the blank data period, the buffer control module uses the output buffer to reduce the energy consumption of the output buffer, and during the active data period, the buffer control module starts and maintains the driving capability of the output buffer, so that The display panel can be driven normally to maintain the display quality of the flat panel display. Thereby, the embodiment can save energy consumption while maintaining the display quality of the flat panel display.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 30‧‧‧ flat panel display

110‧‧‧Sequence Controller

120‧‧‧Source Driver

130‧‧‧Drive circuit

140‧‧‧Output buffer

160‧‧‧ display panel

165‧‧‧pixel circuit

310‧‧‧Buffer control module

510‧‧‧buffer control unit

520‧‧‧First buffer switch unit

530‧‧‧Second snubber switch unit

610‧‧‧First current source

620‧‧‧second current source

630, 750‧‧‧Operational Amplifier

640, 701‧‧‧ first power switch

650, 702‧‧‧ second power switch

710‧‧‧Input amplifier

SW2‧‧‧second switch

Vdd‧‧‧ system voltage

Vss‧‧‧ Grounding voltage

V1‧‧‧ first switching voltage

V2‧‧‧second switching voltage

V3, V4‧‧‧ voltage

VS‧‧‧ vertical sync signal

D‧‧‧Information signal

DE‧‧‧Information enable signal

CLK‧‧‧ system clock signal

PD, OPD‧‧‧ pixel data

HT‧‧‧ horizontal scanning time

Ssw‧‧‧ Buffer Switch Signal

VSW‧‧‧ switching period

During the VBP‧‧‧ porch

During the VFP‧‧ ‧ front porch

T1‧‧‧ blank data period

720‧‧‧Output amplifier

M1~M6‧‧‧O crystal

SW1‧‧‧ first switch

T2‧‧‧ valid data period

VT‧‧‧ frame cycle

Figure 1 is a block diagram of a flat panel display.

2 is a waveform diagram of a vertical sync signal, a data enable signal, and a bias voltage of an output buffer.

3 is a block diagram of a flat panel display in accordance with an embodiment of the invention.

4 is a waveform diagram of a vertical sync signal, a data enable signal, and a bias voltage of an output buffer according to an embodiment of the invention.

FIG. 5 is a block diagram of a buffer control module according to an embodiment of the invention.

6 is a circuit diagram of a buffer control module according to a first embodiment of the present invention.

Figure 7 is a circuit diagram of a buffer control module in accordance with a second embodiment of the present invention.

VS‧‧‧ vertical sync signal

DE‧‧‧Information enable signal

CLK‧‧‧ system clock signal

Ssw‧‧‧ Buffer Switch Signal

VSW‧‧‧ switching period

During the VBP‧‧‧ porch

During the VFP‧‧ ‧ front porch

T1‧‧‧ blank data period

T2‧‧‧ valid data period

VT‧‧‧ frame cycle

HT‧‧‧ horizontal scanning time

Claims (12)

A driving device for a flat panel display, comprising: a driving circuit for outputting pixel data during an active data; an output buffer having an input end receiving an output of the driving circuit, the output end of the output buffer driving a display panel; A buffer control module closes the output buffer during a blank data and activates the output buffer during the valid data. The driving device of claim 1, further comprising: a timing controller for generating a system clock signal, and the output buffer control module is configured to enable a data signal according to the system clock signal Sampling to discriminate between the blank data period and the valid data period. The driving device of claim 1, further comprising: a timing controller for generating a vertical synchronization signal, wherein the buffer control module is based on the vertical synchronization signal, a front corridor period, and a back corridor The period during which the blank data period is obtained and the valid data period are calculated. The driving device of claim 1, wherein the buffer control module comprises: a buffer control unit, wherein the buffer control unit adjusts a buffer switch signal to a first potential during the blank data, and Adjusting the buffer switch signal to a second potential during the valid data period; and a first buffer switch unit connected to the buffer control unit for determining the first potential or the second according to the buffer switch signal Potential to turn off or start the output buffer. The driving device of claim 4, wherein the first buffer switch unit comprises: a first transistor, the first end of which receives a system voltage, and the control end of the first transistor is coupled to the a second end of the first transistor to generate a first switching voltage; a first switch having a first end coupled to the second end of the first transistor, the second end of the first switch coupled to The system voltage, the control end of the first switch receives the buffer switch signal; and a first current source, the supply end of which is coupled to the third end of the first switch, wherein when the buffer switch signal is the first At a potential, the first end of the first switch is electrically connected to the second end of the first switch, and when the buffer switch signal is the second potential, the first end of the first switch and the first end of the first switch Three-terminal conduction. The driving device of claim 5, wherein the output buffer comprises: an operational amplifier having a non-inverting terminal as an input end of the output buffer, and an inverting terminal of the operational amplifier coupled to the operational amplifier The output end of the operational amplifier serves as an output of the output buffer; and a first power switch, the control terminal receives the first switching voltage, and the first end of the first power switch receives the system voltage, The second end of the first power switch is coupled to a first power terminal of the operational amplifier, wherein the first power terminal is powered to the operational amplifier. The driving device of claim 4, wherein the buffer control module further comprises: a second buffer switch unit connected to the buffer control unit for shutting down or starting according to the buffer switch signal The output buffer. The driving device of claim 7, wherein the second buffer switch unit comprises: a second transistor, the first end of which receives a ground voltage, and the control end of the second transistor is coupled to the a second end of the second transistor to generate a second switching voltage; a second switch having a first end coupled to the second end of the second transistor, the second end of the second switch coupled to The grounding voltage, the control end of the second switch receives the buffer switch signal; and a second current source, the supply end of which is coupled to the third end of the second switch, wherein when the buffer switch signal is the first At a potential, the first end of the second switch is electrically connected to the second end of the second switch, and when the buffer switch signal is the second potential, the first end of the second switch and the second end of the second switch Three-terminal conduction. The driving device of claim 8, wherein the output buffer comprises: an operational amplifier having a non-inverting terminal as an input end of the output buffer, and an inverting terminal of the operational amplifier coupled to the operational amplifier Output of the operational amplifier as an output of the output buffer; a second power switch, the control terminal receives the second switch voltage, the first end of the second power switch receives the ground voltage, and the second end of the second power switch is coupled to a second power end of the operational amplifier . A driving method for a flat panel display, comprising: providing a driving circuit, wherein the driving circuit outputs a pixel data during an effective data period; providing an output buffer, wherein an input end of the output buffer receives an output of the driving circuit, The output of the output buffer drives a display panel; the output buffer is turned off during a blank data; and the output buffer is enabled during the active data. The driving method of claim 10, further comprising: sampling a data enable signal according to a system clock signal to determine the blank data period and the valid data period. The driving method of claim 10, further comprising: calculating the blank data period and the valid data period according to a vertical sync signal, a front corridor period, and a back corridor period.