WO2017016243A1 - 工艺偏差检测电路、方法和计算机存储介质 - Google Patents

工艺偏差检测电路、方法和计算机存储介质 Download PDF

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Publication number
WO2017016243A1
WO2017016243A1 PCT/CN2016/079627 CN2016079627W WO2017016243A1 WO 2017016243 A1 WO2017016243 A1 WO 2017016243A1 CN 2016079627 W CN2016079627 W CN 2016079627W WO 2017016243 A1 WO2017016243 A1 WO 2017016243A1
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Prior art keywords
signal
transmission
analog
process deviation
buffer
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English (en)
French (fr)
Inventor
蔡晓伟
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a process deviation detecting circuit, method, and computer storage medium.
  • circuits such as integrated circuits, digital-analog hybrid integrated circuits
  • embodiments of the present invention are expected to provide a process deviation detecting circuit, method, and computer storage medium to enable easy and accurate detection of process variations.
  • the technical solution of the present invention is implemented as follows:
  • the first aspect of the present invention discloses a process deviation detecting circuit, and the circuit includes:
  • a first transmission path configured to receive and transmit a first enable signal, and output a first transmission signal
  • a second transmission path configured to receive and transmit the first enable signal, and output a second transmission signal
  • the detecting unit is configured to detect a process deviation based on a transmission delay of the first transmission signal and the second transmission signal;
  • the process deviation sensitivity of the first transmission path is a first sensitivity
  • the process deviation sensitivity of the second transmission path is a second sensitivity.
  • the detecting unit includes a counter
  • the counter includes:
  • a reference clock signal pin configured to receive a reference clock
  • a first enable pin configured to receive a second enable signal formed based on the first transmission signal, or receive a third enable signal formed based on the second transmission signal;
  • the counter is configured to count the reference clock to output a first count value based on the second enable signal, or to count the reference clock based on the third enable signal to output a second count value;
  • first count value and the second count value are used together to characterize the process deviation.
  • the detection circuit further includes:
  • An exclusive OR circuit exclusive OR circuit configured to XOR the first enable signal and the first transmit signal to form a first exclusive OR signal; or to transmit the first enable signal and the second transmit The signal is XORed to form a second exclusive OR signal; wherein the first exclusive OR signal and the second exclusive OR signal are XOR results;
  • an AND gate configured to process the first enable signal and the XOR result to form the second enable signal or the third enable signal.
  • the detecting unit includes an analog signal conversion circuit
  • the analog signal conversion circuit is configured to receive the first transmission signal and the second transmission signal, and output a corresponding analog signal according to a transmission delay of the first transmission signal and the second transmission signal;
  • the analog signal conversion circuit When the first transmission signal is applied to the analog signal conversion circuit, the analog signal conversion circuit outputs a first analog signal; when the second transmission signal is applied to the analog signal conversion circuit, the analog signal conversion circuit Outputting a second analog signal;
  • the first analog signal and the second analog signal can be used together to characterize the process deviation.
  • the detecting unit further includes an analog to digital converter
  • An analog input end of the analog-to-digital converter is connected to an output end of the analog signal conversion circuit for receiving and performing analog-to-digital conversion on the first analog signal or the second analog signal;
  • the analog to digital conversion unit When the first transmission signal is applied to the analog signal conversion circuit, the analog to digital conversion unit outputs a first digital signal corresponding to the first analog signal; and the second transmission signal acts on the analog signal conversion In the circuit, the analog to digital conversion unit outputs a second digital signal corresponding to the second analog signal;
  • the first digital signal and the second digital signal are used together to characterize the process deviation.
  • the first transmission path and the second transmission path each include an M-stage serial buffer; the first transmission signal includes M first buffer signals; and the second transmission signal includes M first Two buffered signal;
  • the analog signal conversion circuit includes: M controlled current sources and load capacitances;
  • the mth controlled current source is configured to receive a control signal formed based on the mth first buffer signal or the mth second buffer signal, and continue or stop the load according to the control signal Capacitor charging; the m is an integer not greater than the M; wherein the M is not less than an integer of 1;
  • An analog input of the analog-to-digital converter is coupled to the load capacitor for converting a capacitive voltage of the load capacitor into a corresponding digital signal.
  • the detecting unit includes a time to digital converter
  • the time digital signal converter is configured to receive the first transmission signal and the second transmission signal, and output a conversion signal
  • the conversion signal can be used to characterize the process deviation.
  • the time digital conversion circuit includes:
  • a third buffer of N stages connected in series, configured to receive a first input signal and perform N-level buffer processing on the first input signal
  • An nth delay flip-flop connected to the output end of the nth third buffer, receiving the second input signal and the first input signal that has undergone n-stage buffer processing, based on the second input signal pair The first input signal is subjected to delay trigger processing, and outputs a delayed trigger result;
  • n is a positive integer not greater than N; and the N is an integer not less than 1;
  • the first input signal is the first transmission signal, and the second input signal is the second transmission signal; or the first input signal is the second transmission signal, the second input signal Is the first transmission signal.
  • the first transmission path and the second transmission path each include a buffer of M stages in series;
  • the M is not less than an integer of 1.
  • a second aspect of the embodiments of the present invention provides a process deviation detecting method, where the method includes:
  • the process deviation sensitivity of the first transmission path is a first sensitivity
  • the process deviation sensitivity of the second transmission path is a second sensitivity
  • the first sensitivity is not equal to the second sensitivity.
  • the detecting a process deviation based on a transmission delay of the first transmission signal and the second transmission signal including:
  • first count value and the second count value are used together to characterize the process deviation.
  • the method further includes:
  • the detecting a process deviation based on a transmission delay of the first transmission signal and the second transmission signal including:
  • the first transmission signal is simulated a first analog signal is output when the signal is converted, and a second analog signal is output when the second signal is subjected to analog signal conversion; the first analog signal and the second analog signal can be used together to characterize the process deviation.
  • the detecting a process deviation based on a transmission delay of the first transmission signal and the second transmission signal further including:
  • the digital signal includes a first digital signal corresponding to the first analog signal and corresponding to the a second digital signal of the second analog signal;
  • the first digital signal and the second digital signal are used together to characterize the process deviation.
  • the first transmission signal includes M first buffer signals, wherein the mth first buffer signal is formed by buffering the m-1th first buffer signal;
  • the second transmission signal includes M second buffer signals; wherein the mth second buffer signal is formed by buffering the m-1th second buffer signal;
  • the detecting a process deviation based on a transmission delay of the first transmission signal and the second transmission signal further comprising:
  • the m is an integer not greater than the M; wherein the M is not less than an integer of 1.
  • the detecting a process deviation based on a transmission delay of the first transmission signal and the second transmission signal including:
  • the conversion signal can be used to characterize the process deviation.
  • performing time-to-digital conversion processing on the first transmission signal and the second transmission signal, and outputting the conversion signal includes:
  • n is a positive integer not greater than N; and the N is not less than 1 Integer
  • the first input signal is the first transmission signal, and the second input signal is the second transmission signal; or the first input signal is the second transmission signal, the second input signal Is the first transmission signal.
  • the receiving and transmitting the first enable signal by using the first transmission path, and outputting the first transmission signal includes:
  • the first enable signal is buffered by using an M-level serial buffer located on the first transmission path to form the first transmission signal;
  • Receiving and transmitting the first enable signal by using the second transmission path, and outputting the second transmission signal including:
  • the first enable signal is buffered by using a M-level serial buffer located on the second transmission path to form the second transmission signal;
  • the M is not less than an integer of 1.
  • a third aspect of the embodiments of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute at least one of the foregoing process deviation detecting methods.
  • the process deviation detecting circuit, method and computer storage medium according to the embodiments of the present invention can easily detect and characterize by detecting the transmission delays of the first transmission signal and the second transmission signal transmitted by the first transmission path and the second transmission path.
  • the signal of the process deviation enables accurate and simple detection of process variations.
  • FIG. 1 is a schematic structural diagram of a first process deviation detecting circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a buffer according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a second process deviation detecting circuit according to an embodiment of the present invention.
  • Figure 4 is a timing diagram of an operation of the circuit shown in Figure 3;
  • FIG. 5 is a schematic structural diagram of a third process deviation detecting circuit according to an embodiment of the present invention.
  • FIG. 6 is a diagram showing a relationship between a capacitor voltage of a load capacitor and a charging time according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a fourth process deviation detecting circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart diagram of the method for detecting a process deviation according to an embodiment of the present invention.
  • the embodiment provides a process deviation detecting circuit, and the circuit includes:
  • the first transmission path 110 is configured to receive and transmit a first enable signal, and output a first transmission signal
  • the second transmission path 120 is configured to receive and transmit the first enable signal, and output a second transmission signal
  • the detecting unit 130 is configured to detect a process deviation based on a transmission delay of the first transmission signal and the second transmission signal;
  • the process deviation sensitivity of the first transmission path is a first sensitivity
  • the process deviation sensitivity of the second transmission path is a second sensitivity.
  • a detection circuit is provided.
  • the detection circuit is provided with two transmission paths; the two transmission paths may have the same or different process sensitivity; that is, the first sensitivity may be equal to or Not equal to the second sensitivity.
  • One of the first sensitivity and the second sensitivity is known or negligible; the neglect here is not to be sensitive to process variation, and the influence of process variation on its electrical characteristics may be Ignore, so that the transmission path corresponding to the sensitivity can be used as the reference transmission path of another transmission path.
  • one of the first transmission path 110 and the second transmission path 120 is less than a predetermined threshold for process sensitivity, and the transmission path can be used as a reference transmission path for process deviation detection.
  • the predetermined threshold may be a predetermined value, which may be a threshold determined according to a simulation or a test of the test article. If the process deviation sensitivity is less than the predetermined threshold, it indicates that the transmission path is insensitive to the process deviation; and generally the reference transmission path is negligible in performing detection because of low sensitivity to process deviation. Moreover, the process deviation of the reference transmission path is neglected, and the accuracy of the process deviation detection is generally small.
  • the process sensitivity of one of the first transmission path 110 and the second transmission path 120 may be known in advance through simulation or pre-testing of the test article.
  • the transmission path can also be used as the above reference transmission path for process deviation detection.
  • the detecting unit 130 is further included in the embodiment, and the detecting unit 130 determines the process deviation by detecting the delay of the signal transmission by the first transmission path and the second transmission path.
  • the first transmission path and the second transmission path are both designed to transmit signals to specified electronic components at a specified time delay according to design criteria, due to process deviations.
  • the electrical characteristics such as the impedance of the generated transmission path are changed, which may cause a problem that the signal transmission delay is too large or the transmission delay is too small. Therefore, in the embodiment, the detection unit is used to detect the first transmission path.
  • the process deviation can be detected by the transmission delay of the second transmission path.
  • the process deviation detecting circuit in the embodiment may be a component of the integrated circuit internal circuit or a component of the circuit on the printed circuit board. In the circuit structure, the process deviation detecting circuit in the embodiment is added, which is convenient for These circuit structures perform process deviation detection to accurately determine the power required to provide the corresponding electronic components in the circuit structure.
  • the first transmission path and the second transmission path each include an M-stage serial buffer; wherein the M is not less than an integer of 1.
  • M is 2, 3, 4, 5, 7, ..., 20, ..., 30, etc., and the specific range of values is set according to the needs of the circuit design.
  • the buffer can be used to temporarily buffer the input signal, and after performing a certain delay processing on the input signal, input the corresponding input signal.
  • this embodiment provides an internal structure of the aforementioned buffer.
  • the buffer includes an input terminal, an output terminal, two P-channel MOSFETs, and two N-channel MOSFETs (Negative channel) Metal Oxide Semiconductor, NMOS).
  • the two PMOSs are respectively M1 and M2 in FIG. 2; the two NMOSs are M3 and M4 in FIG. 2, respectively.
  • the input of the buffer is connected to M1 And the gate of M3.
  • the drains of M1 and M2 are connected to the supply voltage.
  • the source of M1 is connected to the drain of M3, and the source of M3 is grounded.
  • the drain of M4 is connected to the source of M2, and the source of M4 is grounded.
  • the gates of M2 and M4 are connected to the drain of M3.
  • the source of M2 and the drain of M4 are connected to the output.
  • the use of the buffer shown in Figure 2 has the characteristics of simple structure and low production cost.
  • a first controlled switch K1 is disposed in the first transmission path 110, and a second controlled switch K2 is disposed in the second transmission path 120.
  • the first controlled switch K1 and the second controlled switch K2 can be used to turn on or off the first transmission path 110 and the second transmission path 120.
  • the first controlled switch K1 and the second controlled switch K2 may be structures such as transistors or transistors. The use of the transistor or the triode has the characteristics of simple structure and low cost.
  • the working state of the process deviation detecting circuit can be conveniently controlled.
  • the detecting unit 130 includes a counter
  • the counter includes:
  • a reference clock signal pin CLK configured to receive a reference clock
  • a first enable pin EN configured to receive a second enable signal formed based on the first transmission signal, or receive a third enable signal formed based on the second transmission signal;
  • the counter is configured to count the reference clock to output a first count value based on the second enable signal, or to count the reference clock based on the third enable signal to output a second count value;
  • first count value and the second count value are used together to characterize the process deviation.
  • the reference clock signal pin CLK of the counter in this embodiment receives the reference clock.
  • the first enable pin EN is used to receive an enable signal.
  • the enable signal of the first enable pin receiving EN is a second enable signal formed based on the first transfer signal or a third enable signal formed based on the second transfer signal.
  • the counter is configured to count the received clock signal under the action of the second enable signal or the third enable signal.
  • the counter is configured to count 1 for each of the reference clock cycles received if the second enable signal and the second enable signal enable the counter.
  • the first count value and the second count value are both the count results output by the counter in FIG.
  • FIG. 4 is a timing chart of the counter formation detecting unit 130 in the present embodiment.
  • the number of clocks P1 corresponding to the standard delay and the number of clocks P3 corresponding to the excessive delay are delayed by a small number of clocks P2.
  • the P1, P2, and P3 may all be the count results of the counter shown in FIG.
  • the second enable signal and the third enable signal are respectively formed based on the first transmission signal and the second transmission signal, and the result of the counter is only possible for two count results in one detection. .
  • the process deviation is determined by considering one of the count results as the number of clocks P1 corresponding to the standard delay.
  • the detection circuit 130 further includes: an exclusive OR circuit for XOR processing the first enable signal and the first transmission signal to form a first exclusive OR signal; or for using the first enable Examining a signal with the second transmission signal to form a second exclusive OR signal; wherein the first exclusive OR signal and the second exclusive OR signal are XOR results; and an AND gate for The first enable signal is processed and processed with the XOR result to form the second enable signal or the third enable signal.
  • Forming the second enable signal and the third enable signal by using the exclusive OR circuit and the AND gate have the characteristics of simple circuit structure and low device cost.
  • FIG. 3 Also included in FIG. 3 are two first controlled switches SW11 and SW12; two second controlled switches SW21 and SW22. Two first controlled switches are respectively located at two ends of the first transmission path 110; The second controlled switches are respectively located at two ends of the second transmission path 120. These controlled switches are both used to control the operating states of the first transmission path 110 and the second transmission path 120.
  • the process deviation may be determined by comparing the first count value with the second count value.
  • the first transmission signal is the last stage of the first transmission path 110.
  • An output signal of the buffer; the second transmission signal is an output signal of the buffer of the last stage of the second transmission path 120.
  • the detecting unit 130 includes an analog signal conversion circuit.
  • the analog signal conversion circuit is configured to receive the first transmission signal and the second transmission signal, and output a corresponding analog signal according to a transmission delay of the first transmission signal and the second transmission signal;
  • the analog signal conversion circuit When the first transmission signal is applied to the analog signal conversion circuit, the analog signal conversion circuit outputs a first analog signal; when the second transmission signal is applied to the analog signal conversion circuit, the analog signal conversion circuit Outputting a second analog signal;
  • the first analog signal and the second analog signal can be used together to characterize the process deviation.
  • the first transmission signal is converted into an analog signal conversion circuit, so that the first transmission signal and the second transmission signal having different delays can be converted into the first analog signal and the second analog signal.
  • the process deviation of the circuit can be known by comparing the first analog signal with the second analog signal.
  • the first analog signal and the second analog signal may each be a voltage signal or a current signal or the like.
  • the detecting unit 130 further includes an Analog-to-Digital Convertor (ADC).
  • ADC Analog-to-Digital Convertor
  • An analog input terminal of the analog to digital converter and the analog signal conversion circuit The output ends are connected for receiving and performing analog-to-digital conversion on the first analog signal or the second analog signal; when the first transmission signal is applied to the analog signal conversion circuit, the analog-to-digital conversion unit Outputting a first digital signal corresponding to the first analog signal; when the second transmission signal is applied to the analog signal conversion circuit, the analog to digital conversion unit outputs a second number corresponding to the second analog signal a signal; the first digital signal and the second digital signal are used together to characterize the process deviation.
  • ADC Analog-to-Digital Convertor
  • a mode converter is introduced, and the first digital signal and the second digital signal are directly characterized by the analog-to-digital converter ADC.
  • ADC analog-to-digital converter
  • the first transmission path 110 and the second transmission path 120 each include an M-stage serial buffer; the first transmission signal includes M first buffer signals; The two transmission signals include M second buffer signals.
  • the buffer concatenation in the embodiment of the present application refers to the output of the previous stage buffer as the input of the subsequent stage buffer until the last stage buffer.
  • the value of the M may be an integer of 2, 3 or 4.
  • the analog signal conversion circuit includes: M controlled current sources I and a load capacitor C; the mth controlled current source I is configured to receive the m based on the first buffer signal or the mth a control signal formed by the second buffer signal, and continues or stops charging of the load capacitor C according to the control signal; the m is an integer not greater than the M; wherein the M is not less than an integer of 1.
  • the M controlled current sources may be packaged as a whole, including M power supply circuits that supply the load capacitor C.
  • the control signal may adopt a first buffer signal or a second buffer signal outputted by the first transmission path 110 or the second transmission path 120 through a bus where the controlled switch SW12 and the controlled switch SW22 are located as shown in FIG.
  • the first enable signal is input to the exclusive OR circuit for exclusive OR processing, and the XOR result formed after the exclusive OR process is a control signal of the controlled current and I.
  • the first enable signal is transmitted to the mth buffer of the first transmission path 110, the first buffer signal of the mth buffer output is at a high level, and the first enable signal is also a high level, An exclusive OR with the first enable signal will form a control signal that outputs a logic low level that controls the mth controlled source to stop charging the load capacitor.
  • the output of the mth buffer may be a logic low level and the first enable signal has passed the mth buffer. Then the output of the mth buffer is also the logic low level.
  • the logic high level is higher than a level of the reference low level relative to a reference level with respect to a reference level.
  • the analog input terminal of the analog-to-digital converter is connected to the load capacitor C for converting the capacitor voltage V Cap of the load capacitor C into a corresponding digital signal.
  • the capacitor voltage V Cap is the aforementioned first analog signal and the second analog signal.
  • Each of the controlled circuits is controlled by one of the first buffer and one of the second buffers, and determines whether to charge the load capacitor C according to an output of the first buffer or the second buffer.
  • the connection of the first transmission path 110 to the controlled current source I and the second transmission path 120 are turned on in a time division multiplexing manner. The connection of the controlled current source I is described. If the delay of the transmission path transmission signal is smaller, the shorter the time that the controlled capacitance receives the transmission signal, the shorter the charging time of the load capacitance C is, which may affect the load capacitance C. Finally, the capacitor voltage V Cap when charging is stopped; in this case, the analog signal input received by the analog-to-digital converter ADC is different, so that digital signals of different values will be output.
  • the digital signal output by the analog-to-digital converter ADC is detected when the signal transmitted by the first transmission path 110 and the second transmission path is applied to the controlled current source I by using the process deviation detecting circuit of the embodiment. And finally comparing the two digital signals can easily and accurately detect the process deviation.
  • the structure of the detection unit, the analog signal conversion circuit used in relation to the first structure Structures such as analog-to-digital converter ADCs are used for detection without additional reference clocks.
  • a plurality of process deviation detecting circuits in the embodiment may be flexibly disposed in the integrated chip, without considering Multiple process deviation detection circuits require the same reference clock, resulting in a reference clock that limits the layout of the detection circuitry or affects the setup of other functional structures within the integrated chip.
  • FIG. 6 is a graph showing the charging time of the load capacitor C of FIG. 5 as a function of the capacitor voltage V Cap .
  • the horizontal axis represents charging time
  • the vertical axis represents charging capacitance V Cap .
  • the charging time depends on the delay of the signals output by the buffers of the first transmission path 110 and the second transmission path 120. The smaller the delay, the corresponding controlled current source I charges the charging capacitor. The shorter the C charging time, the smaller the contribution to the formation of the larger capacitance voltage V Cap .
  • first controlled switches SW11 and SW12 at both ends of the first transmission path 110
  • second controlled switches SWE21 and SW22 are provided at both ends of the second transmission path 120.
  • the first controlled switch is for controlling an operating state of the first transmission path 110
  • the second controlled switch is for controlling an operating state of the second transmission path 120.
  • the process deviation detection when the process deviation detection is performed, if the first controlled switch is closed, the first transmission path 110 is in an active state to the The detecting unit 130 transmits a signal, the second controlled switch is in an off state, the second transmission path 120 is in a non-operating state, and the detecting unit 130 is a first transmission signal formed based on the first transmission path 110. Form the test results. If the second controlled switch is closed, the second transmission path 120 is in an active state to transmit a signal to the detecting unit 130, and when the first controlled switch is in an open state, the first transmission path 110 is in a non- In the working state, the detecting unit 130 forms a detection result based on the first transmission signal formed by the second transmission path 120. When the process deviation is determined subsequently, the two detection results are compared and processed, and the process deviation can be accurately and easily determined.
  • the first transmission signal includes M sub-signals, The output of the first buffer of each stage is respectively included; the second transmission signal also includes M sub-signals, which are output results of the second buffer of each stage.
  • the structure of the first buffer and the second buffer may be the buffer shown in FIG. 2, or a buffer of other structure may be used.
  • the third type is the third type.
  • the detecting unit 130 includes a Time-to-Digital Convertor (TDC);
  • TDC Time-to-Digital Convertor
  • the time digital signal converter is configured to receive the first transmission signal and the second transmission signal and output a conversion signal; the conversion signal can be used to characterize the process deviation.
  • One of the first transmission signal and the second transmission signal is used as a sampling clock of the time digital signal converter, and the other is used as a sampling signal of the time digital signal converter. If the transmission delay of the first transmission signal and the second transmission signal coincides, the number of outputs 1 in the converted signal of the TDC is equal to the number of outputs 0. If the output delays of the first transmission signal and the second transmission signal are inconsistent, the number of outputs 1 in the converted signal of the TDC is different from the number of outputs 0. Finally, in determining the process deviation, the process deviation can be calculated based on the number of 0s and 1 in the conversion signal and the number of phase differences between 0 and 1.
  • the time-to-digital conversion circuit TDC includes:
  • a third buffer of N stages in series is configured to receive the first input signal and perform N-stage buffering processing on the first input signal.
  • An nth delay flip-flop connected to the output end of the nth third buffer, receiving the first input signal and the second input signal subjected to the n-stage buffering process, based on the second input signal The first input signal performs delay trigger processing and outputs a delayed trigger result;
  • n is a positive integer not greater than N; and the N is an integer not less than 1;
  • the first input signal is the first transmission signal, and the second input signal is the first And transmitting the signal; or, the first input signal is the second transmission signal, and the second input signal is the first transmission signal.
  • the N triggers are in order: Q0, Q1, Q2, ..., QN-1 and QN.
  • the N delay flip-flops under the action of the first input signal and the second input signal, each of the delay flip-flops will output the delayed trigger result of 0 or 1 at its output terminal Q.
  • the N delay trigger results together constitute the converted signal.
  • the process deviation can be determined by counting the number of 0 or 1 of the delayed trigger results of the N delay flip-flops in the time-to-digital converter TDC.
  • the specific structure of the third buffer may adopt a structure as shown in FIG. 2, and other buffers in the prior art may also be used.
  • the buffer is used to buffer delay processing of the signal.
  • the third detecting unit 130 described in this embodiment can detect the process deviation caused by detecting the formed one-time conversion signal; and the above two methods have the characteristics of detecting the fast response speed.
  • the detection circuit 130 in this mode only needs to input a first enable signal, and does not need to introduce a signal such as a reference clock, and has the characteristics of simple structure and simple signal input.
  • the first input signal is used as the second transmission signal
  • the second input signal is the second transmission signal
  • the embodiment provides a process deviation detecting method, where the method includes:
  • Step S110 receiving and transmitting the first enable signal by using the first transmission path, and outputting the first transmission signal
  • Step S120 receiving and transmitting the first enable signal by using a second transmission path, and outputting a second transmission signal
  • Step S130 detecting a process deviation based on a transmission delay of the first transmission signal and the second transmission signal
  • the process deviation sensitivity of the first transmission path is a first sensitivity
  • the process deviation sensitivity of the second transmission path is a second sensitivity.
  • the method of this embodiment can be applied to the process deviation detecting circuit described in the foregoing circuit embodiment, and one of the first transmission path and the second transmission path serves as a reference transmission path of the other.
  • the process deviation sensitivity of the reference transmission path is known or negligible, so that the transmission delays of the first transmission signal and the second transmission signal formed by the two transmission paths can be easily and accurately measured. The process deviation.
  • the step S130 may include multiple implementation manners, and three optional methods are described below:
  • the step S130 may include:
  • first count value and the second count value are used together to characterize the process deviation.
  • the step S130 described herein is applicable to the circuit shown in FIG. 3, by which the received reference clock cycle is counted based on the second enable signal and the third enable signal, thereby obtaining the first
  • the transmission delay of the transmission signal and the second transmission signal is converted into a first count value and a second count value for the reference clock period.
  • the process deviation may be determined by comparing the first count value and the second count value when the process deviation is subsequently calculated.
  • the method for determining the process deviation described in this embodiment has the characteristics of simple implementation and simple circuit structure.
  • the method further includes:
  • the exclusive OR processing in this embodiment can be implemented by using a logic circuit exclusive OR circuit.
  • the AND process can be implemented using logic circuits and gates.
  • the step S130 may also include;
  • the first transmission signal is simulated a first analog signal is output when the signal is converted, and a second analog signal is output when the second signal is subjected to analog signal conversion; the first analog signal and the second analog signal can be used together to characterize the process deviation.
  • the transmission delays of the first transmission signal and the second transmission signal may be the same or different.
  • the first transmission signal and the second transmission signal are correspondingly converted into analog signals.
  • the analog signals herein may include voltage signals and current signals.
  • the analog signal can be detected by a detection device capable of detecting an analog signal, such as an ammeter or a voltmeter, and the detected analog signal can be used to characterize the process deviation.
  • the transmission delays of the first transmission signal and the second transmission signal are not directly measured, for example, the time when the first transmission signal and the second transmission signal are respectively measured by the timer component, and the time difference is represented by the arrival time difference. Process deviation.
  • the detecting unit 130 may further include a timer component such as a timer.
  • the first transmission signal and the second transmission signal are converted by an analog signal, and converted into an analog signal such as a voltage or a current, thereby simplifying the measurement.
  • the detecting unit 130 may further include a structure such as a detecting instrument that measures the analog signal.
  • step S130 further includes:
  • the digital signal includes a first digital signal corresponding to the first analog signal and corresponding to the a second digital signal of the second analog signal;
  • the first digital signal and the second digital signal are used together to characterize the process deviation.
  • the processing is further simplified, and the first analog signal and the second analog signal are also analog-to-digital converted, so that the output result is directly a digital signal.
  • the digital signal facilitates operations such as comparison processing to determine the process deviation.
  • Performing the analog to digital conversion can be performed using an analog to digital converter ADC.
  • the first transmission signal includes M first buffer signals; wherein the mth first buffer signal is buffering the m-1th first buffer signal Forming; the second transmission signal includes M second buffer signals; wherein the mth second buffer signal is formed by buffering the m-1th second buffer signal.
  • the step S110 may include: performing M-level buffer processing on the first enable signal to form a first transmission signal including M first buffer signals; and inputting the m-1th first buffer signal The mth level buffering process is performed to form the mth first buffered signal.
  • the step S120 may include: performing M-level buffer processing on the first enable signal to form a second transmission signal including M second buffer signals; and inputting the m-1th second buffer signal into the The mth level buffering process forms the mth of the second buffered signals.
  • step S130 further includes:
  • the m is an integer not greater than the M; wherein the M is not less than an integer of 1.
  • the mth controlled current source stops supplying power to the load capacitor, in which case the mth controlled current source The time to supply the load capacitor is short, which results in a small capacitor voltage of the load capacitor.
  • the first buffer signal and the second buffer signal are used as control signals of the controlled current source at different time points respectively, and the first transmission signal and the second transmission are implemented by the load capacitance.
  • the signal is converted into a corresponding analog signal.
  • the capacitor voltage of the load capacitor formed under the control of the first transmission signal and the second transmission signal is analog-digital converted as an analog signal to form a corresponding digital signal. Subsequent processing of the first digital signal and the second digital signal, etc., can accurately calculate the process deviation.
  • the step S130 may include:
  • the conversion signal can be used to characterize the process deviation.
  • the time-to-digital conversion process in the present embodiment may be a processing operation by the time-to-digital converter TDC. Transmitting the transmission delay of the first transmission signal and the second transmission signal by the number of times
  • the word conversion process which uses the conversion signal to characterize the process deviation, is also characterized by simple implementation.
  • step S130 may specifically include:
  • n is a positive integer not greater than N; and the N is not less than 1 Integer
  • the first input signal is the first transmission signal, and the second input signal is the second transmission signal; or the first input signal is the second transmission signal, the second input signal Is the first transmission signal.
  • the buffering process can be performed using a buffer, which can be a buffer as shown in FIG.
  • the delay trigger can be used to perform the delay trigger processing.
  • the delayed trigger result formed by the N delay triggers is used as the conversion result.
  • the second transmission path is preferably used as the reference transmission path, and the first transmission path is used as the detection path.
  • the method described in the present mode can be applied to the process deviation detecting circuit shown in FIG.
  • This embodiment provides an example of a method for detecting a parameter deviation different from the first mode and the second mode.
  • the method has the characteristics of simple implementation and fast detection speed.
  • the step S110 may include: buffering the first enable signal by using an M-stage serial buffer located on the first transmission path to form the first transmission signal.
  • the step S120 may include buffering the first enable signal by using an M-stage serial buffer located on the second transmission path to form the second transmission signal; wherein the M is not less than 1 The integer.
  • the detection of the process deviation can be implemented by using the counter as shown in FIG.
  • the detection circuit includes a first transmission path 110, a second transmission path 120, an exclusive OR circuit, an AND gate, and a counter.
  • the path of the first enable signal transmission is selected by controlling the controlled switches SW11, SW12, SW21, and SW22.
  • the first step is to first select the first transmission path 110, and the first enable signal and the output signal of the first transmission path 110 pass through the logic of the exclusive OR circuit and the AND gate as the enable signal of the counter.
  • the enable signal of the counter is high and the high level is not transmitted to the output A terminal of the first transmission path 110, the EN end of the counter is high, the counter starts and continues to count; when the high signal of the enable signal When transmitting to the output A terminal of the first transmission path 110, the EN terminal of the counter is low, the counter is stopped and the counting result is maintained.
  • the counter count result of the first transmission path 110 will remain a stable value.
  • the counting result of the first transmission path 110 is taken as a reference.
  • the second transmission path 120 is selected, and the same counting operation is repeated to obtain a counting result of the second transmission path 120.
  • the enable signal of the counter is high level and the high level is not transmitted to the output B terminal of the second transmission path 120
  • the EN end of the counter is high, the counter starts and continues to count; when the high signal of the enable signal When transmitting to the output B terminal of the second transmission path 120, the EN terminal of the counter is low, the counter is stopped and the counting result is maintained.
  • the counter count results of the second transmission path 120 may vary greatly under different process variations.
  • the count results of the two transmission paths are compared to detect the current process deviation.
  • the detection of the process deviation can be performed using the ADC as shown in FIG.
  • the electronic components also included in Figure 5 are: an OR gate, a charge current source, a load capacitor, a controlled switch, and an ADC.
  • the transmission of the first enable signal is performed through the first transmission path 110 by the conduction of the controlled switches SW11 and SW12.
  • the output of each stage buffer in the first transmission path 110 is collected to the A terminal, and each output of the A terminal is passed through an inverter, and is subjected to XOR processing of the first energy signal as a charging current source.
  • the charging control signal controls the magnitude of the charging current and the charging time of the load capacitor.
  • the output of each of the stages of buffers is the first buffered signal described in the previous embodiment. After the output signal of each stage buffer is XORed with the first enable signal, it is used as a control signal of the controlled current source.
  • the second transmission path 120 is controlled to perform transmission of the first enable signal by turning on and off the controlled switches SW21 and SW22.
  • the output of each stage buffer in the second transmission path 120 is collected to the B terminal, and each output of the B terminal is passed through an inverter, and after the first energy signal is made NAND, as a charging current source.
  • the charging control signal controls the magnitude of the charging current and the charging time of the load capacitor.
  • the output of each stage buffer is the second buffer signal described in the foregoing embodiment.
  • the deviation of the process is judged by comparing the outputs of the two ADCs.
  • the output of the ADC herein includes the first digital signal and the second digital signal. It should be noted that before the second transmission path 120 is turned on, the switch SW3 needs to be turned off to completely discharge the load capacitance; otherwise, the accuracy of the result will be affected.
  • first and second steps in this example can also be reversed.
  • only one of the controlled switches may be disposed on the first transmission path 110, and only one of the controlled switches may be disposed on the second transmission path 120.
  • a TDC is used to form a detection circuit.
  • the TDC mainly includes a buffer and a delay flip-flop.
  • the delay trigger can be a D flip-flop.
  • the first enable signal is simultaneously input to the first transmission path 110 and the second transmission path 120; the output of the first transmission path 110 serves as a clock of the TDC internal flip-flop, and the output of the second transmission path 120 is input to the TDC.
  • the buffer as the input signal of the D flip-flop in the TDC.
  • the Q-terminal output of the D flip-flop in the TDC is the final output of the detection circuit.
  • the output result here is the aforementioned conversion signal.
  • the first type: tDELAY1 tDELAY2, half of the TDC output result is 1 and half is 0; the tDELAY1 indicates the delay of the first transmission signal transmitted by the first transmission path 110; and the tDELAY2 indicates the transmission of the second transmission path 120. The delay of the second transmission signal.
  • the process deviation can be determined according to the number of 1s and the number of 0s in the output result of the TDC.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used in at least one of the process deviation detecting methods provided by any of the foregoing embodiments. For example, the process deviation detecting method as shown in FIG. 8 is performed.
  • the computer storage medium provided in this embodiment includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like.
  • the medium of the code optionally, the computer storage medium provided by the embodiment may be a non-transitory storage medium.
  • the non-transitory storage medium provided in this embodiment may be a flash memory of a non-volatile storage medium type.
  • two transmission paths can be created when the circuit is fabricated, which are a first transmission path and a second transmission path respectively, and an enable signal is input to the two transmission paths, and the detection path is transmitted. After that, the transmission signal is output; comparing the delays of the two transmission signals, the process deviation can be detected, the detection of the process deviation is simplified, and the detection accuracy can be improved.

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Abstract

一种工艺偏差检测电路及方法，所述电路包括：第一传输路径（110），用于接收并传输第一使能信号，输出第一传输信号；第二传输路径（120），用于接收并传输所述第一使能信号，输出第二传输信号；检测单元（130），用于基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差；其中，所述第一传输路径的工艺偏差敏感度为第一敏感度；所述第二传输路径的工艺偏差敏感度为第二敏感度。上述电路能够简便地检测表征工艺偏差的信号，实现工艺偏差精确和简便的检测。

Description

工艺偏差检测电路、方法和计算机存储介质 技术领域
本发明涉及电子技术领域，尤其涉及一种工艺偏差检测电路、方法和计算机存储介质。
背景技术
在电路(如集成电路、数模混合集成电路)设计中，为了保证芯片的性能，并且尽量地降低芯片的功耗，通常需要检测出芯片所处的工艺偏差，并根据工艺偏差动态地调整电源电压，从而达到降低功耗的目的。故如何检测及精确的检测出电路的工艺偏差是十分重要的。
发明内容
有鉴于此，本发明实施例期望提供一种工艺偏差检测电路、方法和计算机存储介质，以能简便精确够检测出工艺偏差。
本发明的技术方案是这样实现的：本发明第一方面公开了一种工艺偏差检测电路，所述电路包括：
第一传输路径，配置为接收并传输第一使能信号，输出第一传输信号；
第二传输路径，配置为接收并传输所述第一使能信号，输出第二传输信号；
检测单元，配置为基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差；
其中，所述第一传输路径的工艺偏差敏感度为第一敏感度；
所述第二传输路径的工艺偏差敏感度为第二敏感度。
基于上述方案，所述检测单元包括计数器；
所述计数器包括：
参考时钟信号引脚，配置为接收参考时钟；
第一使能引脚，配置为接收基于所述第一传输信号形成的第二使能信号，或接收基于所述第二传输信号形成的第三使能信号；
所述计数器，配置为基于所述第二使能信号对所述参考时钟进行计数输出第一计数值，或基于所述第三使能信号对所述参考时钟进行计数输出第二计数值；
其中，所述第一计数值和所述第二计数值共同用于表征所述工艺偏差。
基于上述方案，所述检测电路还包括：
异或电路异或电路，配置为将所述第一使能信号与所述第一传输信号进行异或处理形成第一异或信号；或将所述第一使能信号与所述第二传输信号进行异或处理形成第二异或信号；其中，所述第一异或信号和所述第二异或信号均为异或结果；
与门，配置为将所述第一使能信号与所述异或结果进行与处理，形成所述第二使能信号或所述第三使能信号。
基于上述方案，所述检测单元包括模拟信号转换电路；
所述模拟信号转换电路，配置为接收所述第一传输信号和所述第二传输信号，并根据所述第一传输信号和第二传输信号的传输时延，输出对应的模拟信号；
所述第一传输信号作用于所述模拟信号转换电路时，所述模拟信号转换电路输出第一模拟信号；所述第二传输信号作用于所述模拟信号转换电路时，所述模拟信号转换电路输出第二模拟信号；
所述第一模拟信号和所述第二模拟信号能够共同用于表征所述工艺偏差。
基于上述方案，所述检测单元还包括模数转换器；
所述模数转换器的模拟输入端与所述模拟信号转换电路的输出端相连，用于接收并对所述第一模拟信号或所述第二模拟信号进行模数转换；
所述第一传输信号作用于所述模拟信号转换电路时，所述模数转换单元输出对应于所述第一模拟信号的第一数字信号；所述第二传输信号作用于所述模拟信号转换电路时，所述模数转换单元输出对应于所述第二模拟信号的第二数字信号；
所述第一数字信号和所述第二数字信号共同用于表征所述工艺偏差。
基于上述方案，所述第一传输路径和所述第二传输路径均包括M级串联的缓冲器；所述第一传输信号包括M个第一缓冲信号；所述第二传输信号包括M个第二缓冲信号；
所述模拟信号转换电路包括：M个受控电流源及负载电容；
所述第m个受控电流源，配置为接收基于第m个所述第一缓冲信号或第m个所述第二缓冲信号形成的控制信号，并根据所述控制信号继续或停止所述负载电容充电；所述m为不大于所述M的整数；其中，所述M不小于1的整数；
所述模数转换器的模拟输入端，与所述负载电容相连，用于将所述负载电容的电容电压转换成对应的数字信号。
基于上述方案，所述检测单元包括时间数字转换器；
所述时间数字信号转换器，配置为接收第一传输信号和所述第二传输信号，并输出转换信号；
所述转换信号能够用于表征所述工艺偏差。
基于上述方案，所述时间数字转换电路包括：
N级串联的第三缓冲器，配置为接收第一输入信号并对所述第一输入信号进行N级缓冲处理；
N个延迟触发器；
第n个延迟触发器，连接在第n个所述第三缓冲器的输出端，接收所述第二输入信号及已进行n级缓冲处理的第一输入信号，基于所述第二输入信号对所述第一输入信号做延迟触发处理，并输出延迟触发结果；
其中，所述n为不大于N的正整数；所述N为不小于1的整数；
所述第一输入信号为所述第一传输信号，所述第二输入信号为所述第二传输信号；或，所述第一输入信号为所述第二传输信号，所述第二输入信号为所述第一传输信号。
基于上述方案，所述第一传输路径和所述第二传输路径均包括M级串联的缓冲器；
其中，所述M不小于1的整数。
本发明实施例第二方面提供一种工艺偏差检测方法，所述方法包括：
利用第一传输路径接收并传输第一使能信号，输出第一传输信号；
利用第二传输路径接收并传输所述第一使能信号，输出第二传输信号；
基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差；
其中，所述第一传输路径的工艺偏差敏感度为第一敏感度；
所述第二传输路径的工艺偏差敏感度为第二敏感度；
所述第一敏感度不等于所述第二敏感度。
基于上述方案，所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，包括：
接收参考时钟；
接收基于所述第一传输信号形成的第二使能信号或基于所述第二传输信号形成的第三使能信号；
基于所述第二使能信号对所述参考时钟进行计数输出第一计数值，或基于所述第三使能信号对所述参考时钟进行计数输出第二计数值；
其中，所述第一计数值和所述第二计数值共同用于表征所述工艺偏差。
基于上述方案，所述方法还包括：
将所述第一使能信号与所述第一传输信号进行异或处理形成第一异或信号；将所述第一使能信号与所述第二传输信号进行异或处理形成第二异或信号；其中，所述第一异或信号和所述第二异或信号均为异或结果；
将所述第一使能信号与所述异或结果进行与处理，形成所述第二使能信号或所述第三使能信号。
基于上述方案，所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，包括；
接收所述第一传输信号和所述第二传输信号，并根据所述第一传输信号和第二传输信号的传输时延，输出对应的模拟信号；其中，对所述第一传输信号进行模拟信号转换时，输出第一模拟信号；对所述第二传输信号进行模拟信号转换时，输出第二模拟信号；所述第一模拟信号和所述第二模拟信号能够共同用于表征所述工艺偏差。
基于上述方案，所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，还包括；
接收并对所述第一模拟信号或所述第二模拟信号进行模数转换，形成数字信号；其中，所述数字信号包括对应于所述第一模拟信号的第一数字信号及对应于所述第二模拟信号的第二数字信号；
所述第一数字信号和所述第二数字信号共同用于表征所述工艺偏差。
基于上述方案，所述第一传输信号包括M个第一缓冲信号；其中，第m个所述第一缓冲信号是对第m-1个所述第一缓冲信号进行缓冲处理形成的；
所述第二传输信号包括M个第二缓冲信号；其中，第m个所述第二缓冲信号是对第m-1个所述第二缓冲信号进行缓冲处理形成的；
所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，还包括；
根据基于第m个所述第一缓冲信号或第m个所述第二缓冲信号形成的控制信号，继续或停止第m个受控电流源向负载电容充电；
将所述负载电容的电容电压转换成对应的数字信号；
所述m为不大于所述M的整数；其中，所述M不小于1的整数。
基于上述方案，所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，包括：
对第一传输信号和所述第二传输信号进行时间数字转换处理，并输出转换信号；所述转换信号能够用于表征所述工艺偏差。
基于上述方案，所述对第一传输信号和所述第二传输信号进行时间数字转换处理，并输出转换信号，包括：
接收第一输入信号并对所述第一输入信号进行N级缓冲处理；
基于所述第二输入信号对已进行n级缓冲处理的第一输入信号做延迟触发处理，并输出延迟触发结果；其中，所述n为不大于N的正整数；所述N为不小于1的整数；
所述第一输入信号为所述第一传输信号，所述第二输入信号为所述第二传输信号；或，所述第一输入信号为所述第二传输信号，所述第二输入信号为所述第一传输信号。
基于上述方案，所述利用第一传输路径接收并传输第一使能信号，输出第一传输信号，包括：
利用位于所述第一传输路径上的M级串联的缓冲器对所述第一使能信号进行缓冲处理，形成所述第一传输信号；
所述利用第二传输路径接收并传输所述第一使能信号，输出第二传输信号，包括：
利用位于所述第二传输路径上的M级串联的缓冲器对所述第一使能信号进行缓冲处理，形成所述第二传输信号；
其中，所述M不小于1的整数。
本发明实施例第三方面提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述述工艺偏差检测方法的至少其中之一。
本发明实施例所述的工艺偏差检测电路、方法和计算机存储介质，通过检测第一传输路径和第二传输路径传输的第一传输信号和第二传输信号的传输时延，能够简便的检测表征所述工艺偏差的信号，从而实现了工艺偏差精确和简便的检测。
附图说明
图1为本发明实施例提供的第一种工艺偏差检测电路的结构示意图；
图2为本发明实施例提供的一种缓冲器的结构示意图；
图3为本发明实施例提供的第二种工艺偏差检测电路的结构示意图；
图4为图3所示电路的一种工作时序图；
图5为本发明实施例提供的第三种工艺偏差检测电路的结构示意图；
图6为本发明实施例提供的一种负载电容的电容电压与充电时间的函数关系图；
图7为本发明实施例提供的第四种工艺偏差检测电路的结构示意图；
图8为本发明实施例提供的所述工艺偏差检测方法的流程示意图。
具体实施方式
以下结合说明书附图及具体实施例对本发明的技术方案做进一步的详细阐述，应当理解，以下所说明的优选实施例仅用于说明和解释本发明， 并不用于限定本发明。
如图1所示，本实施例提供一种工艺偏差检测电路，所述电路包括：
第一传输路径110，配置为接收并传输第一使能信号，输出第一传输信号；
第二传输路径120，配置为接收并传输所述第一使能信号，输出第二传输信号；
检测单元130，配置为基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差；
其中，所述第一传输路径的工艺偏差敏感度为第一敏感度；
所述第二传输路径的工艺偏差敏感度为第二敏感度。
在本实施例中提供了一种检测电路，该检测电路中设置有两条传输路径；这两条传输路径对工艺敏感度可以一样，也可不一样的；即所述第一敏感度可等于或不等于所述第二敏感度。所述第一敏感度和所述第二敏感度中的其中一个为已知的或可忽略不计的；此处的忽略不计为对工艺偏差敏感度小，工艺偏差对其电气性特性的影响可忽略不计，这样的话该敏感度对应的传输路径就可作为另一条传输路径的参考传输路径。
通常所述第一传输路径110和第二传输路径120中的其中一条为工艺敏感度是小于预定阈值，该传输路径可作为工艺偏差检测的参考传输路径。所述预定阈值可为事先预定的值，可为根据模拟仿真或对试验品的检测确定得到的阈值。若工艺偏差敏感度小于所述预定阈值，则表示该条传输路径对工艺偏差不敏感的参考传输路径；且通常参考传输路径由于对工艺偏差的敏感度小，在进行检测可以忽略不计。且对参考传输路径的工艺偏差的忽略不计，对工艺偏差检测精确度一般很小。
当然，所述第一传输路径110和第二传输路径120中的其中一条对工艺敏感度可以是事先通过模拟仿真或对试验品预先知道的，这时，该条传 输路径也可以作为上述参考传输路径，用于工艺偏差检测。
在本实施例中还包括检测单元130，所述检测单元130通过检测所述第一传输路径和第二传输路径对信号传输的时延来确定工艺偏差。当不存在工艺偏差时，制作出的所述第一传输路径和所述第二传输路径都应该是按照设计标准，在指定时延将信号传输到指定的电子元器件，由于工艺偏差的存在可能导致制作出的传输路径的阻抗等电气特性发生了改变，从而将导致信号传输时延过大或传输时延过小等问题，故在本实施例中利用所述检测单元通过检测第一传输路径和第二传输路径的传输时延，就能检测出所述工艺偏差。
本实施例所述工艺偏差检测电路可为集成芯片内部电路的组成部分、也可以为印刷电路板上电路的组成部分，这些电路结构中通过增设本实施例中所述工艺偏差检测电路，方便对这些电路结构进行工艺偏差检测，从而能够精确的确定出需要给所述电路结构中对应的电子元器件提供的电源。
在本实施例中所述第一传输路径和所述第二传输路径均包括M级串联的缓冲器；其中，所述M不小于1的整数。譬如所述M为2、3、4、5、7……、20……、30……等值，具体的取值范围根据电路设计的需要来设定。
所述缓冲器能够用于暂时缓冲输入信号，对输入信号做一定延时处理之后，输入对应的输入信号。
如图2所示，本实施例提供一种前述缓冲器的内部结构。所述缓冲器包括一个输入端、一个输出端、两个P沟道金属氧化物半导体场效应晶体管(Positive channel Metal Oxide Semiconductor，PMOS)及两个N沟道金属氧化物半导体场效应晶体管(Negative channel Metal Oxide Semiconductor，NMOS)。两个所述PMOS分别为图2中的M1和M2；两个所述NMOS分别为图2中的M3和M4。所述缓冲器的输入端连接在M1 和M3的栅极。M1和M2的漏极都与电源电压相连。M1的源极与M3的漏极相连，M3的源极接地。M4的漏极与M2的源极相连，M4的源极接地。M2和M4的栅极连接在M3的漏极。M2的源极和M4的漏极与输出端相连。采用如图2所示的缓冲器，具有结构简单及制作成本低廉的特点。
如图1所示，为了方便控制所述检测电路的工作，在所述第一传输路径110设置有第一受控开关K1，在所述第二传输路径120设置有第二受控开关K2，所述第一受控开关K1和第二受控开关K2，能够用于导通或断开所述第一传输路径110和所述第二传输路径120。所述第一受控开关K1和第二受控开关K2可为晶体管或三极管等结构。采用所述晶体管或三极管具有结构简单、成本低等特点。在本实施例中通过所述第一受控开关K1和第二受控开关K2的设置，能够便捷的控制所述工艺偏差检测电路的工作状态。
所述检测单元的电路结构有多种，以下提供几种可选方式。
第一种：
如图3所示，所述检测单元130包括计数器；
所述计数器包括：
参考时钟信号引脚CLK，配置为接收参考时钟；
第一使能引脚EN，配置为接收基于所述第一传输信号形成的第二使能信号，或接收基于所述第二传输信号形成的第三使能信号；
所述计数器，配置为基于所述第二使能信号对所述参考时钟进行计数输出第一计数值，或基于所述第三使能信号对所述参考时钟进行计数输出第二计数值；
其中，所述第一计数值和所述第二计数值共同用于表征所述工艺偏差。
本实施例中所述计数器的参考时钟信号引脚CLK，接收参考时钟。第一使能引脚EN用于接收使能信号。而第一使能引脚接收EN的使能信号是 基于第一传输信号形成的第二使能信号或基于第二传输信号形成的第三使能信号。
本实施例中所述计数器用于在所述第二使能信号或所述第三使能信号的作用下，对接收到的时钟信号进行计数。所述计数器配置为在第二使能信号和第二使能信号使能所述计数器的情况下，每接收到一个所述参考时钟周期就计1。所述第一计数值和第二计数值均为图3中计数器输出的计数结果。
图4为本实施例中利用计数器形成检测单元130的一个时序图。在图4中，标准时延对应的时钟个数P1、时延过大对应的时钟个数P3及时延过小的时钟个数P2。所述P1、P2和P3都可能成为图3所示计数器的计数结果。当然在本实施例中基于第一传输信号和第二传输信号分别形成所述第二使能信号和第三使能信号，这样的所述计数器的结果在一次检测时，仅可能两个计数结果。将其中一个计数结果视为标准时延对应的时钟个数P1进行工艺偏差的确定。
本实施例中所述第二使能信号和所述第三使能信号的形成电路有很多种，以下提供一种简便的实现方式。所述检测电路130还包括：异或电路，用于将所述第一使能信号与所述第一传输信号进行异或处理形成第一异或信号；或用于将所述第一使能信号与所述第二传输信号进行异或处理形成第二异或信号；其中，所述第一异或信号和所述第二异或信号均为异或结果；与门，用于将所述第一使能信号与所述异或结果进行与处理，形成所述第二使能信号或所述第三使能信号。
采用上述异或电路和与门形成所述第二使能信号和第三使能信号具有电路结构简单、器件成本低等特点。
在图3中还包括两个第一受控开关SW11和SW12；两个第二受控开关SW21和SW22。两个第一受控开关分别位于第一传输路径110的两端；两 个所述第二受控开关分别位于所述第二传输路径120的两端。这些受控开关均用于控制所述第一传输路径110和第二传输路径120的工作状态。
在后续具体确定工艺偏差时，可以通过比较所述第一计数值和所述第二计数值，确定出所述工艺偏差。
值得注意的是：在本种结构中，若所述第一传输路径110和第二传输路径120均包括M级的缓冲器，所述第一传输信号为第一传输路径110最后一级所述缓冲器的输出信号；所述第二传输信号的为所述第二传输路径120最后一级所述缓冲器的输出信号。
第二种：
所述检测单元130包括模拟信号转换电路。
所述模拟信号转换电路，配置为接收所述第一传输信号和所述第二传输信号，并根据所述第一传输信号和第二传输信号的传输时延，输出对应的模拟信号；
所述第一传输信号作用于所述模拟信号转换电路时，所述模拟信号转换电路输出第一模拟信号；所述第二传输信号作用于所述模拟信号转换电路时，所述模拟信号转换电路输出第二模拟信号；
所述第一模拟信号和所述第二模拟信号能够共同用于表征所述工艺偏差。
本实施例中将所述第一传输信号转换成模拟信号转换电路，这样的话，就能把具有不同延时的第一传输信号和第二传输信号，转换成第一模拟信号和第二模拟信号。在检测所述工艺偏差时，通过比对所述第一模拟信号和第二模拟信号，就可以知道电路的工艺偏差。所述第一模拟信号和第二模拟信号均可为电压信号或电流信号等。
如图5所示，所述检测单元130还包括模数转换器(Analog-to-Digital Convertor，ADC)。所述模数转换器的模拟输入端与所述模拟信号转换电路 的输出端相连，用于接收并对所述第一模拟信号或所述第二模拟信号进行模数转换；所述第一传输信号作用于所述模拟信号转换电路时，所述模数转换单元输出对应于所述第一模拟信号的第一数字信号；所述第二传输信号作用于所述模拟信号转换电路时，所述模数转换单元输出对应于所述第二模拟信号的第二数字信号；所述第一数字信号和所述第二数字信号共同用于表征所述工艺偏差。
在本实施例中为了方便确定所述工艺偏差，不用检测第一模拟信号和第二模拟信号，引入了模式转化器，通过模数转换器ADC直接表征第一数字信号和第二数字信号。通过比较所述第一数字信号和所述第二数字信号，就知道第一传输路径110和第二传输路径120的传输时延，进而确定出工艺偏差。
作为本种结构另一个实施例，所述第一传输路径110和所述第二传输路径120均包括M级串联的缓冲器；所述第一传输信号包括M个第一缓冲信号；所述第二传输信号包括M个第二缓冲信号。本申请实施例中所述缓冲器串联是指前一级缓冲器的输出作为后一级缓冲器的输入，直至到最后一级缓冲器。所述M的取值可为2、3或4等整数。
所述模拟信号转换电路包括：M个受控电流源I及负载电容C；所述第m个受控电流源I，配置为接收基于第m个所述第一缓冲信号或第m个所述第二缓冲信号形成的控制信号，并根据所述控制信号继续或停止所述负载电容C充电；所述m为不大于所述M的整数；其中，所述M不小于1的整数。在具体的实现时，M个所述受控电流源可以封装为一个整体，包括M个向负载电容C供电的供电电路。
所述控制信号可采用如图5所示的通过受控开关SW12和受控开关SW22所在的总线，将第一传输路径110或第二传输路径120输出的第一缓冲信号或第二缓冲信号及第一使能信号输入异或电路进行异或处理，异或 处理之后形成的异或结果为受控电流与I的控制信号。第一使能信号传输到第一传输路径110的第m个缓冲器时，所述第m个缓冲器输出端的第一缓冲信号为高电平，第一使能信号也为高电平，通过与第一使能信号的异或处理，将形成输出为逻辑低电平的控制信号，该控制信号控制控制第m个受控电源停止向负载电容充电。当然若所述第一使能信号为传输到第m个缓冲器则第m个缓冲器的输出可为逻辑低电平且所述第一使能信号已过了所述第m个缓冲器，则所述第m个缓冲器的输出也为所述逻辑低电平。所述逻辑高电平为相对于参考电平比所述逻辑低电平相对于参考电平的电平高。所述模数转换器的模拟输入端，与所述负载电容C相连，用于将所述负载电容C的电容电压VCap转换成对应的数字信号。这里所述电容电压VCap即为前述所述第一模拟信号和所述第二模拟信号。
每一个所述受控电路受一个所述第一缓冲器和一个所述第二缓冲器控制，根据所述第一缓冲器或第二缓冲器的输出，确定是否向所述负载电容C充电。在图5所示的电路中，采用时分复用的方式，在不同时间内导通所述第一传输路径110与所述受控电流源I的连接，及所述第二传输路径120与所述受控电流源I的连接。若传输路径传输信号的时延越小，则受控电容接收到所述传输信号的时间越短，则对所述负载电容C充电的时间也就越短，这样从而会影响所述负载电容C最后被停止充电时的电容电压VCap；这样的话，所述模数转换器ADC接收到的模拟信号输入就不同，从而将输出不同值的数字信号。
利用本实施例所述的工艺偏差检测电路分别检测所述第一传输路径110和第二传输路径传输的信号作用于所述受控电流源I时，所述模数转换器ADC输出的数字信号，并最终比较这两个数字信号就可以简便精确的检测出所述工艺偏差。
本种检测单元的结构，相对于第一种结构，采用的模拟信号转换电路 及模数转换器ADC等结构来进行检测，不用额外引入参考时钟。这样的话，当集成芯片中需要检测多个集成芯片内的元器件附件的工艺偏差时，可以在所述集成芯片中灵活的设置多个本实施例中所述工艺偏差检测电路，而不用考虑在多个工艺偏差检测电路需要采用同样的参考时钟，导致参考时钟限制了检测电路布局或影响集成芯片内部其他功能结构的设置的问题。
图6所示的为图5所述负载电容C的充电时间与电容电压VCap的函数关系图。在图6中横轴表示充电时间，纵轴表示充电电容VCap。而所述充电时间取决于所述第一传输路径110和所述第二传输路径120上各级缓冲器输出的信号的时延，时延越小，对应的受控电流源I向充电电容充电C充电的时间越短，对形成较大的所述电容电压VCap的贡献值就越小。
在图5中同样在所述第一传输路径110的两端设置有第一受控开关SW11和SW12，在所述第二传输路径120的两端设置有第二受控开关SWE21和SW22。第一受控开关用于控制所述第一传输路径110的工作状态，第二受控开关用于控制所述第二传输路径120的工作状态。
在所述检测单元130的第一种结构和第二种结构中，在进行所述工艺偏差检测时，若所述第一受控开关闭合，所述第一传输路径110处于工作状态向所述检测单元130传输信号，在所述第二受控开关处于断开，所述第二传输路径120处于非工作状态，所述检测单元130是基于所述第一传输路径110形成的第一传输信号形成检测结果。若所述第二受控开关闭合，所述第二传输路径120处于工作状态向所述检测单元130传输信号，在所述第一受控开关处于断开，所述第一传输路径110处于非工作状态，所述检测单元130是基于所述第二传输路径120形成的第一传输信号形成检测结果。在后续确定所述工艺偏差时，将这两次的检测结果进行比对等处理，就能精确简便的确定出所述工艺偏差。
值得注意的是：在本种结构中，所述第一传输信号包括M个子信号， 分别为每一级所述第一缓冲器的输出结果；所述第二传输信号也包括M个子信号，分别是每一级所述第二缓冲器的输出结果。
本实施例中所述第一缓冲器和所述第二缓冲器的结构可以采用图2中所示的缓冲器，也可以采用其他结构的缓冲器。
第三种：
所述检测单元130包括时间数字转换器(Time-to-Digital Convertor，TDC)；
所述时间数字信号转换器，配置为接收第一传输信号和所述第二传输信号，并输出转换信号；所述转换信号能够用于表征所述工艺偏差。
所述第一传输信号和所述第二传输信号中有一个作为所述时间数字信号转换器的采样时钟，另外一个则作为所述时间数字信号转换器的采样信号。若所述第一传输信号与所述第二传输信号的传输时延一致，则所述TDC的转换信号中输出1的个数与输出0的个数相等。若所述第一传输信号和所述第二传输信号的输出延时不一致，则所述TDC的转换信号中输出1的个数与输出0的个数不等。最后在确定所述工艺偏差时，可以根据转换信号中0和1的个数以及0和1的相差个数计算出所述工艺偏差。
如图7所示，所述时间数字转换电路TDC包括：
N级串联的第三缓冲器，配置为接收第一输入信号并对所述第一输入信号进行N级缓冲处理。
N个延迟触发器；
第n个延迟触发器，连接在第n个所述第三缓冲器的输出端，接收进行了n级缓冲处理的第一输入信号及第二输入信号，基于所述第二输入信号对所述第一输入信号做延迟触发处理，并输出延迟触发结果；
其中，所述n为不大于N的正整数；所述N为不小于1的整数；
所述第一输入信号为所述第一传输信号，所述第二输入信号为所述第 二传输信号；或，所述第一输入信号为所述第二传输信号，所述第二输入信号为所述第一传输信号。
所述N个触发器依次是：Q0、Q1、Q2……QN-1及QN。所述N个延迟触发器在所述第一输入信号和所述第二输入信号的作用下，每一个所述延迟触发器将在其输出端Q输出为0或1的所述延迟触发结果。N个所述延迟触发结果共同组成了所述转换信号。通过统计所述时间数字转换器TDC内N个延迟触发器的所述延迟触发结果中的0或1的个数，从而能够确定工艺偏差。
所述第三缓冲器的具体结构均可以采用如图2中所示结构，也可以采用现有技术中其他的缓冲器。总之所述缓冲器用于对信号进行缓冲延时处理。
显然本实施例所述第三种检测单元130，检测形成的一次转换信号，就能表征出工艺偏差；相对前述两种方法具有检测响应速度快的特点。同样，本种方式中的所述检测电路130仅需输入一个第一使能信号即可，不用引入参考时钟等信号，具有结构简单及信号输入简单的特点。
本种结构中，图7所示的结果中，采用所述第一输入信号为第二传输信号，所述第二输入信号为所述第二传输信号。
如图8所示，本实施例提供一种工艺偏差检测方法，所述方法包括：
步骤S110：利用第一传输路径接收并传输第一使能信号，输出第一传输信号；
步骤S120：利用第二传输路径接收并传输所述第一使能信号，输出第二传输信号；
步骤S130：基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差；
其中，所述第一传输路径的工艺偏差敏感度为第一敏感度；
所述第二传输路径的工艺偏差敏感度为第二敏感度。
本实施例所述方法能够应用于前述电路实施例中所述的工艺偏差检测电路中，所述第一传输路径和所述第二传输路径中的一个作为另一个的参考传输路径。而通常所述参考传输路径的工艺偏差敏感度已知或可忽略不计，这样通过两个传输路径形成的第一传输信号和所述第二传输信号的传输时延，就能简便精确的测量出所述工艺偏差。
所述步骤S130可包括多种实现方式，以下介绍三种可选方式：
方式一：
所述步骤S130可包括：
接收参考时钟；
接收基于所述第一传输信号形成的第二使能信号或基于所述第二传输信号形成的第三使能信号；
基于所述第二使能信号对所述参考时钟进行计数输出第一计数值，或基于所述第三使能信号对所述参考时钟进行计数输出第二计数值；
其中，所述第一计数值和所述第二计数值共同用于表征所述工艺偏差。
此处所述的步骤S130可应用于如图3所示的电路中，通过所述计数器，基于第二使能信号和第三使能信号对接收的参考时钟周期进行计数，从而获得将第一传输信号和第二传输信号的传输时延，转换成对所述参考时钟周期的第一计数值和第二计数值。在后续计算所述工艺偏差时，可通过比对所述第一计数值和所述第二计数值，确定出所述工艺偏差。
本实施例所述的确定所述工艺偏差的方法，具有实现简单及实现电路结构简单的特点。
所述方法还包括：
将所述第一使能信号与所述第一传输信号进行异或处理形成第一异或信号；将所述第一使能信号与所述第二传输信号进行异或处理形成第二异 或信号；其中，所述第一异或信号和所述第二异或信号均为异或结果；
将所述第一使能信号与所述异或结果进行与处理，形成所述第二使能信号或所述第三使能信号。
此处，进一步限定了如何根据第一传输信号和第二传输信号，分别形成所述第二使能信号和第三使能信号。
本实施例所述异或处理可以采用逻辑电路异或电路来实现。所述与处理可以采用逻辑电路与门来实现。
基于所述第一传输信号和第二传输信号形成所述第二使能信号和所述第三使能信号的方法还有多种，不局限于上述任意一种，此处就不再一一进行描述了。
方式二：
所述步骤S130也可包括；
接收所述第一传输信号和所述第二传输信号，并根据所述第一传输信号和第二传输信号的传输时延，输出对应的模拟信号；其中，对所述第一传输信号进行模拟信号转换时，输出第一模拟信号；对所述第二传输信号进行模拟信号转换时，输出第二模拟信号；所述第一模拟信号和所述第二模拟信号能够共同用于表征所述工艺偏差。
所述第一传输信号和所述第二传输信号的传输时延，可能相同也可能不同，在本实施例中，将所述第一传输信号和第二传输信号对应转换成模拟信号。此处的模拟信号可包括电压信号和电流信号。所述模拟信号可以用电流表或电压表等能够检测模拟信号的检测器件检测到，检测到的所述模拟信号可用于表征所述工艺偏差。
当然在具体实现，本实施例中不是直接测量第一传输信号和第二传输信号的传输时延，例如通过计时器件分别计量第一传输信号和第二传输信号达到的时间，通过到达时间差表征所述工艺偏差。这样方式虽然可以实 现表征工艺偏差的参数的测量，但是要求所述计时器件的灵敏度和精确度高，就当前的计时仪表的性能，可能实现较为困难。但是不排除后续随着技术的发展，利用所述计时器件也能简易的测量出表征所述工艺偏差的参数。故结合前述电路实施例，所述检测单元130还可以包括计时器等计时器件。而在本实施例中为了实现检测简便，将第一传输信号和第二传输信号通过模拟信号转换，转换成电压或电流等模拟信号，简化了测量。结合前述电路实施例可知，所述检测单元130还可包括测量所述模拟信号的检测仪表等结构。
具体地，所述步骤S130还包括；
接收并对所述第一模拟信号或所述第二模拟信号进行模数转换，形成数字信号；其中，所述数字信号包括对应于所述第一模拟信号的第一数字信号及对应于所述第二模拟信号的第二数字信号；
所述第一数字信号和所述第二数字信号共同用于表征所述工艺偏差。
在本实施例中进一步简化处理，还将所述第一模拟信号和第二模拟信号机型模数转换处理，这样输出的结果直接为数字信号。所述数字信号方便进行比对处理等操作，确定出所述工艺偏差。
进行所述模数转换可以采用模数转换器ADC来进行。
作为本实施例中的进一步改进，所述第一传输信号包括M个第一缓冲信号；其中，第m个所述第一缓冲信号是对第m-1个所述第一缓冲信号进行缓冲处理形成的；所述第二传输信号包括M个第二缓冲信号；其中，第m个所述第二缓冲信号是对第m-1个所述第二缓冲信号进行缓冲处理形成的。
即所述步骤S110可包括：对所述第一使能信号进行M级缓冲处理，形成包括M个第一缓冲信号的第一传输信号；且将第m-1个所述第一缓冲信号输入进行第m级缓冲处理形成所述第m个所述第一缓冲信号。
所述步骤S120可包括：对所述第一使能信号进行M级缓冲处理，形成包括M个第二缓冲信号的第二传输信号；且将第m-1个所述第二缓冲信号输入进行第m级缓冲处理形成所述第m个所述第二缓冲信号。
这样的话，所述步骤S130还包括；
根据基于第m个所述第一缓冲信号或第m个所述第二缓冲信号形成的控制信号，控制第m个受控电流源向负载电容充电；
将所述负载电容的电容电压转换成对应的数字信号；
所述m为不大于所述M的整数；其中，所述M不小于1的整数。
通常所述第m个受控电流源在接收到所述第一缓冲信号后，所述第m个受控电流源停止向所述负载电容供电，这样的话，所述第m个受控电流源向所述负载电容供电的时间就短，这样就会导致所述负载电容的电容电压较小。
在本实施例中利用第一缓冲信号和第二缓冲信号，在不同的时间点分别作为所述受控电流源的控制信号，通过向所述负载电容，实现将第一传输信号和第二传输信号转换成对应的模拟信号。为了方便检测，将在所述第一传输信号和第二传输信号分别控制下形成的负载电容的电容电压作为模拟信号进行模数转换形成对应的数字信。后续通过比对所述第一数字信号和所述第二数字信号等处理，可以精确计算出所述工艺偏差。
本方式所述的方法可以应用于如图5所示的电路中。
方式三：
所述步骤S130可包括：
对第一传输信号和所述第二传输信号进行时间数字转换处理，并输出转换信号；所述转换信号能够用于表征所述工艺偏差。
在本实施例中所述时间数字转换处理可为由时间数字转换器TDC进行处理操作。将所述第一传输信号和第二传输信号的传输时延，通过时间数 字转换处理，利用转换信号来表征所述工艺偏差，同样具有实现简单的特点。
在本方式中，所述步骤S130可具体包括：
接收第一输入信号并对所述第一输入信号进行N级缓冲处理；
基于所述第二输入信号对已进行n级缓冲处理的第一输入信号做延迟触发处理，并输出延迟触发结果；其中，所述n为不大于N的正整数；所述N为不小于1的整数；
所述第一输入信号为所述第一传输信号，所述第二输入信号为所述第二传输信号；或，所述第一输入信号为所述第二传输信号，所述第二输入信号为所述第一传输信号。
在本方式中可以利用缓冲器做所述缓冲处理，所述缓冲器可如图2所示的缓冲器。可以利用所述延时触发器做所述延时触发处理。N个所述延时触发器形成的延时触发结果作为所述转换结果。
在本方式中优选为所述第二传输路径作为所述参考传输路径，所述第一传输路径作为所述检测路径。
本方式中所述的方法能够应用于图7所示的工艺偏差检测电路中。
本实施例提供例一种有别于方式一和方式二的另一种表征工艺偏差的参数的检测方法，同样具有实现简单的特点，且具有检测速度快的特点。
在方式一和方式三中，所述步骤S110可包括：利用位于所述第一传输路径上的M级串联的缓冲器对所述第一使能信号进行缓冲处理，形成所述第一传输信号。所述步骤S120可包括利用位于所述第二传输路径上的M级串联的缓冲器对所述第一使能信号进行缓冲处理，形成所述第二传输信号；其中，所述M不小于1的整数。
以上结合上述任意实施例提供三个具体示例：
示例一：
在应用场景中如果有参考时钟及计数器，可以采用如图3为计数器实现工艺偏差的检测。
检测电路包括第一传输路径110、第二传输路径120、一个异或电路，一个与门以及一个计数器。
通过控制受控开关SW11、SW12、SW21和SW22来选择第一使能信号传输的路径。
第一步：首先选择第一传输路径110，第一使能信号与第一传输路径110的输出信号经过异或电路及与门组成的逻辑，作为计数器的使能信号。当计数器的使能信号为高电平，并且高电平并未传输到第一传输路径110的输出A端时，计数器的EN端为高，计数器开始并持续计数；当使能信号的高电平传输到第一传输路径110的输出A端时，计数器的EN端为低，计数器停止并保持计数结果。
假设第一传输路径110的时延受工艺偏差影响很小，因此第一传输路径110的计数器计数结果将保持一个稳定值。以第一传输路径110的计数结果作为参考。
第二步：
选择第二传输路径120，并且重复相同的计数操作得到第二传输路径120的计数结果。当计数器的使能信号为高电平，并且高电平并未传输到第二传输路径120的输出B端时，计数器的EN端为高，计数器开始并持续计数；当使能信号的高电平传输到第二传输路径120的输出B端时，计数器的EN端为低，计数器停止并保持计数结果。假设第二传输路径120的传输延时对工艺偏差很敏感，因此第二传输路径120的计数器计数结果在不同的工艺偏差下会有很大差别。第三步：
将两个传输路径的计数结果作比较，从而检测出当前的工艺偏差。
值得注意的是：本示例中所述第一步和第二步的顺序可颠倒。
示例二：
如果应用场景中有ADC，并且允许使用电容、充电电流源等模拟模块，则可以采用如图5所示的ADC就行所述工艺偏差的检测。
在图5中还包括的电子元器件有：一个或门，充电电流源，一个负载电容，受控开关及ADC。
利用图5所示的电路可以采用以下方法进行工艺偏差检测：
第一步：
通过受控开关SW11和SW12的导通，通过第一传输路径110进行第一使能信号的传输。第一传输路径110中的每一级缓冲器的输出均汇集到A端，将A端的每个输出均经过反相器，并与使第一能信号做异或处理后，作为充电电流源的充电控制信号，控制其对负载电容的充电电流大小与充电时间。所述每一级缓冲器的输出即为前述实施例中所述第一缓冲信号。各级缓冲器的输出信号与第一使能信号进行异或处理之后，作为所述受控电流源的控制信号。
当第一使能信号的正向脉冲传输到最后一级缓冲器时，充电电流源上的所有控制信号均为低，充电使能关闭，VCap电压保持。因此，第一传输路径110的延时越长，负载电容上面的电压VCap越高。VCap电压最后经ADC输出转化为数字信号。
第二步：
同样通过受控开关SW21和SW22的导通和关闭，控制第二传输路径120进行所述第一使能信号的传输。第二传输路径120中的每一级缓冲器的输出均汇集到B端，将B端的每个输出均经过反相器，并与使第一能信号做与非处理后，作为充电电流源的充电控制信号，控制其对负载电容的充电电流大小与充电时间。所述每一级缓冲器的输出即为前述实施例中所述第二缓冲信号。
第三步：
通过比较两次ADC的输出判断工艺的偏差。这里的所述ADC的输出即包括所述第一数字信号和所述第二数字信号。有一点需要注意的是，在导通第二传输路径120之前，需要先关闭开关SW3，对负载电容进行彻底放电；否则会影响结果的精确性。
值得注意的是：本示例中的所述第一步和第二步同样可颠倒。在示例一和示例二中第一传输路径110上可仅设置一个所述受控开关，所述第二传输路径120上也可以仅设置一个所述受控开关。
示例三：
本示例中利用TDC组成检测电路。如图7所示，所述TDC主要包括缓冲器和延时触发器。所述延时触发器可为D触发器。
第一步：
将所述第一使能信号同时输入第一传输路径110和第二传输路径120；所述第一传输路径110的输出作为TDC内部触发器的时钟，而第二传输路径120的输出，输入TDC的缓冲器中，作为TDC中D触发器的输入信号。TDC中D触发器的Q端输出结果作为检测电路最终输出结果。此处的输出结果即为前述的转换信号。
输出结果存在以下三种情形：
第一种：tDELAY1＝tDELAY2，TDC输出结果中一半为1，一半为0；所述tDELAY1表示第一传输路径110传输的第一传输信号的时延；所述tDELAY2表示第二传输路径120传输的第二传输信号的时延。
第二种：tDELAY1>tDELAY2，TDC的输出结果中1比0多。
第三种：tDELAY1<tDELAY2时，TDC的输出结果中1比0少。
最后可根据TDC的输出结果中1的个数和0的个数确定出所述工艺偏差。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于前述任意实施例提供的所述工艺偏差检测方法的至少其中之一，例如，执行如图8所示的工艺偏差检测方法。
本实施例提供的所述计算机存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质，可选地，本实施例提供的计算机存储介质可为非瞬间存储介质。本实施例提供的非瞬间存储介质可为非易失性存储介质类型的闪存flash。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，凡按照本发明原理所作的修改，都应当理解为落入本发明的保护范围任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
工业实用性
本发明实施例中提供的电路，在制作电路时就可制作出两条传输路径，分别是第一传输路径和第二传输路径，向这两条传输路径分别输入使能信号，检测径过传输之后输出传输信号；比较两传输信号的时延，就能够检测出工艺偏差，简化了工艺偏差的检测，且能够提高检测精确度。

Claims (19)

  1. 一种工艺偏差检测电路，所述电路包括：
    第一传输路径，配置为接收并传输第一使能信号，输出第一传输信号；
    第二传输路径，配置为接收并传输所述第一使能信号，输出第二传输信号；
    检测单元，配置为基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差；
    其中，所述第一传输路径的工艺偏差敏感度为第一敏感度；
    所述第二传输路径的工艺偏差敏感度为第二敏感度。
  2. 根据权利要求1所述的电路，其中，
    所述检测单元包括计数器；
    所述计数器包括：
    参考时钟信号引脚，配置为接收参考时钟；
    第一使能引脚，配置为接收基于所述第一传输信号形成的第二使能信号，或接收基于所述第二传输信号形成的第三使能信号；
    所述计数器，配置为基于所述第二使能信号对所述参考时钟进行计数输出第一计数值，或基于所述第三使能信号对所述参考时钟进行计数输出第二计数值；
    其中，所述第一计数值和所述第二计数值共同用于表征所述工艺偏差。
  3. 根据权利要求2所述的电路，其中，
    所述检测电路还包括：
    异或电路异或电路，配置为将所述第一使能信号与所述第一传输信号进行异或处理形成第一异或信号；或将所述第一使能信号与所述第二传输信号进行异或处理形成第二异或信号；其中，所述第一异或信号和所述第 二异或信号均为异或结果；
    与门，配置为将所述第一使能信号与所述异或结果进行与处理，形成所述第二使能信号或所述第三使能信号。
  4. 根据权利要求1所述的电路，其中，
    所述检测单元包括模拟信号转换电路；
    所述模拟信号转换电路，配置为接收所述第一传输信号和所述第二传输信号，并根据所述第一传输信号和第二传输信号的传输时延，输出对应的模拟信号；
    所述第一传输信号作用于所述模拟信号转换电路时，所述模拟信号转换电路输出第一模拟信号；所述第二传输信号作用于所述模拟信号转换电路时，所述模拟信号转换电路输出第二模拟信号；
    所述第一模拟信号和所述第二模拟信号能够共同用于表征所述工艺偏差。
  5. 根据权利要求4所述的电路，其中，
    所述检测单元还包括模数转换器；
    所述模数转换器的模拟输入端与所述模拟信号转换电路的输出端相连，配置为接收并对所述第一模拟信号或所述第二模拟信号进行模数转换；
    所述第一传输信号作用于所述模拟信号转换电路时，所述模数转换单元输出对应于所述第一模拟信号的第一数字信号；所述第二传输信号作用于所述模拟信号转换电路时，所述模数转换单元输出对应于所述第二模拟信号的第二数字信号；
    所述第一数字信号和所述第二数字信号共同用于表征所述工艺偏差。
  6. 根据权利要求5所述的电路，其中，
    所述第一传输路径和所述第二传输路径均包括M级串联的缓冲器；所述第一传输信号包括M个第一缓冲信号；所述第二传输信号包括M个第二 缓冲信号；
    所述模拟信号转换电路包括：M个受控电流源及负载电容；
    所述第m个受控电流源，配置为接收基于第m个所述第一缓冲信号或第m个所述第二缓冲信号形成的控制信号，并根据所述控制信号继续或停止所述负载电容充电；所述m为不大于所述M的整数；其中，所述M不小于1的整数；
    所述模数转换器的模拟输入端，与所述负载电容相连，配置为将所述负载电容的电容电压转换成对应的数字信号。
  7. 根据权利要求1所述的电路，其中，
    所述检测单元包括时间数字转换器；
    所述时间数字信号转换器，配置为接收第一传输信号和所述第二传输信号，并输出转换信号；
    所述转换信号能够用于表征所述工艺偏差。
  8. 根据权利要求7所述的电路，其中，
    所述时间数字转换电路包括：
    N级串联的第三缓冲器，配置为接收第一输入信号并对所述第一输入信号进行N级缓冲处理；
    N个延迟触发器；
    第n个延迟触发器，连接在第n个所述第三缓冲器的输出端，接收所述第二输入信号及已进行n级缓冲处理的第一输入信号，基于所述第二输入信号对所述第一输入信号做延迟触发处理，并输出延迟触发结果；
    其中，所述n为不大于N的正整数；所述N为不小于1的整数；
    所述第一输入信号为所述第一传输信号，所述第二输入信号为所述第二传输信号；或，所述第一输入信号为所述第二传输信号，所述第二输入信号为所述第一传输信号。
  9. 根据权利要求1至5和7至8任一项所述的电路，其中，
    所述第一传输路径和所述第二传输路径均包括M级串联的缓冲器；
    其中，所述M不小于1的整数。
  10. 一种工艺偏差检测方法，所述方法包括：
    利用第一传输路径接收并传输第一使能信号，输出第一传输信号；
    利用第二传输路径接收并传输所述第一使能信号，输出第二传输信号；
    基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差；
    其中，所述第一传输路径的工艺偏差敏感度为第一敏感度；
    所述第二传输路径的工艺偏差敏感度为第二敏感度；
    所述第一敏感度不等于所述第二敏感度。
  11. 根据权利要求10所述的方法，其中，
    所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，包括：
    接收参考时钟；
    接收基于所述第一传输信号形成的第二使能信号或基于所述第二传输信号形成的第三使能信号；
    基于所述第二使能信号对所述参考时钟进行计数输出第一计数值，或基于所述第三使能信号对所述参考时钟进行计数输出第二计数值；
    其中，所述第一计数值和所述第二计数值共同用于表征所述工艺偏差。
  12. 根据权利要求11所述的方法，其中，
    所述方法还包括：
    将所述第一使能信号与所述第一传输信号进行异或处理形成第一异或信号；将所述第一使能信号与所述第二传输信号进行异或处理形成第二异或信号；其中，所述第一异或信号和所述第二异或信号均为异或结果；
    将所述第一使能信号与所述异或结果进行与处理，形成所述第二使能信号或所述第三使能信号。
  13. 根据权利要求10所述的方法，其中，
    所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，包括；
    接收所述第一传输信号和所述第二传输信号，并根据所述第一传输信号和第二传输信号的传输时延，输出对应的模拟信号；其中，对所述第一传输信号进行模拟信号转换时，输出第一模拟信号；对所述第二传输信号进行模拟信号转换时，输出第二模拟信号；所述第一模拟信号和所述第二模拟信号能够共同用于表征所述工艺偏差。
  14. 根据权利要求13所述的方法，其中，
    所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，还包括；
    接收并对所述第一模拟信号或所述第二模拟信号进行模数转换，形成数字信号；其中，所述数字信号包括对应于所述第一模拟信号的第一数字信号及对应于所述第二模拟信号的第二数字信号；
    所述第一数字信号和所述第二数字信号共同用于表征所述工艺偏差。
  15. 根据权利要求14所述的方法，其中，
    所述第一传输信号包括M个第一缓冲信号；其中，第m个所述第一缓冲信号是对第m-1个所述第一缓冲信号进行缓冲处理形成的；
    所述第二传输信号包括M个第二缓冲信号；其中，第m个所述第二缓冲信号是对第m-1个所述第二缓冲信号进行缓冲处理形成的；
    所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，还包括；
    根据基于第m个所述第一缓冲信号或第m个所述第二缓冲信号形成的 控制信号，继续或停止第m个受控电流源向负载电容充电；
    将所述负载电容的电容电压转换成对应的数字信号；
    所述m为不大于所述M的整数；其中，所述M不小于1的整数。
  16. 根据权利要求10所述的方法，其中，
    所述基于所述第一传输信号和所述第二传输信号的传输时延，检测工艺偏差，包括：
    对第一传输信号和所述第二传输信号进行时间数字转换处理，并输出转换信号；所述转换信号能够用于表征所述工艺偏差。
  17. 根据权利要求16所述的方法，其中，
    所述对第一传输信号和所述第二传输信号进行时间数字转换处理，并输出转换信号，包括：
    接收第一输入信号并对所述第一输入信号进行N级缓冲处理；
    基于所述第二输入信号对已进行n级缓冲处理的第一输入信号做延迟触发处理，并输出延迟触发结果；其中，所述n为不大于N的正整数；所述N为不小于1的整数；
    所述第一输入信号为所述第一传输信号，所述第二输入信号为所述第二传输信号；或，所述第一输入信号为所述第二传输信号，所述第二输入信号为所述第一传输信号。
  18. 根据权利要求10至14和16至17任一项所述的方法，其中，
    所述利用第一传输路径接收并传输第一使能信号，输出第一传输信号，包括：
    利用位于所述第一传输路径上的M级串联的缓冲器对所述第一使能信号进行缓冲处理，形成所述第一传输信号；
    所述利用第二传输路径接收并传输所述第一使能信号，输出第二传输信号，包括：
    利用位于所述第二传输路径上的M级串联的缓冲器对所述第一使能信号进行缓冲处理，形成所述第二传输信号；
    其中，所述M不小于1的整数。
  19. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求10至18所述工艺偏差检测方法的至少其中之一。
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