WO2017016178A1 - 基于fpga的接口信号重映射方法 - Google Patents

基于fpga的接口信号重映射方法 Download PDF

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WO2017016178A1
WO2017016178A1 PCT/CN2016/000002 CN2016000002W WO2017016178A1 WO 2017016178 A1 WO2017016178 A1 WO 2017016178A1 CN 2016000002 W CN2016000002 W CN 2016000002W WO 2017016178 A1 WO2017016178 A1 WO 2017016178A1
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signal
module
fpga chip
fpga
asynchronous
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PCT/CN2016/000002
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French (fr)
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张坚
姜群兴
王晓凯
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国核自仪系统工程有限公司
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Priority to EP16829550.9A priority Critical patent/EP3249543A4/en
Priority to US15/565,870 priority patent/US10318468B2/en
Publication of WO2017016178A1 publication Critical patent/WO2017016178A1/zh
Priority to ZA2017/05494A priority patent/ZA201705494B/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag

Definitions

  • the present invention relates to nuclear power system technology, and in particular to a technique for an FPGA based interface signal remapping method.
  • FPGA technology has the advantages of structural rules and high reliability.
  • the field of instrument control systems is increasingly using FPGA technology to implement various communication protocols, logic processing and control functions.
  • the signal external to the chip needs to be introduced into the chip for processing.
  • the main clock signal offset, the data collision caused by the single signal line input and output bidirectional data signal, and the asynchronous reset signal cause the register.
  • the Chinese Patent Publication No. CN101833431A discloses a bidirectional high speed FIFO memory based on FPGA, the bidirectional high speed FIFO memory including the first asynchronous bus interface module, the first communication mailbox, and the first single Asynchronous FIFO read/write module, second asynchronous bus interface module, second communication mailbox and second one-way asynchronous FIFO read/write module; capable of implementing programmable logic output line width, synchronous or asynchronous input and output clock, two-way mailbox communication Features.
  • bidirectional port I / O in FPGA is aimed at the characteristics of field programmable gate array (FPGA) chip, the design of bidirectional port I / O in FPGA, and the method of simulating the initialization of bidirectional port I / O .
  • FPGA field programmable gate array
  • the Chinese patent application No. 201010547869.X discloses an FPGA-based single interrupt real-time data transmission method, which is to pass data of multiple asynchronous data sources through FPGA.
  • the single interrupt data transmission device is buffered and then sent to the upper computer for a real-time data transmission method, belonging to the field of real-time signal processing technology.
  • the method first selects the appropriate interrupt period according to the data transfer condition inequality without losing data, and then creates data inside the FPGA. Buffer, and create a write status register of each data buffer, and then generate a periodic interrupt signal according to the half full and full full signal sent by the buffer, and the host computer triggers the interrupt service program by responding to the periodic signal to complete the real-time continuous Transmission purpose.
  • the method reduces the complexity of software and hardware programming debugging and improves the reliability of the system. Since the amount of data generated by each interrupt is relatively stable, the data is more convenient for centralized bulk transmission and post-processing. .
  • the Chinese Patent No. CN201805409U discloses a reset circuit of the FPGA system, which realizes a reliable reset of the system and improves the stability of the system after reset.
  • the circuit includes a reset chip and a reset branch connected to the manual reset pin of the reset chip, the reset branch generating a low level signal, thereby controlling the reset chip to generate a low level signal as a system reset signal .
  • FPGA-based protection system platform urgently needs to solve the above problems in a functional module, so that the logic module inside the FPGA can focus on performing functions such as communication, arithmetic operation, logic processing, etc., improving its reliability, readability and debugability.
  • the technical problem to be solved by the present invention is to provide an external signal of the FPGA chip can be reliably transmitted into the FPGA chip, so that the logic module inside the FPGA can focus on performing communication and arithmetic operations.
  • FPGA-based interface signal remapping method that enhances reliability, readability, and debugability.
  • an FPGA-based interface signal remapping method provided by the present invention is characterized in that:
  • the internal programmable logic of the FPGA chip is divided into two independent modules, one of which is an IO module and the other is a Core module.
  • the IO module is used to process the signal offset of the FPGA chip external signal input and output FPGA chip. And signal collision caused by line multiplexing, during data transmission Metastable, data transmission error between asynchronous clock domains; logical processing and calculation using Core module; and the main clock signal external to the FPGA chip is introduced into the FPGA chip through the global clock pin of the FPGA chip;
  • the IO module includes a three-state gate circuit and an asynchronous FIFO;
  • the Core module performs bidirectional data signal transmission with an external device through a three-state gate circuit in the IO module;
  • the asynchronous clock domain data signal outside the FPGA chip is buffered by the asynchronous FIFO in the IO module and input into the Core module.
  • the IO module includes a first stage register and a second level register
  • the global asynchronous reset signal external to the FPGA chip is connected to the set port of the first stage register in the IO module, and the constant "0" is used as the input of the first stage register, and the output of the first stage register is used as the second stage register. Input, the output of the second stage register is used as a sampling signal of the global reset signal to reset other registers inside the FPGA chip.
  • the FPGA-based interface signal remapping method utilizes the IO module to process the signal offset faced by the FPGA chip external signal input and output FPGA chip, and the signal conflict caused by the line multiplexing, and the metastable in the data transmission process.
  • State data transmission error between asynchronous clock domains; use Core module for logic processing and calculation; and introduce the main clock signal outside the FPGA chip into the FPGA chip through the global clock pin of the FPGA chip; thereby avoiding and alleviating the transmission process
  • the main clock signal offset, the data signal conflict on a single signal line, the asynchronous reset signal causes the register output metastable state, the data signal transmission speed error between the asynchronous clock domains, and the poor readability of the signal name inside the FPGA chip, etc.
  • the Core module can focus on performing functions such as communication, arithmetic operations, logic processing, etc., improving reliability, readability, and debugability.
  • FIG. 1 is a schematic diagram of an FPGA-based interface signal remapping method according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of implementing a bidirectional data signal transmission by using a three-state gate circuit in an FPGA-based interface signal remapping method according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of sampling an asynchronous reset signal by using a two-stage register in an FPGA-based interface signal remapping method according to an embodiment of the present invention.
  • an FPGA-based interface signal remapping method provided by an embodiment of the present invention is characterized in that:
  • the internal programmable logic of the FPGA chip is divided into two independent modules, one of which is an IO module and the other is a Core module.
  • the IO module is used to process the signal offset of the FPGA chip external signal input and output FPGA chip. Signal collision caused by line multiplexing, metastability during data transmission, data transmission error between asynchronous clock domains; logic processing and calculation using Core module; and main clock signal external to FPGA chip through FPGA chip
  • the global clock pin is introduced into the FPGA chip to alleviate the clock signal offset caused by too much output load of the main clock signal;
  • the IO module includes a three-state gate circuit, an asynchronous FIFO, a first-stage register, and a second-level register;
  • the Core module performs bidirectional data signal transmission with external devices through the tri-state gate circuit in the IO module to avoid signal collision caused by data input and output multiplexing; as shown in Figure 2, Dinout performs bidirectional data transmission outside the FPGA chip.
  • the signal line, Dout is the data output signal line of the Core module
  • Din is the data input signal line of the Core module
  • the asynchronous clock domain data signal outside the FPGA chip is buffered by the asynchronous FIFO in the IO module and then input into the Core module to avoid data loss caused by the mismatch between the two clock domain clock signals; the asynchronous FIFO in the IO module of the embodiment of the present invention
  • the bit width is 8 and the depth is 4.
  • the asynchronous FIFO means that the read/write clocks are not the same clock but independent of each other.
  • the asynchronous data input signal Vdout of the asynchronous FIFO is controlled by the write data clock Clock1.
  • the output data signal Vdin is controlled by the read data clock Clock2, Vdout is the signal external to the FPGA chip, and Vdin is the signal that Vdout is sent to the Core module.
  • the asynchronous FIFO is mainly used to buffer data and isolate the clock or phase difference in the FPGA design, and access the asynchronous FIFO.
  • the address line is not needed, only the data line and the read/write control signal line are needed, and the data address is determined by the internal read/write pointer. Adding 1 or subtracting 1 for control, so using asynchronous FIFO to realize data caching has the advantages of simple interface and convenient reading and writing;
  • the two-stage register is used to sample the asynchronous reset signal of the input to avoid the metastable problem of the register output signal caused by the asynchronous reset signal;
  • the asynchronous reset signal means that when the reset signal Reset is input into the FPGA chip, it is not controlled by the clock signal and may be input into the FPGA chip at any time. This may cause the recovery/removal time of the register to be unsatisfactory, which may result in a register.
  • the output data metastability is generated. When a flip-flop enters the metastable state, it cannot predict the output level, nor can it predict when the output will stabilize at a certain level. During this period, the flip-flop will output some Intermediate level, or may be in an oscillating state, resulting in system instability;
  • the global asynchronous reset signal Reset external to the FPGA chip is connected to the set port of the first-stage register R1 in the IO module, and the constant “0” is used as the input of the first-level register R1.
  • the output of the first stage register R1 is used as the input of the second stage register R2, and the output of the second stage register R2 is used as the sampling signal Rst1 of the global reset signal for resetting other registers inside the FPGA chip, due to the Reset signal and the clock.
  • the Reset signal may not satisfy the recovery/removal time of the Clock signal.
  • the output of the first-stage register R1 may have a metastable state, but this metastable state passes after one clock cycle. In most cases, the state that the input of the second-stage register R2 is still not stable will not last for too long, and the second-stage register R2 outputs the sampling signal Rst1 synchronized with the clock signal Clock signal for the FPGA.
  • the other registers R3 and R4 inside the chip are reset, so that the asynchronous reset signal Reset is sampled by the two-stage register, and the output is the same as the clock signal Clock.
  • the sampling signal Rst1 of the step can avoid the metastable problem of the register output which may be caused by the global asynchronous reset signal.

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Abstract

一种基于FPGA的接口信号重映射方法，涉及核电系统技术领域，所解决的是现有方法可靠性、可读性及可调试性差的技术问题。该方法将FPGA芯片的内部可编程逻辑分为两个独立模块，其中的一个模块为IO模块，另一个模块为Core模块，利用IO模块处理FPGA芯片外部信号输入输出FPGA芯片内部所面临的信号偏移，及线路复用所导致的信号冲突，数据传输过程中的亚稳态，异步时钟域之间的数据传输错误；利用Core模块进行逻辑处理及计算；并将FPGA芯片外部的主时钟信号通过FPGA芯片的全局时钟引脚引入FPGA芯片。本方法，适用于核电保护系统平台。

Description

基于FPGA的接口信号重映射方法 技术领域
本发明涉及核电系统技术，特别是涉及一种基于FPGA的接口信号重映射方法的技术。
背景技术
FPGA技术具有结构规则、可靠性高等优点，仪控系统领域越来越多地采用FPGA技术实现各种通信协议、逻辑处理及控制等功能。在FPGA芯片使用场合，需要将芯片外部的信号引入芯片内部进行处理，在这个过程中可能会产生主时钟信号偏移、单根信号线输入输出双向数据信号导致的数据冲突、异步复位信号导致寄存器输出亚稳态、异步时钟域之间数据信号传输速错误、FPGA芯片内部的信号名可读性差等问题。
关于双向数据信号的传输方面，公开号为CN101833431A的中国专利公开了一种基于FPGA实现的双向高速FIFO存储器，该该双向高速FIFO存储器包括第一异步总线接口模块、第一通信信箱、第一单向异步FIFO读写模块、第二异步总线接口模块、第二通信信箱和第二单向异步FIFO读写模块；能够实现可编程逻辑的输出线宽，同步或异步的输入输出时钟，双向信箱通信功能。其利用FPGA实现双向FIFO，具有稳定、速度快、易于实现及占用资源少的优点，同时易于与其他逻辑功能集成，从而可以有效提高系统集成度减小系统尺寸降低功耗。另外，文献《FPGA中双向端口I/O的研究》针对现场可编程门阵列(FPGA)芯片的特点，研究FPGA中双向端口I/O的设计，同时给出仿真初始化双向端口I/O的方法。采用这种双向端口的设计方法，选用Xilinx的Spartan2E芯片设计一个多通道图像信号处理系统。
关于异步时钟域之间数据信号的传输方面，申请号为201010547869.X的中国专利文献公开了一种基于FPGA的单中断实时数据传输方法，该方法是将多个异步数据源的数据经过基于FPGA的单中断数据传输设备进行缓存，再发送到上位机的一种实时数据传输方法，属于实时信号处理技术领域。该方法首先根据不丢失数据下数据传输条件不等式选择合适的中断周期，然后在FPGA内部创建数据 缓冲区，并且创建各数据缓冲区的写状态寄存器，接着根据缓冲区发出的半满和全满信号来产生一个周期性中断信号，上位机通过响应这个周期信号来触发中断服务程序从而完成实时连续传输目的。该方法相比多中断源触发方式，降低了软硬件编程调试的复杂度并且提高了系统的可靠性，由于每次中断产生的数据量大小相对稳定，故数据更便于集中进行批量传输和后处理。
关于FPGA芯片的全局复位信号处理方面，授权公告号为CN201805409U的中国专利公开了一种FPGA系统的复位电路，该电路实现了系统的可靠复位，提高了复位后系统的稳定性。该电路包括复位芯片和所述复位芯片的手控复位管脚相连接的复位支路，所述复位支路产生低电平信号，从而控制所述复位芯片产生作为系统复位信号的低电平信号。
但是，目前的核电仪控系统FPGA设计中，主时钟信号传输、双向数据传输信号传输、异步时钟域之间的数据传输、异步复位信号的传输以及不同信号名之间的映射都处于不同的功能模块内部，具有可读性及可调试性较差的缺陷，不利于FPGA的模块化设计及调试，也没有适用于核电保护系统平台领域的，能将保护系统平台中FPGA芯片所有外部信号可靠地传入FPGA芯片内部的技术。基于FPGA的保护系统平台的研发急需在一个功能模块解决上述问题，使得FPGA内部的逻辑模块可以专注于执行通信、算术运算、逻辑处理等功能，提高其可靠性、可读性及可调试性。
发明内容
针对上述现有技术中存在的缺陷，本发明所要解决的技术问题是提供一种能将FPGA芯片的外部信号可靠地传入FPGA芯片内部，使得FPGA内部的逻辑模块可以专注于执行通信、算术运算、逻辑处理等功能，从而提高其可靠性、可读性及可调试性的基于FPGA的接口信号重映射方法。
为了解决上述技术问题，本发明所提供的一种基于FPGA的接口信号重映射方法，其特征在于：
将FPGA芯片的内部可编程逻辑分为两个独立模块，其中的一个模块为IO模块，另一个模块为Core模块，利用IO模块处理FPGA芯片外部信号输入输出FPGA芯片内部所面临的信号偏移，及线路复用所导致的信号冲突，数据传输过程中的 亚稳态，异步时钟域之间的数据传输错误；利用Core模块进行逻辑处理及计算；并将FPGA芯片外部的主时钟信号通过FPGA芯片的全局时钟引脚引入FPGA芯片；
其中，IO模块中包含有三态门电路、异步FIFO；
Core模块通过IO模块中的三态门电路与外部器件进行双向数据信号传输；
FPGA芯片外部的异步时钟域数据信号通过IO模块中的异步FIFO缓冲后输入Core模块。
进一步的，所述IO模块中包含有第一级寄存器、第二级寄存器；
将FPGA芯片外部的全局异步复位信号接入IO模块中的第一级寄存器的置位端口，将常数“0”作为第一级寄存器的输入，将第一级寄存器的输出作为第二级寄存器的输入，将第二级寄存器的输出作为全局复位信号的采样信号用以对FPGA芯片内部的其它寄存器进行复位。
本发明提供的基于FPGA的接口信号重映射方法，利用IO模块处理FPGA芯片外部信号输入输出FPGA芯片内部所面临的信号偏移，及线路复用所导致的信号冲突，数据传输过程中的亚稳态，异步时钟域之间的数据传输错误；利用Core模块进行逻辑处理及计算；并将FPGA芯片外部的主时钟信号通过FPGA芯片的全局时钟引脚引入FPGA芯片；从而避免及缓解了传输过程中的主时钟信号偏移、单根信号线上数据信号冲突、异步复位信号导致寄存器输出亚稳态、异步时钟域之间数据信号传输速错误、FPGA芯片内部的信号名可读性差等问题，使得Core模块可以专注于执行通信、算术运算、逻辑处理等功能，提高了可靠性、可读性及可调试性。
附图说明
图1是本发明实施例的基于FPGA的接口信号重映射方法的原理图；
图2是本发明实施例的基于FPGA的接口信号重映射方法中利用三态门电路实现双向数据信号传输的原理图；
图3是本发明实施例的基于FPGA的接口信号重映射方法中利用两级寄存器对异步复位信号进行采样的原理图。
具体实施方式
以下结合附图说明对本发明的实施例作进一步详细描述，但本实施例并不用于限制本发明，凡是采用本发明的相似结构及其相似变化，均应列入本发明的保护范围，本发明中的顿号均表示和的关系。
如图1所示，本发明实施例所提供的一种基于FPGA的接口信号重映射方法，其特征在于：
将FPGA芯片的内部可编程逻辑分为两个独立模块，其中的一个模块为IO模块，另一个模块为Core模块，利用IO模块处理FPGA芯片外部信号输入输出FPGA芯片内部所面临的信号偏移，及线路复用所导致的信号冲突，数据传输过程中的亚稳态，异步时钟域之间的数据传输错误；利用Core模块进行逻辑处理及计算；并将FPGA芯片外部的主时钟信号通过FPGA芯片的全局时钟引脚引入FPGA芯片，以缓解主时钟信号输出负载太多导致的时钟信号偏移；
其中，IO模块中包含有三态门电路、异步FIFO、第一级寄存器、第二级寄存器；
Core模块通过IO模块中的三态门电路与外部器件进行双向数据信号传输，以避免数据线被输入输出复用所导致的信号冲突；如图2所示，Dinout为FPGA芯片外部进行双向数据传输的信号线，Dout为Core模块的数据输出信号线，Din为Core模块的数据输入信号线，Z为控制三态门电路输出状态的信号线，当Z＝1时，三态门电路设置为高阻态，此时数据只能从Dinout信号线输入至Din信号线，Dinout信号线作为输入端口；当Z＝0时，三态门电路导通，数据从Dout信号线输出至Dinout双向信号线，此时Dinout信号线作为输出端口，从而通过控制Z信号线的高低电平控制了Core模块与Dinout信号线之间的数据双向传输；
FPGA芯片外部的异步时钟域数据信号通过IO模块中的异步FIFO缓冲后输入Core模块，以避免两个时钟域时钟信号不匹配所导致的数据丢失；本发明实施例的IO模块中的异步FIFO的位宽为8，深度为4，异步FIFO是指读写时钟不是同一个时钟，而是相互独立的，如图1所示，异步FIFO的输入数据信号Vdout由写数据时钟Clock1控制，异步FIFO的输出数据信号Vdin由读数据时钟Clock2控制，Vdout为FPGA芯片外部的信号，Vdin为Vdout传入Core模块的信号，异步FIFO在FPGA设计中主要用来缓冲数据和隔离时钟或相位差异，访问异步FIFO时不需要地址线，只需要数据线和读写控制信号线，数据地址由内部读写指针自 动加1或减1进行控制，因此利用异步FIFO实现数据的缓存具有接口简单、读写方便的优点；
利用两级寄存器来对输入的异步复位信号进行采样，避免异步复位信号导致的寄存器输出信号的亚稳态问题；
异步复位信号是指在复位信号Reset输入FPGA芯片内部时，不受时钟信号的控制，可能在任意时间输入FPGA芯片内部，从而可能会导致寄存器的恢复/移除时间不满足要求，进而会导致寄存器输出数据亚稳态的产生，当一个触发器进入亚稳态时，就无法预测该输出电平，也无法预测何时输出才能稳定在某个电平上，在这期间，触发器会输出一些中间电平，或者可能处于振荡状态，从而导致系统不稳定；
如图3所示，本发明实施例将FPGA芯片外部的全局异步复位信号Reset接入IO模块中的第一级寄存器R1的置位端口，将常数“0”作为第一级寄存器R1的输入，将第一级寄存器R1的输出作为第二级寄存器R2的输入，将第二级寄存器R2的输出作为全局复位信号的采样信号Rst1用以对FPGA芯片内部的其它寄存器进行复位，由于Reset信号与时钟信号Clock之间不存在固定的时序关系，因此Reset信号可能不满足Clock信号的恢复/移除时间，第一级寄存器R1的输出端可能存在亚稳态，但这个亚稳态经过一个时钟周期后在绝大多数情况下都会消除，即第二级寄存器R2的输入端仍未稳定的状态不会持续太久，第二级寄存器R2输出与时钟信号Clock信号同步的采样信号Rst1，用以对FPGA芯片内部的其它寄存器R3、R4进行复位，这样异步复位信号Reset经过两级寄存器采样之后，输出与时钟信号Clock同步的采样信号Rst1，可避免全局异步复位信号可能导致的寄存器输出的亚稳态问题。

Claims (2)

  1. 一种基于FPGA的接口信号重映射方法，其特征在于：
    将FPGA芯片的内部可编程逻辑分为两个独立模块，其中的一个模块为IO模块，另一个模块为Core模块，利用IO模块处理FPGA芯片外部信号输入输出FPGA芯片内部所面临的信号偏移，及线路复用所导致的信号冲突，数据传输过程中的亚稳态，异步时钟域之间的数据传输错误；利用Core模块进行逻辑处理及计算；并将FPGA芯片外部的主时钟信号通过FPGA芯片的全局时钟引脚引入FPGA芯片；其中，IO模块中包含有三态门电路、异步FIFO；
    Core模块通过IO模块中的三态门电路与外部器件进行双向数据信号传输；
    FPGA芯片外部的异步时钟域数据信号通过IO模块中的异步FIFO缓冲后输入Core模块。
  2. 根据权利要求1所述的基于FPGA的接口信号重映射方法，其特征在于：所述IO模块中包含有第一级寄存器、第二级寄存器；
    将FPGA芯片外部的全局异步复位信号接入IO模块中的第一级寄存器的置位端口，将常数“0”作为第一级寄存器的输入，将第一级寄存器的输出作为第二级寄存器的输入，将第二级寄存器的输出作为全局复位信号的采样信号用以对FPGA芯片内部的其它寄存器进行复位。
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