WO2017012306A1 - 阵列基板的制备方法、阵列基板及显示装置 - Google Patents

阵列基板的制备方法、阵列基板及显示装置 Download PDF

Info

Publication number
WO2017012306A1
WO2017012306A1 PCT/CN2016/070855 CN2016070855W WO2017012306A1 WO 2017012306 A1 WO2017012306 A1 WO 2017012306A1 CN 2016070855 W CN2016070855 W CN 2016070855W WO 2017012306 A1 WO2017012306 A1 WO 2017012306A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
photoresist
array substrate
layer
drain
Prior art date
Application number
PCT/CN2016/070855
Other languages
English (en)
French (fr)
Chinese (zh)
Inventor
刘正
郭总杰
陈曦
张小祥
张治超
刘明悬
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP16727927.2A priority Critical patent/EP3327763B1/de
Priority to KR1020167031087A priority patent/KR101900170B1/ko
Priority to JP2016566218A priority patent/JP6818554B2/ja
Priority to US15/106,052 priority patent/US9761617B2/en
Publication of WO2017012306A1 publication Critical patent/WO2017012306A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a display device.
  • Thin Film Transistor Liquid Crystal Display is an important flat panel display device.
  • the thin film transistor liquid crystal display can be classified into a vertical electric field type and a horizontal electric field type according to the direction of the electric field driving the liquid crystal.
  • the vertical electric field type TFT-LCD needs to form a pixel electrode on the array substrate, and form a common electrode on the color filter substrate, such as a common TN mode; and the horizontal electric field type TFT-LCD needs to simultaneously form a pixel electrode and a common electrode on the array substrate.
  • ADS Advanced Super Dimension Switch
  • ADS technology refers to the planar electric field wide viewing angle core technology.
  • the main idea is to form a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that the inside of the liquid crystal cell All of the aligned liquid crystal molecules between the slit electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • ADS technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • ADS technology has improved high-transmission I-ADS technology, high aperture ratio H-ADS and high-resolution S-ADS technology.
  • the array substrate of the I-ADS mode will be described in conjunction with the following preparation method.
  • Step 1 Form a first transparent conductive layer on the substrate, and form a pattern including a pixel electrode (plate electrode) by a patterning process.
  • Step 2 forming a gate metal film on the substrate on which the above steps are completed, and forming a pattern including a gate electrode of the thin film transistor by a patterning process.
  • Step 3 Form a gate insulating layer on the substrate on which the above steps are completed.
  • Step 4 forming an active layer film on the substrate on which the above steps are completed, and forming a pattern including the active layer by a patterning process.
  • Step 5 Form a source/drain metal film on the substrate on which the above steps are completed, and form a pattern including a source and a drain by a patterning process.
  • Step 6 Form a passivation layer on the substrate on which the above steps are completed, and form a pattern including a main via hole penetrating the passivation layer and the gate insulating layer by a patterning process.
  • Step 7 Form a second transparent conductive layer on the substrate on which the above steps are completed, and form a connection electrode connecting the drain electrode and the pixel electrode through the main via hole by a patterning process, and form a common electrode (slit electrode) by a patterning process Graphics.
  • the inventors have found that at least the following problems exist in the prior art: since dry etching is usually used in the process of forming the main via hole in step 6, the source/drain metal film is not etched away, and the active layer is The material is polysilicon, amorphous silicon, etc., which will be etched away, so there will be a problem of undercut under the drain. It is not difficult to understand that the second transparent conductive layer formed thereafter is easily broken at a floating position due to the phenomenon of dangling below the drain.
  • the present invention provides a method for fabricating an array substrate, an array substrate, and a display device, which effectively eliminate the problem of floating under the drain.
  • Embodiments of the present invention provide a method of fabricating an array substrate, the method comprising the steps of:
  • step S2 after step S1, forming a pattern including a gate of the thin film transistor on the substrate;
  • step S3 after step S2, forming a gate insulating layer on the substrate;
  • step S3 After step S3, forming an active layer including a thin film transistor by a patterning process on the substrate, and forming a source and a drain on the active layer shape;
  • step S5 after step S4, forming a passivation layer on the substrate;
  • step S6 after step S5, forming a main via extending through the gate insulating layer and the passivation layer and a main via extension under a partial region of the drain by a patterning process on the substrate a pattern in which the main via is continuous with the main via extension;
  • step S7 after step S6, removing a portion of the drain protruding from the main via extension to form a pattern including a final via;
  • step S8 After step S7, forming a pattern including a connection electrode and a common electrode on the substrate, wherein the connection electrode electrically connects the drain and the pixel electrode through the final via.
  • the array substrate includes: a thin film transistor region, a common electrode region, and a via region between the thin film transistor region and the common electrode region; and the step S6 includes the following steps:
  • the remaining photoresist is removed.
  • the first photoresist layer may have a thickness of 2.2 to 2.5 ⁇ m.
  • the step of removing portions of the passivation layer and the gate insulating layer under the first photoresist completely removed region by an etching process and removing the passivation layer by an etching process The etching process used in the step of the active layer and the portion of the gate insulating layer under the first photoresist portion remaining region is dry etching.
  • step S7 includes the following steps:
  • a portion of the drain protruding from the via extension is removed by a patterning process on a substrate formed with a pattern including the main via and the main via extension to form the final including A pattern of vias.
  • step S8 includes the following steps:
  • a transparent conductive film is formed, and a pattern including the connection electrode and the common electrode is formed by one patterning process.
  • the common electrode region includes a first region and a second region that are alternately arranged;
  • step S8 includes the following steps:
  • the remaining photoresist is removed using a step strip process and a pattern of the common electrode and the connection electrode is formed.
  • the second photoresist layer may have a thickness of 2.5 to 3.0 ⁇ m.
  • step S4 includes the following steps:
  • a pattern including the active layer of the thin film transistor and the source and the drain on the active layer is formed by a patterning process using a gray scale mask or a halftone mask.
  • step S4 comprises the following steps:
  • a source/drain metal film is deposited, and a pattern including a source and a drain of the thin film transistor is formed by another patterning process.
  • Embodiments of the present invention also provide an array substrate prepared by the above preparation method.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • a pattern including a main via extending through the gate insulating layer and the passivation layer and a main via extension located under a partial region of the drain is formed by a patterning process, and thereafter
  • the drain metal protruding above the main via extension is effectively removed, thereby solving the problem of floating under the drain in the prior art, and the performance of the formed array substrate is better without increasing the process steps.
  • the rate is higher.
  • FIG. 1 is a schematic view showing a step S1 of a method of fabricating an array substrate according to a first embodiment of the present invention
  • step S2 is a schematic diagram of step S2 of the method for fabricating the array substrate according to the first embodiment of the present invention
  • step S3 is a schematic diagram of step S3 of the method for fabricating the array substrate according to the first embodiment of the present invention
  • step S4 is a schematic diagram of step S4 of the method for fabricating the array substrate according to the first embodiment of the present invention
  • FIG. 5 is a schematic diagram of steps S5 and S6 of the method for fabricating the array substrate according to the first embodiment of the present invention
  • FIG. 6 is a schematic diagram of step S7 of the method for fabricating the array substrate according to the first embodiment of the present invention.
  • FIG. 7 is a schematic diagram of step S8 of the method for fabricating the array substrate according to the first embodiment of the present invention.
  • step S6 is a schematic view showing a specific preparation procedure of step S6 of the method for fabricating the array substrate according to the first embodiment of the present invention
  • FIG. 9 is a schematic view showing a specific preparation procedure of step S8 of the method for fabricating the array substrate according to the first embodiment of the present invention.
  • the present embodiment provides a method for fabricating an array substrate, which is an array substrate of an I-ADS mode, and includes at least a thin film transistor and a pixel electrode 1 , wherein the thin film transistor can be Top gate type thin film transistor or bottom gate type thin film transistor.
  • the top gate type thin film transistor The biggest difference from the bottom gate type thin film transistor is that the active layer 4 and the gate 2 are located at different positions. Specifically, a thin film transistor in which the active layer 4 is located under the gate 2 is referred to as a top gate type thin film transistor, and a thin film transistor in which the active layer 4 is located above the gate 2 is referred to as a bottom gate type thin film transistor.
  • the metal gate 2 of the bottom gate type thin film transistor can serve as a protective layer of the semiconductor active layer 4 to prevent the light emitted from the backlight from being irradiated to the amorphous silicon layer.
  • the generated photo-generated carriers break the electrical characteristics of the active layer 4. Therefore, a method of fabricating an array substrate having a bottom gate type thin film transistor will be described below as an example.
  • the preparation method does not constitute a limitation on the present embodiment, and the preparation method can also be applied to the preparation of an array substrate having a top gate type thin film transistor.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in this embodiment.
  • the method for preparing the array substrate in this embodiment specifically includes the following steps S1 to S8.
  • Step S1 a pattern including the pixel electrode 1 is formed on the substrate 10 by a patterning process.
  • the substrate 10 may be made of a transparent material such as glass, resin, sapphire, quartz or the like in this step and pre-cleaned.
  • a sputtering method a thermal evaporation method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, a Low Pressure Chemical Vapor Deposition (LPCVD) method, and an atmospheric pressure chemistry may be employed.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • a first transparent conductive film by an Atmospheric Pressure Chemical Vapor Deposition (APCVD) method or an Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD) method, and then performing the first transparent conductive film Photoresist coating, exposure, development, etching, photoresist stripping to form a pattern including the pixel electrode 1, as shown in FIG.
  • APCVD Atmospheric Pressure Chemical Vapor Deposition
  • ECR-CVD Electron Cyclotron Resonance Chemical Vapor Deposition
  • the first transparent conductive film has high reflectivity and meets certain work function requirements, and usually adopts a two-layer film or a three-layer film structure: such as ITO (indium tin oxide) / Ag (silver) / ITO or Ag / ITO structure;
  • ITO indium tin oxide
  • Ag silver
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • InGaSnO indium gallium tin oxide
  • the inorganic metal oxide includes indium tin oxide or zinc oxide
  • the organic conductive polymer includes PEDOT: PSS, PANI. (Polyaniline)
  • the metal material includes one or more of gold, copper, silver, and platinum.
  • Step S2 on the substrate 10 on which the step S1 is completed, a pattern including the gate electrode 2 of the thin film transistor is formed by a patterning process, as shown in FIG.
  • a gate metal film may be formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition, and then The gate metal film is coated with a photoresist, exposed, developed, etched, and stripped to form a pattern of the gate electrode 2 including the thin film transistor.
  • the material for forming the gate metal film (gate 2) may be molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • Step S3 on the substrate 10 on which the step S2 is completed, the gate insulating layer 3 is formed.
  • the gate insulating layer 3 may be formed by a thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, or the like, as shown in FIG.
  • the material forming the gate insulating layer 3 may be silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON) or aluminum oxide ( AlOx), etc., or from silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), and aluminum oxide (AlOx)
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON germanium oxide
  • AlOx aluminum oxide
  • Step S4 sequentially depositing an active layer film on the substrate 10 on which step S3 is completed And a source/drain metal film, and a pattern including the active layer 4 of the thin film transistor and the source 51 and the drain 52 is formed by a patterning process.
  • the active layer film may be first deposited by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition; then sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure may be employed.
  • a source/drain metal film is formed by chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition; followed by using a Half Tone Mask (HTM) or a Gray Tone Mask (Gray Tone Mask). GTM), through the first patterning process (film formation, exposure, development, wet etching or dry etching), simultaneously forming a pattern including the source 51, the drain 52 and the active layer 4, as shown in FIG. Show.
  • the material forming the active layer film may be an amorphous silicon film (a-Si) or a polysilicon film (p-Si); and the material forming the source/drain metal film (source 51 and drain 52) may be molybdenum (Mo) , a single-layer or multi-layer composite laminate formed of one or a plurality of materials of molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu) It is preferably a single layer or a multilayer composite film composed of Mo and/or Al or a single layer or multilayer composite film composed of an alloy containing Mo and Al.
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • the active layer 4, the source 51 and the drain 52 formed in the step S4 can also be formed by two patterning processes, that is, the active layer 4 is formed by one patterning process, and the source 51 and the drain 52 are formed. Formed by another patterning process.
  • Step S5 on the substrate 10 on which step S4 is completed, a passivation layer 6 is formed.
  • the passivation layer 6 may be formed by a thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, or sputtering.
  • the material forming the passivation layer 6 may be an oxide of silicon (SiOx), a nitride of silicon (SiNx), an oxide of hafnium (HfOx), an oxide of silicon (SiON) or an oxide of aluminum (AlOx). Or etc., or two or three of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), and aluminum oxide (AlOx) The composition of the multilayer film composition.
  • Step S6 forming a package by the patterning process on the substrate 10 completing the step S5
  • a pattern of the main via 71 and the main via extension 72 extending through the gate insulating layer 3 and the passivation layer 6 is formed, wherein the main via 71 and the main via extension 72 are penetrated as shown in FIG.
  • the main via extension portion 72 refers to inevitably etching the active layer 4 and the gate insulating layer 3 under the drain 52 in the process of forming the main via 71 by a patterning process.
  • the via hole that is, the portion defined by the lower surface of the drain electrode 52, the right side surface of the active layer 4 and the gate insulating layer 3, the upper surface of the substrate 10, and the broken line in FIG. 5 in FIG.
  • step S6 specifically includes the following steps S61 to S66.
  • Step S61 on the passivation layer 6, a first photoresist layer is formed.
  • Step S62 exposing and developing the first photoresist layer by using a halftone mask or a gray scale mask, so that the first photoresist layer forms a first photoresist completely removed region (not shown), first The photoresist completely retains the region 91 and the first photoresist portion retention region 92.
  • a first photoresist completely removed region corresponding to an intermediate region of the via region a first photoresist portion reserved region 92 corresponding to a portion of the thin film transistor region near the via region and the portion a peripheral region of the via region adjacent to the thin film transistor region, a first photoresist completely remaining region 91 and a first region including a common electrode region other than the above region (a region corresponding to a position of the common electrode 81 formed later) Corresponds to a portion of the thin film transistor region.
  • the photoresist thickness of the first photoresist completely remaining region 91 is not changed, the photoresist of the first photoresist completely removed region is completely removed, and the photoresist of the first photoresist portion retaining region 92 is completely removed.
  • the thickness is reduced.
  • the thickness of the first photoresist layer is 2.2 to 2.5 ⁇ m, and after the development process, the thickness of the photoresist of the first photoresist portion remaining region 92 is 1 to 1.5 ⁇ m.
  • Step S63 through the etching process, specifically, the portion of the passivation layer 6 and the gate insulating layer 3 under the first photoresist completely removed region may be removed by dry etching.
  • Step S64 removing the photoresist of the first photoresist portion remaining region 92 by an ashing process to expose a portion of the passivation layer 6 under the first photoresist portion remaining region 92 and the via region. Near the peripheral region of the thin film transistor region.
  • Step S65 through the etching process, specifically, the portion of the passivation layer 6, the active layer 4, and the gate insulating layer 3 under the first photoresist portion remaining region 92 may be sequentially removed by dry etching to form A pattern including the main via 71 and the main via extension 72 is included. At this time, the drain 52 will protrude from the main via extension 72.
  • Step S66 removing the remaining photoresist.
  • the formation of the main via extension portion 72 is not intentionally formed, but because the material of the active layer 4 is polysilicon or amorphous silicon, etc., in the passivation layer 6 and the gate insulating layer. 3
  • the etching is performed, the portion of the active layer 4 that is in contact with the etched passivation layer 6 and the gate insulating layer 3 is inevitably etched, resulting in the occurrence of the main via extension 72 under the drain 52.
  • the main via extension portion 72 formed by the exposure mode using the gray scale mask or the halftone mask in the above steps will be small, and the floating phenomenon under the drain 52 is improved to some extent, but it cannot be improved. Completely eliminate this defect.
  • main via 71 can also be formed by a single etching process using an ordinary mask. At this time, the main via extension 72 will be large, and the floating under the drain 52 will be apparent.
  • Step S7 on the substrate 10 completing step S6, the portion of the drain electrode 52 protruding from the main via extension portion 72 is removed by a patterning process to form a final via hole including the main via hole 71 and the main via hole.
  • the pattern of the via extensions 72) is shown in FIG.
  • the portion of the drain electrode 52 that protrudes from the main via extension portion 72 means a portion of the drain electrode 52 that is suspended due to the underlying active layer 4 being partially etched.
  • a wet etching process is employed in step S7.
  • Step S8 on the substrate 10 completing the step S7, a pattern including the connection electrode 82 and the common electrode 81 is formed by one patterning process, wherein the connection electrode 82 electrically connects the drain electrode 52 and the pixel electrode 1 through the final via hole. , as shown in Figure 7.
  • the common electrode region includes a first region (a region corresponding to the position of the common electrode 81) and a second region (a region corresponding to the interval between the adjacent common electrodes 81) which are alternately arranged.
  • the step S8 specifically includes the following steps S81 to S86.
  • Step S81 forming a diagram including the main via 71 and the main via extension 72 On the shaped substrate 10, a second photoresist layer is formed.
  • Step S82 exposing and developing the second photoresist layer by using a gray scale mask or a halftone mask, so that the second photoresist layer forms a second photoresist completely removed region (not shown), and second The photoresist completely retains the region 94, the second photoresist portion retention region 95.
  • a second photoresist complete removal region corresponding to a source region of the thin film transistor region, the via region, and a second region of the common electrode region, the second photoresist portion retention region 95 corresponding to the The drain region of the thin film transistor region, the second photoresist completely remaining region 94 corresponds to a region other than the above region.
  • the thickness of the photoresist in the completely remaining region of the second photoresist is not changed, the photoresist in the completely removed region of the second photoresist is completely removed, and the thickness of the photoresist in the second photoresist portion remains in the region 95. Reduced.
  • the thickness of the second photoresist layer is 2.5 to 3.0 ⁇ m; after the development process, the thickness of the photoresist of the second photoresist portion remaining region 95 is 0.5 to 1.0 ⁇ m.
  • Step S83 removing a portion of the drain electrode 52 protruding above the main via extension portion 72 by an etching process, specifically by a wet etching process, to form a final via hole (the final via hole includes the main via hole 71 and The pattern of the main via extension 72).
  • Step S84 removing the photoresist of the second photoresist partial retention region 95 by an ashing process.
  • Step S85 depositing a transparent conductive film (second transparent conductive film) 80.
  • the material of the transparent conductive film 80 is any one of an ITO/Ag/ITO structure and an Ag/ITO structure; or, the ITO in the above structure is replaced with any one of IZO, IGZO, and InGaSnO.
  • Step S85 removing the remaining photoresist by a step stripping process, and forming a pattern including the common electrode 81 and the connection electrode 82.
  • the method for preparing the array substrate provided in this embodiment effectively solves the problem that the floating layer exists below the drain, and does not increase the process steps, and the formed array substrate has better performance and higher yield.
  • a second embodiment of the present invention provides an array substrate, the array
  • the substrate was prepared by the method of the first embodiment, and its performance was better.
  • a third embodiment of the present invention provides a display device including the array substrate of the second embodiment.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
PCT/CN2016/070855 2015-07-17 2016-01-14 阵列基板的制备方法、阵列基板及显示装置 WO2017012306A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP16727927.2A EP3327763B1 (de) 2015-07-17 2016-01-14 Verfahren zur herstellung eines array-substrats, array-substrat und anzeigevorrichtung
KR1020167031087A KR101900170B1 (ko) 2015-07-17 2016-01-14 어레이 기판의 제조 방법, 어레이 기판 및 디스플레이 디바이스
JP2016566218A JP6818554B2 (ja) 2015-07-17 2016-01-14 アレイ基板の製造方法、アレイ基板および表示装置
US15/106,052 US9761617B2 (en) 2015-07-17 2016-01-14 Method for manufacturing array substrate, array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510424976.6A CN105070684B (zh) 2015-07-17 2015-07-17 阵列基板的制备方法、阵列基板及显示装置
CN201510424976.6 2015-07-17

Publications (1)

Publication Number Publication Date
WO2017012306A1 true WO2017012306A1 (zh) 2017-01-26

Family

ID=54500020

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/070855 WO2017012306A1 (zh) 2015-07-17 2016-01-14 阵列基板的制备方法、阵列基板及显示装置

Country Status (6)

Country Link
US (1) US9761617B2 (de)
EP (1) EP3327763B1 (de)
JP (1) JP6818554B2 (de)
KR (1) KR101900170B1 (de)
CN (1) CN105070684B (de)
WO (1) WO2017012306A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105070684B (zh) * 2015-07-17 2018-01-05 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板及显示装置
CN106094366B (zh) * 2016-08-23 2019-02-01 深圳市华星光电技术有限公司 Ips型阵列基板的制作方法及ips型阵列基板
CN107996002A (zh) * 2016-12-30 2018-05-04 深圳市柔宇科技有限公司 阵列基板及阵列基板制造方法
CN206479745U (zh) * 2017-01-03 2017-09-08 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN107065347A (zh) * 2017-03-28 2017-08-18 上海天马微电子有限公司 阵列基板、液晶显示面板及阵列基板的制作方法
CN107017267A (zh) * 2017-03-29 2017-08-04 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
TWI662526B (zh) * 2018-05-02 2019-06-11 友達光電股份有限公司 半導體結構及畫素結構
CN109752891B (zh) * 2019-01-14 2021-03-19 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN109991787B (zh) * 2019-03-15 2022-06-07 惠科股份有限公司 一种阵列基板及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1707340A (zh) * 2004-06-05 2005-12-14 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
EP2023194A1 (de) * 2007-07-26 2009-02-11 Epson Imaging Devices Corporation Flüssigkristallanzeigevorrichtung und Verfahren zur Herstellung der Flüssigkristallanzeigevorrichtung
CN105070684A (zh) * 2015-07-17 2015-11-18 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499376B1 (ko) * 2003-10-10 2005-07-04 엘지.필립스 엘시디 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
KR101090257B1 (ko) * 2005-01-20 2011-12-06 삼성전자주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101263193B1 (ko) * 2006-05-02 2013-05-10 삼성디스플레이 주식회사 표시 기판의 제조 방법 및 표시 기판
KR101246024B1 (ko) 2006-07-21 2013-03-26 삼성디스플레이 주식회사 어레이 기판의 제조방법, 어레이 기판 및 이를 갖는표시장치
KR101300183B1 (ko) * 2006-11-20 2013-08-26 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
JP2011164196A (ja) * 2010-02-05 2011-08-25 Seiko Epson Corp 電気光学装置用基板、電気光学装置及び電子機器
KR101298612B1 (ko) * 2010-10-12 2013-08-26 엘지디스플레이 주식회사 횡전계 방식 액정표시장치용 어레이기판 및 그 제조방법
CN102109721B (zh) * 2010-11-22 2013-04-24 深圳市华星光电技术有限公司 液晶显示器的像素阵列制造方法
JP2012118199A (ja) * 2010-11-30 2012-06-21 Panasonic Liquid Crystal Display Co Ltd 液晶パネル、液晶表示装置、及びその製造方法
KR101888422B1 (ko) * 2011-06-01 2018-08-16 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
CN103887245B (zh) * 2014-03-28 2017-03-08 深圳市华星光电技术有限公司 一种阵列基板的制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1707340A (zh) * 2004-06-05 2005-12-14 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
EP2023194A1 (de) * 2007-07-26 2009-02-11 Epson Imaging Devices Corporation Flüssigkristallanzeigevorrichtung und Verfahren zur Herstellung der Flüssigkristallanzeigevorrichtung
CN105070684A (zh) * 2015-07-17 2015-11-18 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板及显示装置

Also Published As

Publication number Publication date
CN105070684A (zh) 2015-11-18
KR101900170B1 (ko) 2018-09-18
EP3327763B1 (de) 2022-03-02
US9761617B2 (en) 2017-09-12
CN105070684B (zh) 2018-01-05
KR20170026327A (ko) 2017-03-08
JP6818554B2 (ja) 2021-01-20
EP3327763A4 (de) 2019-04-24
EP3327763A1 (de) 2018-05-30
US20170200749A1 (en) 2017-07-13
JP2018523140A (ja) 2018-08-16

Similar Documents

Publication Publication Date Title
WO2017012306A1 (zh) 阵列基板的制备方法、阵列基板及显示装置
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
US9515095B2 (en) Array substrate and method for manufacturing the same, and display device
US9613986B2 (en) Array substrate and its manufacturing method, display device
US9859304B2 (en) Manufacturing method of array substrate, array substrate and display device
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
JP6043815B2 (ja) 薄膜トランジスタのアレイ基板及びその製造方法、並びに電子デバイス
US10504943B2 (en) Method for manufacturing an array substrate motherboard
US10651204B2 (en) Array substrate, its manufacturing method and display device
WO2015043268A1 (zh) 阵列基板及其制备方法、和显示装置
US9893206B2 (en) Thin film transistor, array substrate, their manufacturing methods, and display device
US8895334B2 (en) Thin film transistor array substrate and method for manufacturing the same and electronic device
WO2015043282A1 (zh) 阵列基板及其制造方法和显示装置
WO2014206035A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
US20150214253A1 (en) Array substrate, manufacturing method thereof and display device
WO2015000255A1 (zh) 阵列基板、显示装置及阵列基板的制造方法
US9502437B2 (en) Method of manufacturing array substrate, array substrate and display device
WO2013166831A1 (zh) 薄膜晶体管阵列基板及制作方法和显示装置
WO2016169355A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2017140058A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
WO2015035832A1 (zh) 阵列基板及其制备方法和显示装置
CN102931138B (zh) 阵列基板及其制造方法、显示装置
WO2013189144A1 (zh) 阵列基板及其制造方法、以及显示装置
WO2015055039A1 (zh) 阵列基板及其制造方法、显示装置
WO2014117444A1 (zh) 阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15106052

Country of ref document: US

ENP Entry into the national phase

Ref document number: 2016566218

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20167031087

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16727927

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2016727927

Country of ref document: EP