WO2017012254A1 - 阵列基板行驱动电路单元、驱动电路和显示面板 - Google Patents

阵列基板行驱动电路单元、驱动电路和显示面板 Download PDF

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Publication number
WO2017012254A1
WO2017012254A1 PCT/CN2015/097114 CN2015097114W WO2017012254A1 WO 2017012254 A1 WO2017012254 A1 WO 2017012254A1 CN 2015097114 W CN2015097114 W CN 2015097114W WO 2017012254 A1 WO2017012254 A1 WO 2017012254A1
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WIPO (PCT)
Prior art keywords
gate
output
clock signal
array substrate
input
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Ceased
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PCT/CN2015/097114
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English (en)
French (fr)
Inventor
张锴
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/106,491 priority Critical patent/US9881542B2/en
Publication of WO2017012254A1 publication Critical patent/WO2017012254A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate row driving circuit unit. Further, the present invention relates to a driving circuit including the array substrate row driving circuit unit. Still further, the present invention relates to a display panel including the drive circuit.
  • the manufacture of the existing display usually adopts a design of a Gate Driver on Array (GOA) in which a gate switching circuit of a Thin Film Transistor (TFT) is integrated on an array substrate of a display panel.
  • GAA Gate Driver on Array
  • TFT Thin Film Transistor
  • CK and CKB are clock signals that are inverted with respect to each other
  • CN and CNB are complementary DC levels for controlling the direction of positive and negative sweep
  • STV_N-1 and STV_N+1 are inputs for positive and negative sweep, respectively.
  • the signal, STV_N is the generated intermediate scan signal
  • OUT_1 and OUT_2 are gate drive pulses supplied to different rows of pixels.
  • An object of the present invention is to provide an array substrate row driving circuit unit capable of outputting gate driving pulses for two rows of pixels, thereby reducing the number of required GOA cells, and thus reducing the frame area to be occupied. Further, another object of the present invention is to provide a driving circuit including the array substrate row driving circuit unit. Further, it is still another object of the present invention to provide a display panel including the driving circuit.
  • an array substrate row driving circuit unit comprising: a first input terminal for receiving an excitation pulse of a current stage; a second input terminal for receiving a first additional clock signal; Receiving a third input of the second additional clock signal, the second additional clock signal being an inverted version of the first additional clock signal; a fourth input for receiving the first clock signal; for receiving the second a fifth input terminal of the clock signal, the second clock signal being an inverted version of the first clock signal; a first output terminal for outputting a secondary excitation pulse; and a first output signal for outputting a first gate line driving pulse a first stage output terminal; a second local stage output terminal for outputting a second gate line driving pulse; an array substrate row driving register module having a shift register unit; and an array substrate row driving output module having a digital logic circuit Wherein the first stage excitation pulse, the first additional clock signal and the first clock signal are synchronized, and the width of the current stage excitation pulse is equal to the first additional clock One period of the number
  • the digital logic circuit can include: an AND gate, one of its two inputs being provided with the current stage excitation pulse, and the other input being provided with the second additional clock signal; a NAND gate having one input connected to the output of the AND gate, and the other input being provided with the first clock signal; the first NOT gate, the input An input terminal is connected to the output of the first NAND gate; a second NAND gate, one input terminal is connected to the output end of the AND gate, and the other input terminal is provided with the second clock signal; a second NOT gate having an input coupled to the output of the second NAND gate; wherein an output signal of the first NOT gate is routed to the first local output as the first gate Driving a pulse, and the output signal of the second NOT gate is routed to the second local stage output as the second gate line driving pulse.
  • the digital logic circuit may further include: a first buffer circuit for buffering the first gate line drive pulse before routing it to the first stage output for output And a second buffer circuit for buffering the second gate line drive pulse before routing it to the second stage output for output.
  • the first buffer circuit may include an even number of NOT gates connected in series with each other
  • the second buffer circuit may include an even number of NOT gates connected in series with each other.
  • the shift register unit may include: a third NOT gate whose input terminal is provided with the first additional clock signal; a first tri-state NOT gate whose input terminal is provided with the current-level excitation a pulse having a first control terminal coupled to the input of the third NOT gate and a second control terminal coupled to the output of the third NOT gate; a second tri-state NOT gate having an output coupled to the output An output of the first three-state gate, a first control end of which is coupled to an output of the third NOT gate, and a second control end of which is coupled to an input of the third NOT gate; and a fourth non- a gate having an input coupled to the output of the second tri-state NOT gate, an output coupled to the input of the second tri-state NOT gate, and an output signal thereof routed to the first output as The secondary excitation pulse.
  • the array substrate row driving circuit unit may further include a scanning direction control module, wherein the scanning direction control module may include: a sixth input end for receiving a positive sweep excitation pulse; a seventh input end of the sweep excitation pulse; a first scan direction control end to which the first DC level is applied; a second scan direction control end to which the second DC level is applied, the second DC level and the first DC level Complementary; a second output coupled to the first input; and an analog switch that, under control of the first DC level and the second DC level, the positive sweep excitation pulse and the One of the anti-sweep excitation pulses is selectively routed to the second output as the current stage excitation pulse.
  • the scanning direction control module may include: a sixth input end for receiving a positive sweep excitation pulse; a seventh input end of the sweep excitation pulse; a first scan direction control end to which the first DC level is applied; a second scan direction control end to which the second DC level is applied, the second DC level and the first DC level Complementary; a second output coupled to
  • the analog switch may include a first transmission gate and a second transmission gate, the positive sweep excitation pulse being provided to an input end of the first transmission gate, the first a DC level is applied to the first control terminal of the first transmission gate, the second DC level is applied to a second control terminal of the first transmission gate, and an output signal of the first transmission gate is routed To the second output terminal as the current stage excitation pulse, the reverse sweep excitation pulse is supplied to an input end of the second transmission gate, and the second DC level is applied to the second transmission gate a first control terminal, the first DC level is applied to a second control end of the second transmission gate, and an output signal of the second transmission gate is routed to the second output terminal as the current level excitation pulse.
  • the array substrate row driver circuit unit may be fabricated based on a CMOS or NMOS process.
  • an array substrate row driving circuit comprising at least two cascaded array substrate row driving circuit units as described in the first aspect of the invention, wherein the array substrate
  • the row driving circuit unit does not include the scanning direction control module, the first output end of each array substrate row driving circuit unit is connected to the next-level array substrate row except for the last-stage array substrate row driving circuit unit.
  • each of the array substrate rows except the first-level array substrate row driving circuit unit includes the scanning direction control module, each of the array substrate rows except the first-level array substrate row driving circuit unit
  • the sixth input end of the driving circuit unit is connected to the first output end of the row driving circuit unit of the upper array substrate, and the seventh row driving circuit unit of each array substrate except the last one array substrate driving circuit unit
  • the input terminal is connected to the first output end of the row driving circuit unit of the next-stage array substrate.
  • a display panel comprising the array substrate row driving circuit according to the second aspect of the invention.
  • the present invention is based on the idea of providing a GOA circuit that occupies a smaller area than the prior art.
  • Two sets of clock signals having different frequencies and corresponding logic circuits are introduced, wherein a low frequency clock is used to drive the GOA shift register unit, and a high frequency clock is used to drive the GOA output circuit so that a single GOA unit can output for two
  • the gate drive pulses of the row pixels reduce the number of GOA circuit cells required.
  • Figure 1 illustrates a conventional GOA circuit schematic
  • FIG. 2 schematically illustrates a block diagram of a GOA circuit unit in accordance with one embodiment of the present invention
  • FIG. 3 shows a timing diagram for a GOA circuit unit in accordance with an embodiment of the present invention
  • FIG. 4 schematically illustrates a GOA circuit constructed by cascading GOA circuit elements as shown in Figure 2;
  • Figure 5 illustrates a schematic diagram of an implementation of a GOA circuit in accordance with an embodiment of the invention
  • Figure 6 schematically illustrates a block diagram of a GOA circuit unit in accordance with another embodiment of the present invention.
  • FIG. 7 schematically illustrates a GOA circuit constructed by cascading the GOA circuit unit 200 as shown in FIG. 5;
  • Figure 8 illustrates a schematic diagram of an implementation of a GOA circuit in accordance with another embodiment of the invention.
  • FIG. 2 schematically illustrates a block diagram of a GOA circuit unit 100 in accordance with one embodiment of the present invention.
  • the GOA circuit unit 100 operates under the driving of the current stage excitation pulse inxtpls, the first additional clock signal CKK, the second additional clock signal CKKB, the first clock signal CK, and the second clock signal CKB, which is the same as the conventional one shown in FIG.
  • the GOA circuit unit is similar except that the GOA circuit unit 100 does not have a reverse scan function, and thus the scan direction control circuit and the corresponding DC control levels CN, CNB are not provided.
  • the GOA circuit unit 100 includes a first input for receiving the excitation pulse inxtpls of the current stage, a second input for receiving the first additional clock signal CKK, and a third for receiving the second additional clock signal CKKB.
  • the second additional clock signal CKKB is an inverted version of the first additional clock signal CKK
  • the second clock signal CKB is an inverted version of the first clock signal CK.
  • FIG. 3 shows a timing diagram for the GOA circuit unit 100 in accordance with an embodiment of the present invention.
  • two sets are introduced that are different The frequency clock signals CKK/CKKB and CK/CKB, wherein the frequency of CCK/CKKB is half of the frequency of CK/CKB; in other words, the period of CKK/CKKB is twice the period of CK/CKB.
  • the current excitation pulse inxtpls, the additional clock signal CKK/CKKB and the clock signal CK/CKB are synchronized, the width of the excitation pulse inxtpls of the current stage is equal to one cycle of the first additional clock signal CKK, and the first gate line driving pulse The widths of the OUT_1 and second gate line driving pulses OUT_2 are both equal to half of the period of the first clock signal CK.
  • the hardware description language HDL
  • the electronic design automation (EDA) tool can then be used to convert to a modular combination of actual circuits represented by a gate-level circuit netlist. Then, the netlist can be converted into a specific circuit structure by using an application specific integrated circuit ASIC or a field programmable gate array FPGA automatic place and route tool.
  • the GOA circuit unit 100 may include an array substrate row drive registration module 110 and an array substrate row drive output module 120.
  • the array substrate row drive registration module 110 may have a shift register unit, wherein the current stage excitation pulse inxtpls and the first additional clock signal CKK are supplied to the shift register unit such that the secondary excitation pulse STV_N is output at the first output terminal .
  • the secondary excitation pulse STV_N is a delayed version of the half cycle of the shifted first additional clock signal CKK of the current stage excitation pulse inxtpls.
  • the array substrate row driving output module 120 may have a digital logic circuit, wherein the current stage excitation pulse inxtpls, the second additional clock signal CKKB, the first clock signal CK, and the second clock signal CKB are supplied to the digital logic circuit such that only The first gate line driving pulse OUT_1 is outputted at the first local stage output terminal and the second gate line driving pulse OUT_2 is outputted at the second local stage output terminal during the first half pulse width of the current stage excitation pulse inxtpls.
  • the first gate line driving pulse OUT_1 corresponds in time to the first half cycle of the first clock signal CK
  • the second gate line driving pulse OUT_2 corresponds in time to the second half cycle of the second clock signal CKB.
  • gate drive pulses OUT_1 and OUT_2 for adjacent two pixel rows can be provided by one GOA circuit unit 100.
  • Fig. 4 schematically illustrates a GOA circuit constructed by cascading the GOA circuit unit 100 as shown in Fig. 2, in which only two GOA circuit units 100 are shown, and the two GOA units 100 are output in addition to the present stage.
  • the first output of the first stage GOA circuit unit 100 (which outputs the secondary excitation pulse STV_N) is coupled to the second stage GOA
  • the first input of the way unit 100 (which receives the STV_N from the first stage as the present stage excitation pulse inxtpls), and so on.
  • the first output of each GOA circuit unit 100 is connected to the first input of the next stage array substrate row driver circuit unit.
  • the corresponding gate drive pulses OUT_1, OUT_2, OUT_3, OUT_4, ..., OUT_n can be sequentially supplied to the respective pixel rows.
  • FIG. 5 illustrates a schematic diagram of an implementation of a GOA circuit in which only two cascaded GOA circuit units are shown, in accordance with an embodiment of the invention.
  • one GOA circuit unit includes an array substrate row drive register module 110 and an array substrate row drive output module 120.
  • the array substrate row drive output module 120 includes digital logic circuitry for generating two gate drive pulses in accordance with the timing relationships previously described with reference to FIG.
  • the digital logic circuit includes an AND gate A1, a first NAND gate AN1, a first NOT gate N1, a second NAND gate AN2, and a second NOT gate N2.
  • One of the two inputs of the AND gate A1 is supplied with the own stage excitation pulse inxtpls, and the other is supplied with the second additional clock signal CKKB.
  • One input of the first NAND gate AN1 is connected to the output of the AND gate A1, and the other input is supplied with the first clock signal CK.
  • the input of the first NOT gate N1 is connected to the output of the first NAND gate AN1.
  • One input of the second NAND gate AN2 is connected to the output of the AND gate A1, and the other input is supplied with the second clock signal CKB.
  • the input of the second NOT gate N2 is connected to the output of the second NAND gate AN2.
  • the output signal of the first NOT gate N1 may be routed to the first local stage output as the first gate line driving pulse OUT_1, and the output signal of the second NOT gate N2 may be routed to the second local stage output as the second gate The line drives the pulse OUT_2.
  • the digital logic circuit may further include a first buffer circuit for buffering the first gate line driving pulse before routing it to the first local stage output for output, and for A second buffer circuit that buffers the second gate line drive pulse before routing it to the second stage output for output.
  • the first buffer circuit includes an even number of NOT gates connected in series with each other
  • the second buffer circuit includes an even number of NOT gates connected in series with each other.
  • the array substrate row drive registration module 110 includes a shift register unit for generating a secondary excitation pulse in accordance with the timing relationship previously described with reference to FIG.
  • the shift register unit includes a third NOT gate N3, a first tri-state NOT gate TN1, a second tri-state NOT gate TN2, and a fourth NOT gate N4.
  • the input of the third NOT gate N3 is provided with the first additional clock letter No. CKK.
  • the input end of the first tri-state NOT gate TN1 is supplied with the excitation pulse inxtpls of the current stage, the first control terminal thereof is connected to the input terminal of the third NOT gate N3, and the second control terminal thereof is connected to the output terminal of the third NOT gate N3. .
  • the output of the second tri-state NOT gate TN2 is connected to the output of the first tri-state NOT gate TN1, the first control terminal thereof is connected to the output terminal of the third NOT gate N3, and the second control terminal thereof is connected to the third non-gate The input of the door N3.
  • the input end of the fourth NOT gate N4 is connected to the output end of the second tri-state NOT gate TN2, the output end thereof is connected to the input end of the second tri-state NOT gate TN2, and the output signal thereof is routed to the array substrate row drive registration module.
  • the first output of 110 acts as a secondary excitation pulse STV_N.
  • the first three-state NOT gate TN1 of the shift register unit is turned off, so that inxtpls cannot enter the bistable circuit composed of the second three-state NOT gate TN2 and the fourth NOT gate N4, but is directly input to the AND gate together with the CKKB.
  • the output of the AND gate A1 is a high level, and the high level is respectively input to one input terminal of each of the two NAND gates AN1, AN2, and the other input terminals of the two NAND gates AN1, AN2 CK and CKB are provided separately.
  • CK is high and CKB is low, making OUT_1 high and OUT_2 low.
  • CK is low and CKB is high, making OUT_1 low and OUT_1 high.
  • inxtpls remains high, CCK is high, and CKKB is low.
  • the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
  • the second half of the inxtpls pulse is routed through the first three-state NOT gate TN1 and the fourth NOT gate N4 to the first output, and the output is input to the high level signal of the next-stage GOA unit (ie, the STV_N pulse
  • the first half of the cycle will enable the next stage GOA unit to generate two gate drive pulses OUT_3/OUT_4).
  • CKKB since CKKB is low, the output of the AND gate A1 is low, so that OUT_1/OUT_2 is kept low regardless of whether CK/CKB is high.
  • inxtpls goes low, CCK is low, and CKKB is high.
  • the first three-state NOT gate TN1 of the shift register unit is turned off, and the bistable circuit operates to latch the high level of the previous time therein as the second half of the STV_N pulse.
  • OUT_1/OUT_2 is low regardless of the CK/CKB signal.
  • inxtpls is still low, CCK is high, and CKKB is low.
  • the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
  • the low level signal of inxtpls pulls STV_N low to low level via the first three-state NOT gate TN1 and the fourth NOT gate N4. At this time, the OUT_1/OUT_2 output remains low regardless of the CK/CKB signal.
  • STV_N and OUT_1/OUT_2 remain at a low level.
  • Each level of GOA operates in accordance with the above process to complete the shift of the scan excitation pulse and the output of the drive pulse of the stage.
  • FIG. 6 schematically illustrates a block diagram of a GOA circuit unit 200 in accordance with another embodiment of the present invention.
  • the GOA circuit unit 200 may further include a scan direction control module 130 in addition to the array substrate row drive register module 110 and the array substrate row drive output module 120.
  • the scan direction control module 130 includes a sixth input for receiving the positive sweep excitation pulse STV_N-1, a seventh input for receiving the reverse sweep excitation pulse STV_N+1, and a first applied first DC level CN
  • the second DC level CNB is complementary to the first DC level CN.
  • the analog switch selectively routes one of the positive sweep excitation pulse STV_N-1 and the reverse sweep excitation pulse STV_N+1 to the second output terminal as the current stage excitation under the control of the first DC level CN and the second DC level CNB.
  • Pulse inxtpls For example, when CN is high and CNB is low, the analog switch routes the positive sweep excitation pulse STV_N-1 to the second output as the current excitation pulse inxtpls to perform forward scanning; otherwise, when CN is low When the CNB is high, the analog switch routes the anti-sweep excitation pulse STV_N+1 to the second output terminal as the current excitation pulse inxtpls to perform reverse scanning.
  • Fig. 7 schematically illustrates a GOA circuit constructed by cascading the GOA circuit unit 200 as shown in Fig. 6, in which only two GOA circuit units 200 are shown, and the two GOA units 200 are output in addition to the present stage.
  • the first output of the first stage GOA circuit unit 200 which outputs the secondary excitation pulse STV_N in the case of forward scanning
  • the sixth input of the second stage GOA circuit unit 200 which is In the case of forward scanning, STV_N from the first stage is received as the current stage excitation pulse inxtpls
  • the first output of the second stage GOA circuit unit 200 which outputs the secondary excitation pulse STV_N in the case of reverse scanning
  • Connected to a seventh input of the first stage GOA circuit unit 200 its In the case of reverse scanning, STV_N from the second stage is received as the current excitation pulse inxtpls
  • each array substrate row driver circuit unit in addition to the first-stage array substrate row driver circuit unit, the sixth input terminal of each array substrate row driver circuit unit is connected to the first output terminal of the upper-order array substrate row driver circuit unit, and except for the last stage In addition to the array substrate row driving circuit unit, the seventh input terminal of each array substrate row driving circuit unit is connected to the first output terminal of the next-stage array substrate row driving circuit unit.
  • FIG. 8 illustrates a schematic diagram of an implementation of a GOA circuit in which only two cascaded GOA circuit units are shown, in accordance with another embodiment of the invention.
  • one GOA circuit unit includes an array substrate row drive registration module 110, an array substrate row drive output module 120, and an optional scan direction control module 130.
  • the array substrate row drive registration module 110 and the array substrate row drive output module 120 illustrated in FIG. 8 are the same as those previously described, and will not be described in detail herein.
  • the optional scan direction control module 130 includes means for selecting one of the positive sweep excitation pulse STV_N-1 and the reverse sweep excitation pulse STV_N+1 under the control of the first DC level CN and the second DC level CNB.
  • the analog switch is routed to the second output.
  • the analog switch includes a first transmission gate TG1 and a second transmission gate TG2.
  • the positive sweep excitation pulse STV_N-1 is supplied to the input terminal of the first transfer gate TG1, the first DC level CN is applied to the first control terminal of the first transfer gate TG1, and the second DC level CNB is applied to the first transfer gate
  • the second control terminal of TG1 and the output signal of the first transmission gate TG1 is routed to the second output of the scanning direction control module 130 as the current excitation pulse inxtpls.
  • the reverse sweep excitation pulse STV_N+1 is supplied to the input terminal of the second transfer gate TG2, the second DC level CNB is applied to the first control terminal of the second transfer gate TG2, and the first DC level CN is applied to the second transfer gate At the second control end of TG2, the output signal of the second transmission gate TG2 is routed to the second output of the scanning direction control module 130 as the current excitation pulse inxtpls.
  • the GOA circuit of FIG. 8 will be described in detail below in conjunction with the signal timing shown in FIG. operating. Assuming that the first DC level CN is at a high level, the second DC level CNB is at a low level, that is, the GOA circuit operates in a forward scan mode.
  • CK is high and CKB is low, making OUT_1 high and OUT_2 low.
  • CK is low and CKB is high, making OUT_1 low and OUT_1 high.
  • STV_N-1 remains at a high level, CCK is at a high level, and CKKB is at a low level.
  • the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
  • the second half of the STV_N-1 pulse is routed through the first three-state NOT gate TN1 and the fourth NOT gate N4 to the first output, and the output is input to the high-level signal of the next-stage GOA unit (ie, STV_N The first half of the pulse, which will enable the next stage of the GOA unit to generate two gate drive pulses OUT_3/OUT_4).
  • STV_N the output of the AND gate A1 is low, so that OUT_1/OUT_2 is kept low regardless of whether CK/CKB is high.
  • STV_N-1 is still low, CCK is high, and CKKB is low.
  • the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
  • the low level signal of STV_N-1 pulls STV_N low to the low level via the first three-state NOT gate TN1 and the fourth NOT gate N4. At this time, the OUT_1/OUT_2 output remains low regardless of the CK/CKB signal.
  • STV_N and OUT_1/OUT_2 remain at a low level.
  • Each level of GOA operates in accordance with the above process to complete the shift of the scan excitation pulse and the output of the drive pulse of the stage.
  • circuit configurations shown in Figures 5 and 8 are merely exemplary.
  • different gate structures can be obtained based on Boolean algebraic formulas.
  • the functions of the digital logic circuit of the array substrate row drive output module 120 illustrated in FIGS. 5 and 8 can be expressed as:
  • each Boolean algebra expression can represent a specific gate structure. Therefore, instead of the gate circuit structure as illustrated in FIGS. 5 and 8, it is also possible to generate the first gate line drive pulse OUT_1 using, for example, a digital logic circuit composed of a NAND gate, a NOT gate, and a NOR gate. which is, Such variations are known to those skilled in the art and will not be described in detail herein.
  • the previously described GOA circuit units 100, 200 may be fabricated based on a CMOS process. In an alternate embodiment, the previously described GOA circuit units 100, 200 may be fabricated based on an NMOS process. In the latter case, the number of transistors can be further reduced, resulting in a further reduced GOA footprint.
  • a display panel comprising the GOA circuit described above, the GOA circuit comprising a plurality of cascaded GOA circuit units 100 or 200.
  • the display panel can be applied to any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.

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Abstract

一种阵列基板行驱动电路单元（100、200），包括：具有移位寄存器单元的阵列基板行驱动寄存模块（110）以及具有数字逻辑电路的阵列基板行驱动输出模块（120）。本级激励脉冲、第二附加时钟信号、第一时钟信号和第二时钟信号被提供给所述数字逻辑电路，使得仅在本级激励脉冲的前半个脉宽期间在第一本级输出端输出与第一时钟信号的前半个周期对应的第一栅线驱动脉冲，并且在第二本级输出端输出与第二时钟信号的后半个周期对应的第二栅线驱动脉冲。还公开了一种通过级联所述阵列基板行驱动电路单元（100、200）而构成的阵列基板行驱动电路和包括该驱动电路的显示面板。该单个GOA单元能够输出用于两行像素的栅极驱动脉冲，减少了所需要的GOA电路单元的数目。

Description

阵列基板行驱动电路单元、驱动电路和显示面板 技术领域
本发明涉及显示技术领域，具体来说涉及一种阵列基板行驱动电路单元。进一步地，本发明涉及一种包括该阵列基板行驱动电路单元的驱动电路。再进一步地，本发明涉及一种包括该驱动电路的显示面板。
背景技术
现有显示器的制造通常采用阵列基板行驱动(Gate Driver on Array，GOA)的设计，其中将薄膜晶体管(Thin Film Transistor，TFT)的栅极开关电路集成在显示面板的阵列基板上。这样，可以省掉栅极驱动电路的绑定(bonding)区域以及外围布线空间，从而实现显示面板的窄边框的美观设计。
图1图示了一种常规的GOA电路原理图，其中仅示出了两个级联的GOA电路单元，并且这两个GOA单元中除了本级输出端(OUT_x，x＝1，2，3，...)之外对应的端子用相同的参考文字表示。在图1中，CK与CKB为相对于彼此反相的时钟信号，CN与CNB为用于控制正反扫方向的互补的直流电平，STV_N-1和STV_N+1分别为正、反扫的输入信号，STV_N为生成的中间扫描信号，并且OUT_1和OUT_2为提供给不同像素行的栅极驱动脉冲。当CN为高电平，CNB为低电平时，进行正向扫描，其中在施加到第一级GOA单元的STV_N-1的激励下顺序地在OUT_1，OUT_2，...OUT_n(n为像素行的数目)上输出栅极驱动脉冲；反之，当CN为低电平，CNB为高电平时，进行反向扫描，其中在施加到最后一级GOA单元的STV_N+1的激励下顺序地在OUT_n，OUT_n-1，...OUT_1上输出栅极驱动脉冲。在该常规的GOA电路中，每一行像素需要一个相应的GOA电路单元来生成一个栅极驱动脉冲。因此，所需要的GOA电路单元数目庞大，使得GOA电路占用较大的边框空间，这不利于显示屏边框的进一步变窄。
因此，需要一种改进的阵列基板行驱动电路配置。
发明内容
本发明的目的是提供一种能够输出用于两行像素的栅极驱动脉冲的阵列基板行驱动电路单元，从而减少所需要的GOA单元的数目，并且因此减少要占用的边框面积。进一步地，本发明的另一目的是提供一种包括该阵列基板行驱动电路单元的驱动电路。此外，本发明的再一目的是提供一种包括该驱动电路的显示面板。
根据本发明的第一方面，提供了一种阵列基板行驱动电路单元，包括：用于接收本级激励脉冲的第一输入端；用于接收第一附加时钟信号的第二输入端；用于接收第二附加时钟信号的第三输入端，所述第二附加时钟信号是所述第一附加时钟信号的反相版本；用于接收第一时钟信号的第四输入端；用于接收第二时钟信号的第五输入端，所述第二时钟信号是所述第一时钟信号的反相版本；用于输出次级激励脉冲的第一输出端；用于输出第一栅线驱动脉冲的第一本级输出端；用于输出第二栅线驱动脉冲的第二本级输出端；阵列基板行驱动寄存模块，其具有移位寄存器单元；以及阵列基板行驱动输出模块，其具有数字逻辑电路；其中，所述本级激励脉冲、所述第一附加时钟信号和所述第一时钟信号是同步的，所述本级激励脉冲的宽度等于所述第一附加时钟信号的一个周期，所述第一附加时钟信号的周期是所述第一时钟信号的周期的两倍，并且，所述第一栅线驱动脉冲和所述第二栅线驱动脉冲的宽度均等于所述第一时钟信号的周期的一半；其中，所述本级激励脉冲和所述第一附加时钟信号被提供给所述移位寄存器单元，使得在所述第一输出端输出所述次级激励脉冲，所述次级激励脉冲是所述本级激励脉冲的被移位所述第一附加时钟信号的半个周期的延迟版本；并且其中，所述本级激励脉冲、所述第二附加时钟信号、所述第一时钟信号和所述第二时钟信号被提供给所述数字逻辑电路，使得仅在所述本级激励脉冲的前半个脉宽期间在所述第一本级输出端输出与所述第一时钟信号的前半个周期时序上对应的所述第一栅线驱动脉冲，并且在所述第二本级输出端输出与所述第二时钟信号的后半个周期时序上对应的所述第二栅线驱动脉冲。
在一个实现方式中，所述数字逻辑电路可以包括：与门，其两个输入端之一被提供所述本级激励脉冲，并且另一个输入端被提供所述第二附加时钟信号；第一与非门，其一个输入端连接到所述与门的输出端，并且另一个输入端被提供所述第一时钟信号；第一非门，其输 入端连接到所述第一与非门的输出端；第二与非门，其一个输入端连接到所述与门的输出端，并且另一个输入端被提供所述第二时钟信号；以及第二非门，其输入端连接到所述第二与非门的输出端；其中，所述第一非门的输出信号被路由到所述第一本级输出端作为所述第一栅线驱动脉冲，并且所述第二非门的输出信号被路由到所述第二本级输出端作为所述第二栅线驱动脉冲。
在一个实现方式中，所述数字逻辑电路可以还包括：第一缓冲电路，用于在将所述第一栅线驱动脉冲路由到所述第一本级输出端以供输出之前对其进行缓冲；以及第二缓冲电路，用于在将所述第二栅线驱动脉冲路由到所述第二本级输出端以供输出之前对其进行缓冲。
在一个实现方式中，所述第一缓冲电路可以包括相互串联的偶数个非门，并且所述第二缓冲电路可以包括相互串联的偶数个非门。
在一个实现方式中，所述移位寄存器单元可以包括：第三非门，其输入端被提供所述第一附加时钟信号；第一三态非门，其输入端被提供所述本级激励脉冲，其第一控制端连接到所述第三非门的输入端，并且其第二控制端连接到所述第三非门的输出端；第二三态非门，其输出端连接到所述第一三态非门的输出端，其第一控制端连接到所述第三非门的输出端，并且其第二控制端连接到所述第三非门的输入端；以及第四非门，其输入端连接到所述第二三态非门的输出端，其输出端连接到所述第二三态非门的输入端，并且其输出信号被路由到所述第一输出端作为所述次级激励脉冲。
在一个实现方式中，所述阵列基板行驱动电路单元可以还包括扫描方向控制模块，其中，所述扫描方向控制模块可以包括：用于接收正扫激励脉冲的第六输入端；用于接收反扫激励脉冲的第七输入端；被施加第一直流电平的第一扫描方向控制端；被施加第二直流电平的第二扫描方向控制端，所述第二直流电平与所述第一直流电平是互补的；被连接到所述第一输入端的第二输出端；以及模拟开关，其在所述第一直流电平和所述第二直流电平的控制下，将所述正扫激励脉冲和所述反扫激励脉冲中的一个选择性地路由到所述第二输出端作为所述本级激励脉冲。
在一个实现方式中，所述模拟开关可以包括第一传输门和第二传输门，所述正扫激励脉冲被提供给所述第一传输门的输入端，所述第 一直流电平被施加到所述第一传输门的第一控制端，所述第二直流电平被施加到所述第一传输门的第二控制端，所述第一传输门的输出信号被路由到所述第二输出端作为所述本级激励脉冲，所述反扫激励脉冲被提供给所述第二传输门的输入端，所述第二直流电平被施加到所述第二传输门的第一控制端，所述第一直流电平被施加到所述第二传输门的第二控制端，所述第二传输门的输出信号被路由到所述第二输出端作为所述本级激励脉冲。
在一个实现方式中，所述阵列基板行驱动电路单元可以是基于CMOS或NMOS工艺制造的。
根据本发明的第二方面，提供了一种阵列基板行驱动电路，包括至少两个级联的如本发明的第一方面中所述的阵列基板行驱动电路单元，其中，在所述阵列基板行驱动电路单元不包括所述扫描方向控制模块的情况下，除最后一级阵列基板行驱动电路单元之外，每一个阵列基板行驱动电路单元的第一输出端连接到下一级阵列基板行驱动电路单元的第一输入端；并且其中，在所述阵列基板行驱动电路单元包括所述扫描方向控制模块的情况下，除第一级阵列基板行驱动电路单元之外，每一个阵列基板行驱动电路单元的第六输入端连接到上一级阵列基板行驱动电路单元的第一输出端，并且除最后一级阵列基板行驱动电路单元之外，每一个阵列基板行驱动电路单元的第七输入端连接到下一级阵列基板行驱动电路单元的第一输出端。
根据本发明的第三方面，提供了一种显示面板，包括如本发明的第二方面所述的阵列基板行驱动电路。
本发明基于提供与现有技术相比占用较小面积的GOA电路的构思。引入了具有不同频率的两套时钟信号和对应的逻辑电路，其中，低频率时钟用于驱动GOA移位寄存器单元，并且高频率时钟用于驱动GOA输出电路，使得单个GOA单元能够输出用于两行像素的栅极驱动脉冲，减少了所需要的GOA电路单元的数目。
附图说明
图1图示了一种常规的GOA电路原理图；
图2示意性地图示了根据本发明的一个实施例的GOA电路单元的框图；
图3示出了用于根据本发明的实施例的GOA电路单元的时序图；
图4示意性地图示了通过级联如图2所示的GOA电路单元而构成的GOA电路；
图5图示了根据发明的实施例的一种GOA电路的实现方式的原理图；
图6示意性地图示了根据本发明的另一个实施例的GOA电路单元的框图；
图7示意性地图示了通过级联如图5所示的GOA电路单元200而构成的GOA电路；以及
图8图示了根据发明的另一个实施例的一种GOA电路的实现方式的原理图。
具体实施方式
以下结合附图对本发明的各实施例进行详细描述。
图2示意性地图示了根据本发明的一个实施例的GOA电路单元100的框图。该GOA电路单元100在本级激励脉冲inxtpls、第一附加时钟信号CKK、第二附加时钟信号CKKB、第一时钟信号CK、第二时钟信号CKB的驱动下工作，这与图1所示的常规GOA电路单元类似，除了GOA电路单元100不具有反向扫描功能，并且因此未提供扫描方向控制电路和对应的直流控制电平CN、CNB。相应地，该GOA电路单元100包括用于接收本级激励脉冲inxtpls的第一输入端、用于接收第一附加时钟信号CKK的第二输入端、用于接收第二附加时钟信号CKKB的第三输入端、用于接收第一时钟信号CK的第四输入端、用于接收第二时钟信号CKB的第五输入端、用于输出次级激励脉冲STV_N的第一输出端、用于输出第一栅线驱动脉冲OUT_1的第一本级输出端、用于输出第二栅线驱动脉冲OUT_2的第二本级输出端、阵列基板行驱动寄存模块110以及阵列基板行驱动输出模块120。第二附加时钟信号CKKB是第一附加时钟信号CKK的反相版本，并且第二时钟信号CKB是第一时钟信号CK的反相版本。
下面结合图3所示的信号时序来详细介绍图2中的GOA电路单元100的操作，该图3示出了用于根据本发明的实施例的GOA电路单元100的时序图。如前所述，根据本发明的实施例，引入了两套具有不同 频率的时钟信号CKK/CKKB与CK/CKB，其中，CKK/CKKB的频率是CK/CKB的频率的一半；换言之，CKK/CKKB的周期是CK/CKB的周期的两倍。另外，本级激励脉冲inxtpls、附加时钟信号CKK/CKKB和时钟信号CK/CKB是同步的，本级激励脉冲inxtpls的宽度等于第一附加时钟信号CKK的一个周期，并且，第一栅线驱动脉冲OUT_1和第二栅线驱动脉冲OUT_2的宽度均等于第一时钟信号CK的周期的一半。基于这样的输入-输出时序关系，可以利用硬件描述语言(HDL)来描述GOA电路单元100的行为、结构和数据流。然后，可以利用电子设计自动化(EDA)工具转换为以门级电路网表表示的实际电路的模块组合。接着，可以用专用集成电路ASIC或现场可编程门阵列FPGA自动布局布线工具，把网表转换为具体的电路结构。
具体地，GOA电路单元100可以包括阵列基板行驱动寄存模块110和阵列基板行驱动输出模块120。阵列基板行驱动寄存模块110可以具有移位寄存器单元，其中，本级激励脉冲inxtpls和第一附加时钟信号CKK被提供给所述移位寄存器单元，使得在第一输出端输出次级激励脉冲STV_N。所述次级激励脉冲STV_N是本级激励脉冲inxtpls的被移位第一附加时钟信号CKK的半个周期的延迟版本。阵列基板行驱动输出模块120可以具有数字逻辑电路，其中，本级激励脉冲inxtpls、第二附加时钟信号CKKB、第一时钟信号CK和第二时钟信号CKB被提供给所述数字逻辑电路，使得仅在本级激励脉冲inxtpls的前半个脉宽期间在第一本级输出端输出第一栅线驱动脉冲OUT_1并且在第二本级输出端输出第二栅线驱动脉冲OUT_2。所述第一栅线驱动脉冲OUT_1在时序上与第一时钟信号CK的前半个周期对应，并且所述第二栅线驱动脉冲OUT_2在时序上与第二时钟信号CKB的后半个周期对应。
这样，利用一个GOA电路单元100可以提供用于相邻两个像素行的栅极驱动脉冲OUT_1和OUT_2。
图4示意性地图示了通过级联如图2所示的GOA电路单元100而构成的GOA电路，其中仅示出了两个GOA电路单元100，并且这两个GOA单元100中除了本级输出端(OUT_x，x＝1，2，3，...n)之外对应的端子用相同的参考文字表示。如所示的，第一级GOA电路单元100的第一输出端(其输出次级激励脉冲STV_N)连接到第二级GOA电 路单元100的第一输入端(其接收来自第一级的STV_N作为本级激励脉冲inxtpls)，依此类推。换言之，除最后一级GOA电路单元100之外，每一个GOA电路单元100的第一输出端连接到下一级阵列基板行驱动电路单元的第一输入端。由此，在施加到第一级GOA电路单元100的本级激励脉冲inxtpls的激励下，可以向各个像素行顺序地提供相应的栅极驱动脉冲OUT_1，OUT_2，OUT_3，OUT_4，...，OUT_n。
图5图示了根据发明的实施例的一种GOA电路的实现方式的原理图，其中仅示出了两个级联的GOA电路单元。如图5所示的，一个GOA电路单元包括阵列基板行驱动寄存模块110和阵列基板行驱动输出模块120。
阵列基板行驱动输出模块120包括用于按照前面参考图3所描述的时序关系生成两个栅极驱动脉冲的数字逻辑电路。在该实现方式中，数字逻辑电路包括与门A1、第一与非门AN1、第一非门N1、第二与非门AN2以及第二非门N2。与门A1的两个输入端之一被提供本级激励脉冲inxtpls，并且另一个被提供第二附加时钟信号CKKB。第一与非门AN1的一个输入端连接到与门A1的输出端，并且另一个输入端被提供第一时钟信号CK。第一非门N1的输入端连接到第一与非门AN1的输出端。第二与非门AN2的一个输入端连接到与门A1的输出端，并且另一个输入端被提供第二时钟信号CKB。第二非门N2的输入端连接到第二与非门AN2的输出端。第一非门N1的输出信号可以被路由到第一本级输出端作为第一栅线驱动脉冲OUT_1，并且第二非门N2的输出信号可以被路由到第二本级输出端作为第二栅线驱动脉冲OUT_2。为了提高栅线驱动脉冲的驱动能力，数字逻辑电路可以还包括用于在将第一栅线驱动脉冲路由到第一本级输出端以供输出之前对其进行缓冲的第一缓冲电路以及用于在将第二栅线驱动脉冲路由到第二本级输出端以供输出之前对其进行缓冲的第二缓冲电路。在该实现方式中，第一缓冲电路包括相互串联的偶数个非门，并且第二缓冲电路包括相互串联的偶数个非门。
阵列基板行驱动寄存模块110包括用于按照前面参考图3所描述的时序关系生成次级激励脉冲的移位寄存器单元。在该实现方式中，移位寄存器单元包括第三非门N3、第一三态非门TN1、第二三态非门TN2以及第四非门N4。第三非门N3的输入端被提供第一附加时钟信 号CKK。第一三态非门TN1的输入端被提供本级激励脉冲inxtpls，其第一控制端连接到第三非门N3的输入端，并且其第二控制端连接到第三非门N3的输出端。第二三态非门TN2的输出端连接到第一三态非门TN1的输出端，其第一控制端连接到第三非门N3的输出端，并且其第二控制端连接到第三非门N3的输入端。第四非门N4的输入端连接到第二三态非门TN2的输出端，其输出端连接到第二三态非门TN2的输入端，并且其输出信号被路由到阵列基板行驱动寄存模块110的第一输出端作为次级激励脉冲STV_N。
下面结合图3中所示的信号时序来详细介绍图5中的GOA电路的操作。
在时间段T1期间，CKK为低电平，CKKB为高电平，inxtpls为高电平。移位寄存器单元的第一三态非门TN1被关闭，使得inxtpls不能进入由第二三态非门TN2和第四非门N4组成的双稳态电路，而是直接和CKKB一起输入至与门A1。此时，与门A1的输出为高电平，此高电平分别输入两个与非门AN1、AN2中的每一个的一个输入端，该两个与非门AN1、AN2的另一输入端分别被提供CK和CKB。在CK的前半个周期期间，CK为高电平，CKB为低电平，使得OUT_1为高，OUT_2为低。与此相反，在CK的后半个周期期间，CK为低电平，CKB为高电平，使得OUT_1为低，OUT_1为高。
在时间段T2期间，inxtpls仍然保持在高电平，CKK为高电平，CKKB为低电平。移位寄存器单元的第一三态非门TN1被打开，并且第二三态非门TN2被关闭，使得双稳态电路不工作。inxtpls脉冲的后半个周期经过第一三态非门TN1和第四非门N4被路由到第一输出端，输出将被输入至下一级GOA单元的高电平信号(即，STV_N脉冲的前半个周期，其将使得下一级GOA单元能够生成两个栅极驱动脉冲OUT_3/OUT_4)。此时，由于CKKB为低，所以与门A1的输出为低电平，使得无论CK/CKB是否为高电平，OUT_1/OUT_2保持为低电平。
在时间段T3期间，inxtpls变为低电平，CKK为低电平，CKKB为高电平。移位寄存器单元的第一三态非门TN1被关闭，双稳态电路工作，将上一时刻的高电平锁存在其中，作为STV_N脉冲的后半个周期。此时，与时间段T2一样，无论CK/CKB信号如何，OUT_1/OUT_2都为低。
在时间段T4期间，inxtpls仍为低电平，CKK为高电平，CKKB为低电平。移位寄存器单元的第一三态非门TN1被打开，并且第二三态非门TN2被关闭，使得双稳态电路不工作。inxtpls的低电平信号经由第一三态非门TN1和第四非门N4将STV_N拉低为低电平。此时，无论CK/CKB信号如何，OUT_1/OUT_2输出保持为低电平。
此后，STV_N和OUT_1/OUT_2保持在低电平。每一级GOA都按照上述过程工作来完成扫描激励脉冲的移位和本级驱动脉冲的输出。
图6示意性地图示了根据本发明的另一个实施例的GOA电路单元200的框图。与图2所示的GOA电路单元100相比，GOA电路单元200除了阵列基板行驱动寄存模块110和阵列基板行驱动输出模块120之外，还可以包括扫描方向控制模块130。所述扫描方向控制模块130包括用于接收正扫激励脉冲STV_N-1的第六输入端、用于接收反扫激励脉冲STV_N+1的第七输入端、被施加第一直流电平CN的第一扫描方向控制端、被施加第二直流电平CNB的第二扫描方向控制端、被连接到所述第一输入端的第二输出端，以及模拟开关。第二直流电平CNB与第一直流电平CN是互补的。模拟开关在第一直流电平CN和第二直流电平CNB的控制下，将正扫激励脉冲STV_N-1和反扫激励脉冲STV_N+1中的一个选择性地路由到第二输出端作为本级激励脉冲inxtpls。例如，当CN为高电平，CNB为低电平时，模拟开关将正扫激励脉冲STV_N-1路由到第二输出端作为本级激励脉冲inxtpls，执行正向扫描；反之，当CN为低电平，CNB为高电平时，模拟开关将反扫激励脉冲STV_N+1路由到第二输出端作为本级激励脉冲inxtpls，执行反向扫描。
图7示意性地图示了通过级联如图6所示的GOA电路单元200而构成的GOA电路，其中仅示出了两个GOA电路单元200，并且这两个GOA单元200中除了本级输出端(OUT_x，x＝1，2，3，...n)之外对应的端子用相同的参考文字表示。如所示的，第一级GOA电路单元200的第一输出端(其在正向扫描的情况下输出次级激励脉冲STV_N)连接到第二级GOA电路单元200的第六输入端(其在正向扫描的情况下接收来自第一级的STV_N作为本级激励脉冲inxtpls)，并且第二级GOA电路单元200的第一输出端(其在反向扫描的情况下输出次级激励脉冲STV_N)连接到第一级GOA电路单元200的第七输入端(其 在反向扫描的情况下接收来自第二级的STV_N作为本级激励脉冲inxtpls)，依此类推。换言之，除第一级阵列基板行驱动电路单元之外，每一个阵列基板行驱动电路单元的第六输入端连接到上一级阵列基板行驱动电路单元的第一输出端，并且除最后一级阵列基板行驱动电路单元之外，每一个阵列基板行驱动电路单元的第七输入端连接到下一级阵列基板行驱动电路单元的第一输出端。由此，在正向扫描的情况下，在施加到第一级GOA电路单元200的正扫激励脉冲STV_N-1的激励下，可以从上到下向各个像素行顺序地提供相应的栅极驱动脉冲OUT_1，OUT_2，OUT_3，OUT_4，...，OUT_n；反之，在反向扫描的情况下，在施加到最后一级GOA电路单元200的反扫激励脉冲STV_N+1的激励下，可以从下到上向各个像素行顺序地提供相应的栅极驱动脉冲OUT_n，OUT_n-1，OUT_n-2，OUT_n-3，…，OUT_1。
图8图示了根据发明的另一实施例的一种GOA电路的实现方式的原理图，其中仅示出了两个级联的GOA电路单元。如所示的，一个GOA电路单元包括阵列基板行驱动寄存模块110、阵列基板行驱动输出模块120和可选的扫描方向控制模块130。
图8中图示的阵列基板行驱动寄存模块110和阵列基板行驱动输出模块120与前面描述的那些相同，并且在此不进行详细描述。
特别地，可选的扫描方向控制模块130包括用于在第一直流电平CN和第二直流电平CNB的控制下，将正扫激励脉冲STV_N-1和反扫激励脉冲STV_N+1中的一个选择性地路由到第二输出端的模拟开关。在该实现方式中，该模拟开关包括第一传输门TG1和第二传输门TG2。正扫激励脉冲STV_N-1被提供给第一传输门TG1的输入端，第一直流电平CN被施加到第一传输门TG1的第一控制端，第二直流电平CNB被施加到第一传输门TG1的第二控制端，并且第一传输门TG1的输出信号被路由到扫描方向控制模块130第二输出端作为本级激励脉冲inxtpls。反扫激励脉冲STV_N+1被提供给第二传输门TG2的输入端，第二直流电平CNB被施加到第二传输门TG2的第一控制端，第一直流电平CN被施加到第二传输门TG2的第二控制端，第二传输门TG2的输出信号被路由到扫描方向控制模块130的第二输出端作为本级激励脉冲inxtpls。
下面结合图3中所示的信号时序来详细介绍图8中的GOA电路的 操作。假定第一直流电平CN为高电平，第二直流电平CNB为低电平，也即，GOA电路工作在正向扫描模式下。
在时间段T1期间，CKK为低电平，CKKB为高电平，STV_N-1为高电平。移位寄存器单元的第一三态非门TN1被关闭，使得STV_N-1不能进入由第二三态非门TN2和第四非门N4组成的双稳态电路，而是直接和CKKB一起输入至与门A1。此时，与门A1的输出为高电平，此高电平分别输入两个与非门AN1、AN2中的每一个的一个输入端，该两个与非门AN1、AN2的另一输入端分别被提供CK和CKB。在CK的前半个周期期间，CK为高电平，CKB为低电平，使得OUT_1为高，OUT_2为低。与此相反，在CK的后半个周期期间，CK为低电平，CKB为高电平，使得OUT_1为低，OUT_1为高。
在时间段T2期间，STV_N-1仍然保持在高电平，CKK为高电平，CKKB为低电平。移位寄存器单元的第一三态非门TN1被打开，并且第二三态非门TN2被关闭，使得双稳态电路不工作。STV_N-1脉冲的后半个周期经过第一三态非门TN1和第四非门N4被路由到第一输出端，输出将被输入至下一级GOA单元的高电平信号(即，STV_N脉冲的前半个周期，其将使得下一级GOA单元能够生成两个栅极驱动脉冲OUT_3/OUT_4)。此时，由于CKKB为低，所以与门A1的输出为低电平，使得无论CK/CKB是否为高电平，OUT_1/OUT_2保持为低电平。
在时间段T3期间，STV_N-1变为低电平，CKK为低电平，CKKB为高电平。移位寄存器单元的第一三态非门TN1被关闭，双稳态电路工作，将上一时刻的高电平锁存在其中，作为STV_N脉冲的后半个周期。此时，与时间段T2一样，无论CK/CKB信号如何，OUT_1/OUT_2都为低。
在时间段T4期间，STV_N-1仍为低电平，CKK为高电平，CKKB为低电平。移位寄存器单元的第一三态非门TN1被打开，并且第二三态非门TN2被关闭，使得双稳态电路不工作。STV_N-1的低电平信号经由第一三态非门TN1和第四非门N4将STV_N拉低为低电平。此时，无论CK/CKB信号如何，OUT_1/OUT_2输出保持为低电平。
此后，STV_N和OUT_1/OUT_2保持在低电平。每一级GOA都按照上述过程工作来完成扫描激励脉冲的移位和本级驱动脉冲的输出。
还应当理解，图5和8中所示的电路配置仅是示例性的。对于同样的电路行为或功能，可以基于布尔代数公式得到不同的门电路结构。例如，在忽略缓冲电路的情况下，图5和8中所图示的阵列基板行驱动输出模块120的数字逻辑电路的功能可以表示为：
Figure PCTCN2015097114-appb-000001
Figure PCTCN2015097114-appb-000002
其中，每一个布尔代数表达式都可以表示一个具体的门电路结构。因此，代替如图5和8中所图示的门电路结构，还可以利用例如由一个与非门、一个非门以及一个或非门组成的数字逻辑电路来生成第一栅线驱动脉冲OUT_1，即，
Figure PCTCN2015097114-appb-000003
这样的变型是本领域技术人员已知的，并且在此将不进行详细描述。
根据一个实施例，前面描述的GOA电路单元100、200可以是基于CMOS工艺制造的。在一个供替换的实施例中，前面描述的GOA电路单元100、200可以是基于NMOS工艺制造的。在后者的情况下，晶体管的数目可以进一步减少，从而导致进一步减小的GOA占用面积。
此外，根据本发明的另一方面，还提供了一种显示面板，其包括前面描述的GOA电路，该GOA电路可以包括多个级联的GOA电路单元100或200。该显示面板可以应用于液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或者部件。
虽然前面的讨论包含若干特定的实现细节，但是这些不应解释为对任何发明或者可能要求保护的范围的限制，而应解释为对可能仅限于特定发明的特定实施例的特征的描述。在本说明书中不同的实施例中描述的特定特征也可以在单个实施例中以组合形式实现。与此相反，在单个实施例中描述的不同特征也可以在多个实施例中分别地或者以任何适当的子组合形式实现。此外，尽管前面可能将特征描述为以特定组合起作用，甚至最初也被如此要求保护，但是来自所要求保护的组合中的一个或多个特征在某些情况下也可以从该组合中排除，并且该要求保护的组合可以被导向子组合或子组合的变型。
鉴于前面的描述并结合阅读附图，对前述本发明的示例性实施例的各种修改和改动对于相关领域的技术人员可以变得显而易见。任何和所有修改仍将落入本发明的非限制性和示例性实施例的范围内。此 外，属于本发明的这些实施例所属领域的技术人员，在得益于前面的描述和相关附图所给出的教导后，将会想到在此描述的本发明的其他实施例。
因此，应当理解，本发明的实施例并不限于所公开的特定实施例，并且修改和其他的实施例也意图被包含在所附权利要求书的范围内。尽管此处使用了特定术语，但是它们仅在通用和描述性意义上使用，而非为了限制的目的。

Claims (10)

  1. 一种阵列基板行驱动电路单元，包括：
    用于接收本级激励脉冲的第一输入端；
    用于接收第一附加时钟信号的第二输入端；
    用于接收第二附加时钟信号的第三输入端，所述第二附加时钟信号是所述第一附加时钟信号的反相版本；
    用于接收第一时钟信号的第四输入端；
    用于接收第二时钟信号的第五输入端，所述第二时钟信号是所述第一时钟信号的反相版本；
    用于输出次级激励脉冲的第一输出端；
    用于输出第一栅线驱动脉冲的第一本级输出端；
    用于输出第二栅线驱动脉冲的第二本级输出端；
    阵列基板行驱动寄存模块，其具有移位寄存器单元；以及
    阵列基板行驱动输出模块，其具有数字逻辑电路；
    其中，所述本级激励脉冲、所述第一附加时钟信号和所述第一时钟信号是同步的，所述本级激励脉冲的宽度等于所述第一附加时钟信号的一个周期，所述第一附加时钟信号的周期是所述第一时钟信号的周期的两倍，并且，所述第一栅线驱动脉冲和所述第二栅线驱动脉冲的宽度均等于所述第一时钟信号的周期的一半；
    其中，所述本级激励脉冲和所述第一附加时钟信号被提供给所述移位寄存器单元，使得在所述第一输出端输出所述次级激励脉冲，所述次级激励脉冲是所述本级激励脉冲的被移位所述第一附加时钟信号的半个周期的延迟版本；
    并且其中，所述本级激励脉冲、所述第二附加时钟信号、所述第一时钟信号和所述第二时钟信号被提供给所述数字逻辑电路，使得仅在所述本级激励脉冲的前半个脉宽期间在所述第一本级输出端输出与所述第一时钟信号的前半个周期时序上对应的所述第一栅线驱动脉冲，并且在所述第二本级输出端输出与所述第二时钟信号的后半个周期时序上对应的所述第二栅线驱动脉冲。
  2. 根据权利要求1所述的阵列基板行驱动电路单元，其中，所述数字逻辑电路包括：
    与门，其两个输入端之一被提供所述本级激励脉冲，并且另一个输入端被提供所述第二附加时钟信号；
    第一与非门，其一个输入端连接到所述与门的输出端，并且另一个输入端被提供所述第一时钟信号；
    第一非门，其输入端连接到所述第一与非门的输出端；
    第二与非门，其一个输入端连接到所述与门的输出端，并且另一个输入端被提供所述第二时钟信号；以及
    第二非门，其输入端连接到所述第二与非门的输出端；
    其中，所述第一非门的输出信号被路由到所述第一本级输出端作为所述第一栅线驱动脉冲，并且所述第二非门的输出信号被路由到所述第二本级输出端作为所述第二栅线驱动脉冲。
  3. 根据权利要求1所述的阵列基板行驱动电路单元，其中，所述数字逻辑电路还包括：
    第一缓冲电路，用于在将所述第一栅线驱动脉冲路由到所述第一本级输出端以供输出之前对其进行缓冲；以及
    第二缓冲电路，用于在将所述第二栅线驱动脉冲路由到所述第二本级输出端以供输出之前对其进行缓冲。
  4. 根据权利要求3所述的阵列基板行驱动电路单元，其中，所述第一缓冲电路包括相互串联的偶数个非门，并且所述第二缓冲电路包括相互串联的偶数个非门。
  5. 根据权利要求1所述的阵列基板行驱动电路单元，其中，所述移位寄存器单元包括：
    第三非门，其输入端被提供所述第一附加时钟信号；
    第一三态非门，其输入端被提供所述本级激励脉冲，其第一控制端连接到所述第三非门的输入端，并且其第二控制端连接到所述第三非门的输出端；
    第二三态非门，其输出端连接到所述第一三态非门的输出端，其第一控制端连接到所述第三非门的输出端，并且其第二控制端连接到所述第三非门的输入端；以及
    第四非门，其输入端连接到所述第二三态非门的输出端，其输出端连接到所述第二三态非门的输入端，并且其输出信号被路由到所述第一输出端作为所述次级激励脉冲。
  6. 根据权利要求1所述的阵列基板行驱动电路单元，还包括扫描方向控制模块，其中，所述扫描方向控制模块包括：
    用于接收正扫激励脉冲的第六输入端；
    用于接收反扫激励脉冲的第七输入端；
    被施加第一直流电平的第一扫描方向控制端；
    被施加第二直流电平的第二扫描方向控制端，所述第二直流电平与所述第一直流电平是互补的；
    被连接到所述第一输入端的第二输出端；以及
    模拟开关，其在所述第一直流电平和所述第二直流电平的控制下，将所述正扫激励脉冲和所述反扫激励脉冲中的一个选择性地路由到所述第二输出端作为所述本级激励脉冲。
  7. 根据权利要求6所述的阵列基板行驱动电路单元，其中，所述模拟开关包括第一传输门和第二传输门，所述正扫激励脉冲被提供给所述第一传输门的输入端，所述第一直流电平被施加到所述第一传输门的第一控制端，所述第二直流电平被施加到所述第一传输门的第二控制端，所述第一传输门的输出信号被路由到所述第二输出端作为所述本级激励脉冲，所述反扫激励脉冲被提供给所述第二传输门的输入端，所述第二直流电平被施加到所述第二传输门的第一控制端，所述第一直流电平被施加到所述第二传输门的第二控制端，所述第二传输门的输出信号被路由到所述第二输出端作为所述本级激励脉冲。
  8. 根据权利要求1所述的阵列基板行驱动电路单元，其中，所述阵列基板行驱动电路单元是基于CMOS或NMOS工艺制造的。
  9. 一种阵列基板行驱动电路，包括至少两个级联的根据权利要求1-7中任一项所述的阵列基板行驱动电路单元，
    其中，在所述阵列基板行驱动电路单元不包括所述扫描方向控制模块的情况下，除最后一级阵列基板行驱动电路单元之外，每一个阵列基板行驱动电路单元的第一输出端连接到下一级阵列基板行驱动电路单元的第一输入端；
    并且其中，在所述阵列基板行驱动电路单元包括所述扫描方向控制模块的情况下，除第一级阵列基板行驱动电路单元之外，每一个阵列基板行驱动电路单元的第六输入端连接到上一级阵列基板行驱动电路单元的第一输出端，并且除最后一级阵列基板行驱动电路单元之外， 每一个阵列基板行驱动电路单元的第七输入端连接到下一级阵列基板行驱动电路单元的第一输出端。
  10. 一种显示面板，包括根据权利要求9所述的阵列基板行驱动电路。
PCT/CN2015/097114 2015-07-21 2015-12-11 阵列基板行驱动电路单元、驱动电路和显示面板 Ceased WO2017012254A1 (zh)

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