WO2016206133A1 - 像素结构、阵列基板及显示装置 - Google Patents

像素结构、阵列基板及显示装置 Download PDF

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Publication number
WO2016206133A1
WO2016206133A1 PCT/CN2015/083648 CN2015083648W WO2016206133A1 WO 2016206133 A1 WO2016206133 A1 WO 2016206133A1 CN 2015083648 W CN2015083648 W CN 2015083648W WO 2016206133 A1 WO2016206133 A1 WO 2016206133A1
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Prior art keywords
layer
connection
insulating layer
scan line
disposed
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English (en)
French (fr)
Inventor
明星
申智渊
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/783,927 priority Critical patent/US10088723B2/en
Publication of WO2016206133A1 publication Critical patent/WO2016206133A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a pixel structure, an array substrate having the pixel structure, and a display device using the array substrate.
  • touch touch
  • display Display
  • thin film transistor type liquid crystal display Thin Film Transistor-Liquid Crystal Display, TFT- LCD
  • OGS Over Film Transistor-Liquid Crystal Display
  • Touch Touch
  • Hybrid In-Cell Touch Hybrid In-Cell Touch
  • In-Cell Touch panels are more lightweight, less process-intensive, and more stable.
  • In-Cell Touch technology integrates the touch circuit into the LCD, eliminating the need to externally touch the sensor glass or perform the On-Cell process on the LCD, thereby achieving integration and shortening the production process. Production time makes LCD manufacturers more profitable.
  • the In-Cell Touch panel can achieve higher resolution and effectively prevent Murray interference. Therefore, the In-Cell Touch panel will become the mainstream direction for the future development of small and medium-sized touch panels.
  • electrodes and traces for touch display are designed on the array substrate.
  • a low temperature poly-silicon (LTPS) array is used, and the array process is more traditional than the conventional one.
  • the crystalline silicon ( ⁇ -Si) process is much more complicated. Therefore, the integration of In-Cell Touch and LTPS will not only make the array process more complicated, but also have a longer production cycle and stricter requirements on the array process.
  • In-Cell Touch panels are generally classified into self-contained and mutual-capacitance types, both of which require connection electrodes for connecting pixel regions. Therefore, one or two Photo Engraving Process (PEP) processes are added to the process. A connection electrode (or called Metal3 or M3) connecting the pixel regions and a corresponding insulating layer are formed.
  • PEP Photo Engraving Process
  • M3 Metal3
  • M3 has to be used to connect the pixel area, thus limiting the yield improvement of the In-Cell Touch panel to some extent.
  • the present invention provides a pixel structure for fabricating connection electrodes for connecting pixel regions by utilizing existing gate metal and source/drain metal, thereby simplifying the process of the array substrate, reducing the risk of occurrence of speckle defects, and improving product yield. .
  • the present invention also provides an array substrate to which the pixel structure is applied.
  • the present invention also provides a display device to which the array substrate is applied.
  • a pixel structure includes a scan line, a data line, and a pixel area, the scan lines are arranged in parallel in a horizontal direction, the data lines are arranged in parallel in a vertical direction, and the scan lines and the data lines overlap each other to form The pixel region, wherein the pixel structure further includes a connection electrode for connecting the pixel region, the connection electrode includes a first connection layer and a second connection layer, the first connection layer and the scan line Located in the same layer and disposed across the scan line, the first connection layer is cut off at the intersection with the scan line, and the second connection layer is on the same layer as the data line and spans The scan line is disposed, and the first connection layer is electrically connected to the second connection layer through the first via hole at two sides of the intersection.
  • first connection layer is disposed under the data line and extends in the same direction parallel to the direction of the scan line on both sides of the scan line partition to extend at a distance from the partition.
  • a connecting end is formed on each of the two sides, and two ends of the second connecting layer partially overlap the connecting end in a front projection direction, and are electrically connected to the connecting end through the first through hole.
  • the pixel structure further includes a thin film transistor formed at an intersection of the scan line and the data line, and a thin film transistor including a gate, a polysilicon layer, and a source And a drain, the gate is electrically connected to the scan line, the polysilicon layer is disposed above the gate, and the source and the drain are disposed above the polysilicon layer, and respectively pass through a first
  • the second via is electrically connected to the polysilicon layer
  • the common electrode is electrically connected to the second connection layer through a third via
  • the pixel electrode passes through a third via and a fourth via
  • the drain is electrically connected.
  • the pixel structure further includes a substrate and a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer which are sequentially stacked on the substrate, the gate and the first connecting layer
  • the first insulating layer is disposed on the substrate, the first insulating layer is disposed above the gate and the first connecting layer, and the polysilicon layer is disposed above the first insulating layer, and is in the orthographic projection direction
  • the gate is aligned, the second insulating layer is disposed above the polysilicon layer, the third insulating layer is disposed above the second insulating layer, and the common electrode is disposed above the third insulating layer,
  • the fourth insulating layer is disposed above the common electrode, and the pixel electrode is disposed above the fourth insulating layer.
  • the source, the drain, and the second connection layer are disposed in the third insulating layer, and the source partially overlaps one end of the polysilicon layer in a right projection direction, the drain The other end portion of the polysilicon layer partially overlaps in a front projection direction, the second connection layer being over the first connection layer and partially overlapping the first connection layer in a right projection direction.
  • the polysilicon layer includes a first connection segment, a second connection segment, and a third connection segment, and the first connection segment and the third connection segment are disposed across the scan line in parallel with each other, the second The connecting segment is connected between the first connecting segment and the third connecting segment at both ends of the same side of the scanning line, and is parallel to the scanning line.
  • the first connection layer is located in the same layer as the gate and the scan line, and the second connection layer is in the same layer as the source, the drain and the data line.
  • a connection layer is formed in synchronization with the gate and the scan line in the same fabrication process, and the second connection layer is formed synchronously with the source, the drain, and the data line in the same fabrication process.
  • An array substrate comprising a plurality of scan lines, a plurality of data lines and a plurality of pixel regions, the scan lines are arranged in parallel in a horizontal direction, the data lines are arranged in parallel in a vertical direction, the scan lines and the scan lines The data lines overlap each other to form the pixel region, wherein the array substrate further includes a connection electrode for connecting the pixel region, the connection electrode includes a first connection layer and a second connection layer, the first connection The layer is located in the same layer as the scan line and is disposed across the scan line, the first connection layer is cut off at an intersection with the scan line, and the second connection layer is located at the data line The same layer is disposed across the scan line, and the first connection layer is open on both sides of the intersection The first via is electrically connected to the second connection layer.
  • first connection layer is disposed under the data line and extends in the same direction parallel to the direction of the scan line on both sides of the scan line partition to extend at a distance from the partition.
  • a connecting end is formed on each of the two sides, and two ends of the second connecting layer partially overlap the connecting end in a front projection direction, and are electrically connected to the connecting end through the first through hole.
  • the array substrate further includes a plurality of thin film transistors, a plurality of common electrodes, and a plurality of pixel electrodes, the plurality of thin film transistors being formed at an intersection of the scan lines and the data lines, each of the thin films
  • the transistor includes a gate, a polysilicon layer, a source and a drain, the gate is electrically connected to the scan line, the polysilicon layer is disposed above the gate, and the source and the drain are disposed on the Above the polysilicon layer, and electrically connected to the polysilicon layer through a second via hole, the common electrode is electrically connected to the second connection layer through a third via hole, and the pixel electrode passes through a third The via hole and the fourth via hole are electrically connected to the drain.
  • the array substrate further includes a substrate and a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer which are sequentially stacked on the substrate, the gate and the first connecting layer
  • the first insulating layer is disposed on the substrate, the first insulating layer is disposed above the gate and the first connecting layer, and the polysilicon layer is disposed above the first insulating layer, and is in the orthographic projection direction
  • the gate is aligned, the second insulating layer is disposed above the polysilicon layer, the third insulating layer is disposed above the second insulating layer, and the common electrode is disposed above the third insulating layer,
  • the fourth insulating layer is disposed above the common electrode, and the pixel electrode is disposed above the fourth insulating layer.
  • the source, the drain, and the second connection layer are disposed in the third insulating layer, and the source partially overlaps one end of the polysilicon layer in a right projection direction, the drain The other end portion of the polysilicon layer partially overlaps in a front projection direction, the second connection layer being over the first connection layer and partially overlapping the first connection layer in a right projection direction.
  • the polysilicon layer includes a first connection segment, a second connection segment, and a third connection segment, and the first connection segment and the third connection segment are disposed across the scan line in parallel with each other, the second The connecting segment is connected between the first connecting segment and the third connecting segment at both ends of the same side of the scanning line, and is parallel to the scanning line.
  • the first connection layer is located in the same layer as the gate and the scan line, and the second connection layer is in the same layer as the source, the drain and the data line.
  • a connection layer and said The gate and the scan line are simultaneously formed in the same fabrication process, and the second connection layer is formed synchronously with the source, the drain, and the data line in the same fabrication process.
  • a display device includes an array substrate, wherein the array substrate includes a plurality of scan lines, a plurality of data lines, and a plurality of pixel regions, the scan lines are arranged in parallel in a horizontal direction, and the data lines are parallel in a vertical direction An interval, the scan line and the data line overlap each other to form the pixel area, wherein the array substrate further includes a connection electrode for connecting the pixel area, the connection electrode includes a first connection layer and a second connection layer, the first connection layer is located in the same layer as the scan line, and is disposed to intersect with the scan line, and the first connection layer is cut off at an intersection with the scan line, The second connection layer is located in the same layer as the data line and is disposed across the scan line, and the first connection layer is electrically connected to the second connection layer through the first via hole at both sides of the intersection connection.
  • first connection layer is disposed under the data line and extends in the same direction parallel to the direction of the scan line on both sides of the scan line partition to extend at a distance from the partition.
  • a connecting end is formed on each of the two sides, and two ends of the second connecting layer partially overlap the connecting end in a front projection direction, and are electrically connected to the connecting end through the first through hole.
  • the array substrate further includes a plurality of thin film transistors, a plurality of common electrodes, and a plurality of pixel electrodes, the plurality of thin film transistors being formed at an intersection of the scan lines and the data lines, each of the thin films
  • the transistor includes a gate, a polysilicon layer, a source and a drain, the gate is electrically connected to the scan line, the polysilicon layer is disposed above the gate, and the source and the drain are disposed on the Above the polysilicon layer, and electrically connected to the polysilicon layer through a second via hole, the common electrode is electrically connected to the second connection layer through a third via hole, and the pixel electrode passes through a third The via hole and the fourth via hole are electrically connected to the drain.
  • the array substrate further includes a substrate and a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer which are sequentially stacked on the substrate, the gate and the first connecting layer
  • the first insulating layer is disposed on the substrate, the first insulating layer is disposed above the gate and the first connecting layer, and the polysilicon layer is disposed above the first insulating layer, and is in the orthographic projection direction
  • the gate is aligned, the second insulating layer is disposed above the polysilicon layer, the third insulating layer is disposed above the second insulating layer, and the common electrode is disposed above the third insulating layer,
  • the fourth insulating layer is disposed above the common electrode, and the pixel electrode is disposed above the fourth insulating layer.
  • the source, the drain and the second connection layer are disposed in the third insulation layer, and
  • the source electrode partially overlaps one end of the polysilicon layer in a right projection direction
  • the drain portion overlaps another end portion of the polysilicon layer in a right projection direction
  • the second connection layer is located at the first connection layer Upper, and partially overlapping the first connection layer in the forward projection direction.
  • the polysilicon layer includes a first connection segment, a second connection segment, and a third connection segment, and the first connection segment and the third connection segment are disposed across the scan line in parallel with each other, the second The connecting segment is connected between the first connecting segment and the third connecting segment at both ends of the same side of the scanning line, and is parallel to the scanning line.
  • the pixel structure of the present invention is formed by synchronizing the first connection layer with the gate and the scan line in the same fabrication process, and the second connection layer and the source, the drain, and the The data lines are formed synchronously in the same fabrication process, and the first connection layer and the second connection layer are electrically connected through the first via hole to form a connection electrode for connecting the pixel regions. Therefore, it is not necessary to separately add one or more manufacturing processes to form the connecting electrode, which simplifies the process flow, reduces the risk of occurrence of speckle defects, and improves product yield.
  • FIG. 1 is a schematic plan view showing the structure of a pixel structure according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional structural view of the pixel structure shown in FIG. 1.
  • FIG 3 is a schematic plan view showing the structure of an array substrate according to a second embodiment of the present invention.
  • the present invention provides a pixel structure 100 for fabricating connection electrodes for connecting pixel regions by utilizing existing gate metal and source/drain metal to simplify the process and reduce the risk of speckle defects. Improve product yield.
  • the pixel structure 100 includes a scan line 110, a data line 130, a pixel area 150, and a connection electrode 50 for connecting the pixel area 150.
  • the scan lines 110 are gate scan lines which are arranged in parallel with each other in the horizontal direction.
  • the data lines 130 are arranged in parallel with each other in the vertical direction. Two adjacent scan lines 110 and two adjacent ones are disposed. The data lines 130 overlap each other to form a pixel region 150.
  • the connection electrode 50 includes a first connection layer 51 and a second connection layer 53.
  • the first connection layer 51 is located in the same layer as the scan line 110
  • the second connection layer 53 is located in the same layer as the data line 130.
  • the first connection layer 51 and the scan line 110 are disposed to cross each other, and are separated by the scan line 110 at an intersection with the scan line 110.
  • the second connection layer 53 and the number Lines 130 are parallel and are disposed across the scan line 110.
  • the first connection layer 51 is electrically connected to the second connection layer 53 through the first via hole H1 at both sides of the intersection, that is, the first connection layer 51 is at the two of the scan lines 110.
  • the first via hole H1 is electrically connected to the second connection layer 53 so that the first connection layer 51 located in different pixel regions 150 are electrically connected to each other to form the connection electrode 50. Different pixel regions 150 are connected.
  • the first connection layer 51 is disposed under the data line 130 and extends in the same direction parallel to the direction of the scan line 110 on both sides of the partition line 111.
  • a connecting end 511 is formed on each side of the partition. Both ends of the second connection layer 53 partially overlap the connection end 511 on both sides of the first connection layer 51 at the partition of the scan line 110 in the front projection direction, and pass through the first via hole H1 and The connecting end 511 is electrically connected.
  • FIG. 2 is a partial cross-sectional structural view of the pixel structure 100 of FIG. It should be noted that the cross-sectional structural diagram shown in FIG. 2 is not strictly cut according to any cross-sectional direction in the planar structure diagram of the pixel structure 100 shown in FIG. 1. Therefore, FIG. 2 is only used in conjunction with FIG. The internal structure of the pixel structure 100 is explained.
  • the pixel structure 100 further includes a substrate 10 and a first insulating layer 11, a second insulating layer 13, a third insulating layer 15, and a fourth insulating layer 17, which are sequentially stacked on the substrate 10, and a thin film transistor 20, a common Electrode 30 and pixel electrode 40.
  • the thin film transistor 20 includes a gate electrode 21, a polysilicon layer 22, a source electrode 23, and a drain electrode 25.
  • the gate electrode 21 is spaced apart from the first connection layer 51 of the connection electrode 50 on the substrate 10 .
  • the first insulating layer 11 is disposed above the gate electrode 21 and the first connection layer 51.
  • the polysilicon layer 22 is disposed above the first insulating layer 11 and substantially aligned with the gate 21 in a right projection direction.
  • the second insulating layer 13 is disposed on the polysilicon layer 22 and is in close contact with the polysilicon layer 22.
  • the third insulating layer 15 is disposed above the second insulating layer 13 .
  • the source 23 , the drain 25 , and the second connection layer 53 of the connection electrode 50 are disposed in the third insulating layer 15 .
  • the source 23 and the drain 25 are located above the polysilicon layer 22, and the source 23 partially overlaps one end of the gate 21 and the polysilicon layer 22 in a right projection direction, and the drain 25 is positive
  • the other ends of the gate electrode 21 and the polysilicon layer 22 partially overlap in the projection direction.
  • the source 23 and the drain 25 are electrically connected to opposite ends of the polysilicon layer 22 through a second via H2.
  • the second connection layer 53 is located above the first connection layer 51 and partially overlaps the first connection layer 51 in the orthogonal projection direction.
  • the first Two sides of the two connection layers 53 are electrically connected to the first connection layer 51 through a first via hole H1.
  • the common electrode 30 is disposed above the third insulating layer 15 and electrically connected to the second connecting layer 53 through a third via H3.
  • the fourth insulating layer 17 is disposed above the common electrode 30.
  • the pixel electrode 40 is disposed above the fourth insulating layer 17 and passes through a fourth via hole H4 penetrating the fourth insulating layer 17 and a third via hole H3 penetrating a portion of the third insulating layer 15
  • the drain 25 of the thin film transistor 20 is electrically connected.
  • the thin film transistor 20 is formed at an intersection of the scan line 110 and the data line 130.
  • the gate 21 is located in the same layer as the scan line 110 and is electrically connected to the scan line 110.
  • the polysilicon layer 22 has a substantially " ⁇ " shape and includes a first connecting section 221, a second connecting section 223, and a third connecting section 225.
  • the first connecting section 221 and the third connecting section 225 are disposed across the scanning line 110 at intervals in parallel with each other.
  • the second connecting section 223 is connected between the two ends of the first connecting section 221 and the third connecting section 225 on the same side of the scanning line 110 and is parallel to the scanning line 110.
  • the source 23 and the drain 25 are respectively disposed above the one ends of the first connection segment 221 and the third connection segment 225 away from the second connection segment 223 (ie, the source 23 and the drain 25 are respectively disposed.
  • the first connecting segment 221 and the third connecting segment 225 are opposite to the other ends of the scan line 110, and are connected to the first connecting segment 221 and the third through the second via H2, respectively.
  • Segment 225 is electrically connected.
  • the source 23 is located in the same layer as the data line 130 and is electrically connected to the data line 130.
  • the drain electrode 25 is electrically connected to the pixel electrode (not shown) through the third via hole H3 and the fourth via hole H4.
  • the common electrode 30 is electrically connected to the second connection layer 53 through the third via hole H3.
  • first connection layer 51 and the gate electrode 21 and the scan line 110 are located in the same layer, the second connection layer 53 and the source 23, the drain 25 and the data line 130. Located on the same layer. Therefore, the first connection layer 51 may be formed in synchronization with the gate electrode 21 and the scan line 110 in the same fabrication process, and the second connection layer 53 may be connected to the source 23, the drain 25, and the The data lines 130 are formed synchronously in the same fabrication process. Further, the first connection layer 51 and the second connection layer 53 are electrically connected through the first via hole H1 to form a connection for the connection.
  • the pixel region 150 is connected to the electrode 50, so that it is not necessary to separately add one or more fabrication processes to form the connection electrode 50, which simplifies the process flow.
  • a second embodiment of the present invention provides an array substrate 200 using the pixel structure 100 shown in FIGS. 1 and 2.
  • the array substrate 200 includes a plurality of scan lines 210 , a plurality of data lines 230 , and a plurality of pixel regions 250 .
  • the plurality of scan lines 210 are gate scan lines, which are arranged in parallel with each other in a horizontal direction.
  • the plurality of data lines 230 are arranged in parallel with each other in a vertical direction, and two adjacent scan lines 210 are adjacent to each other.
  • the two data lines 230 overlap each other to form a pixel region 250.
  • the array substrate 200 further includes a plurality of connection electrodes 50 for connecting the pixel regions 250.
  • the connection electrode 50 includes a first connection layer 51 and a second connection layer 53.
  • the first connection layer 51 is located in the same layer as the scan line 210
  • the second connection layer 53 is located in the same layer as the data line 230.
  • the first connection layer 51 and the scan line 210 are disposed to cross each other, and are separated by the scan line 210 at an intersection with the scan line 210.
  • the second connection layer 53 is parallel to the data line 230 and is disposed across the scan line 210.
  • the first connection layer 51 is electrically connected to the second connection layer 53 through the first via hole H1 on both sides of the intersection, that is, the first connection layer 51 is on the scan line 210
  • the first via hole H1 is electrically connected to the second connection layer 53 so that the first connection layers 51 located in different pixel regions 250 are electrically connected to each other to form the connection electrode 50. Different pixel areas 250 are connected.
  • the first connection layer 51 is disposed under the data line 230 and extends in the same direction in a direction parallel to the scan line 210 on both sides of the partition where the scan line 210 is blocked.
  • a connecting end 511 is formed on each side of the partition. Both ends of the second connection layer 53 partially overlap the connection end 511 on both sides of the first connection layer 51 at the partition of the scan line 210 in the front projection direction, and pass through the first via hole H1 and The connecting end 511 is electrically connected.
  • the array substrate 200 further includes a plurality of thin film transistors T, a plurality of common electrodes Vcom, and a plurality of pixel electrodes (not shown).
  • the plurality of thin film transistors T are formed at an intersection of the scan line 210 and the data line 230.
  • Each of the thin film transistors T includes a gate g, a polysilicon layer p, a source s, and a drain d.
  • the gate g is located in the same layer as the scan line 210 and is electrically connected to the scan line 210.
  • the polysilicon layer p has a substantially " ⁇ " shape and includes a first connection segment p1, a second connection segment p3, and a third connection segment p5.
  • the first connecting segment p1 and the third connecting segment p5 are parallel to each other Arranged across the scan line 210 at intervals.
  • the second connecting segment p3 is connected between the two ends of the first connecting segment p1 and the third connecting segment p5 on the same side of the scanning line 210 and is parallel to the scanning line 210.
  • the source s and the drain d are respectively disposed above the one ends of the first connection segment p1 and the third connection segment p5 away from the second connection segment p3 (ie, the source s and the drain d are respectively set
  • the first connecting segment p1 and the third connecting segment p3 are opposite to opposite ends of the scan line 210, and respectively pass through a second via hole H2 and the first connecting segment p1 and the third connecting segment P5 is electrically connected.
  • the common electrode Vcom is electrically connected to the second connection layer 53 through a third via H3.
  • the source s is located in the same layer as the data line 230 and is electrically connected to the data line 230.
  • the drain d is electrically connected to the pixel electrode (not shown) through a third via H3 and a fourth via H4. It can be understood that, in FIG. 3 of the present application, since the positions of the source s and the second via H2 overlap, the two are represented by one lead. Similarly, the gate g and the scan line 210 in FIG. The lead wire indicates that the drain d and the second via hole H2 are represented by one lead, and the pixel region 250 and the common electrode Vcom are also represented by one lead.
  • the first connection layer 51 is located in the same layer as the gate g and the scan line 210, the second connection layer 53 and the source g, the drain d and the data line 230. Located on the same layer. Therefore, the first connection layer 51 may be formed in synchronization with the gate g and the scan line 210 in the same fabrication process, and the second connection layer 53 may be coupled to the source s, the drain d, and the The data lines 230 are formed synchronously in the same fabrication process.
  • connection electrode 50 for connecting the pixel region 250, so that there is no need to separately add a Or a plurality of fabrication processes to form the connection electrode 50 simplifies the process flow for fabricating the array substrate 200.
  • the present invention further provides a display device using the array substrate 200, which is formed by synchronizing the first connection layer 51 with the gate electrode g and the scan line 210 in the same fabrication process, and The second connection layer 53 is formed in synchronization with the source s, the drain d, and the data line 230 in the same fabrication process.
  • the first connection layer 51 and the second connection layer 53 are electrically connected through the first via hole H1 to form the connection electrode 50 for connecting the pixel region 250, so that it is not necessary to separately add one or more
  • the fabrication process to form the connection electrode 50 simplifies the process flow for manufacturing the display device, reduces the risk of speckle defects, and improves product yield.

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Abstract

一种像素结构（100），包括扫描线（110）、数据线（130）及像素区域（150），所述扫描线（110）沿水平方向平行间隔设置，所述数据线（130）沿垂直方向平行间隔设置，所述扫描线（110）与所述数据线（130）相互交叠形成所述像素区域（150），所述像素结构（100）还包括用于连接所述像素区域的连接电极（50），所述连接电极（50）包括第一连接层（51）和第二连接层（53），所述第一连接层（51）与所述扫描线（110）位于同一图层，并与所述扫描线（110）交叉设置，所述第一连接层（51）在与所述扫描线（110）的交叉处被隔断，所述第二连接层（53）与所述数据线（130）位于同一图层，并跨越所述扫描线（110）设置，所述第一连接层（51）在所述交叉处的两侧通过第一过孔（H1）与所述第二连接层（53）电性连接。还提供一种阵列基板（200）及显示装置。所述像素结构（100）可以简化所述阵列基板（200）的工艺流程。

Description

像素结构、阵列基板及显示装置
本发明要求2015年6月26日递交的发明名称为“像素结构、阵列基板及显示装置”的申请号(201510362528.8)的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种像素结构、一种具有该像素结构的阵列基板及一种应用该阵列基板的显示装置。
背景技术
随着触摸屏技术的不断发展，触控(Touch)和显示(Display)不再是两种独立的技术形式，越来越多的薄膜晶体管型液晶显示屏(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)厂家开始尝试将Touch和Display两者进行有机的结合，内嵌式触控(In-Cell Touch)、单片式触控(One Glass Solution，OGS)、覆盖表面式触控(On-Cell Touch)和混合内嵌式触控(Hybrid In-Cell Touch)等将Touch和Display相结合的触控技术竞相涌现。
相比OGS、On-Cell Touch或Hybrid In-Cell Touch面板，In-Cell Touch面板具备更加轻薄、工艺流程更少、结构更加稳定等优点。In-Cell Touch技术将触控电路全部集成在LCD内部，无须再外贴触控感应玻璃(Touch Sensor Glass)或者在LCD上面再进行On-Cell制程，从而实现了集成化及缩短了生产流程和生产时间，使得LCD生产厂商的利润更大化。同时，通过使用高分辨的曝光机，可以实现In-Cell Touch面板更高的分辨率，并能有效防止莫瑞干涉。因此，In-Cell Touch面板将成为中小尺寸触控面板未来发展的主流方向。
在In-Cell Touch面板的生产过程中，需要在阵列基板上设计为了触控显示的电极和走线，如采用低温多晶硅(Low Temperature Poly-silicon，LTPS)阵列，其阵列制程比传统的传统非晶硅(α-Si)制程复杂得多。所以In-Cell Touch和LTPS的集成不但会使得阵列制程更加复杂，生产周期更长，而且对阵列制程的要求也更加严格。
In-Cell Touch面板一般可分为自容式和互容式，二者都需要用于连接像素区域的连接电极，因此制程上会增加一道或两道光刻(Photo Engraving Process，PEP)制程来制作连接像素区域的连接电极(或称作Metal3或M3)和相应的绝缘层。增加的M3制程会对产品的良率产生风险，因为M3的刻蚀制程会导致斑纹(Mura)缺陷。然而，在In-Cell Touch技术中又不得不采用M3以连接像素区域，因此一定程度上限制了In-Cell Touch面板良率提升。
发明内容
本发明提供一种像素结构，通过利用现有的栅极金属和源/漏极金属来制作用于连接像素区域的连接电极，以简化阵列基板制程、降低产生斑纹缺陷的风险、提升产品良率。
另外，本发明还提供一种应用该像素结构的阵列基板。
此外，本发明还提供一种应用该阵列基板的显示装置。
一种像素结构，包括扫描线、数据线及像素区域，所述扫描线沿水平方向平行间隔设置，所述数据线沿垂直方向平行间隔设置，所述扫描线与所述数据线相互交叠形成所述像素区域，其中，所述像素结构还包括用于连接所述像素区域的连接电极，所述连接电极包括第一连接层和第二连接层，所述第一连接层与所述扫描线位于同一图层，并与所述扫描线交叉设置，所述第一连接层在与所述扫描线的交叉处被隔断，所述第二连接层与所述数据线位于同一图层，并跨越所述扫描线设置，所述第一连接层在所述交叉处的两侧通过第一过孔与所述第二连接层电性连接。
其中，所述第一连接层设置于所述数据线下方，并在被所述扫描线隔断处的两侧沿平行于所述扫描线的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端，所述第二连接层的两端在正投影方向上与所述连接端部分重叠，并通过所述第一过孔与所述连接端电性连接。
其中，所述像素结构还包括薄膜晶体管、公共电极和像素电极，所述薄膜晶体管形成于所述扫描线与所述数据线的交叠处，所述薄膜晶体管包括栅极、多晶硅层、源极和漏极，所述栅极与所述扫描线电性连接，所述多晶硅层设置于所述栅极上方，所述源极和漏极设置于所述多晶硅层上方，并分别通过一第 二过孔与所述多晶硅层电性连接，所述公共电极通过一第三过孔与所述第二连接层电性连接，所述像素电极通过一第三过孔及一第四过孔与所述漏极电性连接。
其中，所述像素结构还包括基板及依次层叠设置于所述基板上的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述栅极与所述第一连接层间隔设置于所述基板上，所述第一绝缘层设置于所述栅极及第一连接层上方，所述多晶硅层设置于所述第一绝缘层上方，且在正投影方向上与所述栅极对齐，所述第二绝缘层设置于所述多晶硅层上方，所述第三绝缘层设置于所述第二绝缘层上方，所述公共电极设置于所述第三绝缘层上方，所述第四绝缘层设置于所述公共电极上方，所述像素电极设置于所述第四绝缘层上方。
其中，所述源极、漏极及所述第二连接层设置于所述第三绝缘层内，且所述源极在正投影方向上与所述多晶硅层的一端部分重叠，所述漏极在正投影方向上所述多晶硅层的另一端部分重叠，所述第二连接层位于所述第一连接层上方，且在正投影方向上与所述第一连接层部分重叠。
其中，所述多晶硅层包括第一连接段、第二连接段及第三连接段，所述第一连接段与所述第三连接段相互平行间隔地跨越所述扫描线设置，所述第二连接段连接于所述第一连接段和第三连接段位于所述扫描线同一侧的两端之间，并与所述扫描线平行。
其中，所述第一连接层与所述栅极和所述扫描线位于同一图层，所述第二连接层与所述源极、漏极和所述数据线位于同一图层，所述第一连接层与所述栅极和扫描线在同一次制作工艺中同步形成，所述第二连接层与所述源极、漏极和所述数据线在同一次制作工艺中同步形成。
一种阵列基板，包括多条扫描线、多条数据线及多个像素区域，所述扫描线沿水平方向平行间隔设置，所述数据线沿垂直方向平行间隔设置，所述扫描线与所述数据线相互交叠形成所述像素区域，其中，所述阵列基板还包括用于连接所述像素区域的连接电极，所述连接电极包括第一连接层和第二连接层，所述第一连接层与所述扫描线位于同一图层，并与所述扫描线交叉设置，所述第一连接层在与所述扫描线的交叉处被隔断，所述第二连接层与所述数据线位于同一图层，并跨越所述扫描线设置，所述第一连接层在所述交叉处的两侧通 过第一过孔与所述第二连接层电性连接。
其中，所述第一连接层设置于所述数据线下方，并在被所述扫描线隔断处的两侧沿平行于所述扫描线的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端，所述第二连接层的两端在正投影方向上与所述连接端部分重叠，并通过所述第一过孔与所述连接端电性连接。
其中，所述阵列基板还包括多个薄膜晶体管、多个公共电极和多个像素电极，所述多个薄膜晶体管形成于所述扫描线与所述数据线的交叠处，每一所述薄膜晶体管包括栅极、多晶硅层、源极和漏极，所述栅极与所述扫描线电性连接，所述多晶硅层设置于所述栅极上方，所述源极和漏极设置于所述多晶硅层上方，并分别通过一第二过孔与所述多晶硅层电性连接，所述公共电极通过一第三过孔与所述第二连接层电性连接，所述像素电极通过一第三过孔及一第四过孔与所述漏极电性连接。
其中，所述阵列基板还包括基板及依次层叠设置于所述基板上的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述栅极与所述第一连接层间隔设置于所述基板上，所述第一绝缘层设置于所述栅极及第一连接层上方，所述多晶硅层设置于所述第一绝缘层上方，且在正投影方向上与所述栅极对齐，所述第二绝缘层设置于所述多晶硅层上方，所述第三绝缘层设置于所述第二绝缘层上方，所述公共电极设置于所述第三绝缘层上方，所述第四绝缘层设置于所述公共电极上方，所述像素电极设置于所述第四绝缘层上方。
其中，所述源极、漏极及所述第二连接层设置于所述第三绝缘层内，且所述源极在正投影方向上与所述多晶硅层的一端部分重叠，所述漏极在正投影方向上所述多晶硅层的另一端部分重叠，所述第二连接层位于所述第一连接层上方，且在正投影方向上与所述第一连接层部分重叠。
其中，所述多晶硅层包括第一连接段、第二连接段及第三连接段，所述第一连接段与所述第三连接段相互平行间隔地跨越所述扫描线设置，所述第二连接段连接于所述第一连接段和第三连接段位于所述扫描线同一侧的两端之间，并与所述扫描线平行。
其中，所述第一连接层与所述栅极和所述扫描线位于同一图层，所述第二连接层与所述源极、漏极和所述数据线位于同一图层，所述第一连接层与所述 栅极和扫描线在同一次制作工艺中同步形成，所述第二连接层与所述源极、漏极和所述数据线在同一次制作工艺中同步形成。
一种显示装置，包括阵列基板，其中，所述阵列基板包括多条扫描线、多条数据线及多个像素区域，所述扫描线沿水平方向平行间隔设置，所述数据线沿垂直方向平行间隔设置，所述扫描线与所述数据线相互交叠形成所述像素区域，其中，所述阵列基板还包括用于连接所述像素区域的连接电极，所述连接电极包括第一连接层和第二连接层，所述第一连接层与所述扫描线位于同一图层，并与所述扫描线交叉设置，所述第一连接层在与所述扫描线的交叉处被隔断，所述第二连接层与所述数据线位于同一图层，并跨越所述扫描线设置，所述第一连接层在所述交叉处的两侧通过第一过孔与所述第二连接层电性连接。
其中，所述第一连接层设置于所述数据线下方，并在被所述扫描线隔断处的两侧沿平行于所述扫描线的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端，所述第二连接层的两端在正投影方向上与所述连接端部分重叠，并通过所述第一过孔与所述连接端电性连接。
其中，所述阵列基板还包括多个薄膜晶体管、多个公共电极和多个像素电极，所述多个薄膜晶体管形成于所述扫描线与所述数据线的交叠处，每一所述薄膜晶体管包括栅极、多晶硅层、源极和漏极，所述栅极与所述扫描线电性连接，所述多晶硅层设置于所述栅极上方，所述源极和漏极设置于所述多晶硅层上方，并分别通过一第二过孔与所述多晶硅层电性连接，所述公共电极通过一第三过孔与所述第二连接层电性连接，所述像素电极通过一第三过孔及一第四过孔与所述漏极电性连接。
其中，所述阵列基板还包括基板及依次层叠设置于所述基板上的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述栅极与所述第一连接层间隔设置于所述基板上，所述第一绝缘层设置于所述栅极及第一连接层上方，所述多晶硅层设置于所述第一绝缘层上方，且在正投影方向上与所述栅极对齐，所述第二绝缘层设置于所述多晶硅层上方，所述第三绝缘层设置于所述第二绝缘层上方，所述公共电极设置于所述第三绝缘层上方，所述第四绝缘层设置于所述公共电极上方，所述像素电极设置于所述第四绝缘层上方。
其中，所述源极、漏极及所述第二连接层设置于所述第三绝缘层内，且所 述源极在正投影方向上与所述多晶硅层的一端部分重叠，所述漏极在正投影方向上所述多晶硅层的另一端部分重叠，所述第二连接层位于所述第一连接层上方，且在正投影方向上与所述第一连接层部分重叠。
其中，所述多晶硅层包括第一连接段、第二连接段及第三连接段，所述第一连接段与所述第三连接段相互平行间隔地跨越所述扫描线设置，所述第二连接段连接于所述第一连接段和第三连接段位于所述扫描线同一侧的两端之间，并与所述扫描线平行。
本发明所述像素结构，通过将所述第一连接层与所述栅极和扫描线在同一次制作工艺中同步形成，以及将所述第二连接层与所述源极、漏极和所述数据线在同一次制作工艺中同步形成，进一步通过所述第一过孔将所述第一连接层和所述第二连接层电性连接，形成用于连接所述像素区域的连接电极，从而无需单独增加一道或多道制作工艺来形成所述连接电极，简化了工艺流程，并能降低产生斑纹缺陷的风险，提升产品良率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例的像素结构的平面结构示意图。
图2是图1所示像素结构的剖面结构示意图。
图3是本发明第二实施例的阵列基板的平面结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为便于描述，这里可以使用诸如“在…之下”、“在…下面”、“下”、“在… 之上”、“上”等空间相对性术语来描述如图中所示的一个元件或特征与另一个(些)元件或特征的关系。可以理解，当一个元件或层被称为在另一元件或层“上”、“连接到”或“耦接到”另一元件或层时，它可以直接在另一元件或层上、直接连接到或耦接到另一元件或层，或者可以存在居间元件或层。相反，当一个元件被称为“直接在”另一元件或层上、“直接连接到”或“直接耦接到”另一元件或层时，不存在居间元件或层。
可以理解，这里所用的术语仅是为了描述特定实施例，并非要限制本发明。在这里使用时，除非上下文另有明确表述，否则单数形式“一”和“该”也旨在包括复数形式。进一步地，当在本说明书中使用时，术语“包括”和/或“包含”表明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、组件和/或其组合的存在或增加。
除非另行定义，这里使用的所有术语(包括技术术语和科学术语)都具有本发明所属领域内的普通技术人员所通常理解的相同含义。将进一步理解，诸如通用词典中所定义的术语，否则应当被解释为具有与它们在相关领域的语境中的含义相一致的含义，而不应被解释为理想化或过度形式化的意义，除非在此明确地如此定义。
请参阅图1，本发明提供一种像素结构100，其通过利用现有的栅极金属和源/漏极金属来制作用于连接像素区域的连接电极，以简化制程、降低产生斑纹缺陷的风险、提升产品良率。
所述像素结构100包括扫描线110、数据线130、像素区域150以及用于连接所述像素区域150的连接电极50。所述扫描线110为栅极扫描线，其沿水平方向相互平行间隔设置，所述数据线130沿垂直方向相互平行间隔设置，相邻的两条所述扫描线110与相邻的两条所述数据线130相互交叠，从而形成一个像素区域150。
所述连接电极50包括第一连接层51和第二连接层53。所述第一连接层51与所述扫描线110位于同一图层，所述第二连接层53与所述数据线130位于同一图层。所述第一连接层51与所述扫描线110相互交叉设置，并在与所述扫描线110的交叉处被所述扫描线110隔断。所述第二连接层53与所述数 据线130平行，并跨越所述扫描线110设置。所述第一连接层51在所述交叉处的两侧通过第一过孔H1与所述第二连接层53电性连接，即，所述第一连接层51在所述扫描线110的两侧通过该第一过孔H1与所述第二连接层53电性连接，从而使得位于不同像素区域150的所述第一连接层51之间相互电性连接，形成所述连接电极50，以连接不同的像素区域150。
在本实施例中，所述第一连接层51设置于所述数据线130下方，并在被所述扫描线110隔断处的两侧沿平行于所述扫描线110的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端511。所述第二连接层53的两端在正投影方向上与所述第一连接层51被所述扫描线110隔断处两侧的连接端511部分重叠，并通过所述第一过孔H1与所述连接端511电性连接。
请一并参阅图2，图2为图1所示像素结构100的部分剖面结构示意图。需要说明的是，图2所示的剖面结构示意图并非严格按照图1所述像素结构100的平面结构示意图中某一切剖方向进行切剖而得到，因此，图2仅用于结合图1以进一步解释所述像素结构100的内部结构。
所述像素结构100还包括基板10及依次层叠设置于所述基板10上的第一绝缘层11、第二绝缘层13、第三绝缘层15和第四绝缘层17，以及薄膜晶体管20、公共电极30和像素电极40。
所述薄膜晶体管20包括栅极21、多晶硅层22、源极23和漏极25。所述栅极21与所述连接电极50的第一连接层51间隔设置于所述基板10上。所述第一绝缘层11设置于所述栅极21及第一连接层51上方。所述多晶硅层22设置于所述第一绝缘层11上方，且在正投影方向上与所述栅极21大致对齐。所述第二绝缘层13设置于所述多晶硅层22上，并贴紧该多晶硅层22。所述第三绝缘层15设置于所述第二绝缘层13上方。所述源极23、漏极25及所述连接电极50的第二连接层53设置于所述第三绝缘层15内。所述源极23和漏极25位于所述多晶硅层22上方，且所述源极23在正投影方向上与所述栅极21及多晶硅层22的一端部分重叠，所述漏极25在正投影方向上所述栅极21及多晶硅层22的另一端部分重叠。所述源极23和漏极25分别通过一第二过孔H2与所述多晶硅层22的相对两端电性连接。所述第二连接层53位于所述第一连接层51上方，且在正投影方向上与所述第一连接层51部分重叠。所述第 二连接层53两侧分别通过一第一过孔H1与所述第一连接层51电性连接。
所述公共电极30设置于所述第三绝缘层15上方，并通过一第三过孔H3与所述第二连接层53电性连接。所述第四绝缘层17设置于所述公共电极30上方。所述像素电极40设置于所述第四绝缘层17上方，并通过一贯穿所述第四绝缘层17的第四过孔H4和贯穿部分第三绝缘层15的第三过孔H3与所述薄膜晶体管20的漏极25电性连接。
请再次参阅图1，所述薄膜晶体管20形成于所述扫描线110与所述数据线130的交叠处。所述栅极21与所述扫描线110位于同一图层，并与所述扫描线110电性连接。所述多晶硅层22大致呈“ㄩ”形，其包括第一连接段221、第二连接段223及第三连接段225。所述第一连接段221与所述第三连接段225相互平行间隔地跨越所述扫描线110设置。所述第二连接段223连接于所述第一连接段221和第三连接段225位于所述扫描线110同一侧的两端之间，并与所述扫描线110平行。所述源极23、漏极25分别设置于所述第一连接段221和第三连接段225远离所述第二连接段223一端的上方(即，所述源极23和漏极25分别设置于所述第一连接段221和第三连接段225相对所述扫描线110另一侧的两端)，并分别通过所述第二过孔H2与所述第一连接段221和第三连接段225电性连接。所述源极23与所述数据线130位于同一图层，并与所述数据线130电性连接。所述漏极25通过所述第三过孔H3和第四过孔H4与所述像素电极(图未示)电性连接。所述公共电极30通过所述第三过孔H3与所述第二连接层53电性连接。可以理解的是，在本申请的图1中，由于源极23与第二过孔H2的位置重叠，因此二者用一条引线表示，同理，图1中栅极21与扫描线110用一条引线表示，漏极25与第二过孔H2用一条引线表示，像素区域150与公共电极30也用一条引线表示。
可以理解，所述第一连接层51与所述栅极21和所述扫描线110位于同一图层，所述第二连接层53与所述源极23、漏极25和所述数据线130位于同一图层。因此，所述第一连接层51可以与所述栅极21和扫描线110在同一次制作工艺中同步形成，所述第二连接层53可以与所述源极23、漏极25和所述数据线130在同一次制作工艺中同步形成。进一步地，通过所述第一过孔H1将所述第一连接层51和所述第二连接层53电性连接，形成用于连接所述 像素区域150的连接电极50，从而无需单独增加一道或多道制作工艺来形成所述连接电极50，简化了工艺流程。
请参阅图3，本发明第二实施例提供一应用图1及图2所示的像素结构100的阵列基板200。所述阵列基板200包括多条扫描线210、多条数据线230及多个像素区域250。所述多条扫描线210为栅极扫描线，其沿水平方向相互平行间隔设置，所述多条数据线230沿垂直方向相互平行间隔设置，相邻的两条所述扫描线210与相邻的两条所述数据线230相互交叠，从而形成一个像素区域250。
所述阵列基板200还包括多条用于连接所述像素区域250的连接电极50。所述连接电极50包括第一连接层51和第二连接层53。所述第一连接层51与所述扫描线210位于同一图层，所述第二连接层53与所述数据线230位于同一图层。所述第一连接层51与所述扫描线210相互交叉设置，并在与所述扫描线210的交叉处被所述扫描线210隔断。所述第二连接层53与所述数据线230平行，并跨越所述扫描线210设置。所述第一连接层51在所述交叉处的两侧通过第一过孔H1与所述第二连接层53电性连接，即，所述第一连接层51在所述扫描线210的两侧通过该第一过孔H1与所述第二连接层53电性连接，从而使得位于不同像素区域250的所述第一连接层51之间相互电性连接，形成所述连接电极50，以连接不同像素区域250。
在本实施例中，所述第一连接层51设置于所述数据线230下方，并在被所述扫描线210隔断处的两侧沿平行于所述扫描线210的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端511。所述第二连接层53的两端在正投影方向上与所述第一连接层51被所述扫描线210隔断处两侧的连接端511部分重叠，并通过所述第一过孔H1与所述连接端511电性连接。
所述阵列基板200还包括多个薄膜晶体管T、多个公共电极Vcom及多个像素电极(图未示)。所述多个薄膜晶体管T形成于所述扫描线210与所述数据线230交叠处。每一所述薄膜晶体管T包括栅极g、多晶硅层p、源极s和漏极d。，所述栅极g与所述扫描线210位于同一图层，并与所述扫描线210电性连接。所述多晶硅层p大致呈“ㄩ”形，其包括第一连接段p1、第二连接段p3及第三连接段p5。所述第一连接段p1与所述第三连接段p5相互平行 间隔地跨越所述扫描线210设置。所述第二连接段p3连接于所述第一连接段p1和第三连接段p5位于所述扫描线210同一侧的两端之间，并与所述扫描线210平行。所述源极s、漏极d分别设置于所述第一连接段p1和第三连接段p5远离所述第二连接段p3一端的上方(即，所述源极s和漏极d分别设置于所述第一连接段p1和第三连接段p3相对所述扫描线210另一侧的两端)，并分别通过一第二过孔H2与所述第一连接段p1和第三连接段p5电性连接。所述公共电极Vcom通过一第三过孔H3与所述第二连接层53电性连接。所述源极s与所述数据线230位于同一图层，并与所述数据线230电性连接。所述漏极d通过一第三过孔H3及一第四过孔H4与所述像素电极(图未示)电性连接。可以理解的是，在本申请的图3中，由于源极s与第二过孔H2的位置重叠，因此二者用一条引线表示，同理，图1中栅极g与扫描线210用一条引线表示，漏极d与第二过孔H2用一条引线表示，像素区域250与公共电极Vcom也用一条引线表示。
可以理解，所述第一连接层51与所述栅极g和所述扫描线210位于同一图层，所述第二连接层53与所述源极g、漏极d和所述数据线230位于同一图层。因此，所述第一连接层51可以与所述栅极g和扫描线210在同一次制作工艺中同步形成，所述第二连接层53可以与所述源极s、漏极d和所述数据线230在同一次制作工艺中同步形成。进一步地，通过所述第一过孔H1将所述第一连接层51和所述第二连接层53电性连接，形成用于连接所述像素区域250的连接电极50，从而无需单独增加一道或多道制作工艺来形成所述连接电极50，简化了制造所述阵列基板200的工艺流程。
另，本发明还提供一种应用所述阵列基板200的显示装置，通过将所述第一连接层51与所述栅极g和扫描线210在同一次制作工艺中同步形成，并将所述第二连接层53与所述源极s、漏极d和所述数据线230在同一次制作工艺中同步形成。进而通过所述第一过孔H1将所述第一连接层51和所述第二连接层53电性连接，形成用于连接所述像素区域250的连接电极50，从而无需单独增加一道或多道制作工艺来形成所述连接电极50，简化了制造所述显示装置的工艺流程，并能降低产生斑纹缺陷的风险，提升产品良率。
以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明 之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (20)

  1. 一种像素结构，包括扫描线、数据线及像素区域，所述扫描线沿水平方向平行间隔设置，所述数据线沿垂直方向平行间隔设置，所述扫描线与所述数据线相互交叠形成所述像素区域，其中，所述像素结构还包括用于连接所述像素区域的连接电极，所述连接电极包括第一连接层和第二连接层，所述第一连接层与所述扫描线位于同一图层，并与所述扫描线交叉设置，所述第一连接层在与所述扫描线的交叉处被隔断，所述第二连接层与所述数据线位于同一图层，并跨越所述扫描线设置，所述第一连接层在所述交叉处的两侧通过第一过孔与所述第二连接层电性连接。
  2. 如权利要求1所述的像素结构，其中，所述第一连接层设置于所述数据线下方，并在被所述扫描线隔断处的两侧沿平行于所述扫描线的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端，所述第二连接层的两端在正投影方向上与所述连接端部分重叠，并通过所述第一过孔与所述连接端电性连接。
  3. 如权利要求1所述的像素结构，其中，所述像素结构还包括薄膜晶体管、公共电极和像素电极，所述薄膜晶体管形成于所述扫描线与所述数据线的交叠处，所述薄膜晶体管包括栅极、多晶硅层、源极和漏极，所述栅极与所述扫描线电性连接，所述多晶硅层设置于所述栅极上方，所述源极和漏极设置于所述多晶硅层上方，并分别通过一第二过孔与所述多晶硅层电性连接，所述公共电极通过一第三过孔与所述第二连接层电性连接，所述像素电极通过一第三过孔及一第四过孔与所述漏极电性连接。
  4. 如权利要求3所述的像素结构，其中，所述像素结构还包括基板及依次层叠设置于所述基板上的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述栅极与所述第一连接层间隔设置于所述基板上，所述第一绝缘层设置于所述栅极及第一连接层上方，所述多晶硅层设置于所述第一绝缘层上方，且在正投影方向上与所述栅极对齐，所述第二绝缘层设置于所述多晶硅层上方，所述第三绝缘层设置于所述第二绝缘层上方，所述公共电极设置于所述第三绝缘层上方，所述第四绝缘层设置于所述公共电极上方，所述像素电极设置于所 述第四绝缘层上方。
  5. 如权利要求4所述的像素结构，其中，所述源极、漏极及所述第二连接层设置于所述第三绝缘层内，且所述源极在正投影方向上与所述多晶硅层的一端部分重叠，所述漏极在正投影方向上所述多晶硅层的另一端部分重叠，所述第二连接层位于所述第一连接层上方，且在正投影方向上与所述第一连接层部分重叠。
  6. 如权利要求3所述的像素结构，其中，所述多晶硅层包括第一连接段、第二连接段及第三连接段，所述第一连接段与所述第三连接段相互平行间隔地跨越所述扫描线设置，所述第二连接段连接于所述第一连接段和第三连接段位于所述扫描线同一侧的两端之间，并与所述扫描线平行。
  7. 如权利要求3所述的像素结构，其中，所述第一连接层与所述栅极和所述扫描线位于同一图层，所述第二连接层与所述源极、漏极和所述数据线位于同一图层，所述第一连接层与所述栅极和扫描线在同一次制作工艺中同步形成，所述第二连接层与所述源极、漏极和所述数据线在同一次制作工艺中同步形成。
  8. 一种阵列基板，包括多条扫描线、多条数据线及多个像素区域，所述扫描线沿水平方向平行间隔设置，所述数据线沿垂直方向平行间隔设置，所述扫描线与所述数据线相互交叠形成所述像素区域，其中，所述阵列基板还包括用于连接所述像素区域的连接电极，所述连接电极包括第一连接层和第二连接层，所述第一连接层与所述扫描线位于同一图层，并与所述扫描线交叉设置，所述第一连接层在与所述扫描线的交叉处被隔断，所述第二连接层与所述数据线位于同一图层，并跨越所述扫描线设置，所述第一连接层在所述交叉处的两侧通过第一过孔与所述第二连接层电性连接。
  9. 如权利要求8所述的阵列基板，其中，所述第一连接层设置于所述数据线下方，并在被所述扫描线隔断处的两侧沿平行于所述扫描线的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端，所述第二连接层的两端在正投影方向上与所述连接端部分重叠，并通过所述第一过孔与所述连接端电性连接。
  10. 如权利要求8所述的阵列基板，其中，所述阵列基板还包括多个薄膜 晶体管、多个公共电极和多个像素电极，所述多个薄膜晶体管形成于所述扫描线与所述数据线的交叠处，每一所述薄膜晶体管包括栅极、多晶硅层、源极和漏极，所述栅极与所述扫描线电性连接，所述多晶硅层设置于所述栅极上方，所述源极和漏极设置于所述多晶硅层上方，并分别通过一第二过孔与所述多晶硅层电性连接，所述公共电极通过一第三过孔与所述第二连接层电性连接，所述像素电极通过一第三过孔及一第四过孔与所述漏极电性连接。
  11. 如权利要求10所述的阵列基板，其中，所述阵列基板还包括基板及依次层叠设置于所述基板上的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述栅极与所述第一连接层间隔设置于所述基板上，所述第一绝缘层设置于所述栅极及第一连接层上方，所述多晶硅层设置于所述第一绝缘层上方，且在正投影方向上与所述栅极对齐，所述第二绝缘层设置于所述多晶硅层上方，所述第三绝缘层设置于所述第二绝缘层上方，所述公共电极设置于所述第三绝缘层上方，所述第四绝缘层设置于所述公共电极上方，所述像素电极设置于所述第四绝缘层上方。
  12. 如权利要求11所述的阵列基板，其中，所述源极、漏极及所述第二连接层设置于所述第三绝缘层内，且所述源极在正投影方向上与所述多晶硅层的一端部分重叠，所述漏极在正投影方向上所述多晶硅层的另一端部分重叠，所述第二连接层位于所述第一连接层上方，且在正投影方向上与所述第一连接层部分重叠。
  13. 如权利要求10所述的阵列基板，其中，所述多晶硅层包括第一连接段、第二连接段及第三连接段，所述第一连接段与所述第三连接段相互平行间隔地跨越所述扫描线设置，所述第二连接段连接于所述第一连接段和第三连接段位于所述扫描线同一侧的两端之间，并与所述扫描线平行。
  14. 如权利要求10所述的阵列基板，其中，所述第一连接层与所述栅极和所述扫描线位于同一图层，所述第二连接层与所述源极、漏极和所述数据线位于同一图层，所述第一连接层与所述栅极和扫描线在同一次制作工艺中同步形成，所述第二连接层与所述源极、漏极和所述数据线在同一次制作工艺中同步形成。
  15. 一种显示装置，包括阵列基板，其中，所述阵列基板包括多条扫描线、 多条数据线及多个像素区域，所述扫描线沿水平方向平行间隔设置，所述数据线沿垂直方向平行间隔设置，所述扫描线与所述数据线相互交叠形成所述像素区域，其中，所述阵列基板还包括用于连接所述像素区域的连接电极，所述连接电极包括第一连接层和第二连接层，所述第一连接层与所述扫描线位于同一图层，并与所述扫描线交叉设置，所述第一连接层在与所述扫描线的交叉处被隔断，所述第二连接层与所述数据线位于同一图层，并跨越所述扫描线设置，所述第一连接层在所述交叉处的两侧通过第一过孔与所述第二连接层电性连接。
  16. 如权利要求15所述的显示装置，其中，所述第一连接层设置于所述数据线下方，并在被所述扫描线隔断处的两侧沿平行于所述扫描线的方向同向延伸一段距离，以在所述隔断处的两侧各形成一连接端，所述第二连接层的两端在正投影方向上与所述连接端部分重叠，并通过所述第一过孔与所述连接端电性连接。
  17. 如权利要求15所述的显示装置，其中，所述阵列基板还包括多个薄膜晶体管、多个公共电极和多个像素电极，所述多个薄膜晶体管形成于所述扫描线与所述数据线的交叠处，每一所述薄膜晶体管包括栅极、多晶硅层、源极和漏极，所述栅极与所述扫描线电性连接，所述多晶硅层设置于所述栅极上方，所述源极和漏极设置于所述多晶硅层上方，并分别通过一第二过孔与所述多晶硅层电性连接，所述公共电极通过一第三过孔与所述第二连接层电性连接，所述像素电极通过一第三过孔及一第四过孔与所述漏极电性连接。
  18. 如权利要求17所述的显示装置，其中，所述阵列基板还包括基板及依次层叠设置于所述基板上的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，所述栅极与所述第一连接层间隔设置于所述基板上，所述第一绝缘层设置于所述栅极及第一连接层上方，所述多晶硅层设置于所述第一绝缘层上方，且在正投影方向上与所述栅极对齐，所述第二绝缘层设置于所述多晶硅层上方，所述第三绝缘层设置于所述第二绝缘层上方，所述公共电极设置于所述第三绝缘层上方，所述第四绝缘层设置于所述公共电极上方，所述像素电极设置于所述第四绝缘层上方。
  19. 如权利要求18所述的显示装置，其中，所述源极、漏极及所述第二 连接层设置于所述第三绝缘层内，且所述源极在正投影方向上与所述多晶硅层的一端部分重叠，所述漏极在正投影方向上所述多晶硅层的另一端部分重叠，所述第二连接层位于所述第一连接层上方，且在正投影方向上与所述第一连接层部分重叠。
  20. 如权利要求17所述的显示装置，其中，所述多晶硅层包括第一连接段、第二连接段及第三连接段，所述第一连接段与所述第三连接段相互平行间隔地跨越所述扫描线设置，所述第二连接段连接于所述第一连接段和第三连接段位于所述扫描线同一侧的两端之间，并与所述扫描线平行。
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WO2018062035A1 (ja) * 2016-09-29 2018-04-05 シャープ株式会社 アクティブマトリックス基板、表示パネル、およびそれを備えた表示装置
CN107092394B (zh) * 2017-04-26 2020-06-30 京东方科技集团股份有限公司 触控基板及其制作方法、触摸屏
CN107481936A (zh) * 2017-08-07 2017-12-15 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管及其制备方法
CN110189624A (zh) * 2018-02-23 2019-08-30 群创光电股份有限公司 显示设备
CN108376687B (zh) * 2018-03-30 2020-05-19 武汉华星光电技术有限公司 阵列基板及其制备方法、内嵌式触摸屏
CN111240084B (zh) * 2020-03-25 2022-02-22 厦门天马微电子有限公司 显示面板及显示装置
CN114787701B (zh) * 2020-09-17 2023-12-08 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN117438430A (zh) 2022-07-12 2024-01-23 京东方科技集团股份有限公司 显示基板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090147203A1 (en) * 2004-02-10 2009-06-11 Nec Corporation Active matrix type liquid crystal display having aluminum and silver metal layers
US20130057793A1 (en) * 2010-05-14 2013-03-07 Sharp Kabushiki Kaisha Thin-film transistor substrate and liquid-crystal display device provided with the same
CN103926765A (zh) * 2013-04-22 2014-07-16 上海中航光电子有限公司 一种双栅极扫描线驱动的像素结构及其制作方法
CN104503172A (zh) * 2014-12-19 2015-04-08 深圳市华星光电技术有限公司 阵列基板及显示装置
CN104505391A (zh) * 2014-12-23 2015-04-08 上海天马微电子有限公司 一种阵列基板及其制造方法和显示面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3229066A1 (en) * 2005-12-05 2017-10-11 Semiconductor Energy Laboratory Co., Ltd. Transflective liquid crystal display with a horizontal electric field configuration

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090147203A1 (en) * 2004-02-10 2009-06-11 Nec Corporation Active matrix type liquid crystal display having aluminum and silver metal layers
US20130057793A1 (en) * 2010-05-14 2013-03-07 Sharp Kabushiki Kaisha Thin-film transistor substrate and liquid-crystal display device provided with the same
CN103926765A (zh) * 2013-04-22 2014-07-16 上海中航光电子有限公司 一种双栅极扫描线驱动的像素结构及其制作方法
CN104503172A (zh) * 2014-12-19 2015-04-08 深圳市华星光电技术有限公司 阵列基板及显示装置
CN104505391A (zh) * 2014-12-23 2015-04-08 上海天马微电子有限公司 一种阵列基板及其制造方法和显示面板

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