WO2016201781A1 - 一种实现时序测试的方法及装置 - Google Patents

一种实现时序测试的方法及装置 Download PDF

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WO2016201781A1
WO2016201781A1 PCT/CN2015/087857 CN2015087857W WO2016201781A1 WO 2016201781 A1 WO2016201781 A1 WO 2016201781A1 CN 2015087857 W CN2015087857 W CN 2015087857W WO 2016201781 A1 WO2016201781 A1 WO 2016201781A1
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ddr
reference voltage
timing test
value
voltage value
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PCT/CN2015/087857
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French (fr)
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李为龙
陈之光
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

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  • This document relates to, but is not limited to, dynamic memory testing techniques, and more particularly to a method and apparatus for implementing timing testing.
  • Double Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), first proposed by Samsung in 1996, by Nippon Electric, Mitsubishi, Fujitsu, Toshiba, Hitachi, Texas Instruments, The memory specifications agreed between Samsung and Hyundai Eight companies. Since this memory can perform data processing on both the rising and falling edges of the clock signal, it can make the data transfer rate twice that of synchronous dynamic random access memory (SDRAM).
  • SDRAM synchronous dynamic random access memory
  • the DDR addressing and control signals are the same as SDRAM and are only transmitted on the rising edge of the clock.
  • the core frequency of the DDR is very high; in the case of DDR3, the current mainstream core frequency is 400 MHz to 800 MHz.
  • the core frequency is high, the data transmission rate is correspondingly improved, and the high rate affects the test of the timing signal (referred to as the timing test).
  • the timing test since the DDR data reading and writing is performed on the line in both directions, how to separate the reading and writing will be very difficult.
  • amplitude separation method amplitude separation method
  • preamble separation method preamble separation method
  • phase separation method there are three main methods for DDR read/write separation.
  • the amplitude separation method mainly uses line attenuation to distinguish the reading and writing of data lines, and the read/write amplitude is in the line.
  • the difference between the short occasions is very small, and it is difficult to distinguish;
  • the preamble separation method mainly uses the difference between the read and write preamble width requirements in the DDR specification, but the DDR specification only briefly describes the leading width, and does not Clearly define the width and size, the actual test separation is difficult;
  • the phase separation method is mainly based on the DDR data read and write, DDR data latch (DQS, Data Strobe) and DDR data (DQ) phase difference to distinguish between reading and writing, DDR specification It is stipulated that DQS and DQ are in phase when DDR is written.
  • DDR When DDR is read, DQS and DQ are separated by a quarter clock cycle. In theory, this method can be read and written 100%, but it needs to capture a large amount of data. Analysis, very dependent on the oscilloscope The business capabilities of the pieces and testers.
  • BGA ball grid array
  • the design uses a back-to-back layout, through the inner layer routing, often can not find test points for probe point testing.
  • the application number is “201420634930.8”
  • the Chinese patent with the invention name “embedded single board DDR particle signal test fixture” can solve the problem that the test point is difficult to spot test, but the fixture itself is very large, in practical application. It will take up a lot of space and should not be used for high-density veneers.
  • Embodiments of the present invention provide a method and apparatus for implementing timing testing to solve the technical problem of how to improve the working efficiency of the timing test.
  • An embodiment of the present invention provides a method for implementing a timing test, including:
  • determining whether the DDR meets the timing test requirements includes:
  • the maximum reference voltage is greater than a maximum required value of the timing test, and when the minimum reference voltage is less than a minimum required value of the timing test, determining that the DDR meets the timing test requirement;
  • the maximum reference voltage is less than or equal to the maximum required value of the timing test, or the minimum reference voltage is greater than or equal to the minimum required value of the timing test, it is determined that the DDR does not meet the timing test requirement.
  • the method further includes:
  • the digital-to-analog converter DAC through the reference is the DDR output voltage; the voltage obtained by sampling the DDR through the analog data converter ADC of the reference; the voltage obtained by sampling the DDR is corrected by the ADC for the DDR output voltage, and the output is obtained.
  • the standard reference voltage of DDR is the DDR output voltage; the voltage obtained by sampling the DDR through the analog data converter ADC of the reference; the voltage obtained by sampling the DDR is corrected by the ADC for the DDR output voltage, and the output is obtained.
  • the standard reference voltage of DDR is the standard reference voltage of DDR.
  • the maximum required value of the timing test is 1.1 times the standard reference voltage
  • the minimum required value of the timing test is 0.9 times the standard reference voltage.
  • the standard reference voltage that is biased up or down to the DDR includes:
  • the standard reference voltage output to the DDR is pulled up or down according to the determined unit step size.
  • the present application further provides an apparatus for implementing a timing test, including: a partial pull acquisition unit and a determining unit; wherein
  • the pull-pull acquisition unit is configured to pull the output to the standard reference voltage of the DDR for timing test until the DDR is abnormal, and the current voltage value is taken as the maximum reference voltage value; the downward bias is output to the standard reference voltage of the DDR for the timing test. Until the DDR is abnormal, the current voltage value is taken as the minimum reference voltage value;
  • the determining unit is configured to determine whether the DDR meets the timing test requirement according to the maximum reference voltage value and the minimum reference voltage value.
  • the determining unit is specifically configured to
  • the maximum reference voltage is greater than a maximum required value of the timing test, and when the minimum reference voltage is less than a minimum required value of the timing test, determining that the DDR meets the timing test requirement;
  • the maximum reference voltage is less than or equal to the maximum required value of the timing test, or the minimum reference voltage is greater than or equal to the minimum required value of the timing test, it is determined that the DDR does not meet the timing test requirement.
  • the device further includes a reference voltage source unit configured to disconnect the voltage input provided by the DDR system or the board for the DDR;
  • the maximum required value of the timing test is 1.1 times the standard reference voltage
  • the minimum required value of the timing test is 0.9 times the standard reference voltage.
  • the bias acquisition unit is configured to: pull the output to the standard reference voltage of the DDR of the timing test according to the determined unit step length, and when the DDR is abnormal, use the current voltage value as the maximum reference voltage value;
  • the unit step length is pulled downward to the standard reference voltage of the DDR of the timing test until the DDR is abnormal, and the current voltage value is taken as the minimum reference voltage value;
  • the determined unit step size is determined based on the DDR standard reference voltage.
  • the application also provides a computer storage medium having stored therein computer executable instructions for performing the methods described above.
  • the technical solution of the present application includes: upwardly biasing the standard reference voltage of the DDR outputted to the timing test until the DDR abnormality, using the current voltage value as the maximum reference voltage value; and outputting the downward bias to the timing test.
  • the standard reference voltage of DDR when the DDR is abnormal, the current voltage value is taken as the minimum reference voltage value; according to the maximum reference voltage value and the minimum reference voltage value, it is determined whether the DDR meets the timing test requirement.
  • the method according to the embodiment of the present invention determines the range of the DDR standard reference voltage to be converted according to the maximum reference voltage value and the minimum reference voltage value, and in turn determines that the DDR meets the timing test requirement, thereby avoiding difficulty in reading and writing separation or having an option for the oscilloscope and
  • the reliance of testers' business capabilities and the impact of test points that are difficult to test on timing tests improve the efficiency of timing tests.
  • FIG. 1 is a flowchart of a method for implementing a timing test according to an embodiment of the present invention
  • FIG. 2 is a structural diagram of an apparatus for implementing a timing test according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a reference voltage source unit according to an application example of the present invention.
  • FIG. 4 is a flow chart of a method for applying an example of the present invention.
  • the signal integrity and timing of the DDR are closely related to the DDR standard reference voltage.
  • the range of allowable conversions can in turn determine if the DDR timing test meets the requirements.
  • FIG. 1 is a flowchart of a method for implementing a timing test according to an embodiment of the present invention. As shown in FIG. 1 , the method includes:
  • Step 100 The device that implements the timing test pulls the output to the standard reference voltage of the DDR of the timing test until the DDR is abnormal, and uses the current voltage value as the maximum reference voltage value; and outputs the downward bias to the standard reference of the DDR for the timing test. Voltage, until the DDR is abnormal, the current voltage value is taken as the minimum reference voltage value;
  • a message display is generally performed in the system, for example, the display cannot be printed, and by obtaining such a message, the DDR abnormality can be determined.
  • the specific implementation of how to obtain such a message is a common technical means for those skilled in the art, and will not be described herein.
  • the standard reference voltage that is output to the DDR up or down is:
  • the standard reference voltage output to the DDR is pulled up or down according to the determined unit step size.
  • the determination of the unit step size of the upward or downward bias is mainly determined based on the standard reference voltage of the timing test; in general, the maximum requirement value of the timing test is 1.1 times of the standard reference voltage; the minimum required value of the timing test It is 0.9 times the standard reference voltage. That is, the standard reference voltage of the bias is 10% as the deflection range, and after the standard reference voltage is multiplied by 10%, the obtained value is divided into two segments to two or more segments to obtain the unit step size, which is specifically set in the art. The usual technical means of personnel will not be repeated here.
  • this step also includes:
  • the digital-to-analog converter (DAC) through the reference is the DDR output voltage; the voltage obtained by sampling the DDR through the analog data converter (ADC) of the reference; based on the sampled DDR The obtained voltage is corrected by the ADC for the DDR output voltage to obtain a standard reference voltage that is output to the DDR.
  • ADC analog data converter
  • Step 101 The device implementing the timing test determines whether the DDR meets the timing test requirement according to the maximum reference voltage value and the minimum reference voltage value.
  • determining whether the DDR meets the timing test requirements includes:
  • the maximum reference voltage is greater than the maximum required value of the timing test, and when the minimum reference voltage is less than the minimum required value of the timing test, it is determined that the DDR meets the timing test requirement;
  • the maximum reference voltage is less than or equal to the maximum required value of the timing test, or the minimum reference voltage is greater than or equal to the minimum required value of the timing test, it is determined that the DDR does not meet the timing test requirements.
  • the maximum required value of the timing test is 1.1 times the standard reference voltage
  • the minimum required value for timing testing is 0.9 times the standard reference voltage.
  • the range of the DDR standard reference voltage is allowed to be converted, which in turn determines that the DDR meets the timing test requirement, thereby avoiding difficulty in reading and writing separation or existing options and tests for the oscilloscope.
  • the reliance on the business capability of the personnel and the impact of the test points that are difficult to test on the timing test improve the efficiency of the timing test.
  • the application also provides a computer storage medium having stored therein computer executable instructions for performing the methods described above.
  • FIG. 2 is a structural diagram of an apparatus for implementing a timing test according to an embodiment of the present invention. As shown in FIG. 2, the method includes: a partial pull acquisition unit and a determining unit;
  • the pull-pull acquisition unit is configured to pull the output to the standard reference voltage of the DDR for timing test until the DDR is abnormal, and the current voltage value is taken as the maximum reference voltage value; the downward bias is output to the standard reference voltage of the DDR for the timing test. Until the DDR is abnormal, the current voltage value is taken as the minimum reference voltage value;
  • the bias pull unit is configured to pull the output to the standard reference voltage of the DDR of the timing test according to the determined unit step length, and when the DDR is abnormal, use the current voltage value as the maximum reference voltage value; according to the determined unit step size
  • the lower bias is output to the standard reference voltage of the DDR of the timing test until the DDR is abnormal, and the current voltage value is taken as the minimum reference voltage value;
  • the determined unit step size is determined based on the DDR standard reference voltage.
  • the determining unit is configured to determine whether the DDR meets the timing test requirement according to the maximum reference voltage value and the minimum reference voltage value.
  • the determining unit is specifically set to,
  • the maximum reference voltage is greater than the maximum required value of the timing test, and when the minimum reference voltage is less than the minimum required value of the timing test, it is determined that the DDR meets the timing test requirement;
  • the maximum reference voltage is less than or equal to the maximum required value of the timing test, or the minimum reference voltage is greater than or equal to the minimum required value of the timing test, it is determined that the DDR does not meet the timing test requirements.
  • the maximum requirement for timing testing is 1.1 times the standard reference voltage
  • the minimum required value for timing testing is 0.9 times the standard reference voltage.
  • the device of the embodiment of the present invention further includes a reference voltage source unit configured to disconnect the voltage input provided by the DDR system or the board for the DDR;
  • the DAC is the output voltage through the DAC; the voltage obtained by sampling the DDR by the ADC; based on the voltage obtained by sampling the DDR, the DDR output voltage is corrected by the ADC to obtain a standard reference voltage output to the DDR.
  • FIG. 3 is a schematic diagram of the reference voltage source unit according to the application example of the present invention.
  • the reference voltage module After the reference voltage module outputs the output voltage to the DDR through the DAC, the ADC samples the voltage on the DDR to obtain an accurate voltage value, and obtains the accurate voltage value obtained by sampling, and outputs the DAC to the DDR.
  • the voltage is adjusted until the ADC sample obtains the voltage value of the DDR as a standard reference voltage, and the standard reference voltage value is sent to the reference voltage module, and the reference voltage module outputs the standard reference voltage to the DDR through the DAC.
  • FIG. 4 is a flowchart of a method for applying an example of the present invention. As shown in FIG. 4, the method includes:
  • Step 400 Pull the output to the DDR of the timing test according to the determined unit step size. Quasi-reference voltage, when the DDR abnormality occurs, the current voltage value is taken as the maximum reference voltage value;
  • Step 401 Output a standard reference voltage of the DDR to the timing test according to the determined unit step size, and when the DDR abnormality occurs, use the current voltage value as the minimum reference voltage value;
  • step 400 and step 401 can be reversed.
  • Step 402 Determine, according to the maximum reference voltage value and the minimum reference voltage value, whether the DDR meets the timing test requirement.
  • the maximum reference voltage is greater than the maximum required value of the timing test, and when the minimum reference voltage is less than the minimum required value of the timing test, it is determined that the DDR meets the timing test requirement;
  • the maximum reference voltage is less than or equal to the maximum required value of the timing test, or the minimum reference voltage is greater than or equal to the minimum required value of the timing test, it is determined that the DDR does not meet the timing test requirements.
  • the maximum requirement for timing testing is 1.1 times the standard reference voltage
  • the minimum required value for the timing test is 0.9 times the standard reference voltage.
  • all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
  • the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
  • Each device/function module/function unit in the above embodiment is implemented in the form of a software function module. And when sold or used as a stand-alone product, it can be stored on a computer readable storage medium.
  • the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • the embodiment of the invention avoids the difficulty of reading and writing separation or the dependence on the oscilloscope's own options and the tester's business capability, and the problem that the test point is difficult to test, which affects the timing test, and improves the working efficiency of the time series test. .

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Abstract

一种实现时序测试的方法及装置，包括：向上偏拉输出至时序测试的时序测试的双倍速率同步动态随机存储器(DDR)的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。上述技术方案根据最大参考电压值和最小参考电压值在DDR标准参考电压允许变换的范围，反过来确定DDR满足时序测试要求，避免了由于读写分离困难或存在对示波器自带选件和测试人员的业务能力的依赖，以及测试点不易点测的问题对时序测试造成的影响，提高了时序测试的工作效率。

Description

一种实现时序测试的方法及装置 技术领域
本文涉及但不限于动态存储器测试技术，尤指一种实现时序测试的方法及装置。
背景技术
双倍速率同步动态随机存储器(DDR SDRAM，Double Date Rate Synchronous Dynamic Random Access Memory，简称为DDR)，最早是由三星公司于1996年提出，由日本电气、三菱、富士通、东芝、日立、德州仪器、三星及现代八家公司协议订立的内存规格。由于这种存储器在时钟信号的上升沿与下降沿均可进行数据处理，因此它可以使数据传输率达到同步动态随机存储器(SDRAM)的两倍。而DDR的寻址与控制信号则与SDRAM相同，仅在时钟上升沿传送。
由于在时钟信号的上升沿与下降沿均可进行数据处理，因此DDR的核心频率很高；以DDR3为例，目前主流的核心频率为400MHz到800MHz。核心频率高时，数据传输速率相应的也得到提高，高速率影响了时序信号的测试(简称时序测试)。其中，时序测试时，由于DDR数据读写是在线路上双向进行的，如何分离读写会很困难。目前，DDR读写分离方法主要有三种方法：幅度分离法、前导码分离法和相位分离法；其中，幅度分离法主要是利用线路衰减来区分数据线的读与写，读写幅度在走线较短的场合差异很小，不易进行区分；前导码分离法主要利用DDR规格书中对读与写前导码宽度要求的不同进行区分，但DDR规格书只对前导宽度进行了简要说明，并未明确定义宽度大小，实际测试分离困难；相位分离法主要是根据DDR数据读写时，DDR的数据锁存(DQS，Data Strobe)与DDR的数据(DQ)的相位差来区分读写，DDR规范规定，DDR写操作时，DQS与DQ同相位，DDR读操作时，DQS与DQ相伴相差四分之一时钟周期，理论上该方法可以百分之百地区分读写，但区分读写需要抓取大量数据进行分析，非常依赖示波器自带选 件和测试人员的业务能力。另外，由于DDR采用球栅阵列(BGA)结构的印制电路板封装，设计中采用背靠背布局，通过内层走线，进行时序测试时常找不到用于探头点测的测试点。申请号为“201420634930.8”，发明名称为“嵌入式单板的DDR颗粒信号测试治具”的中国专利，虽然可以解决测试点不易点测的问题，但是该治具本身很大，在实际应用中，会占据很大空间，对于高密度单板来说，不宜使用。
综上所述，由于读写分离困难或存在对示波器自带选件和测试人员的业务能力的依赖，以及测试点不易点测的问题，影响了时序测试的工作效率。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供一种实现时序测试的方法及装置，以解决如何提高时序测试的工作效率的技术问题。
本发明实施例提供了一种实现时序测试的方法，包括：
向上偏拉输出至时序测试的双倍速率同步动态随机存储器DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。
可选地，确定DDR是否满足时序测试要求包括：
所述最大参考电压大于时序测试的最大要求值，和所述最小参考电压小于时序测试的最小要求值时，确定DDR满足时序测试要求；
所述最大参考电压小于或等于时序测试的最大要求值，或所述最小参考电压大于或等于时序测试的最小要求值时，确定DDR不满足时序测试要求。
可选地，该方法之前还包括：
断开DDR所在系统或单板为DDR提供的电压输入；
通过基准电压源的数字模拟转换器DAC为DDR输出电压；通过基准电压源的模拟数据转换器ADC采样DDR获得的电压；基于采样DDR获得的电压，通过ADC为DDR输出电压进行校正，获得输出至DDR的所述标准参考电压。
可选地，所述时序测试的最大要求值为所述标准参考电压的1.1倍；
所述时序测试的最小要求值为所述标准参考电压的0.9倍。
可选地，向上或向下偏拉输出至DDR的标准参考电压包括：
根据DDR标准参考电压确定向上或向下偏拉的单位步长；
根据确定的单位步长向上或向下偏拉输出至DDR的标准参考电压。
另一方面，本申请还提供一种实现时序测试的装置，包括：偏拉获取单元和确定单元；其中，
偏拉获取单元，设置为向上偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
确定单元，设置为根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。
可选地，确定单元具体是设置为，
所述最大参考电压大于时序测试的最大要求值，和所述最小参考电压小于时序测试的最小要求值时，确定DDR满足时序测试要求；
所述最大参考电压小于或等于时序测试的最大要求值，或所述最小参考电压大于或等于时序测试的最小要求值时，确定DDR不满足时序测试要求。
可选地，该装置还包括基准电压源单元，设置为断开DDR所在系统或单板为DDR提供的电压输入；
通过DAC为DDR输出电压；通过ADC采样DDR获得的电压；基于采样DDR获得的电压，通过ADC为DDR输出电压进行校正，获得输出至DDR的所述标准参考电压。
可选地，所述时序测试的最大要求值为所述标准参考电压的1.1倍；
所述时序测试的最小要求值为所述标准参考电压的0.9倍。
可选地，偏拉获取单元具体是设置为，根据确定的单位步长向上偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；根据确定的单位步长向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
所述确定的单位步长根据DDR标准参考电压确定。
本申请还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行上述的方法。
与相关技术相比，本申请技术方案包括：向上偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。本发明实施例方法根据最大参考电压值和最小参考电压值在DDR标准参考电压允许变换的范围，反过来确定DDR满足时序测试要求，避免了由于读写分离困难或存在对示波器自带选件和测试人员的业务能力的依赖，以及测试点不易点测的问题对时序测试造成的影响，提高了时序测试的工作效率。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1为本发明实施例实现时序测试的方法的流程图；
图2为本发明实施例实现时序测试的装置的结构图；
图3为本发明应用示例的基准电压源单元示意图；
图4为为本发明应用示例的方法流程图。
本发明的实施方式
下文中将结合附图对本发明的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
根据双速型电机综合保护器(JESD)中DDR时序定义，分析DDR的信号完整性和时序与DDR标准参考电压有着密切的对应关系。从理论上来说，通过测试DDR标准参考电压允许变换的范围可以反过来确定DDR的时序测试是否满足要求。
图1为本发明实施例实现时序测试的方法的流程图，如图1所示，包括：
步骤100、实现时序测试的装置向上偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
需要说明的是，当出现DDR异常时，一般会在系统中进行消息显示，例如显示无法进行打印，通过获取该类消息，可以确定DDR异常。如何获取该类消息的具体实现为本领域技术人员的惯用技术手段，在此不做赘述。
可选的，本步骤中，向上或向下偏拉输出至DDR的标准参考电压包括：
根据DDR标准参考电压确定向上或向下偏拉的单位步长；
根据确定的单位步长向上或向下偏拉输出至DDR的标准参考电压。
需要说明的是，向上或向下偏拉的单位步长的确定主要基于时序测试的标准参考电压确定；一般的，时序测试的最大要求值为标准参考电压的1.1倍；时序测试的最小要求值为标准参考电压的0.9倍。即偏拉标准参考电压以10％作为偏拉范围，将标准参考电压大小乘以10％后，将获得的值均分为两段到两段以上获得单位步长，具体设定为本领域技术人员的惯用技术手段，在此不做赘述。
可选的，本步骤之前还包括：
断开DDR所在系统或单板为DDR提供的电压输入；
通过基准电压源的数字模拟转换器(DAC)为DDR输出电压；通过基准电压源的模拟数据转换器(ADC)采样DDR获得的电压；基于采样DDR 获得的电压，通过ADC为DDR输出电压进行校正，获得输出至DDR的标准参考电压。
步骤101、实现时序测试的装置根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。
本步骤中，确定DDR是否满足时序测试要求包括：
最大参考电压大于时序测试的最大要求值，和最小参考电压小于时序测试的最小要求值时，确定DDR满足时序测试要求；
最大参考电压小于或等于时序测试的最大要求值，或最小参考电压大于或等于时序测试的最小要求值时，确定DDR不满足时序测试要求。
这里，时序测试的最大要求值为标准参考电压的1.1倍；
时序测试的最小要求值为标准参考电压的0.9倍。
本发明实施例根据最大参考电压值和最小参考电压值在DDR标准参考电压允许变换的范围，反过来确定DDR满足时序测试要求，避免了由于读写分离困难或存在对示波器自带选件和测试人员的业务能力的依赖，以及测试点不易点测的问题对时序测试造成的影响，提高了时序测试的工作效率。
本申请还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行上述的方法。
图2为本发明实施例实现时序测试的装置的结构图，如图2所示，包括：偏拉获取单元和确定单元；其中，
偏拉获取单元，设置为向上偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
偏拉获取单元是设置为，根据确定的单位步长向上偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；根据确定的单位步长向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
确定的单位步长根据DDR标准参考电压确定。
确定单元，设置为根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。
确定单元具体是设置为，
最大参考电压大于时序测试的最大要求值，和最小参考电压小于时序测试的最小要求值时，确定DDR满足时序测试要求；
最大参考电压小于或等于时序测试的最大要求值，或最小参考电压大于或等于时序测试的最小要求值时，确定DDR不满足时序测试要求。
时序测试的最大要求值为标准参考电压的1.1倍；
时序测试的最小要求值为标准参考电压的0.9倍。
本发明实施例装置还包括基准电压源单元，设置为断开DDR所在系统或单板为DDR提供的电压输入；
通过DAC为DDR输出电压；通过ADC采样DDR获得的电压；基于采样DDR获得的电压，通过ADC为DDR输出电压进行校正，获得输出至DDR的标准参考电压。
以下通过应用示例对本发明方法进行清楚详细的说明。
应用示例1
在进行本实施方法时，需要断开单板或系统为DDR提供的电压输入，本实施例通过基准电压源单元为DDR提供标准参考电压，图3为本发明应用示例的基准电压源单元示意图，包括基准电压模块、ADC和DAC，基准电压模块通过DAC将输出电压输出至DDR后，ADC对DDR上的电压进行采样获得准确的电压值，通过采样获得的准确的电压值，对DAC输出至DDR的电压进行调整，直至ADC采样获得DDR的电压值为标准参考电压，将所述标准参考电压值发送至基准电压模块，由基准电压模块经将所述标准参考电压通过DAC输出至DDR。
图4为本发明应用示例的方法流程图，如图4所示，包括：
步骤400、按照确定的单位步长，向上拉偏输出至时序测试的DDR的标 准参考电压，当出现DDR异常时，将当前电压值作为最大参考电压值；
步骤401、按照确定的单位步长，向下拉偏输出至时序测试的DDR的标准参考电压，当出现DDR异常时，将当前电压值作为最小参考电压值；
步骤400和步骤401的顺序可以进行调换。
步骤402、根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。可选的，
最大参考电压大于时序测试的最大要求值，和最小参考电压小于时序测试的最小要求值时，确定DDR满足时序测试要求；
最大参考电压小于或等于时序测试的最大要求值，或最小参考电压大于或等于时序测试的最小要求值时，确定DDR不满足时序测试要求。
时序测试的最大要求值为标准参考电压的1.1倍；
时序测试的最小要求值为所述标准参考电压的0.9倍。
以上内容是结合具体的实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。
本领域普通技术人员可以理解上述实施例的全部或部分步骤可以使用计算机程序流程来实现，所述计算机程序可以存储于一计算机可读存储介质中，所述计算机程序在相应的硬件平台上(如系统、设备、装置、器件等)执行，在执行时，包括方法实施例的步骤之一或其组合。
可选地，上述实施例的全部或部分步骤也可以使用集成电路来实现，这些步骤可以被分别制作成一个个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。
上述实施例中的各装置/功能模块/功能单元可以采用通用的计算装置来实现，它们可以集中在单个的计算装置上，也可以分布在多个计算装置所组成的网络上。
上述实施例中的各装置/功能模块/功能单元以软件功能模块的形式实现 并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。上述提到的计算机可读取存储介质可以是只读存储器，磁盘或光盘等。
工业实用性
本发明实施例避免了由于读写分离困难或存在对示波器自带选件和测试人员的业务能力的依赖，以及测试点不易点测的问题对时序测试造成的影响，提高了时序测试的工作效率。

Claims (11)

  1. 一种实现时序测试的方法，包括：
    向上偏拉输出至时序测试的双倍速率同步动态随机存储器DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
    根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。
  2. 根据权利要求1所述的方法，其中，所述确定DDR是否满足时序测试要求包括：
    所述最大参考电压大于时序测试的最大要求值，和所述最小参考电压小于时序测试的最小要求值时，确定DDR满足时序测试要求；
    所述最大参考电压小于或等于时序测试的最大要求值，或所述最小参考电压大于或等于时序测试的最小要求值时，确定DDR不满足时序测试要求。
  3. 根据权利要求1所述的方法，该方法之前还包括：
    断开DDR所在系统或单板为DDR提供的电压输入；
    通过基准电压源的数字模拟转换器DAC为DDR输出电压；通过基准电压源的模拟数据转换器ADC采样DDR获得的电压；基于采样DDR获得的电压，通过ADC为DDR输出电压进行校正，获得输出至DDR的所述标准参考电压。
  4. 根据权利要求2所述的方法，其中，
    所述时序测试的最大要求值为所述标准参考电压的1.1倍；
    所述时序测试的最小要求值为所述标准参考电压的0.9倍。
  5. 根据权利要求1所述的方法，其中，向上或向下偏拉输出至DDR的标准参考电压包括：
    根据DDR标准参考电压确定向上或向下偏拉的单位步长；
    根据确定的单位步长向上或向下偏拉输出至DDR的标准参考电压。
  6. 一种实现时序测试的装置，包括：偏拉获取单元和确定单元；
    偏拉获取单元，设置为向上偏拉输出至时序测试的双倍速率同步动态随机存储器DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
    确定单元，设置为根据最大参考电压值和最小参考电压值，确定DDR是否满足时序测试要求。
  7. 根据权利要求6所述的装置，其中，
    所述确定单元，是设置为所述最大参考电压大于时序测试的最大要求值，和所述最小参考电压小于时序测试的最小要求值时，确定DDR满足时序测试要求；
    所述最大参考电压小于或等于时序测试的最大要求值，或所述最小参考电压大于或等于时序测试的最小要求值时，确定DDR不满足时序测试要求。
  8. 根据权利要求6所述的装置，该装置还包括：
    基准电压源单元，设置为断开DDR所在系统或单板为DDR提供的电压输入；通过数字模拟转换器DAC为DDR输出电压；通过模拟数据转换器ADC采样DDR获得的电压；基于采样DDR获得的电压，通过ADC为DDR输出电压进行校正，获得输出至DDR的所述标准参考电压。
  9. 根据权利要求6或7所述的装置，其中，
    所述时序测试的最大要求值为所述标准参考电压的1.1倍；
    所述时序测试的最小要求值为所述标准参考电压的0.9倍。
  10. 根据权利要求6所述的装置，其中，
    所述偏拉获取单元，是设置为根据确定的单位步长向上偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最大参考电压值；根据确定的单位步长向下偏拉输出至时序测试的DDR的标准参考电压，直至DDR异常时，将当前电压值作为最小参考电压值；
    所述确定的单位步长根据DDR标准参考电压确定。
  11. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1～5中任一项所述的方法。
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