WO2016188093A1 - 触控驱动电路及其驱动方法、阵列基板及触控显示装置 - Google Patents

触控驱动电路及其驱动方法、阵列基板及触控显示装置 Download PDF

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Publication number
WO2016188093A1
WO2016188093A1 PCT/CN2015/097095 CN2015097095W WO2016188093A1 WO 2016188093 A1 WO2016188093 A1 WO 2016188093A1 CN 2015097095 W CN2015097095 W CN 2015097095W WO 2016188093 A1 WO2016188093 A1 WO 2016188093A1
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Prior art keywords
signal
shift register
touch
field effect
register unit
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PCT/CN2015/097095
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English (en)
French (fr)
Inventor
樊君
李付强
黄飞
乔赟
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/304,951 priority Critical patent/US10177173B2/en
Publication of WO2016188093A1 publication Critical patent/WO2016188093A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present invention relates to the field of display, and in particular, to a touch driving circuit and a driving method thereof, an array substrate, and a touch display device.
  • the in-cell touch display has a touch function and a display function. According to the principle of the touch function, it can be divided into a resistive touch display and a capacitive touch display.
  • the capacitive touch display touch function is realized by sensing the human body current current.
  • the commonly used capacitive touch display screen comprises an array substrate and a color film substrate, and a plurality of electrodes arranged along the X direction are arranged on the array substrate (
  • the touch driving electrode is disposed on the color film substrate with a plurality of electrodes arranged in the Y direction (referred to as a touch sensing electrode), wherein the Y direction is perpendicular to the X direction, and the touch driving electrode and the touch sensing electrode are Capacitance (node capacitance) is formed at the nodes that intersect.
  • each touch driving electrode sequentially loads a high frequency current signal, and at the same time, the current flowing out of each touch sensing electrode is monitored in real time.
  • a coupling capacitance is formed between the finger and the screen at the position, and the current flowing from the corresponding touch sensing electrode changes.
  • the processor monitors the current change of each touch sensing electrode, determines the coordinates of the node capacitance whose current changes, and determines the position of the touch point. In order to accurately sense the touch point of the finger, a large amount of node capacitance is required, which requires a large number of touch drive electrodes.
  • the driving chip outputs a high-frequency current signal to the touch driving electrode through the lead. Since the driving chip and the array substrate are independent of each other, the lead wire needs to pass through the edge of the touch display screen, and when the number of the touch electrodes is large, the touch is caused. The number of leads at the edge of the display is large, making it difficult to achieve a narrow bezel design.
  • the invention provides a touch driving circuit and a driving method thereof, an array substrate and a touch display device, which can reduce the number of leads on the edge of the touch display device and provide convenience for realizing a narrow frame.
  • the present invention provides a touch driving circuit disposed on an array substrate, including a plurality of shift register units that are cascaded with each other, and further includes a plurality of output control units, and output ends of the shift register units of each stage Each is connected to a touch driving electrode through one of the output control units, each touch
  • the control driving electrode includes one or more common electrodes; the output control unit receives a touch enable signal, a common voltage signal, a touch scan signal, and an output signal of the shift register unit connected to the output control unit And controlling the touch scan signal to the touch driving electrode connected to the output control unit during the first time period under the control of the touch enable signal and the output signal, the first time period The scan time allocated to the touch drive electrodes for one frame time.
  • the driving chip when the touch driving circuit provided on the array substrate is provided, the driving chip only needs to be connected to the touch driving circuit through a plurality of wires, and the plurality of wires are used to transmit the touch to the touch driving circuit.
  • the scanning signal, the control signal of the shift register unit, and the control signal of the output control unit can realize the operation of scanning the touch driving electrode.
  • the driving chip needs to be connected to the touch driving electrode through a large number of wires.
  • Each of the leads is used to output a driving signal to a touch driving electrode.
  • the number of leads of the touch driving electrode scanning process reduces the number of leads on the edge of the touch display device, reduces the occupation space of the lead on the edge of the touch display device, and provides convenience for realizing a narrow frame.
  • each touch driving electrode includes one or more common electrodes.
  • the touch scanning signal is loaded in a corresponding first time period, and the corresponding first one is in one frame.
  • the common voltage signal is loaded, so that the common electrode corresponding to each touch electrode is used for both the display function and the touch function, thereby saving the production of the touch driving electrode.
  • the steps are beneficial to reduce costs, improve product yield and increase production efficiency.
  • the present invention further provides a method for driving a touch driving circuit, including: receiving, by the output control unit, the touch enable signal and the common voltage signal during a touch scan period of a frame The touch scan signal, and an output signal of the shift register unit connected to the output control unit; the output control unit is first according to the touch enable signal and the output signal The touch scan signal is outputted to the touch drive electrode connected to the output control unit during a time period, and the first time period is a scan time allocated to the touch drive electrode in one frame time.
  • the shift register unit further receives a start shift signal during the touch scan period, and strobes step by step after receiving the start shift signal.
  • the shift register unit further receives a forward scan control signal and a reverse scan control signal during the touch scan period, and in the forward scan control signal and Under the control of the reverse scan control signal, enter a forward scan mode or a reverse scan
  • the forward scan mode after receiving the start shift signal, the first stage shift register unit sequentially selects from a shift register unit with a low number of stages to a shift register unit with a high number of stages.
  • the reverse scan mode after receiving the start shift signal, the last stage shift register unit sequentially strobes from a shift register unit with a high number of stages to a shift register unit with a low number of stages.
  • the present invention further provides an array substrate comprising the touch driving circuit of any of the above.
  • the present invention further provides a touch display device, wherein the touch display device is provided with the above array substrate.
  • the touch driving method, the array substrate and the touch display device provided by the present invention have the same beneficial effects as the touch driving circuit described above, and are not described herein again.
  • FIG. 1 is a schematic structural diagram of a touch driving circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a touch driving circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a timing diagram of a touch driving circuit according to Embodiment 1 of the present invention.
  • the embodiment provides a touch driving circuit, which is disposed on the array substrate, as shown in FIG. 1 , includes a plurality of shift register units 1 that are cascaded with each other, and further includes a plurality of output control units 2, each stage shift register The outputs of unit 1 are each connected to a respective touch drive electrode 3 via a respective output control unit 2, each touch drive electrode 3 comprising one or more common electrodes.
  • Each output control unit 2 receives a touch enable signal TX_EN, a common voltage signal VCOM, a touch scan signal EXVCOM, and an output signal of the shift register unit 1 connected to the output control unit 2, and Controlling the touch scan signal EXVCOM to the touch driving electrode 3 connected to the output control unit 2 during the first time period under the control of the touch enable signal TX_EN and the output signal of the shift register unit 1
  • the segment is the scan time allocated to the touch driving electrode 3 in one frame time.
  • the shift register unit 1 that is cascaded with each other is gated step by step under the control of the driving chip 4, when a certain shift register unit 1 is gated,
  • the shift register unit 1 transmits its output signal to the output control unit 2 connected thereto;
  • the output control unit 2 controls the touch under the control of the touch enable signal TX_EN and the output signal of the shift register unit 1 connected thereto
  • the scan signal EXVCOM is transmitted to the touch driving electrode 3 connected thereto; therefore, when the shift register unit 1 that is cascaded with each other is gated step by step under the control of the driving chip 4, the plurality of touch driving electrodes 3 can be realized. Scan one by one.
  • the driving chip 4 only needs to provide a control signal to the shift register unit 1 through a plurality of leads and a touch enable signal TX_EN, a common voltage signal VCOM and a touch scan signal EXVCOM to the output control unit 2.
  • One-by-one scanning of the plurality of touch driving electrodes 3 reduces the number of leads used for the scanning process of the touch driving electrodes, compared with the prior art driving chip, which requires a large number of leads to output driving signals to each of the touch driving electrodes.
  • the number of leads on the edge of the touch display device is reduced, and the occupied space of the lead on the edge of the touch display device is reduced, which is convenient for realizing a narrow frame.
  • each touch driving electrode 3 in the embodiment includes one or more common electrodes.
  • the touch driving electrode 3 is used.
  • Loading the touch scan signal EXVCOM when a touch drive electrode 3 is used to implement the display function of the touch display device, the touch drive electrode 3 is loaded with the common voltage signal VCOM, and thus the present invention is compared with the prior art.
  • the manufacturing steps of the touch driving electrode 3 are saved, which is beneficial to reducing cost, improving product yield and improving production efficiency.
  • the multi-stage shift register unit In order to load the touch scan signals one by one, the multi-stage shift register unit needs to be gate-level strobed after receiving the start shift signal TP_IN.
  • TP_IN is the start of the multi-stage shift register unit operation.
  • the signal, in addition, TP_IN can also be used as the start signal of the touch scan period.
  • an optional multi-stage shift register unit is connected in such a manner that the output end of the shift register unit of the previous stage is connected to the input end of the shift register unit.
  • the output signal of the previous stage shift register unit is used as the input signal of the next stage shift register unit; therefore, when the input end of the first stage shift register unit receives the start shift signal TP_IN, it is first strobed, The output signal is passed to the second stage shift register unit, and then the second stage shift register unit is gated.
  • the multi-stage shift register unit is gated step by step.
  • the shift register unit of the present embodiment can also implement a bidirectional shift function. Specifically, the shift register unit receives the forward scan control signal and the reverse scan control signal, and scans the control signal and the reverse scan control signal in the forward direction. Under control, enter the forward scan mode or the reverse scan mode: in the forward scan mode, after the first stage shift register unit receives the start shift signal, the shift register unit with a low number of stages is high to the number of stages The shift register unit is sequentially strobed. In the reverse scan mode, after the last shift register unit receives the start shift signal, the shift register unit with a high number of stages is shifted to the shift register unit with a low number of stages. Sequentially, wherein the forward scan control signal and the reverse scan control signal are in opposite phases.
  • each shift register unit includes a first input end and a second input end, wherein each stage shift The first input end of the bit register unit is connected to the output end of the shift register unit of the first stage, and the second input end of each shift register unit is connected to the output end of the shift register unit of the next stage.
  • the first input of the first stage shift register unit receives the start shift signal
  • the second input of the last stage shift register unit receives the start shift signal.
  • the multi-stage shift register unit implements forward scan according to signals received by the first input terminals of the shift register units of each stage; in the reverse scan mode, the multi-stage shift register The unit implements a reverse scan based on signals received at the second input of each stage of the shift register unit.
  • an optional structure of the touch driving circuit provided by the embodiment, such as 2, wherein the m-th stage shift register unit 1 includes a first field effect transistor M1 whose gate is connected to the output terminal OUT_N-1 of the m-1th stage shift register unit 1 and whose source receives the positive direction.
  • Scan control signal CN Scan control signal CN.
  • the mth stage shift register unit 1 further includes a second field effect transistor M2 whose gate is connected to the output terminal OUT_N+1 of the m+1th stage shift register unit, and whose source receives the reverse scan control signal CNB.
  • the m-th stage shift register unit 1 further includes a third field effect transistor M3 whose gate is connected to the drains of the first field effect transistor M1 and the second field effect transistor M2, respectively, and whose drain is connected to the m-th stage shift register unit.
  • the output of OUT 1 is OUT_N.
  • the source thereof receives the first clock signal TP_CK for the even-order shift.
  • the bit register unit 1 has its source receiving the second clock signal TP_CKB.
  • the first clock signal TP_CK and the second clock signal TP_CKB are in opposite phases.
  • the m-th stage shift register unit 1 further includes a second capacitor C2 having a first end connected to the gate of the third field effect transistor M3 and a second end connected to the drain of the third field effect transistor M3.
  • the m-th stage shift register unit 1 further includes a seventh field effect transistor M7, and the gate of the odd-numbered shift register unit 1 (the shift register unit 1 in FIG. 2 is an odd-numbered shift register unit 1)
  • the second clock signal TP_CKB is received simultaneously with the source, and for the even-numbered shift register unit 1, the gate and the source simultaneously receive the first clock signal TP_CK.
  • the m-th stage shift register unit 1 further includes a fourth field effect transistor M4 having a gate connected to the drain of the seventh field effect transistor M7, a source receiving the power supply signal VSS, and a drain connected to the shift register unit 1 of the present stage. Output OUT_N.
  • the m-th stage shift register unit 1 further includes a fifth field effect transistor M5 having a gate connected to the drain of the seventh field effect transistor M7, a source receiving the power supply signal VSS, and a drain connected to the third field effect transistor M3. Gate.
  • the above m is a natural number greater than 1, as shown in FIG. 1, the gate of the first transistor M1 of the shift register unit 1 of the first stage receives the start shift signal TP_IN, and the shift register unit 1 of the last stage The gate of the second transistor M2 receives the start shift signal TP_IN.
  • the plurality of field effect transistors constituting the shift register unit 1 may be NMOS transistors, that is, N-type metal-oxide-semiconductor transistors (hereinafter, a shift register unit composed of NMOS transistors is simply referred to as an NMOS type shift register unit), It may be a PMOS transistor, that is, a P-type metal-oxide-semiconductor transistor (hereinafter, a shift register unit composed of a PMOS transistor is simply referred to as a PMOS type shift register unit), and the shift register unit 1 in FIG. 3 is NMOS.
  • the type shift register unit is taken as an example to analyze the forward scan operation principle of the odd-level shift register unit.
  • the m-th stage shift register unit 1 (m is an odd number) as shown in FIG. 2, the received control signal includes a power supply signal VSS, a first clock signal TP_CK, a second clock signal TP_CKB, a forward scan control signal CN, and a counter
  • the scan control signal CNB wherein VSS is a low level signal, TP_CK and TP_CKB are periodic signals having the same pulse width and opposite phases, CN is a high level signal, and CNB is a low level signal.
  • the gate time of the m-1th shift register unit is T1.
  • the output terminal OUT_N-1 of the m-1th stage shift register unit is at a high level, the first field effect transistor M1 is turned on, the CN charges C2 through M1, and the PU point level is pulled high, The three field effect transistor M3 is turned on. It should be noted that, since TP_CKB is at a high level at this time, the seventh field effect transistor M7 is in an on state, so that the fifth field effect transistor M5 is in an on state, and therefore, the level value of the PU point is determined by the CN power. Flat value, power signal VSS level value, source of M1 - The drain resistance value is determined together with the source-drain resistance value of M5.
  • the channel width-to-length ratio of M1 and the channel width-to-length ratio of M5 (ie, the source-drain resistance value of M1 and the source-drain resistance value of M5) can be selected such that the level of the PU point at this time is such that M3 leads Pass level.
  • OUT_N-1 becomes a low level
  • M1 is turned off
  • TP_CKB becomes a low level
  • the seventh field effect transistor M7 is turned off
  • the PD is turned off during the end of the seventh field effect transistor M7.
  • the level is pulled low, M5 is turned off; TP_CK is turned to high level; since M3 is turned on, the output terminal OUT_N of the m-th stage shift register unit outputs a high level signal; meanwhile, since the potential at both ends of C2 remains active, the PU point is charged.
  • the level is further pulled high (higher than the source level of M3) OUT_N begins to output a high level signal.
  • TP_CKB remains low, M5 remains off; TP_CK remains high, M3 remains on, and OUT_N remains high.
  • TP_CKB goes high, M7 turns on, PD level is pulled high, M5 turns on, PU level is pulled low, C2 discharges, M3 turns off; The effect transistor M4 is turned on, causing OUT_N to start outputting a low level signal.
  • TP_CKB remains high, M7 turns on, M5 turns on, PU level remains low, M3 remains off, and M4 turns on, OUT_N remains low.
  • the shift register unit of the mth stage outputs a high level signal in the T2 period, that is, its gate time is T2, and T2 is immediately after T1 and the length is equal to the pulse width of the first clock signal TP_CK, through similar
  • the analysis can be deduced that the gate time of the shift register unit of the m+1th stage is immediately after the gate time of the shift register unit of the mth stage, thereby obtaining a conclusion that the multi-level shift provided by this embodiment
  • the registration unit can implement the function of stepping up.
  • the gate time of the shift register unit of the latter stage is after the shift register unit of the previous stage, that is, the multi-stage shift register unit operates at In the forward scan mode; when CN is low and CNB is high, the gate time of the shift register of the previous stage is after the shift register unit of the next stage, and the multi-stage shift register unit Works in reverse scan mode.
  • the above analysis of the operation principle of the shift register unit is for the NMOS type shift register unit
  • the PMOS type shift register unit it has the same circuit structure as the NMOS type shift register unit, and only needs to change the positive and negative of the control signal to obtain the same conclusion as above:
  • the multi-stage shift register unit provided by the embodiment can implement the function of step-by-step gating.
  • the m-th stage shift register unit 1 includes, in addition to the first field effect transistor M1, the second field effect transistor M2, the third field effect transistor M3, and the first The fourth field effect transistor M4, the fifth field effect transistor M5, the seventh field effect transistor M7 and the second capacitor C2 further include: a first capacitor C1 having a first end connected to a drain of the seventh field effect transistor M7, The second terminal receives the power signal VSS; the sixth field effect transistor M6 has a gate connected to the gate of the third field effect transistor M3, a source receiving the power signal VSS, and a drain connected to the first end of the first capacitor C1; The eighth field effect transistor M8 has a gate connected to the first end of the first capacitor C1, a source receiving the power supply signal VSS, and a drain connected to the output terminal OUT_N of the mth stage shift register unit 1.
  • the shift register unit 1 is an odd-numbered NMOS type shift register unit 1, and the forward scan is performed.
  • the control signal CN is at a high level
  • the reverse scan control signal CNB is at a low level
  • the waveforms of the first clock signal TP_CK and the second clock signal TP_CKB are as shown in FIG. 3, and are periodic pulse signals having the same pulse width and opposite phases.
  • TP_CKB when TP_CKB is high, C1 is charged through M7, so that before the T1 period and after the T2 period, both ends of C1 maintain a high level difference, thereby keeping the PD point high.
  • M4 and M5 are kept in the on state, wherein M4 is in the on state, so that OUT_N is kept low, M5 is in the on state, and the PU point is kept low, so that M3 is in the off state, further ensuring the low OUT_N
  • C1 enables the shift register unit 1 to avoid the influence of the noise signal during the above period, and stably output the low level signal.
  • the output terminal OUT_N-1 of the previous stage shift register unit is at a high level, then the first field effect transistor M1 is turned on, and the CN charges C2 through M1, thereby PU point.
  • the level is pulled high, the third field effect transistor M3 is turned on; M6 is turned on, VSS discharges C1 through M6, thereby pulling down the potential of the PD point, so that the source-drain resistance value of M5 is increased, so that M6 can make the PU point A higher level value is reached.
  • TP_CKB remains low, M5 remains off; TP_CK remains high, M3 remains on, and OUT_N remains high.
  • TP_CKB becomes a high level
  • M7 is turned on
  • the PD point level is pulled high
  • C1 is charged
  • M5, M4, and M8 are turned on
  • M5 Turning on
  • the PU point level is pulled low
  • C2 is discharged
  • M3 and M6 are turned off
  • M4 and M8 are turned on, so that OUT_N starts to output a low level signal.
  • M8 can reduce the resistance value between VSS and OUT_N, thereby reducing the level value when OUT_N outputs a low level, and increasing the anti-interference ability of the output signal of the shift register unit 1.
  • TP_CKB remains high, M7 is turned on, M5 is turned on, PU point level remains low, M3 remains off, and M4 and M8 are turned on, and OUT_N remains low.
  • TP_CKB goes low and M7 turns off. Since the potential across capacitor C1 remains active, PD remains high, M5 turns on, PU stays low, M3 remains The off state, and M4 and M8 are turned on, and OUT_N remains low.
  • an optional structure of the touch driving circuit provided in this embodiment is as shown in the figure. 2, wherein the shift register unit 1 comprises: M1, M2, M3, M4, M5, M6, M7, M8, C1 and C2, and the output control unit 2 comprises: a ninth field effect transistor M9, the gate receiving The output signal OUT_N of the shift register unit 1 connected to the output control unit 2 has a source receiving the touch enable signal TX_EN; the twelfth field effect transistor M12 has a gate connected to the drain of the ninth field effect transistor M9.
  • the source receives the touch scan signal EXVCOM, the drain of which is connected to the output terminal TX_OUT of the output control unit 2; the eleventh field effect transistor M11 whose gate is connected to the drain of the ninth field effect transistor M9, and the source thereof receives The power supply signal VSS; the thirteenth field effect transistor M13, the gate of which is connected to the drain of the eleventh field effect transistor M11, the source thereof receives the common voltage signal VCOM, and the drain thereof is connected to the output terminal TX_OUT of the output control unit 2; a fourteenth field effect transistor M14 having a gate connected to a drain of the eleventh field effect transistor M11, a source connected to the power supply signal VSS, and a drain connected to a gate of the twelfth field effect transistor M12; a tenth field effect
  • the transistor M10 has a drain connected to the gate of the thirteenth field effect transistor M13.
  • the gate and the source simultaneously receive the second clock signal TP_CKB, and for the even-numbered output control unit 2, The gate and the source simultaneously receive the first clock signal TP_CK.
  • the odd-numbered output control unit 2 refers to the number of stages of the shift register unit 1 connected thereto being an odd number.
  • the number of stages of the shift register unit 1 is odd, and the shift register unit 1 and the output control unit 2 are composed.
  • the field effect transistors are all NMOS transistors, the forward scan control signal CN is at a high level, the reverse scan control signal CNB is at a low level, the common voltage signal VCOM is a DC signal, and the touch scan signal EXVCOM is an AC signal, first The waveforms of the clock signal TP_CK and the second clock signal TP_CKB are as shown in FIG.
  • the touch enable signal TX_EN is a periodic pulse signal whose signal period is half of the period of the TP_CK signal.
  • the gate time of the shift register unit 1 is T2, that is, OUT_N is a high level in the T2 period.
  • OUT_N is high and TX_EN is low, M9 is on, M11 is off; TP_CKB is low, M10 is off; Gexvcom is low
  • Gvcom point is high, M12 is turned off, M13 and M14 are turned on, and VCOM is loaded to TX_OUT through M13.
  • OUT_N is high level and TX_EN is high level, M11 is on, M14 is off, Gexvcom point is high level and Gvcom point is low level, then M13 is off, M12 is on, EXVCOM Output to TX_OUT through M12.
  • OUT_N goes low
  • M9 turns off
  • TP_CKB goes high
  • M10 turns on
  • Gvcom rises high
  • M14 turns on
  • Gexvcom is pulled low Go low
  • M13 turns on
  • VCOM outputs to TX_OUT through M13.
  • the output control unit 2 connected to the odd-numbered shift register unit 1 is at the touch enable signal TX_EN, the first clock signal TP_CK, and the second clock signal TP_CKB, and the output signal of the shift register unit 1 connected thereto.
  • the touch scan signal EXVCOM is outputted to the touch driving electrode 3 connected thereto, and is output to the touch driving electrode 3 connected thereto in other time periods in one frame.
  • Common voltage signal VCOM Common voltage signal.
  • the output control unit 2 includes, in addition to the ninth field effect transistor M9, the tenth field effect transistor M10, the eleventh field effect transistor M11, the twelfth field effect transistor M12, and the thirteenth field effect.
  • the sixteenth field effect transistor M16 has a gate and a source receiving a common voltage enable signal VCOM_EN, and a drain connected to the gate of the thirteenth field effect transistor M13.
  • the third capacitor C3 has a first end connected to the drain of the eleventh field effect transistor M11 and a second end receiving the power signal VSS.
  • C3 and M16 will be described below with reference to specific examples.
  • the number of stages of the shift register unit 1 is odd, and the field effect transistors constituting the shift register unit 1 and the output control unit 2 are shown. All are NMOS transistors, the forward scan control signal CN is high level, the reverse scan control signal is low level, the common voltage signal VCOM is DC signal, the touch scan signal EXVCOM is an AC signal, the first clock signal TP_CK and the first The waveform of the two clock signals TP_CKB is as shown in FIG.
  • the touch enable signal TX_EN is a periodic pulse signal whose signal period is half of the period of the TP_CK signal.
  • the gate time of the shift register unit 1 is T2, that is, OUT_N is a high level in the T2 period.
  • the field effect transistor may be an N-type MOS transistor or a P-type MOS transistor, which is not limited in this embodiment.
  • the structure and working principle of the NMOS touch drive circuit are described in detail.
  • the power signal VSS in the control signal is a low level signal. It is well known that the NMOS circuit and the PMOS circuit can be converted to each other, and only the N-type MOS in the circuit is needed. The tube is replaced by a P-type MOS tube, and the control signal of the circuit can be changed accordingly.
  • the power supply signal VSS should be adjusted to a high level signal.
  • the NMOS type touch driving circuit and the PMOS type touch driving circuit have simple manufacturing process, can save manufacturing cost, improve product yield and improve production efficiency.
  • the NMOS type touch driving circuit can save the process of fabricating the hole injection region with respect to the CMOS type touch driving circuit.
  • the touch driving circuit provided in this embodiment can reduce the number of leads used to drive the touch driving electrodes, and provide convenience for the touch display device to realize a narrow frame.
  • the embodiment of the present invention further provides a driving method for driving the touch driving circuit of the first embodiment, including: receiving, by a control unit, a touch enable signal and a common voltage during a touch scan period of one frame a signal, a touch scan signal, and an output signal of the shift register unit connected to the output control unit; the output control unit is configured according to the touch enable signal and the output signal of the shift register unit connected to the output control unit
  • the touch scan signal is outputted to the touch drive electrode connected to the output control unit for a period of time, and the first time period is a scan time allocated to the touch drive electrode within one frame time.
  • the shift register unit further receives the initial shift signal, and strobes step by step after receiving the initial shift signal.
  • the shift register unit further receives the forward scan control signal and the reverse scan control signal, and performs the forward scan control signal and the reverse scan control.
  • the registration unit is strobed in sequence.
  • the shift register unit with forward and reverse scan mode can make the function of the touch drive circuit more flexible.
  • An embodiment of the present invention further provides an array substrate, including the touch drive provided in any one of the first embodiments. Dynamic circuit.
  • the embodiment of the invention further provides a touch display device, wherein the touch display device is provided with the above array substrate.
  • the touch display device in the embodiment of the present invention is a mutual capacitive touch display screen.
  • the touch display device in the embodiment of the present invention is provided with the touch driving circuit of the first embodiment. Compared with the prior art, the touch display device in the embodiment of the present invention can easily realize a narrow frame.

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Abstract

一种触控驱动电路及其驱动方法、阵列基板及触控显示装置，涉及显示领域。该驱动方法包括：在一帧的触控扫描时间段内，输出控制单元（2）接收触控使能信号、公共电压信号、触控扫描信号，以及接收与所述输出控制单元（2）相连的移位寄存单元（1）的输出信号；输出控制单元（2）根据触控使能信号和与该输出控制单元（2）相连的移位寄存单元（1）的输出信号，在第一时间段内向与该输出控制单元（2）相连的触控驱动电极（3）输出触控扫描信号，第一时间段为一帧时间内分配给所述触控驱动电极（3）的扫描时间。所述触控驱动电路及其驱动方法用于驱动触控显示装置实现触控功能，能够减少用来驱动触控驱动电极的引线数量，并且便于实现显示器窄边框。

Description

触控驱动电路及其驱动方法、阵列基板及触控显示装置 技术领域
本发明涉及显示领域，尤其涉及一种触控驱动电路及其驱动方法、阵列基板及触控显示装置。
背景技术
内嵌式触控显示屏集触控功能和显示功能于一身，根据其触控功能实现的原理不同，可分为电阻式触控显示屏和电容式触控显示屏等。其中，电容式触控显示屏触控功能是通过感应人体电流实现的，目前常用的电容式触控显示屏包括阵列基板和彩膜基板，在阵列基板上布设有沿X方向排列的若干电极(称为触控驱动电极)，在彩膜基板上布置有沿Y方向排列的若干电极(称为触控感应电极)，其中Y方向与X方向相垂直，在触控驱动电极与触控感应电极相交叉的节点处形成电容(节点电容)。工作时，各触控驱动电极依次加载高频电流信号，与此同时每个触控感应电极流出的电流被实时监测。当手指与屏幕上的某个位置接触时，在该位置处，手指与屏幕间会形成耦合电容，对应的触控感应电极流出的电流会发生变化。处理器监测各个触控感应电极的电流变化情况，确定电流发生变化的节点电容的坐标，从而确定触控点的位置。为精确感知手指的触控点，需设置大量的节点电容，从而需要大量的触控驱动电极。
现有技术中，驱动芯片通过引线向触控驱动电极输出高频电流信号，由于驱动芯片与阵列基板相互独立，引线需经过触控显示屏的边缘，当触控电极数目较多时，导致触控显示屏边缘的引线数目较多，很难实现窄边框设计。
发明内容
本发明提供一种触控驱动电路及其驱动方法、阵列基板及触控显示装置，能够减少触控显示装置边缘的引线数目，为实现窄边框提供方便。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，本发明提供一种触控驱动电路，设置在阵列基板上，包括相互级联的多个移位寄存单元，还包括多个输出控制单元，每级的移位寄存单元的输出端均通过一个所述输出控制单元连接到一个触控驱动电极，每个触 控驱动电极包括一个或多个公共电极；所述输出控制单元接收触控使能信号、公共电压信号、触控扫描信号，以及与所述输出控制单元相连的所述移位寄存单元的输出信号，并在所述触控使能信号和所述输出信号的控制下，在第一时间段内向与该输出控制单元相连的触控驱动电极输出所述触控扫描信号，所述第一时间段为一帧时间内分配给所述触控驱动电极的扫描时间。
由上可知，本发明提供的设置在阵列基板上的触控驱动电路工作时，驱动芯片只需通过数根引线连接到触控驱动电路，数根引线用于向该触控驱动电路传输触控扫描信号、移位寄存单元的控制信号和输出控制单元的控制信号，即可实现对触控驱动电极进行扫描的操作，相比现有技术中驱动芯片需通过大量引线连接到触控驱动电极，每根引线分别用来向一个触控驱动电极输出驱动信号的做法，由于触控驱动电路工作时所需的信号数量远小于触控驱动电极的数量，因而，本发明的技术方案减少了用于触控驱动电极扫描过程的引线数量，从而减少了触控显示装置边缘的引线数目，减少了引线在触控显示装置边缘的占用空间，为实现窄边框提供方便。
另外，每个触控驱动电极包括一个或多个公共电极，每个触控驱动电极工作时，在其对应的第一时间段内加载触控扫描信号，在一帧内除其对应的第一时间段之外的时间段内，均加载公共电压信号，从而将每个触控电极对应的公共电极既用于实现显示功能，又用于实现触控功能，从而节省了触控驱动电极的制作步骤，有利于降低成本、提高产品良率和提高生产效率。
第二方面，本发明还提供一种触控驱动电路的驱动方法，包括：在一帧的触控扫描时间段内，所述输出控制单元接收所述触控使能信号、所述公共电压信号、所述触控扫描信号，以及接收与所述输出控制单元相连的所述移位寄存单元的输出信号；所述输出控制单元根据所述触控使能信号和所述输出信号，在第一时间段内向与该输出控制单元相连的触控驱动电极输出所述触控扫描信号，所述第一时间段为一帧时间内分配给所述触控驱动电极的扫描时间。
上述的触控驱动电路驱动方法中，在所述触控扫描时间段内，所述移位寄存单元还接收起始移位信号，并在接收到所述起始移位信号后逐级选通。
上述的触控驱动电路驱动方法中，在所述触控扫描时间段内，所述移位寄存单元还接收正向扫描控制信号和反向扫描控制信号，并在所述正向扫描控制信号和所述反向扫描控制信号的控制下，进入正向扫描模式或者反向扫 描模式；在所述正向扫描模式下，第一级移位寄存单元接收到所述起始移位信号后，从级数低的移位寄存单元到级数高的移位寄存单元依次选通；在所述反向扫描模式下，最后一级移位寄存单元接收到所述起始移位信号后，从级数高的移位寄存单元到级数低的移位寄存单元依次选通。
第三方面，本发明还提供一种阵列基板，包括上述任一种的触控驱动电路。
第四方面，本发明还提供一种触控显示装置，该触控显示装置设置有上述的阵列基板。
本发明提供的触控驱动方法、阵列基板和触控显示装置均与上述的触控驱动电路有相同的有益效果，此处不再赘述。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例一提供的触控驱动电路的完整结构示意图；
图2为本发明实施例一提供的触控驱动电路的具体结构示意图；
图3为本发明实施例一提供的触控驱动电路的时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
实施例一
本实施例提供一种触控驱动电路，设置在阵列基板上，如图1所示，包括相互级联的多个移位寄存单元1，还包括多个输出控制单元2，每级移位寄存单元1的输出端均通过一个相应的输出控制单元2连接到一个相应的触控驱动电极3，每个触控驱动电极3包括一个或多个公共电极。每个输出控制单元2接收触控使能信号TX_EN、公共电压信号VCOM、触控扫描信号EXVCOM，以及与该输出控制单元2相连的移位寄存单元1的输出信号，并 在触控使能信号TX_EN和该移位寄存单元1的输出信号的控制下，在第一时间段内向与该输出控制单元2相连的触控驱动电极3输出触控扫描信号EXVCOM，第一时间段为一帧时间内分配给触控驱动电极3的扫描时间。
如图1所示，本实施例的触控驱动电路工作时，相互级联的移位寄存单元1在驱动芯片4的控制下逐级选通，当某个移位寄存单元1选通时，该移位寄存单元1将其输出信号传递给与其连接的输出控制单元2；输出控制单元2在触控使能信号TX_EN和与其连接的移位寄存单元1的输出信号的控制下，将触控扫描信号EXVCOM传递给与其连接的触控驱动电极3；因此，当相互级联的移位寄存单元1在驱动芯片4的控制下逐级选通时，即可实现多个触控驱动电极3的逐个扫描。
由上可知，驱动芯片4只需通过数根引线向移位寄存单元1提供控制信号以及向输出控制单元2提供触控使能信号TX_EN、公共电压信号VCOM和触控扫描信号EXVCOM，即可实现多个触控驱动电极3的逐个扫描，相比现有技术驱动芯片需通过大量引线分别向每个触控驱动电极输出驱动信号的做法，减少了用于触控驱动电极扫描过程的引线数量，从而减少了触控显示装置边缘的引线数目，减少了引线在触控显示装置边缘的占用空间，为实现窄边框提供方便。
另外，本实施例中的每个触控驱动电极3包括一个或多个公共电极，当某个触控驱动电极3用于实现触控显示装置的触控功能时，该触控驱动电极3上加载触控扫描信号EXVCOM，当某个触控驱动电极3用于实现触控显示装置的显示功能时，该触控驱动电极3上加载公共电压信号VCOM，因而与现有技术相比，本发明节省了触控驱动电极3的制作步骤，有利于降低成本、提高产品良率和提高生产效率。
为使多个触控驱动电极逐个加载触控扫描信号，需要使多级移位寄存单元接收到起始移位信号TP_IN后逐级选通，换言之，TP_IN为多级移位寄存单元工作的开始信号，另外，TP_IN也可以作为触控扫描时段的开始信号。为使多级移位寄存单元具备上述功能，一种可选的多级移位寄存单元的连接方式为：前一级移位寄存单元的输出端连接后一级移位寄存单元的输入端，即前一级移位寄存单元的输出信号作为下一级移位寄存单元的输入信号；因此，当第一级移位寄存单元的输入端接收到起始移位信号TP_IN后首先选通，将其输出信号传递给第二级移位寄存单元，然后第二级移位寄存单元选通， 依次类推，多级移位寄存单元逐级选通。
本实施例的移位寄存单元还可以实现双向移位功能，具体地，移位寄存单元接收正向扫描控制信号和反向扫描控制信号，并在正向扫描控制信号和反向扫描控制信号的控制下，进入正向扫描模式或者反向扫描模式：在正向扫描模式下，第一级移位寄存单元接收到起始移位信号后，从级数低的移位寄存单元到级数高的移位寄存单元依次选通，在反向扫描模式下，最后一级移位寄存单元接收到起始移位信号后，从级数高的移位寄存单元到级数低的移位寄存单元依次选通，其中，正向扫描控制信号和反向扫描控制信号相位相反。
本实施例中具有正向/反向扫描模式的多级移位寄存单元的一种可选的结构为：每级移位寄存单元包括第一输入端和第二输入端，其中，每级移位寄存单元的第一输入端连接上一级移位寄存单元的输出端，每级移位寄存单元的第二输入端连接下一级移位寄存单元的输出端。第一级移位寄存单元的第一输入端接收起始移位信号，和最后一级移位寄存单元的第二输入端接收起始移位信号。在正向扫描模式下，所述多级移位寄存单元根据各级移位寄存单元的第一输入端接收到的信号实现正向扫描；在反向扫描模式下，所述多级移位寄存单元根据各级移位寄存单元的第二输入端接收到的信号实现反向扫描。
为实现对多个触控驱动电极的逐个扫描，以及实现每个触控扫描电极分时加载触控扫描信号和公共电压信号，本实施例提供的触控驱动电路的一种可选结构，如图2所示，其中，第m级移位寄存单元1包括第一场效应晶体管M1，其栅极连接第m-1级移位寄存单元1的输出端OUT_N-1，其源极接收正向扫描控制信号CN。
第m级移位寄存单元1还包括第二场效应晶体管M2，其栅极连接第m+1级移位寄存单元的输出端OUT_N+1，其源极接收反向扫描控制信号CNB。
第m级移位寄存单元1还包括第三场效应晶体管M3，其栅极分别连接第一场效应晶体管M1和第二场效应晶体管M2的漏极，其漏极连接第m级移位寄存单元1的输出端OUT_N。对于奇数级的移位寄存单元1(图2中的移位寄存单元1为奇数级的移位寄存单元1，即m为奇数)，其源极接收第一时钟信号TP_CK，对于偶数级的移位寄存单元1，其源极接收第二时钟信号TP_CKB。第一时钟信号TP_CK和第二时钟信号TP_CKB相位相反。
第m级移位寄存单元1还包括第二电容C2，其第一端连接第三场效应晶体管M3的栅极，其第二端连接第三场效应晶体管M3的漏极。
第m级移位寄存单元1还包括第七场效应晶体管M7，对于奇数级的移位寄存单元1(图2中的移位寄存单元1为奇数级的移位寄存单元1)，其栅极和源极同时接收第二时钟信号TP_CKB，对于偶数级的移位寄存单元1，其栅极和源极同时接收第一时钟信号TP_CK。
第m级移位寄存单元1还包括第四场效应晶体管M4，其栅极连接第七场效应晶体管M7的漏极，其源极接收电源信号VSS,其漏极连接本级移位寄存单元1的输出端OUT_N。
第m级移位寄存单元1还包括第五场效应晶体管M5，其栅极连接第七场效应晶体管M7的漏极，其源极接收电源信号VSS，其漏极连接第三场效应晶体管M3的栅极。
上述的m为大于1的自然数，如图1所示，第一级的移位寄存单元1的第一晶体管M1的栅极接收起始移位信号TP_IN，最后一级的移位寄存单元1的第二晶体管M2的栅极接收起始移位信号TP_IN。
组成移位寄存单元1的多个场效应晶体管可以均为NMOS晶体管，即N型金属-氧化物-半导体晶体管(以下将由NMOS晶体管组成的移位寄存单元简称为NMOS型移位寄存单元)，也可以均为PMOS晶体管，即P型金属-氧化物-半导体晶体管(以下将由PMOS晶体管组成的移位寄存单元简称为PMOS型移位寄存单元)，下面以图3中的移位寄存单元1为NMOS型移位寄存单元为例，分析奇数级的移位寄存单元的正向扫描工作原理。
如图2所示的第m级移位寄存单元1(m为奇数)，其接收的控制信号包括电源信号VSS、第一时钟信号TP_CK、第二时钟信号TP_CKB、正向扫描控制信号CN和反向扫描控制信号CNB，其中，VSS为低电平信号，TP_CK和TP_CKB为脉宽相同且相位相反的周期信号，CN为高电平信号，CNB为低电平信号。如时序图3所示，第m-1级移位寄存单元的选通时间为T1。
T1时段内，第m-1级移位寄存单元的输出端OUT_N-1为高电平，则第一场效应晶体管M1导通，CN通过M1对C2充电，PU点电平被拉高，第三场效应晶体管M3导通。需要注意的是，由于此时TP_CKB为高电平，第七场效应晶体管M7处于导通状态，使得第五场效应晶体管M5处于导通状态，因此，此时PU点的电平值由CN电平值、电源信号VSS电平值、M1的源- 漏极电阻值和M5的源-漏极电阻值共同决定。可以选择M1的沟道宽长比和M5的沟道宽长比(即M1的源-漏极电阻值和M5的源-漏极电阻值)，使得PU点此时的电平为使得M3导通的电平。
换言之，在T1时段内，M3导通，由于TP_CK为低电平，因此第m级移位寄存单元的输出端OUT_N输出低电平信号。
在T1时段过渡到T2时段时，OUT_N-1变为低电平，M1截止；TP_CKB变为低电平，第七场效应晶体管M7截止，在第七场效应晶体管M7截止的过程中，PD点电平被拉低，M5截止；TP_CK变为高电平，由于M3导通，第m级移位寄存单元的输出端OUT_N输出高电平信号；同时由于C2两端的电位保持作用，PU点电平进一步拉高(高于M3的源极电平)OUT_N开始输出高电平信号。
换言之，在T2时段内，TP_CKB保持低电平，M5保持截止；TP_CK保持高电平，M3保持导通状态，从而OUT_N保持输出高电平。
在T2时段过渡到T3时段时，TP_CKB变为高电平，M7导通，PD点电平被拉高，M5导通，使PU点电平被拉低，C2放电，M3截止；第四场效应晶体管M4导通，使OUT_N开始输出低电平信号。在T3时段内，TP_CKB保持高电平，M7导通，M5导通，PU点电平保持低电平，M3保持截止状态，并且M4导通，OUT_N保持低电平。
换言之，T2时段后，PU点电平保持低电平，M3保持关闭状态，OUT_N保持低电平。
由上可知，第m级的移位寄存单元在T2时段内输出高电平信号，即其选通时间为T2，T2紧挨T1之后且长度等于第一时钟信号TP_CK的脉宽，通过类似的分析可推导出，第m+1级的移位寄存单元的选通时间紧挨在第m级的移位寄存单元的选通时间之后，从而得出结论，本实施例提供的多级移位寄存单元能实现逐级选通的功能。
需要注意的是，当CN为高电平且CNB为低电平时，后一级的移位寄存单元的选通时间在前一级的移位寄存单元之后，即多级移位寄存单元工作在正向扫描模式下；而当CN为低电平且CNB为高电平时，前一级的移位寄存单元的选通时间在后一级的移位寄存单元之后，，多级移位寄存单元工作在反向扫描模式。
上述对移位寄存单元的工作原理的分析是针对NMOS型移位寄存单元 进行的，对于PMOS型移位寄存单元，其与NMOS型移位寄存单元具有相同的电路结构，只需将控制信号的正负性做相应改变，即可得到与上述相同的结论，即：本实施例提供的多级移位寄存单元能实现逐级选通的功能。
为提高移位寄存单元1输出信号的质量，如图2所示，第m级移位寄存单元1除包括第一场效应晶体管M1、第二场效应晶体管M2、第三场效应晶体管M3、第四场效应晶体管M4、第五场效应晶体管M5、第七场效应晶体管M7和第二电容C2外，还包括：第一电容C1，其第一端连接第七场效应晶体管M7的漏极，其第二端接收电源信号VSS；第六场效应晶体管M6，其栅极连接第三场效应晶体管M3的栅极，其源极接收电源信号VSS，其漏极连接第一电容C1的第一端；第八场效应晶体管M8，其栅极连接第一电容C1的第一端，其源极接收电源信号VSS，其漏极连接第m级移位寄存单元1的输出端OUT_N。
下面结合具体示例，说明C1、M6、M8所带来的有益效果，在该具体示例中，如图2所示，移位寄存单元1为奇数级的NMOS型移位寄存单元1，正向扫描控制信号CN为高电平，反向扫描控制信号CNB为低电平，第一时钟信号TP_CK和第二时钟信号TP_CKB的波形如图3所示，为脉宽相同且相位相反的周期脉冲信号。参见图2和图3，当TP_CKB为高电平时会通过M7给C1充电，从而在T1时段之前以及T2时段之后，C1的两端保持较高的电平差，从而使PD点保持高电平，使M4和M5保持导通状态，其中M4处于导通状态，使OUT_N保持低电平，M5处于导通状态，使PU点保持低电平，从而使M3处于截止状态，进一步保证OUT_N的低电平不受干扰，因而，C1能使移位寄存单元1在上述时段内避免噪声信号的影响，稳定输出低电平信号。
继续参见图2和图3，T1时段内，前一级移位寄存单元的输出端OUT_N-1为高电平，则第一场效应晶体管M1导通，CN通过M1对C2充电，从而PU点电平被拉高，第三场效应晶体管M3导通；M6导通，VSS通过M6使C1放电，从而拉低PD点电位，使M5的源-漏极电阻值增加，从而M6可以使PU点达到较高的电平值。
继续参见图2和图3，在T1时段过渡到T2时段时，OUT_N-1变为低电平，M1截止；TP_CKB变为低电平，第七场效应晶体管M7截止,M5截止；TP_CK变为高电平，由于M3导通，第m级移位寄存单元的输出端OUT_N 输出高电平信号；同时由于C2两端的电位保持作用，PU点电平进一步拉高(高于M3的源极电平)，移位寄存单元1的输出端OUT_N开始输出高电平信号。
继续参见图2和图3，在T2时段内，TP_CKB保持低电平，M5保持截止；TP_CK保持高电平，M3保持导通状态，从而OUT_N保持输出高电平。
继续参见图2和图3，在T2时段过渡到T3时段时，TP_CKB变为高电平，M7导通，PD点电平被拉高，C1充电，M5、M4、M8导通；其中，M5导通，使PU点电平被拉低，C2放电，M3和M6截止；其中，M4、M8导通，使OUT_N开始输出低电平信号。M8的存在，可以减小VSS与OUT_N之间的电阻值，从而降低OUT_N输出低电平时的电平值，增加了移位寄存单元1输出信号的抗干扰能力。在T3时段内，TP_CKB保持高电平，M7导通，M5导通，PU点电平保持低电平，M3保持截止状态，并且M4和M8导通，OUT_N保持低电平。
在T3时段过渡到T4时段时，TP_CKB变为低电平，M7截止，由于电容C1两端的电位保持作用，PD点保持高电平，M5导通，PU点电平保持低电平，M3保持截止状态，并且M4和M8导通，OUT_N保持低电平。
此后，重复T3时段和T4时段的操作，直至OUT_N-1再次为高电平。
值得一提的是，上述分析针对奇数级的移位寄存单元1，对于偶数级的移位寄存单元1，C1、M6和M8可带来相同的有益效果，本领域技术人员可通过类似分析得到，此处不做赘述。
为实现对多个触控驱动电极的逐个扫描，以及实现每个触控扫描电极分时加载触控扫描信号和公共电压信号，本实施例提供的触控驱动电路的一种可选结构如图2所示，其中，移位寄存单元1包括：M1、M2、M3、M4、M5、M6、M7、M8、C1和C2，输出控制单元2包括：第九场效应晶体管M9，其栅极接收与输出控制单元2连接的移位寄存单元1的输出信号OUT_N，其源极接收触控使能信号TX_EN；第十二场效应晶体管M12，其栅极连接第九场效应晶体管M9的漏极，其源极接收触控扫描信号EXVCOM，其漏极连接到输出控制单元2的输出端TX_OUT；第十一场效应晶体管M11，其栅极连接第九场效应晶体管M9的漏极，其源极接收电源信号VSS；第十三场效应晶体管M13，其栅极连接第十一场效应晶体管M11的漏极，其源极接收公共电压信号VCOM，其漏极连接到输出控制单元2的输出端TX_OUT； 第十四场效应晶体管M14，其栅极连接第十一场效应晶体管M11的漏极，其源极连接电源信号VSS，其漏极连接第十二场效应晶体管M12的栅极；第十场效应晶体管M10，其漏极连接第十三场效应晶体管M13的栅极，对于奇数级的输出控制单元2，其栅极和源极同时接收第二时钟信号TP_CKB，对于偶数级的输出控制单元2，其栅极和源极同时接收第一时钟信号TP_CK。其中奇数级的输出控制单元2指与其连接的移位寄存单元1的级数为奇数。
下面结合具体示例，说明上述结构的输出控制单元2的功能，在该具体示例中，如图2所示，移位寄存单元1的级数为奇数，组成移位寄存单元1和输出控制单元2的场效应晶体管均为NMOS晶体管，正向扫描控制信号CN为高电平，反向扫描控制信号CNB为低电平，公共电压信号VCOM为直流信号，触控扫描信号EXVCOM为交流信号，第一时钟信号TP_CK和第二时钟信号TP_CKB的波形如图3所示，为脉宽相同且相位相反的周期脉冲信号，触控使能信号TX_EN为周期脉冲信号，其信号周期为TP_CK信号周期的一半。如图3所示，移位寄存单元1的选通时间为T2，即OUT_N在T2时段内为高电平。
参见图2和图3，T2-1时段内，OUT_N为高电平且TX_EN为低电平，M9导通，M11处于截止状态；TP_CKB为低电平，M10处于截止状态；Gexvcom点为低电平且Gvcom点为高电平，则M12截止、M13和M14导通，VCOM通过M13加载到TX_OUT。T2-2时段内，OUT_N为高电平且TX_EN为高电平，M11导通，M14截止，Gexvcom点变为高电平且Gvcom点变为低电平，则M13截止、M12导通，EXVCOM通过M12输出到TX_OUT。在T2-2时段过渡到T3时段时，OUT_N变为低电平，M9截止，TP_CKB变为高电平，M10导通，Gvcom点拉高到高电平，M14导通，Gexvcom点被拉低到低电平；M13导通，VCOM通过M13输出到TX_OUT。T2-2时段后，例如在T3时段和T4时段，M11处于截止状态，Gvcom点保持较高电位，从而TX_OUT持续输出VCOM。
综上所述，奇数级的移位寄存单元1连接的输出控制单元2在触控使能信号TX_EN、第一时钟信号TP_CK和第二时钟信号TP_CKB以及与其连接的移位寄存单元1的输出信号的控制下，在第一时间段内(T2-1)，向与其连接的触控驱动电极3输出触控扫描信号EXVCOM，在一帧内其他时段内，向与其连接的触控驱动电极3输出公共电压信号VCOM。本领域技术人员通过 类似分析可知，偶数级移位寄存单元1连接的输出控制单元2可实现相同功能，此处不做赘述。
优选地，如图2所示，输出控制单元2除包括第九场效应晶体管M9、第十场效应晶体管M10、第十一场效应晶体管M11、第十二场效应晶体管M12、第十三场效应晶体管M13和第十四场效应晶体管M14外，还包括：第十六场效应晶体管M16，其栅极和源极接收公共电压使能信号VCOM_EN，其漏极连接第十三场效应晶体管M13的栅极；第三电容C3，其第一端连接第十一场效应晶体管M11的漏极，第二端接收电源信号VSS。
下面结合具体示例，说明C3和M16的功能，在该具体示例中，如图2所示，移位寄存单元1的级数为奇数，组成移位寄存单元1和输出控制单元2的场效应晶体管均为NMOS晶体管，正向扫描控制信号CN为高电平，反向扫描控制信号为低电平，公共电压信号VCOM为直流信号，触控扫描信号EXVCOM为交流信号，第一时钟信号TP_CK和第二时钟信号TP_CKB的波形如图3所示，为脉宽相同且相位相反的周期脉冲信号，触控使能信号TX_EN为周期脉冲信号，其信号周期为TP_CK信号周期的一半。如图3所示，移位寄存单元1的选通时间为T2，即OUT_N在T2时段内为高电平。
参见图2和图3，在T2时段之前和T2时段之后，TP_CKB为高电平时，M10导通，TP_CKB通过M10给C3充电，通过C3两端电位差的保持作用，使Gvcom点保持高电平，使M13保持导通状态，从而降低噪声信号对Gvcom点电平的影响，使TX_OUT稳定输出VCOM。
继续参见图2和图3，VCOM_EN信号为高电平时，M16导通，Gvcom点为高电平，M13导通，VCOM通过M13输出到TX_OUT，同时M14导通，Gexvcom点为低电平，从而M12截止。因此，控制VCOM_EN电平可以直接控制TX_OUT输出VCOM，从而使触控显示装置兼容显示模式。对于偶数级移位寄存单元2连接的输出控制单元1，C3和M16能带来相同的效果，本领域技术人员可通过类似分析得出上述结论，此处不做赘述。
如图2所示的触控驱动电路，其中的场效应晶体管可以均为N型MOS管，也可以均为P型MOS管，本实施例不做限定。前面详细介绍了NMOS型触控驱动电路的结构和工作原理，控制信号中的电源信号VSS为低电平信号；众所周知，NMOS电路与PMOS电路可以进行相互转换，只需将电路中的N型MOS管换成P型MOS管，并将电路的控制信号做相应改变即可，具 体到本实施例中，当触控驱动电路中的场效应晶体管为P型MOS管时，电源信号VSS应调整为高电平信号。值得一提的是，NMOS型触控驱动电路和PMOS型触控驱动电路，制作工艺简单，可以节省制造成本、提高产品良率和提高生产效率。比如NMOS型触控驱动电路相对于CMOS型触控驱动电路，可以节省制作空穴注入区的工艺。
综上所述，采用本实施例提供的触控驱动电路，可以减少用来驱动触控驱动电极的引线数量，为触控显示装置实现窄边框提供方便。
实施例二
本发明实施例还提供一种驱动方法，用于驱动实施例一所述的触控驱动电路，包括：在一帧的触控扫描时间段内，输出控制单元接收触控使能信号、公共电压信号、触控扫描信号，以及接收与输出控制单元相连的移位寄存单元的输出信号；输出控制单元根据触控使能信号和与该输出控制单元相连的移位寄存单元的输出信号，在第一时间段内向与该输出控制单元相连的触控驱动电极输出触控扫描信号，第一时间段为一帧时间内分配给触控驱动电极的扫描时间。
上述的触控驱动电路驱动方法中，在触控扫描时间段内，移位寄存单元还接收起始移位信号，并在接收到起始移位信号后逐级选通。
上述的触控驱动电路驱动方法中，在触控扫描时间段内，移位寄存单元还接收正向扫描控制信号和反向扫描控制信号，并在正向扫描控制信号和所述反向扫描控制信号的控制下，进入正向扫描模式或者反向扫描模式：在正向扫描模式下，第一级移位寄存单元接收到起始移位信号后，从级数低的移位寄存单元到级数高的移位寄存单元依次选通；在反向扫描模式下，最后一级移位寄存单元接收到起始移位信号后，从级数高的移位寄存单元到级数低的移位寄存单元依次选通。具备正向反向扫描模式的移位寄存单元可以使触控驱动电路的功能实现更加灵活。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于装置实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
实施例三
本发明实施例还提供一种阵列基板，包括实施例一提供的任一的触控驱 动电路。本发明实施例还提供一种触控显示装置，该触控显示装置设置有上述的阵列基板。示例性的，本发明实施例中的触摸显示装置为互容式触摸显示屏。
本发明实施例中的触摸显示装置上设置有实施例一所述的触控驱动电路，相对于现有技术，本发明实施例中的触摸显示装置更容易实现窄边框。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。
本申请要求2015年5月27日提交的申请号为“201510280372.9”且发明名称为“触控驱动电路及其驱动方法、阵列基板及触控显示装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。

Claims (14)

  1. 一种触控驱动电路，设置在阵列基板上，包括相互级联的多个移位寄存单元以及多个输出控制单元，
    其中，每级移位寄存单元的输出端均通过所述多个输出控制单元中的一个相应输出控制单元连接到一个相应的触控驱动电极，每个触控驱动电极包括一个或多个公共电极；
    每个输出控制单元接收触控使能信号、公共电压信号、触控扫描信号，以及与所述输出控制单元相连的所述移位寄存单元的输出信号，并在所述触控使能信号和所述输出信号的控制下，在第一时间段内向与该输出控制单元相连的触控驱动电极输出所述触控扫描信号，所述第一时间段为一帧时间内分配给所述触控驱动电极的扫描时间。
  2. 根据权利要求1所述的触控驱动电路，其中，
    在相互级联的所述多个移位寄存单元中要接收起始移位信号的移位寄存单元接收到起始移位信号后，相互级联的所述多个移位寄存单元逐级选通。
  3. 根据权利要求2所述的触控驱动电路，其中，
    所述移位寄存单元接收正向扫描控制信号和反向扫描控制信号，并在所述正向扫描控制信号和所述反向扫描控制信号的控制下，进入正向扫描模式或者反向扫描模式；
    在所述正向扫描模式下，在第一级移位寄存单元接收到所述起始移位信号后，从级数低的移位寄存单元到级数高的移位寄存单元依次选通；
    在所述反向扫描模式下，在最后一级移位寄存单元接收到所述起始移位信号后，从级数高的移位寄存单元到级数低的移位寄存单元依次选通；
    所述正向扫描控制信号和所述反向扫描控制信号相位相反。
  4. 根据权利要求1所述的触控驱动电路，其中，第m级移位寄存单元包括：
    第一场效应晶体管，其栅极连接第m-1级移位寄存单元的输出端，其源极接收所述正向扫描控制信号；
    第二场效应晶体管，其栅极连接第m+1级移位寄存单元的输出端，其源极接收所述反向扫描控制信号；
    第三场效应晶体管，其栅极分别连接所述第一场效应晶体管和所述第二 场效应晶体管的漏极，其漏极连接第m级移位寄存单元的输出端，对于奇数级的移位寄存单元，其源极接收第一时钟信号，对于偶数级的移位寄存单元，其源极接收所述第二时钟信号，第一时钟信号和第二时钟信号相位相反；
    第二电容，其第一端连接所述第三场效应晶体管的栅极，其第二端连接所述第三场效应晶体管的漏极；以及
    下拉电路，其与第m级移位寄存单元的输出端、所述第三场效应晶体管的栅极、以及电源信号端连接，用于在第m级移位寄存单元不输出栅线驱动信号时将第m级移位寄存单元的输出端和第三场效应晶体管的栅极连接至电源信号端，
    其中，m为大于1的自然数。
  5. 根据权利要求4所述的触控驱动电路，其中，所述下拉电路包括：
    第七场效应晶体管，对于奇数级的移位寄存单元，其栅极和源极同时接收第二时钟信号，对于偶数级的移位寄存单元，其栅极和源极同时接收第一时钟信号；
    第四场效应晶体管，其栅极连接所述第七场效应晶体管的漏极，其源极接收所述电源信号端的电源信号,其漏极连接本级移位寄存单元的输出端；以及
    第五场效应晶体管，其栅极连接所述第七场效应晶体管的漏极，其源极接收所述电源信号，其漏极连接所述第三场效应晶体管的栅极。
  6. 根据权利要求4所述的触控驱动电路，其中，第m级移位寄存单元还包括：
    第一电容，其第一端连接所述第七场效应晶体管的漏极，其第二端接收所述电源信号；
    第六场效应晶体管，其栅极连接所述第三场效应晶体管的栅极，其源极接收所述电源信号，其漏极连接所述第一电容的第一端；
    第八场效应晶体管，其栅极连接所述第一电容的第一端，其源极接收所述电源信号，其漏极连接第m级移位寄存单元的输出端。
  7. 根据权利要求1所述的触控驱动电路，其中，所述输出控制单元包括：
    第九场效应晶体管，其栅极接收与所述输出控制单元连接的移位寄存单元的输出信号，其源极接收所述触控使能信号；
    第十二场效应晶体管，其栅极连接所述第九场效应晶体管的漏极，其源 极接收所述触控扫描信号，其漏极连接到所述输出控制单元的输出端；
    第十一场效应晶体管，其栅极连接所述第九场效应晶体管的漏极，其源极接收所述电源信号；
    第十三场效应晶体管，其栅极连接所述第十一场效应晶体管的漏极，其源极接收所述公共电压信号，其漏极连接到所述输出控制单元的输出端；
    第十四场效应晶体管，其栅极连接所述第十一场效应晶体管的漏极，其源极连接所述电源信号，其漏极连接所述第十二场效应晶体管的栅极；
    第十场效应晶体管，其漏极连接所述第十三场效应晶体管的栅极，对于奇数级的输出控制单元，其栅极和源极同时接收所述第二时钟信号，对于偶数级的输出控制单元，其栅极和源极同时接收所述第一时钟信号。
  8. 根据权利要求7所述的触控驱动电路，其中，所述输出控制单元还包括：
    第十六场效应晶体管，其栅极和源极接收公共电压使能信号，其漏极连接所述第十三场效应晶体管的栅极；
    第三电容，其第一端连接所述第十一场效应晶体管的漏极，第二端接收所述电源信号。
  9. 根据权利要求5-8任一项所述的触控驱动电路，其特征在于，所述场效应晶体管为N型或P型MOS管；
    所述场效应晶体管为N型MOS管时，所述电源信号为低电平信号；
    所述场效应晶体管为P型MOS管时，所述电源信号为高电平信号。
  10. 一种如权利要求1-9任一项所述的触控驱动电路的驱动方法，包括：
    在一帧的触控扫描时间段内，所述输出控制单元接收所述触控使能信号、所述公共电压信号、所述触控扫描信号，以及接收与所述输出控制单元相连的所述移位寄存单元的输出信号；
    所述输出控制单元根据所述触控使能信号和所述输出信号，在第一时间段内向与该输出控制单元相连的触控驱动电极输出所述触控扫描信号，所述第一时间段为一帧时间内分配给所述触控驱动电极的扫描时间。
  11. 根据权利要10所述的触控驱动电路驱动方法，其中，
    在所述触控扫描时间段内，相互级联的所述多个移位寄存单元中要接收起始移位信号的移位寄存单元接收起始移位信号，并且在该移位寄存器单元接收到所述起始移位信号后，相互级联的所述多个移位寄存单元逐级选通。
  12. 根据权利要11所述的触控驱动电路驱动方法，其中，
    在所述触控扫描时间段内，所述移位寄存单元还接收正向扫描控制信号和反向扫描控制信号，并在所述正向扫描控制信号和所述反向扫描控制信号的控制下，进入正向扫描模式或者反向扫描模式；
    在所述正向扫描模式下，第一级移位寄存单元接收到所述起始移位信号后，从级数低的移位寄存单元到级数高的移位寄存单元依次选通；
    在所述反向扫描模式下，最后一级移位寄存单元接收到所述起始移位信号后，从级数高的移位寄存单元到级数低的移位寄存单元依次选通。
  13. 一种阵列基板，包括如权利要求1-9任一所述的触控驱动电路。
  14. 一种触控显示装置，设置有如权利要求13所述的阵列基板。
PCT/CN2015/097095 2015-05-27 2015-12-11 触控驱动电路及其驱动方法、阵列基板及触控显示装置 Ceased WO2016188093A1 (zh)

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