WO2016187922A1 - 一种检测tft阵列基板的缺陷的方法 - Google Patents

一种检测tft阵列基板的缺陷的方法 Download PDF

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WO2016187922A1
WO2016187922A1 PCT/CN2015/082529 CN2015082529W WO2016187922A1 WO 2016187922 A1 WO2016187922 A1 WO 2016187922A1 CN 2015082529 W CN2015082529 W CN 2015082529W WO 2016187922 A1 WO2016187922 A1 WO 2016187922A1
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layer
film
detecting
defect
abnormal region
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French (fr)
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洪日
谢克成
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136268—Switch defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of testing liquid crystal displays, and more particularly to a method for detecting defects of a TFT array substrate.
  • TFT liquid crystal displays have gained increasingly popular applications due to their advantages of lightness, environmental protection and high performance. As the field of liquid crystal display applications expands, so does the size.
  • the 65-inch single-screen LCD monitor currently produced has a screen resolution of 1920*1080. With such high integration, the defect rate of the product will increase accordingly. It is also important to strengthen the quality inspection during the mass production of liquid crystal displays, to find out the defects of the sampled array substrates in time, and to analyze the causes of defects in the array substrate.
  • the prior art has not been very effective in detecting the above-mentioned situations.
  • the commonly used detecting means mainly is that the detecting personnel roughly judges an abnormal region of the array substrate that may be defective according to experience, and cuts the abnormal region for analysis.
  • This method can only roughly locate a thin film transistor that may have defects, but it is difficult to locate a specific film layer with an abnormality, and it is difficult to solve an abnormal point (such as a breaking point or a short circuit point, etc.) after an abnormal point is found by cutting. Size, extent, and perimeter structure for further analysis.
  • this method is also susceptible to damage to the film due to cutting and thus affecting the analysis results.
  • the integration degree of the TFT array substrate is getting higher and higher, the film layer is more and more, and each film is superimposed layer by layer. Therefore, when all the processes are completed, the defective film layer may be covered. below.
  • the COA color filter on array
  • the color resist layer is also integrated on the array substrate, so that an abnormal film layer is less likely to be found.
  • One of the technical problems to be solved by the present invention is to provide a method capable of efficiently determining the position of a defect of a TFT array substrate.
  • an embodiment of the present application provides a method for detecting a defect of a TFT array substrate, comprising: locating an abnormal region on a TFT array substrate; isolating the abnormal region from other regions on the substrate; Processing is performed such that the multi-film layer at the abnormal region is exposed layer by layer, and the exposed film layer is detected to determine a film layer having defects at the abnormal region.
  • each film layer is sequentially removed by etching, so that the multi-film layer at the abnormal region is exposed layer by layer.
  • the selected etchant and corresponding etching time are such that each etching etches only the film layer to be etched without damaging the film layer to be detected.
  • the detection is stopped when the film layer in which the defect exists is detected, or the detection is stopped after the detection of each film layer at the abnormal region is completed.
  • the anomalous area is isolated from other areas on the substrate by a spacer of a particular shape.
  • the step of isolating the abnormal region from the other regions on the substrate further comprises: covering the abnormal region with a spacer of a specific shape; and removing the spacer after the other regions are coated to form the protective layer.
  • the protective layer comprises taffeta gum.
  • the method specifically includes the following steps: Step 1: cover the upper portion of the abnormal region with a spacer; and step 2, remove the protective layer from the Tafel adhesive in other regions, and then remove The isolation plate; Step 3: etching the first passivation layer with phosphoric acid or HF to expose the source/drain metal layer; detecting the source/drain metal layer by using a test device, and stopping detection if a defect is found, if not found The defect is performed in step four; in step 4, the source/drain metal layer is etched to expose the ohmic contact layer; the ohmic contact layer is detected by using a test device, and if the defect is found, the detection is stopped, and if no defect is found, step 5 is performed.
  • Step 5 etching the ohmic contact layer to expose the semiconductor layer; detecting the semiconductor layer by using a test device, stopping detecting if a defect is found, and performing step 6 if no defect is found; step 6
  • the semiconductor layer and the gate protection layer expose the gate metal layer; the gate metal layer is detected by a test device.
  • the method further includes: etching the second passivation layer with phosphoric acid or HF to expose the color resist layer Profit
  • the color resist layer is detected by a test device; the color resist layer is etched away by a strong alkali to expose the first passivation layer located at the outermost layer of the thin film transistor.
  • the spacer is a circular or elliptical iron piece, and the area of the spacer is determined according to the range of the abnormal area.
  • FIG. 1 is a schematic flow chart of a method for detecting defects of a TFT array substrate according to an embodiment of the present application
  • 2(a)-(g) are schematic diagrams showing defect detection of a TFT array substrate by using the method of the embodiment of the present application;
  • 3(a)-(f) are schematic diagrams showing defect detection of a COA array substrate by the method of the embodiment of the present application.
  • the TFT array substrate has a multi-film layer structure formed by a multi-step film formation process.
  • Process steps for forming a multi-layer structure include cleaning, CVD film formation, Sputter film formation, exposure, development and lift-off, wet etching, dry etching, and the like.
  • each step may cause abnormality of the film layer, such as short circuit of the TFT array substrate, open circuit, and the like. Therefore, in the mass production of the substrate, it is necessary to perform sampling detection on the substrate multiple times.
  • the array substrate with abnormality is extracted as a sample for positioning and analysis of defects to accurately locate a specific film layer having an abnormality, and the cause of the defect is found, thereby correspondingly corresponding to other array substrates having the same defect in mass production.
  • the repair is beneficial to improve production efficiency and product yield.
  • a method of detecting a multi-film layer of a TFT array substrate is proposed to locate a specific film layer having defects.
  • FIG. 1 is a schematic flow chart of a method for detecting defects of a TFT array substrate according to an embodiment of the present application, where the method includes the following steps:
  • Step S110 Locating an abnormal region on the TFT array substrate; step S120, isolating the abnormal region from other regions on the substrate; and step S130, processing the abnormal region to make the multi-layer layer at the abnormal region
  • the layer is revealed layer by layer, and the exposed film layer is detected to determine a film layer having defects at the abnormal region.
  • the range in which the TFT array substrate may have internal defects is initially determined.
  • Internal defects in the array substrate may cause significant external faults such as abnormal color or black spots on the liquid crystal display.
  • By observing external faults it is possible to initially determine a rough range of possible internal defects.
  • the area where the internal defect exists that is, the abnormal area, is further narrowed and determined within the above range by the general-purpose substrate detecting apparatus.
  • Commonly used substrate testing devices include open circuit or short circuit inspection devices, optical automatic visual inspection devices, array detection devices, and the like.
  • the anomalous area is then isolated from other areas on the array substrate.
  • a specific shape of the spacer is used to isolate the anomalous area from other areas on the substrate.
  • the shape and area of the spacer are determined according to the range of the abnormal region.
  • the size of the isolation plate is too large to introduce the influence of adjacent pixel units.
  • the small size of the isolation plate is not conducive to subsequent detection operations.
  • the area of the isolation plate can be taken to be 10% to 30% larger than the range of the abnormal region. .
  • the material of the separator needs to ensure that the separator does not react with the membrane to be analyzed or ions are deposited, so as to avoid damage to the underlying membrane layer covered by the separator.
  • the material for making the separator can be selected from chromium, iron, copper or polyvinyl acetate.
  • a specific material is applied around the separator to form a protective layer. It should be ensured that the protective layer formed is not destroyed by the physical or chemical methods that will be used in subsequent steps.
  • a protective layer is formed using Tafel gum.
  • the thickness of the protective layer is not limited and may be in the range of 0.1 mm to 10 mm. Make settings internally. Care should be taken when applying the material of the protective layer so that the material of the protective layer is not in contact with the separator as much as possible, so that the separator can be removed directly after the protective layer is formed. If the material of the protective layer is applied to the separator, etching is required to remove the separator, which will increase labor and cost.
  • the spacer After the spacer is removed, the area previously covered by the spacer is exposed, and the isolation between the abnormal area and other areas is realized in a direction perpendicular to the surface of the liquid crystal display, and the layers are removed layer by layer by physical or chemical methods. When covered by the protective layer, it will not be destroyed.
  • Performing the film layer analysis on the multi-film layer at the abnormal region specifically includes: treating the abnormal region, exposing the multi-film layer at the abnormal region layer by layer, and detecting the exposed film layer.
  • the film layer where the defect is located can be determined by film layer analysis.
  • the method for exposing the multi-film layer at the abnormal region layer by layer is not limited, and various chemical means or physical means may be employed.
  • the specific process flow can be determined by referring to the existing film forming process, which is roughly equivalent to the reverse process of the film forming process, the time and pressure required to remove each layer of the film, and the thickness of the device and the thickness of the film layer. set.
  • the selected etchant and the corresponding etching time are such that each etching etches only the film layer to be etched without damaging the film layer to be detected.
  • the removal liquid of each film layer can be determined according to the film layer to be removed, the organic film can be wet-etched using a strong acid such as hydrochloric acid (HCL), and the inorganic film can use a neutral acid such as hydrofluoric acid (HF), phosphoric acid (H3PO4) or an organic base tetrahydrofuran or the like is subjected to wet etching.
  • a high film layer selection ratio should be used when removing the film layer to ensure that the underlying film layer can be protected from damage when the upper film layer is removed, and the integrity of the film layer is the basis for accurate measurement.
  • the film layer was also tested before removing a film layer.
  • the film test involves comprehensive testing of the appearance quality, surface shape, film thickness, film hardness, adhesion strength, chemical stability, thermal stability, and etchability of the film using a variety of test equipment, based on the results of the test. Determine whether the film has defects and further analyze the cause of the defects. For example, a foreign matter analysis (appearance quality analysis) is performed on a film layer using Fourier Transform infrared spectroscopy (FTIR), and a film quality analysis (film thickness, film hardness, and film thickness) is performed using an ultraviolet spectroscopic spectrometer. Chemical stability analysis, etc.).
  • FTIR Fourier Transform infrared spectroscopy
  • the defect detection is performed on the TFT array substrate shown in FIG. 2, and the area surrounded by the broken line in FIG. 2(a) is an abnormal region. It can be seen that the abnormal region is located at the thin film transistor, and further, the The thin film transistor is composed of a first passivation layer 201, a source/drain metal layer 202, an ohmic contact layer 203, a semiconductor layer 204, a gate protection layer 205, and a gate metal layer 206.
  • the defect detection includes the following steps:
  • Step 1 Cover the upper part of the abnormal area shown by the dotted frame with a spacer.
  • the spacer 208 is circular or elliptical and has an area of 1.2 times the area of the abnormal area, and is made of metal iron to cover it above the abnormal area to be detected.
  • Step 2 After coating the Tafic adhesive to form the protective layer 209 in other regions, the isolation plate 208 is removed, and the first passivation layer 201 not covered by the Tafel adhesive will be exposed, and other areas covered by the Tafel adhesive will be
  • the protective layer 209 has a thickness of 3 mm as shown in Fig. 2(c).
  • Step 3 etching the first passivation layer 201 by using phosphoric acid or HF to expose the source/drain metal layer 202; detecting the source/drain metal layer 202 by using a test device, stopping the detection if a defect is found, and performing the step if no defect is found.
  • the main material of the passivation layer is SiNx
  • hydrofluoric acid (HF) can be used as the removal liquid.
  • Step 4 etching the source/drain metal layer 202 to expose the ohmic contact layer 203; detecting the ohmic contact layer 203 by using a test device, and stopping the detection if a defect is found, and performing step 5 if no defect is found, as shown in FIG. 2(e) Shown.
  • Step 5 etching the ohmic contact layer 203 to expose the semiconductor layer 204; detecting the semiconductor layer 204 by using a test device, stopping the detection if a defect is found, and performing step 6 if no defect is found, as shown in FIG. 2(f).
  • Step 6 sequentially etching the semiconductor layer 204 and the gate protection layer 205 to expose the gate metal layer 206; and detecting the gate metal layer 206 by using a test device, as shown in FIG. 2(g).
  • 207 in Fig. 2 is a pixel electrode which is located outside the abnormal region described above.
  • the pixel electrode 207 is not affected by the action of the protective layer 209.
  • the embodiment of the present application provides an example for detecting defects of a thin film transistor region in a certain pixel unit, but the detection method in the embodiment of the present application may also be used for a thin film transistor inside the pixel unit.
  • the detection of the other multi-layer regions can also be used to detect the multi-film layer region between the two pixel units, which is not specifically limited herein.
  • the method of the embodiment of the present application is used for detecting, the multi-film layer to be detected is isolated independently of the surrounding structure to reduce the influence of the surrounding film structure on the film to be detected.
  • the testing device can be further saved, the testing cost is reduced, and the testing time is reduced.
  • the foreign matter analysis of the film layer can be completed using only one FTIR device.
  • FTIR equipment In the existing substrate inspection technology, it is necessary to use FTIR equipment and atomic points.
  • a plurality of instruments such as a analyzer and an ultraviolet spectroscopic spectrometer perform a foreign matter analysis on the film layer. Because the FITR test is mainly for surface testing, it is necessary to combine the atomic analyzer and the ultraviolet spectrometer to analyze the laminated film layer to obtain the result of the film to be tested, which wastes a lot of resources and test time.
  • the detection method of the array substrate in the embodiment of the present application weakens the interaction between different layers and improves the detection accuracy.
  • the analysis time can be reduced and the analysis capability can be improved.
  • the application of this method to the development of new products can reduce the development time of products and is of great help to enhance the competitiveness of products.
  • the multi-film layer analysis method of the embodiment of the present application is applicable to a TFT array substrate of various structures, including an array substrate of a top gate structure, an array substrate of a bottom gate structure, a COA array substrate, and the like.
  • 3(a)-(f) are schematic diagrams showing defect detection of a COA array substrate by the method of the embodiment of the present application.
  • FIG. 3(a) shows a specific structure of a pixel unit of the COA array substrate. It can be seen that the COA array substrate further increases the color resist layer 210 and the second blunt layer covering the color resist layer as compared with FIG. Layer 211. The following steps are specifically included in the defect detection of the COA array substrate:
  • Step 1 Cover the upper part of the abnormal area with a spacer.
  • the partitioning plate 208 is circular or elliptical, and has an area of 1.2 times the area of the abnormal region. It is made of metallic iron and covers it above the abnormal region to be detected.
  • Step 2 After coating the Tafel adhesive to form a protective layer in other areas, the separator is removed. Specifically, as shown in FIG. 3(b), a protective layer 209 is formed by coating a Tafel gel in a region other than the abnormal region, and the thickness of the protective layer is 3 mm. Further, as shown in FIG. 3(c), the separator is removed, and a place other than the abnormal region is protected by a protective layer formed of Tafel.
  • Step 3 etching the second passivation layer 211 by using phosphoric acid or HF, exposing the color resist layer 210, detecting the color resist layer by using a test device, stopping the detection if a defect is found, and performing step 4 if no defect is found.
  • the main material of the passivation layer is SiNx
  • hydrofluoric acid (HF) is used as the removal liquid.
  • Step 4 etching the color resist layer 210 with a strong alkali to expose the first passivation layer 201 located at the outermost layer of the thin film transistor. If there is no defect, the color resist layer is etched away by using a strong base as a removal liquid, preferably Monoethanolamine. The isolated substrate to be inspected is immersed in the removal liquid, and after heating to 75 degrees, the color resist layer is removed by soaking for 25 minutes. As shown in Figure 3 (e). Through the above steps, the first passivation layer 201 of the thin film transistor is exposed. The detection can be completed by using the foregoing method steps, and details are not described herein again.
  • the detection may be stopped when a film layer having defects is detected, but considering that the multiple film layers may affect each other, it is also possible to continue to complete all the film layers. Stop testing after testing. In addition, if there are a plurality of areas on the substrate that cannot be normally displayed, it is also necessary to perform detection separately for each of the areas.
  • the method of the embodiment of the present application is also applicable to the field of testing and maintenance of an OLED display screen, and can improve the maintenance efficiency while ensuring the maintenance quality.

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  • Crystallography & Structural Chemistry (AREA)
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
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Abstract

一种检测TFT阵列基板的缺陷的方法，包括，定位TFT阵列基板上的异常区域；将异常区域与基板上的其他区域进行隔离；对异常区域进行处理，使异常区域处的多膜层逐层显露，并对显露出来的膜层进行检测从而确定异常区域处存在缺陷的膜层。该方法提高了对基板的缺陷进行检测的能力。

Description

一种检测TFT阵列基板的缺陷的方法
相关申请的交叉引用
本申请要求享有2015年05月26日提交的名称为“一种检测TFT阵列基板的缺陷的方法”的中国专利申请CN201510273831.0的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示器的测试领域，尤其涉及一种检测TFT阵列基板的缺陷的方法。
背景技术
TFT液晶显示器以其轻便、环保、高性能等优点获得了日渐普遍的应用。随着液晶显示器应用领域的扩大，其尺寸也越做越大。目前生产的65寸单屏液晶显示器，其屏幕的分辨率可以达到1920*1080。在如此高的集成度下，产品的不良率也会相应增加。加强在液晶显示器批量生产时的质量检查，及时发现抽检的阵列基板的缺陷以及分析阵列基板产生缺陷的原因，也日显其重要性。
现有技术针对上述情况还没有十分有效的检测方法，目前常用的检测手段主要为，检测人员根据经验大致判断出阵列基板的可能存在缺陷的异常区域，并对异常区域进行切割以供分析。这种方式只能粗略地定位到可能具有缺陷的薄膜晶体管，却很难定位到存在异常的具体膜层，且经过切割发现异常点后很难对异常点(比如断路点或短路点等)的大小、范围以及周边结构进行进一步分析。此外，这种方法还容易因切割而对膜层造成损坏进而影响分析结果。
目前，TFT阵列基板的集成度越来越高，膜层越来越多，且每一层膜都是逐层叠加，因此，当全部工序完成后，存在缺陷的膜层就有可能被覆盖在下面。在COA(color filter on array)技术中，还将色阻层整合到阵列基板上，使得发生异常的膜层更不易被发现。
因此，亟需一种能够有效地确定TFT阵列基板的缺陷的位置的方法以解决上述问题。
发明内容
本发明所要解决的技术问题之一是需要提供一种能够有效地确定TFT阵列基板的缺陷的位置的方法。
为了解决上述技术问题，本申请的实施例提供了一种检测TFT阵列基板的缺陷的方法，包括：定位TFT阵列基板上的异常区域；将异常区域与基板上的其他区域进行隔离；对异常区域进行处理，使所述异常区域处的多膜层逐层显露，并对显露出来的膜层进行检测从而确定所述异常区域处存在缺陷的膜层。
优选地，采用蚀刻的方法依次去除各膜层，使所述异常区域处的多膜层逐层显露。
优选地，所选取的蚀刻剂及对应的蚀刻时间，使每一次蚀刻仅蚀刻待蚀刻的膜层，而不会损坏待检测的膜层。
优选地，在检测到缺陷存在的膜层时停止检测，或在完成对异常区域处的每一层膜层的检测后停止检测。
优选地，采用特定形状的隔离板将所述异常区域与基板上的其他区域进行隔离。
优选地，将异常区域与基板上的其他区域进行隔离的步骤进一步包括：利用特定形状的隔离板覆盖所述异常区域；在其他区域涂覆形成保护层后，去除所述隔离板。
优选地，保护层包括塔菲胶。
优选地，若异常区域位于薄膜晶体管处，则该方法具体包括以下步骤：步骤一、用隔离板覆盖所述异常区域的上方；步骤二、在其他区域涂覆塔菲胶形成保护层后，去掉所述隔离板；步骤三、利用磷酸或HF蚀刻掉第一钝化层，使源漏金属层显露；利用测试设备对所述源漏金属层进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤四；步骤四、蚀刻所述源漏金属层，使欧姆接触层显露；利用测试设备对所述欧姆接触层进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤五；步骤五、蚀刻所述欧姆接触层，使半导体层显露；利用测试设备对所述半导体层进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤六；步骤六、依次蚀刻所述半导体层和栅极保护层，使栅极金属层显露；利用测试设备对所述栅极金属层进行检测。
优选地，若异常区域的薄膜晶体管的上方还具有色阻层和第二钝化层，则在步骤三之前还包括：利用磷酸或HF蚀刻掉第二钝化层，使所述色阻层显露；利 用测试设备对所述色阻层进行检测；利用强碱蚀刻掉色阻层，使位于薄膜晶体管最外层的第一钝化层显露。
优选地，隔离板为圆形或椭圆形铁片，隔离板的面积根据异常区域的范围确定。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
通过对TFT阵列基板的多膜层结构进行逐层解析，降低了测试中多膜层结构的不同层别之间的交互影响，提高了对基板的缺陷进行检测的能力，并进一步减少了分析作业时间，提升了分析能力。将该方法用于新产品的开发，可以减少产品的开发时间，提升产品的竞争力。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1为本申请实施例的检测TFT阵列基板的缺陷的方法的流程示意图；
图2(a)-(g)为采用本申请实施例的方法对TFT阵列基板进行缺陷检测的示意图；
图3(a)-(f)为采用本申请实施例的方法对COA阵列基板进行缺陷检测的示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
TFT阵列基板具有经过多步成膜工艺形成的多膜层结构。用于形成多膜层结构的工艺步骤包括洗净、CVD成膜、Sputter成膜、曝光、显影与剥离、湿蚀刻以及干蚀刻等。在上述各工艺步骤中，每一个步骤都有可能导致膜层发生异常，例如TFT阵列基板的短路、断路等。因此，在基板的批量生产中，需要多次对基板进行抽样检测。进一步地，抽取发生异常的阵列基板作为样品进行缺陷的定位和解析，以准确定位存在异常的具体膜层，并找到产生缺陷的原因，从而对该批量生产中有相同缺陷的其他阵列基板进行相应的修复，有利于提高生产效率与产品的良品率。在本申请的实施例中，提出了一种对TFT阵列基板的多膜层进行检测的方法来定位存在缺陷的具体膜层。
图1为本申请实施例的检测TFT阵列基板的缺陷的方法的流程示意图，该方法包括以下步骤：
步骤S110、定位TFT阵列基板上的异常区域；步骤S120、将所述异常区域与基板上的其他区域进行隔离；步骤S130、对所述异常区域进行处理，使所述异常区域处的多膜层逐层显露，并对显露出来的膜层进行检测从而确定所述异常区域处存在缺陷的膜层。
首先初步确定TFT阵列基板可能存在内部缺陷的范围。阵列基板的内部缺陷可能导致明显的外部故障，例如液晶显示屏的色彩异常或存在黑点等。通过观察外部故障，可以初步确定一个可能存在内部缺陷的大致范围。接下来，利用通用的基板检测设备在上述范围内进一步缩小并确定存在内部缺陷的区域，即异常区域。常用的基板检测设备包括断路或短路检验装置、光学自动外观检查装置、阵列检测装置等。
然后将异常区域与阵列基板上的其他区域进行隔离。在本申请的实施例中，采用特定形状的隔离板将异常区域与基板上的其他区域进行隔离。具体的，隔离板的形状和面积根据异常区域的范围来确定。隔离板的尺寸偏大有可能引入相邻像素单元的影响，隔离板的尺寸偏小则不利于后续的检测操作，通常可以将隔离板的面积取为比异常区域的范围大10％～30％。隔离板的材料需要保证隔离板与待解析的膜层不发生反应或离子析出，以免对隔离板覆盖的下层膜层造成破坏。举例而言，制作隔离板的材料可以选择铬，铁，铜或聚醋酸乙烯脂等。
接下来在隔离板的周围涂敷特定的材料形成保护层。应保证所形成的保护层不被后续步骤中将使用的物理或化学的方法所破坏。举例而言，采用塔菲胶形成保护层。进一步地，对于保护层的厚度不做限定，可以在0.1mm～10mm的范围 内进行设定。在涂敷保护层的材料时应注意，尽可能使保护层的材料与隔离板不接触，这样可以在保护层形成之后直接取下隔离板。若保护层的材料涂敷到隔离板上，则需要采用蚀刻的方法去除隔离板，将增加工时与成本。
去除隔离板后，之前被隔离板覆盖的地方显露出来，在垂直于液晶显示屏表面的方向上实现了异常区域与其他区域之间的隔离，当采用物理或化学的方法逐层去除各膜层时，被保护层覆盖的地方就不会被破坏。
针对异常区域处的多膜层进行膜层解析具体包括：对异常区域进行处理，使异常区域处的多膜层逐层显露，并对显露出来的膜层进行检测。通过膜层解析可以确定缺陷所在的膜层。具体的，对使异常区域处的多膜层逐层显露的方法不做限定，可以采用多种化学手段或物理手段。具体工艺流程可以参照现有的成膜工艺过程进行确定，其大致相当于成膜工艺过程的逆过程，去除各层膜层所需的时间和压力等视所采用的设备以及膜层的厚度而定。进一步地，所选取的蚀刻剂及对应的蚀刻时间，使每一次蚀刻仅蚀刻待蚀刻的膜层，而不会损坏待检测的膜层。举例而言，去除各膜层的去除液可以根据所要去除的膜层进行确定，有机膜可以使用强酸如氢氯酸(HCL)等进行湿蚀刻，无机膜可以使用中性酸如氢氟酸(HF)、磷酸(H3PO4)或有机碱四氢呋喃等进行湿蚀刻。同时，在去除膜层时应采用高的膜层选择比，以确保在去除上层膜层的时候，下层膜层可以免于被破坏，膜层的完整性是实现精确测量的基础。
在去除一层膜层之前还要对该膜层进行测试。膜层测试包括使用多种测试设备对膜层的外观品质、表面形状、膜厚度、膜硬度、密着强度、化学稳定性、热稳定性以及刻蚀性等做全面的检测，根据检测的结果来确定该膜层是否存在缺陷，并进一步分析缺陷产生的原因。举例而言，使用傅氏转换红外线光谱分析仪(Fourier Transform infrared spectroscopy，FTIR)对膜层进行异物分析(外观品质分析)，使用紫外分光光谱仪对膜层进行膜质分析(膜厚度、膜硬度、化学稳定性分析等)等。
举例而言，对如图2所示的TFT阵列基板进行缺陷检测，图2(a)中的虚线所包围的区域为异常区域，可以看出，该异常区域位于薄膜晶体管处，进一步地，该薄膜晶体管由第一钝化层201、源漏金属层202、欧姆接触层203、半导体层204、栅极保护层205以及栅极金属层206组成，对其进行缺陷检测时具体包括以下步骤：
步骤一、用隔离板覆盖在虚线框所示出的异常区域的上方。如图2(b)所 示，隔离板208为圆形或椭圆形，面积为异常区域面积的1.2倍，由金属铁制成，将其覆盖在待检测的异常区域的上方。
步骤二、在其他区域涂覆塔菲胶形成保护层209后，去掉隔离板208，则未被塔菲胶覆盖的第一钝化层201将显露出来，被塔菲胶覆盖的其他区域将被保护，保护层209的厚度为3mm，如图2(c)所示。
步骤三、利用磷酸或HF蚀刻掉第一钝化层201，使源漏金属层202显露；利用测试设备对源漏金属层202进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤四，如图2(d)所示。具体的，当钝化层的主要材质为SiNx时，可以采用氢氟酸(HF)作为去除液。将经过隔离处理的待检测的基板浸入上述去除液中6分钟即可将SiNx保护层蚀刻掉，上述过程所发生的反应的化学方程式为，Si3N4+4HF+9H2O＝3H2SiO3+4NH4F。
步骤四、蚀刻源漏金属层202，使欧姆接触层203显露；利用测试设备对欧姆接触层203进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤五，如图2(e)所示。
步骤五、蚀刻欧姆接触层203，使半导体层204显露；利用测试设备对半导体层204进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤六，如图2(f)所示。
步骤六、依次蚀刻半导体层204和栅极保护层205，使栅极金属层206显露；利用测试设备对栅极金属层206进行检测，如图2(g)所示。
除此之外，图2中207为像素电极，其位于上述异常区域以外。在对薄膜晶体管异常区域处的各膜层进行检测时，由于保护层209的作用，不会对像素电极207造成影响。
需要说明的是，本申请实施例给出了针对某一像素单元内的薄膜晶体管区域的缺陷进行检测的示例，但本申请实施例中的检测方法也可以用于对像素单元内部的薄膜晶体管以外的其他多膜层区域进行检测，还可以用于对两个像素单元之间的多膜层区域进行检测，在此不做具体限定。在采用本申请实施例的方法进行检测时，将待检测的多膜层独立于其周围的结构隔离出来，以降低周围的膜层结构对待检测膜层的影响。
采用本申请实施例的基板检测方法，可以进一步节省测试设备，降低测试成本，减少测试时间。例如在上述测试过程中，只使用一台FTIR设备就可以完成对膜层的异物分析。而在现有的基板检测技术中，需要借助FTIR设备、原子分 析仪以及紫外分光光谱仪等多台仪器共同完成对膜层的异物分析。因为FITR测试主要是进行表面测试，所以需要再结合原子分析仪，紫外分光光谱仪对叠层膜层进行分析才能得到待测膜层的结果，浪费了大量的资源与测试时间。更进一步地，由于每层膜层的分子结构都各不相同，因此即使耗用多台设备也难以得到准确的膜层数据。而采用本申请实施例的阵列基板的检测方法，削弱了不同层别之间的交互影响，提高了检测的精度。
综上，通过对TFT阵列基板上的各膜层进行分层解析可以减少分析作业时间，提升分析能力。将该方法用于新产品的开发，可以减少产品的开发时间，对提升产品竞争力有非常大的帮助。进一步地，本申请实施例的多膜层解析方法适用于多种结构的TFT阵列基板，包括顶栅结构的阵列基板、底栅结构的阵列基板以及COA阵列基板等。
以下结合膜层结构更为复杂的COA阵列基板来说明本申请实施例的方法的实施过程。图3(a)-(f)为采用本申请实施例的方法对COA阵列基板进行缺陷检测的示意图。
图3(a)示出的是该COA阵列基板的像素单元的具体结构，可以看出，与图2相比，该COA阵列基板还增加了色阻层210与覆盖色阻层的第二钝化层211。在对该COA阵列基板进行缺陷检测时具体包括以下步骤：
步骤一、用隔离板覆盖在异常区域的上方。具体如图3(b)所示，隔离板208为圆形或椭圆形，面积为异常区域面积的1.2倍，由金属铁制成，将其覆盖在待检测的异常区域的上方。
步骤二、在其他区域涂覆塔菲胶形成保护层后，去掉隔离板。具体如图3(b)所示，在异常区域以外的其他区域涂敷塔菲胶形成保护层209，保护层的厚度为3mm。进一步地如图3(c)所示，将隔离板去掉，异常区域以外的地方将被塔菲胶形成的保护层保护起来。
步骤三、利用磷酸或HF蚀刻掉第二钝化层211，使色阻层210显露，利用测试设备对色阻层进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤四。如图3(d)所示，当钝化层的主要材质为SiNx时，采用氢氟酸(HF)作为去除液。将经过隔离处理的待检测的基板浸入去除液中6分钟即可将SiNx保护层去除，反应的化学方程式为，Si3N4+4HF+9H2O＝3H2SiO3+4NH4F。
步骤四、利用强碱蚀刻掉色阻层210，使位于薄膜晶体管最外层的第一钝化层201显露。若不存在缺陷，则采用强碱作为去除液将色阻层蚀刻掉，优选采用 单乙醇胺。将经过隔离处理的待检测的基板浸入去除液中，加热到75度之后，浸泡25分钟即可将色阻层去除。如图3(e)所示。经过上述步骤，薄膜晶体管的第一钝化层201显露出来。接下来可以采用前述方法步骤完成检测，此处不再赘述。
需要说明的是，对阵列基板进行缺陷检测时，一般可以在检测到存在缺陷的膜层就停止检测，但考虑到多膜层之间会相互影响，因此，也可以继续完成对所有膜层的测试后再停止检测。另外，如果基板上存在多处不能正常显示的区域，还需要逐一对各区域分别进行检测。
本申请实施例的方法还适用于OLED显示屏的测试和维修领域，在提高维修效率的同时，还能保证维修质量。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (14)

  1. 一种检测TFT阵列基板的缺陷的方法，包括：
    定位TFT阵列基板上的异常区域；
    将所述异常区域与基板上的其他区域进行隔离；
    对所述异常区域进行处理，使所述异常区域处的多膜层逐层显露，并对显露出来的膜层进行检测从而确定所述异常区域处存在缺陷的膜层。
  2. 根据权利要求1所述的方法，其中，采用蚀刻的方法依次去除各膜层，使所述异常区域处的多膜层逐层显露。
  3. 根据权利要求2所述的方法，其中，所选取的蚀刻剂及对应的蚀刻时间，使每一次蚀刻仅蚀刻待蚀刻的膜层，而不会损坏待检测的膜层。
  4. 根据权利要求1所述的方法，其中，在检测到缺陷存在的膜层时停止检测，或在完成对所述异常区域处的每一层膜层的检测后停止检测。
  5. 根据权利要求1所述的方法，其中，所述对显露出来的膜层进行检测包括利用检测设备测试膜层的外观品质、表面形状、膜厚度、膜硬度、密着强度、化学稳定性、热稳定性和/或刻蚀性。
  6. 根据权利要求1所述的方法，其中，采用特定形状的隔离板将所述异常区域与基板上的其他区域进行隔离。
  7. 根据权利要求6所述的方法，其中，所述隔离板的材料包括铬、铁、铜或聚醋酸乙烯脂。
  8. 根据权利要求6所述的方法，其中，将所述异常区域与基板上的其他区域进行隔离的步骤进一步包括：
    利用特定形状的隔离板覆盖所述异常区域；
    在其他区域涂覆形成保护层后，去除所述隔离板。
  9. 根据权利要求8所述的方法，其中，所述保护层包括塔菲胶。
  10. 根据权利要求8所述的方法，其中，所述保护层的厚度为0.1mm～10mm。
  11. 根据权利要求8所述的方法，其中，所述隔离板的面积比异常区域的范围大10％～30％。
  12. 根据权利要求1所述的方法，其中，若所述异常区域位于薄膜晶体管处，则该方法具体包括以下步骤：
    步骤一、用隔离板覆盖所述异常区域的上方；
    步骤二、在其他区域涂覆塔菲胶形成保护层后，去掉所述隔离板；
    步骤三、利用磷酸或HF蚀刻掉第一钝化层，使源漏金属层显露；利用测试设备对所述源漏金属层进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤四；
    步骤四、蚀刻所述源漏金属层，使欧姆接触层显露；利用测试设备对所述欧姆接触层进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤五；
    步骤五、蚀刻所述欧姆接触层，使半导体层显露；利用测试设备对所述半导体层进行检测，若发现缺陷则停止检测，若未发现缺陷则执行步骤六；
    步骤六、依次蚀刻所述半导体层和栅极保护层，使栅极金属层显露；利用测试设备对所述栅极金属层进行检测。
  13. 根据权利要求12所述的方法，其中，若所述异常区域的薄膜晶体管的上方还具有色阻层和第二钝化层，则在步骤三之前还包括：
    利用磷酸或HF蚀刻掉第二钝化层，使所述色阻层显露；
    利用测试设备对所述色阻层进行检测；
    利用强碱蚀刻掉色阻层，使位于薄膜晶体管最外层的第一钝化层显露。
  14. 根据权利要求12所述的方法，其中，所述隔离板为圆形或椭圆形铁片，所述隔离板的面积根据异常区域的范围确定。
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