WO2016184063A1 - 阵列基板、其制造方法以及有机发光二极管显示装置 - Google Patents

阵列基板、其制造方法以及有机发光二极管显示装置 Download PDF

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WO2016184063A1
WO2016184063A1 PCT/CN2015/095056 CN2015095056W WO2016184063A1 WO 2016184063 A1 WO2016184063 A1 WO 2016184063A1 CN 2015095056 W CN2015095056 W CN 2015095056W WO 2016184063 A1 WO2016184063 A1 WO 2016184063A1
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substrate
semiconductor layer
doped
type
layer
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PCT/CN2015/095056
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English (en)
French (fr)
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郭易东
龙春平
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京东方科技集团股份有限公司
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Priority to US14/914,350 priority Critical patent/US10790341B2/en
Publication of WO2016184063A1 publication Critical patent/WO2016184063A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/142—Energy conversion devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and an organic light emitting diode display device.
  • OLEDs Organic electroluminescent displays
  • OLEDs have many advantages such as active illumination, high contrast, fast response, and thinness, making them one of the major next-generation displays.
  • the principle of operation is to cause an organic light-emitting layer located between the anode and the cathode to emit light by applying an appropriate voltage to the anode and the cathode, thereby displaying an image.
  • a solar cell is a semiconductor device that converts solar energy directly into electrical energy.
  • solar cells can be mainly classified into silicon-based thin film solar cells, compound-based thin film solar cells, and organic-based solar cells, wherein silicon-based solar cells can be mainly classified into single crystal silicon solar cells, polycrystalline silicon solar cells, and amorphous cells.
  • Silicon solar cells Illustratively, FIG. 1 shows a cross-sectional view of a polycrystalline silicon solar cell. As shown in FIG.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and an organic light emitting diode display device.
  • the solar cell unit is fabricated in an array substrate, thereby reducing manufacturing cost, improving yield, and making the product easy to implement.
  • an embodiment of the present invention provides an array substrate including a substrate including a display region including: a plurality of data lines and a plurality of gate lines crossing each other, the plurality of pixel regions being formed into a matrix And a plurality of data lines and a plurality of gate lines crossing each other formed on the base substrate Defining, wherein each of the plurality of pixel regions is formed with a thin film transistor; a peripheral region surrounding the display region, further, the array substrate further includes at least one solar cell unit, and the thin film transistor is located in the lining The same side of the base substrate and formed in at least one of the plurality of pixel regions and the peripheral region.
  • an embodiment of the present invention further provides a method of fabricating the above array substrate, comprising: preparing a substrate including: a display region and a peripheral region surrounding the display region; on the same side of the substrate substrate Forming a plurality of gate lines, a plurality of data lines, a plurality of pixel regions defined by the plurality of gate lines and the data lines, a thin film transistor in each of the pixel regions, and at least one of at least one of the plurality of pixel regions and the peripheral region Solar battery unit.
  • an embodiment of the present invention further provides an organic light emitting diode display device comprising: the array substrate as described above and an opposite substrate opposite to the array substrate.
  • FIG. 1 is a schematic working principle diagram of a solar cell
  • FIG. 2 is a plan view of a base substrate in accordance with an embodiment of the present invention.
  • FIG. 3 is an exemplary plan view of an array substrate in which a pixel region is provided with a solar cell unit according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view of an array substrate of a first doped semiconductor layer of a solar cell unit and a second doped semiconductor layer of a thin film transistor in the same layer, in accordance with an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view of an array substrate including a bottom gate type thin film transistor according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view of a solar cell unit of a PIN structure in accordance with an embodiment of the present invention.
  • FIG. 7(a)-7(j) are cross-sectional views showing respective steps of an exemplary manufacturing method of an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and an organic light emitting diode display device.
  • An array substrate includes a base substrate including a display area and a peripheral area surrounding the display area, wherein the display area includes a plurality of data lines and a plurality of gate lines defined by crossing each other A plurality of pixel regions of the matrix are distributed, and a thin film transistor is formed in each of the pixel regions. Further, the array substrate further includes at least one solar cell unit, the at least one solar cell unit and the thin film transistor are located on the same side of the substrate substrate and formed on the plurality of pixel regions and the peripheral region at least One. Since the solar cell is disposed in the array substrate, the solar cell unit can be formed by a photolithography process.
  • the solar cell and the thin film transistor are formed on the same side of the substrate substrate, so that the solar cell can be formed by the same process as the thin film transistor. Therefore, the solar cell unit can be fabricated in the thin film transistor array substrate by utilizing the characteristics of refinement of the photolithography process without increasing the process flow and the material, thereby reducing the manufacturing cost, improving the yield, and making the product easy. achieve.
  • the array substrate when the array substrate adopts a flexible substrate, the array substrate can be used for flexibility
  • the display device can realize a flexible display that is thin, lightweight, bendable or even curlable, and can be applied to wearable products such as watches, clothing, and backpacks.
  • an organic electroluminescence display device when the array substrate is applied to an organic electroluminescence display device, an organic electroluminescence display device integrated with a solar cell can be obtained.
  • the array substrate 10 includes a base substrate 100 including a display area 102 and a peripheral area 101 surrounding the display area 102, wherein as shown in FIG. 3, the display area 102 includes a plurality of pieces of data crossing each other.
  • the line 12 and the plurality of gate lines 11 divide the display area 102 into a plurality of pixel areas 21, and a thin film transistor 32 is disposed in each of the pixel areas 21.
  • at least one solar cell unit is further formed on the base substrate 100, and the at least one solar cell unit and the thin film transistor 32 are located on the same side of the base substrate 100, and are formed in the plurality of pixel regions 21 and the peripheral region 101 at least One.
  • At least one solar cell unit may be disposed in the pixel region 21 or in the peripheral region 101, or may be disposed in both the pixel region 21 and the peripheral region 101.
  • the solar cells may all be disposed in the pixel region 21 or all of them are disposed in the peripheral area 101, or a part is disposed in the pixel area and the remaining part is disposed in the peripheral area 101.
  • each solar cell unit may be disposed in each pixel region, or two or more solar cell units may be disposed, and those skilled in the art may appropriately select other product features such as an aperture ratio.
  • the embodiment of the invention is not specifically limited.
  • FIG. 3 illustrates an exemplary plan view of an array substrate in which a pixel region is provided with a solar cell unit, in which only three pixel regions are illustrated, each of which is provided with one solar cell unit 31, in order to
  • the solar cell unit 31 and the thin film transistor 32 are represented by hatched squares, but this does not mean that the two are square-shaped, and the blocks only show the setting areas of the two.
  • the solar cell unit 31 and the thin film transistor 32 are disposed in different regions.
  • the solar cell unit 31 may be disposed in a region corresponding to the black matrix, corresponding to the gate line or data. Line or corresponding to gate and data lines The area of both.
  • each solar cell unit 31 may include a first doped semiconductor layer
  • the thin film transistor 32 may include a second doped semiconductor layer
  • the first doped semiconductor layer and the second doped semiconductor layer are on the same layer in.
  • the solar cell unit 31 may be a PN structure
  • the first doped semiconductor layer may include a P-type semiconductor and an N-type semiconductor, the P-type semiconductor and the N-type semiconductor being located in the same layer.
  • the P-type semiconductor is doped with a trivalent element in a semiconductor material, for example, a silicon crystal.
  • a hole concentration formed by boron or the like is much larger than a doped semiconductor having a free electron concentration
  • an N-type semiconductor is a semiconductor material.
  • a doped semiconductor in which a concentration of electrons is formed by doping a pentavalent element in a silicon crystal for example, phosphorus, arsenic, antimony or the like, is much larger than the hole concentration.
  • the second doped semiconductor layer of the thin film transistor 32 may include an intermediate doped portion formed in the same layer and a side doped portion located on both sides of the intermediate doped portion, wherein the intermediate doped portion and the The doping type of the side doping portion is reversed, that is, the intermediate doping portion is P type, and accordingly, the side doping portion is N type, and the intermediate doping portion is N type, and correspondingly, the side doping portion is P type.
  • FIG. 4 is a cross-sectional structural view showing an array substrate of a first doped semiconductor layer of the solar cell unit 31 and a second doped semiconductor layer of the thin film transistor 32 in the same layer, wherein (a) shows solar energy The area where the battery unit 31 is located, (b) shows the area where the thin film transistor 32 is located, here a top gate type thin film transistor is taken as an example.
  • the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are disposed in the same layer on the base substrate 100, and the first doped semiconductor layer 12 includes a P-type semiconductor 121 and an N-type semiconductor 122.
  • the second doped semiconductor layer 13 includes an intermediate doped portion 132 and side doped portions 131 on both sides of the intermediate doped portion 132, wherein the side doped portion 131 is shown as a P-type semiconductor and the intermediate doped portion 132 is N
  • the type semiconductor is merely an example here.
  • the side doping portion 131 may also be an N-type semiconductor, and correspondingly, the intermediate doping portion 132 is a P-type semiconductor.
  • the gate insulating layer 14 covers the base substrate 100 on which the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are formed, and the gate electrode 15 is disposed at On the gate insulating layer 14 and corresponding to the intermediate doping portion 132, the interlayer insulating layer 16 covers the gate electrode 15; further, the source and drain electrodes 17 are disposed on the interlayer insulating layer 16, and the source and drain electrodes 17 Electrically connected to the via hole 171 formed in the gate insulating layer 14 and the interlayer insulating layer 16, respectively Side doped portion 131.
  • the planarization layer 18 covers the source and drain electrodes 17, and then the pixel electrode 19 is disposed on the planarization layer 18 and electrically connected to the source electrode through the via 191 in the planarization layer 18. Or drain electrode 17.
  • the via holes 201 and 202 formed in the gate insulating layer 14, the interlayer insulating layer 16, and the planarization layer 18 are respectively connected to the P-type semiconductor 121 and the N-type semiconductor 122.
  • Two electrodes 20 are disposed over the planarization layer 18.
  • FIG. 4 For convenience of illustration, the area where the solar cell is located and the area where the thin film transistor is located are separately shown in FIG. 4, but in practice, other components or other components may be provided between the area where the solar cell is located and the area where the thin film transistor is located.
  • the solar cell unit when the solar cell unit is disposed in the peripheral area, other components are disposed therebetween, which are not shown here for the sake of simplicity of the illustration, but if there are no other components between the two, FIG. 4(a) and FIG. 4(b) is directly connected and combined into a single figure, which can be set by a person skilled in the art according to actual needs, and the embodiment of the present invention will not be limited.
  • the first doped semiconductor layer 12 is shown as being provided with a gate insulating layer 14, an interlayer insulating layer 16, and a planarization layer 18, which is merely an example, in practical applications, A person skilled in the art can set each layer above the first doped semiconductor layer 12 according to actual needs. For example, only a planarization layer may be formed, or a planarization layer and an interlayer insulating layer may be formed without a gate insulating layer.
  • the two electrodes 20 of the solar cell unit may be disposed on the gate insulating layer or may be disposed on the gate insulating layer and the interlayer insulating layer, and correspondingly may be formed only in the gate insulating layer.
  • the holes may be formed in the gate insulating layer and the interlayer insulating layer, which is not limited by the embodiment of the present invention, and can be selected by those skilled in the art according to actual needs.
  • the thin film transistor in the embodiment of the present invention may also be a bottom gate thin film transistor, that is, the gate is formed under the second doped semiconductor layer of the thin film transistor.
  • 5 is a schematic cross-sectional view showing an array substrate including a bottom gate type thin film transistor, wherein (a) is a cross-sectional view of a region where the solar cell is located, and (b) is a cross-sectional view of a region where the thin film transistor is located, as shown in FIG.
  • the gate electrode 15 and the gate insulating layer 14 are sequentially formed on the base substrate 100, and the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are formed on the gate insulating layer 14, and the intermediate doped portion corresponds to At the gate electrode 15, the source and drain electrodes 17 are connected to the side doping portion 131 through via holes in the interlayer insulating layer 16.
  • the region of the thin film transistor is further provided with a pixel electrode 19 connected to the source or drain electrode 17 through the through hole 191 in the planarization layer 18, and the electrode cell is also provided with two electrodes 20 in the region where the solar cell is respectively
  • the vias 201 and 202 in the layer 18 and the interlayer insulating layer 16 are connected to the P-type or N-type semiconductor 121 and the N-type or P-type semiconductor 122.
  • the differences from those shown in FIG. 4 are mainly described herein, and the same portions will not be described again.
  • planarization layer 18 may be disposed over the first doped semiconductor layer 12, and accordingly, the electrode 20 is connected to the first doped semiconductor layer 12 only through the via holes in the planarization layer.
  • the electrode 20 connected to the first doped semiconductor layer 12 can also be disposed at other locations, for example, under the first doped semiconductor layer, which is not limited by the embodiment of the present invention, as long as It can be used to realize the electrical connection function.
  • the position of the source electrode and the drain electrode of the thin film transistor may be set according to actual needs, for example, under the second doped semiconductor layer, etc., which is not limited by the embodiment of the present invention.
  • the first doped semiconductor layer and the second doped semiconductor layer may not be located on the same layer but only on the same side of the base substrate 100.
  • the array may be The peripheral driving circuits of the substrate are stacked or arranged in parallel with the peripheral driving circuit of the array substrate.
  • the solar cell unit 31 may also be a PIN structure, and the first doped semiconductor layer included may further include an intrinsic semiconductor disposed between the P-type semiconductor and the N-type semiconductor.
  • the intrinsic semiconductor 123 is located between the P-type semiconductor 121 and the N-type semiconductor 122.
  • the solar cell unit 31 may also be a series PN or PIN structure
  • the first doped semiconductor layer may include a plurality of P-type semiconductors and a plurality of N-type semiconductors alternately disposed, and the plurality of P-type semiconductors and The plurality of N-type semiconductors are formed in the same layer; further, the first doped semiconductor layer may further include a plurality of intrinsic semiconductors, each of the intrinsic semiconductors being disposed adjacent to the P-type semiconductors and the N Between semiconductors.
  • the base substrate 100 may be a flexible substrate that is bendable, for example, various plastic films such as polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate. (Polycarbonate, PC) or a substrate made of polyimide (PI) and its derivatives.
  • the base substrate 100 may be a rigid substrate such as a glass substrate, a stainless steel substrate, or the like.
  • the first and second doped semiconductor layers of the embodiments of the present invention may be doped polysilicon Layer, doped single crystal silicon layer, and the like.
  • the array substrate according to an embodiment of the present invention may further include a buffer layer between the substrate substrate and the functional layers formed thereon.
  • the solar battery cells and the thin film transistors are formed on the same side of the base substrate, so that they can be formed in the same process as the thin film transistors, thereby
  • the solar cell unit is fabricated in the thin film transistor array substrate by utilizing the characteristics of refinement of the photolithography process without increasing the number of processes and materials, thereby reducing the manufacturing cost, improving the yield, and making the product easy to implement.
  • a second embodiment of the present invention provides a method of fabricating an array substrate according to the first embodiment, comprising: step S1, preparing a substrate, wherein the substrate includes: a display area and a peripheral area surrounding the display area And step S2, forming a plurality of gate lines, a plurality of data lines, a plurality of pixel regions defined by the plurality of gate lines and the data lines, a thin film transistor in each of the pixel regions, and a plurality of the plurality of pixel lines on the same side of the base substrate At least one solar cell in at least one of the pixel area and the peripheral area.
  • each solar cell unit may include a first doped semiconductor layer
  • the thin film transistor may include a second doped semiconductor layer
  • the first doped semiconductor layer and the second doped semiconductor layer are located in the same layer.
  • step S2 may include simultaneously forming the first doped semiconductor layer and the second doped semiconductor layer by a patterning process and a doping process.
  • the first doped semiconductor layer includes: a P-type semiconductor and an N-type semiconductor
  • the second doped semiconductor layer includes an intermediate doped portion and a side opposite to the intermediate doped portion and having a doping type opposite to the intermediate doped portion
  • the doping portion, simultaneously forming the first doped semiconductor layer and the second doped semiconductor layer by the patterning process and the doping process may include:
  • the semiconductor layer may be a polysilicon layer or a single crystal silicon layer.
  • forming the semiconductor material layer on the substrate substrate may include: depositing on the substrate substrate The amorphous silicon layer is crystallized; and the amorphous silicon layer is crystallized to form a polysilicon layer by a crystallization method, for example, Excimer-Laser Annealing or Solid Phase Crystallization (SPC).
  • a crystallization method for example, Excimer-Laser Annealing or Solid Phase Crystallization (SPC).
  • the semiconductor layer of the thin film transistor region is doped with P-type/N-type impurities by using the first mask to form an intermediate doped portion while doping the semiconductor layer of the solar cell region with P Type / N type impurities to form a P type / N type semiconductor;
  • the impurity portion is doped with an N-type/P-type impurity to form an N-type/P-type semiconductor.
  • the base substrate according to an embodiment of the present invention may be a flexible substrate, for example, various plastic films such as polyethylene terephthalate (PET), polyether sulfone (PES), poly A substrate made of a carbonate (Polycarbonate, PC) or a polyimide (PI) and a derivative thereof.
  • the base substrate 100 may be a rigid substrate such as a glass substrate, a stainless steel substrate, or the like.
  • step S1 includes: preparing a glass substrate; and coating a flexible substrate material, for example, a polyimide material, on the glass substrate to form a flexible substrate.
  • step S2 the method of fabricating an array substrate according to an embodiment of the present invention further includes: peeling the flexible substrate and the thin film transistor formed thereon and the at least one solar cell unit from the glass substrate.
  • the manufacturing method according to the embodiment of the present invention after step S1 and before step S2, further includes forming a buffer layer on the base substrate.
  • FIGS. 7(a)-(j) An exemplary manufacturing method of an array substrate according to an embodiment of the present invention will be described below with reference to FIGS. 7(a)-(j).
  • a top gate type thin film transistor is taken as an example and the area and film of the solar cell unit are continuously shown. The area where the transistor is located, but there may be other components in the middle of the two, which are not shown for the sake of brevity.
  • Step S11 preparing a substrate 100, the substrate substrate 100 includes a display area 102 and a peripheral area 101 surrounding the display area 102;
  • Step S12 depositing a semiconductor material layer 110 on the base substrate 100, as shown in FIG. 7(a), and then forming a semiconductor layer 120 by a first patterning process, wherein the semiconductor layer 120-1 of the thin film transistor region A1 and the solar cell
  • the semiconductor layers 120-2 of the cell region A2 are not connected to each other as shown in FIG. 7(b);
  • Step S13 the P-type/N-type impurity is doped to the semiconductor layer 120-1 of the thin film transistor region A1 by using the first mask on the base substrate 100 obtained after the completion of the step S12 to form the intermediate doped portion 132, and simultaneously to the solar energy
  • the semiconductor layer 120-2 of the battery cell region A2 is doped with the same type of P-type/N-type impurities to form a P-type/N-type semiconductor 122, as shown in FIG. 7(c);
  • Step S14 sequentially depositing a gate insulating layer 14 and a gate metal layer 150 on the base substrate 100 after the step S13 is completed, as shown in FIG. 7(d);
  • Step S15 patterning the gate metal layer 150 by a second patterning process to form a pattern including a gate electrode 15 and a gate line (not shown) in the thin film transistor region, as shown in FIG. 7(e);
  • Step S16 using the second mask to dope the semiconductor layer 120-2 of the thin film transistor region A2 and doping N-type/P-type impurities on both sides of the intermediate doping portion 132 to form the side doping portion 131 while simultaneously feeding the solar cell
  • the undoped portion of the semiconductor layer 120-1 of the cell region A1 is doped with N-type/P-type impurities to form an N-type/P-type semiconductor 121, as shown in FIG. 7(f), here the side doped portion 131 As a thin film transistor source region and drain region.
  • the gate 15 can also be used as a doping mask;
  • Step S17 depositing an interlayer insulating layer 16 on the substrate after the step S16 is completed, and then forming two in the interlayer insulating layer and the gate insulating layer corresponding to the source region and the drain region by a third patterning process. a via 171, as shown in Figure 7(g);
  • Step S18 forming a source/drain electrode metal layer 170 on the interlayer insulating layer 16, and then forming a source electrode and a drain electrode 17 connected to the source region and the drain region 131 by a fourth patterning process, as shown in FIG. 7(h) Show.
  • a pixel electrode connected to the source electrode or the drain electrode may be formed in the thin film transistor region, and accordingly, electrodes respectively connected to the P-type semiconductor and the N-type semiconductor may be formed in the solar cell region.
  • Step S19 depositing a planarization layer 18 on the substrate after completion of step S18, and forming a via 191 over the source or drain electrode in the planarization layer to expose the source or drain electrode 17 by using a fifth patterning process, And via holes 201 and 202 corresponding to the P-type semiconductor and the N-type semiconductor are formed in the planarization layer 18, the interlayer insulating layer 16, and the gate insulating layer 15 of the solar cell unit region A1, as shown in FIG. 7(i). ;
  • Step 20 depositing a metal layer 190 on the base substrate 100 after the step 19 is completed, using the The six patterning process patterns the metal layer 190 to form an electrical connection to the pixel electrode 19 and the electrode 20 as shown in Fig. 7(j).
  • the manufacturing method is similar, except that the order of formation of the layers is slightly different, but the patterning process and the layer forming process are similar to each other.
  • the patterning process referred to in the embodiments of the present invention includes processes including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • a third embodiment of the present invention provides an organic light emitting display device including: a display panel including the array substrate according to the first embodiment and an opposite substrate opposed to the array substrate.
  • the organic light emitting display device may further include an energy storage unit configured to store electrical energy generated by the at least one solar cell unit.
  • the energy storage units are respectively connected to the two electrodes of the solar cell unit by wiring.
  • the solar cell unit can also directly supply power to the gate driver and/or the source/drain driver, such that the two electrodes do not need to be connected to the energy storage unit outside the array substrate, but only internal wiring is required for connection. can.
  • the organic light-emitting display device can realize a flexible display that is thin, lightweight, bendable, and even curlable, so that it can be applied to watches, clothing, backpacks, and the like.
  • an organic electroluminescence display device integrated with a solar cell can be realized.
  • An array substrate, a method of fabricating the same, and an organic light emitting diode display device in which at least one solar cell unit and a thin film transistor are located on the same side of a substrate substrate and formed in a plurality of pixel regions and peripheral regions
  • the solar cell can be formed by a photolithography process, and further, the solar cell and the thin film transistor are formed on the same side of the substrate, so that it can be used with the thin film transistor.
  • the same process is formed, so that the solar cell can be fabricated in the thin film transistor array substrate by utilizing the characteristics of the lithography process without increasing the process flow and the material, thereby reducing the manufacturing cost and improving the quality. Rate and make the product easy to implement.
  • the organic light emitting diode display device using the array substrate can display an organic light emitting display device and solar energy
  • the batteries are integrated together, and in particular, when the array substrate is a flexible substrate, it can also be integrated with the flexible display, thereby realizing a self-powered, self-illuminating, bendable display device.

Abstract

一种阵列基板、其制造方法以及有机发光二极管显示装置，该阵列基板(10)包括衬底基板(100)，该衬底基板(100)包括显示区域(102)以及围绕显示区域(102)的周边区域(101)，该显示区域(102)包括：彼此交叉的多条数据线(12)和多条栅线(11)，多个像素区域(21)，形成为矩阵且由形成在该衬底基板(100)上的彼此交叉的多条数据线(12)和多条栅线(11)限定，其中该多个像素区域(21)的每个中形成有薄膜晶体管(32)，进一步地，该阵列基板(10)还包括至少一个太阳能电池单元(31)，与该薄膜晶体管(32)位于该衬底基板(100)的同一侧且形成在该多个像素区域(21)和该周边区域(101)至少之一中。

Description

阵列基板、其制造方法以及有机发光二极管显示装置 技术领域
本发明的实施例涉及一种阵列基板、其制造方法以及有机发光二极管显示装置。
背景技术
有机电致发光显示器(OLED)具有主动发光、对比度高、响应速度快、轻薄等诸多优点，成为主要的新一代显示器之一。其工作原理是通过向阳极和阴极施加适当的电压，而使得位于阳极和阴极之间的有机发光层发光，从而显示图像。
太阳能电池是将太阳光能直接转换成电能的半导体器件。例如，太阳能电池可以主要分为基于硅的薄膜太阳能电池、基于化合物的薄膜太阳能电池和基于有机物的太阳能电池，其中基于硅的太阳能电池可主要分为单晶硅太阳能电池、多晶硅太阳能电池和非晶硅太阳能电池。示例性地，图1示出了多晶硅太阳能电池的截面图，如图1所示，由N型半导体2和P型半导体3形成的PN结被光照后，被束缚的高能级状态下的电子被激发而成为自由电子，自由电子在晶体内向各方向移动，当通过第一电极1和第二电极4连接到外部闭合环路，电流便产生。
随着显示技术的不断发展如何将有机电致发光显示器和太阳能电池整合在一起，成为当下高技术的主要研究方向。
发明内容
本发明的实施例提供一种阵列基板、其制造方法以及有机发光二极管显示装置，将太阳能电池单元制作在阵列基板中，由此能够降低制作成本、提高良率且使得产品易于实现。
一方面，本发明的实施例提供一种阵列基板，包括衬底基板，该衬底基板包括显示区域，包括：彼此交叉的多条数据线和多条栅线，多个像素区域，形成为矩阵且由形成在所述衬底基板上的彼此交叉的多条数据线和多条栅线 限定，其中所述多个像素区域的每个中形成有薄膜晶体管；周边区域，围绕所述显示区域，进一步地，该阵列基板还包括至少一个太阳能电池单元，与所述薄膜晶体管位于所述衬底基板的同一侧且形成在所述多个像素区域和所述周边区域至少之一中。
另一方面，本发明的实施例还提供一种上述阵列基板的制造方法，包括：准备衬底基板，该衬底基板包括：显示区域以及围绕显示区域的周边区域；在衬底基板的同一侧形成多条栅线、多条数据线、由多条栅线和数据线限定的多个像素区域、每个像素区域中的薄膜晶体管以及位于多个像素区域和周边区域至少之一中的至少一个太阳能电池单元。
再一方面，本发明的实施例还提供一种有机发光二极管显示装置，包括：如上所述的阵列基板以及与阵列基板对置的相对基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是太阳能电池的示意性工作原理图；
图2是根据本发明实施例的衬底基板的平面图；
图3是根据本发明实施例的像素区域设置有太阳能电池单元的阵列基板的示例性平面图；
图4是根据本发明实施例的太阳能电池单元的第一掺杂半导体层和薄膜晶体管的第二掺杂半导体层在同一层中的阵列基板的示意性截面图；
图5是根据本发明实施例的包括底栅型薄膜晶体管的阵列基板的示意性截面图；
图6是根据本发明实施例的PIN结构的太阳能电池单元的示意性截面图；
图7(a)-7(j)示出了根据本发明实施例的阵列基板的示例性制造方法的各步骤的截面图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明的实施例提供一种阵列基板、其制造方法以及有机发光二极管显示装置。
根据本发明实施例的阵列基板包括衬底基板，该衬底基板包括显示区域和围绕该显示区域的周边区域，其中该显示区域包括由彼此交叉的多条数据线和多条栅线限定的成矩阵分布的多个像素区域，且每个像素区域中形成有薄膜晶体管。进一步地，该阵列基板还包括至少一个太阳能电池单元，该至少一个太阳能电池单元与所述薄膜晶体管位于所述衬底基板的同一侧且形成在所述多个像素区域和所述周边区域至少之一中。由于太阳能电池设置在阵列基板中，所以太阳能电池单元可以采用光刻工艺形成，进一步地，太阳能电池与薄膜晶体管形成在衬底基板的同一侧，这样，其可以与薄膜晶体管采用相同的工艺形成，从而可以在不增加工艺流程和制作材料的前提下，通过利用光刻工艺精细化的特点，将太阳能电池单元制作在薄膜晶体管阵列基板中，由此能够降低制作成本、提高良率且使得产品易于实现。
进一步地，当阵列基板采用柔性衬底基板时，该阵列基板可以用于柔性 显示装置，从而可以实现厚度薄、重量轻、可弯折甚至可卷曲的柔性显示，使其能够应用于手表、服装、背包等穿戴产品中。尤其是，当该阵列基板应用于有机电致发光显示装置时，能够获得集成有太阳能电池的有机电致发光显示装置。
以下将结合附图对本发明实施例提供的阵列基板、其制造方法以及有机发光二极管显示装置进行详细说明，以使得本发明的技术方案更加清楚。
第一实施例
如图2所示，阵列基板10包括衬底基板100，衬底基板100包括显示区域102和围绕显示区域102的周边区域101，其中如图3所示，显示区域102包括彼此交叉的多条数据线12和多条栅线11，将显示区域102划分为多个像素区域21，在每个像素区域21中设置有薄膜晶体管32。进一步地，衬底基板100上还形成有至少一个太阳能电池单元，该至少一个太阳能电池单元与薄膜晶体管32位于衬底基板100的同一侧，且形成在多个像素区域21和周边区域101至少之一中。
在本实施例中，至少一个太阳能电池单元可以设置在像素区域21中或者周边区域101中，或者可以设置在像素区域21和周边区域101二者中。例如，如果有一个太阳能电池单元，则其可以设置在一个像素区域21或周边区域101中；如果阵列基板10包括两个或两个以上的太阳能电池单元，则太阳能电池单元可以全部设置在像素区域21中或者全部设置在周边区域101中，或者一部分设置在像素区域中而剩余部分设置在周边区域101中。
进一步地，每个像素区域中可以仅设置有一个太阳能电池单元，也可以设置两个或更多太阳能电池单元，本领域的技术人员可以在兼顾开口率等其他产品特征的前提下适当选择，本发明的实施例不做具体限定。
图3示出了根据本发明实施例的像素区域设置有太阳能电池单元的阵列基板的示例性平面图，其中仅示出了三个像素区域，每个像素区域中设置有一个太阳能电池单元31，为了图示方便，太阳能电池单元31和薄膜晶体管32由带阴影的方框表示，但是这并非是指二者就是方框形状的，方框仅表示的是二者的设置区域。由图可见，太阳电池单元31和薄膜晶体管32设置在不同的区域，示例性地，为了不减小有效显示区域，太阳能电池单元31可以设置在对应于黑矩阵的区域、对应于栅线或数据线或者对应于栅线和数据线 二者的区域。
示例性地，每个太阳能电池单元31可以包括第一掺杂半导体层，薄膜晶体管32可以包括第二掺杂半导体层，而且第一掺杂半导体层和所述第二掺杂半导体层位于同一层中。
可选地，太阳能电池单元31可以为PN结构，第一掺杂半导体层可以包括P型半导体和N型半导体，该P型半导体和N型半导体位于同一层中。需要说明的是，P型半导体即在半导体材料，例如，硅晶体中掺杂三价元素，例如，硼等形成的空穴浓度远大于自由电子浓度的掺杂半导体；N型半导体即在半导体材料，例如，硅晶体中掺杂五价元素，例如，磷、砷、锑等而形成的电子浓度远大于空穴浓度的掺杂半导体。
可选地，薄膜晶体管32的第二掺杂半导体层可以包括形成在同一层中的中间掺杂部分和位于所述中间掺杂部分两侧的侧掺杂部分，其中中间掺杂部分和所述侧掺杂部分的掺杂类型相反，也就是，中间掺杂部分为P型则相应地，侧掺杂部分为N型，中间掺杂部分为N型则相应地，侧掺杂部分为P型。
图4示例性地示出了太阳能电池单元31的第一掺杂半导体层和薄膜晶体管32的第二掺杂半导体层在同一层中的阵列基板的截面结构图，其中(a)示出了太阳能电池单元31所在区域，(b)示出了薄膜晶体管32所在区域，这里以顶栅型薄膜晶体管为例。如图4所示，第一掺杂半导体层12和第二掺杂半导体层13在衬底基板100上设置在同一层中，第一掺杂半导体层12包括P型半导体121和N型半导体122，第二掺杂半导体层13包括中间掺杂部分132和位于中间掺杂部分132两侧的侧掺杂部分131，其中侧掺杂部分131示出为P型半导体，中间掺杂部分132为N型半导体，这里仅是示例，当然侧掺杂部分131也可以为N型半导体，对应地，中间掺杂部分132为P型半导体。
进一步地，在图4给出的顶栅型薄膜晶体管中，栅极绝缘层14覆盖形成有第一掺杂半导体层12和第二掺杂半导体层13的衬底基板100，栅极15设置在栅极绝缘层14上且对应于中间掺杂部分132，层间绝缘层16覆盖栅极15；进一步地，源电极和漏电极17设置在层间绝缘层16上，且源电极和漏电极17分别通过栅极绝缘层14和层间绝缘层16中形成的通孔171电连接到 侧掺杂部分131。
进一步地，在薄膜晶体管32所在区域，平坦化层18覆盖源电极和漏电极17，然后，像素电极19设置在平坦化层18上且通过平坦化层18中的通孔191电连接到源电极或漏电极17。相对应地，在太阳能电池单元31所在区域，分别通过栅极绝缘层14、层间绝缘层16和平坦化层18中形成的通孔201和202连接到P型半导体121和N型半导体122的两个电极20设置在平坦化层18之上。
为了图示方便，图4中将太阳能电池单元所在区域和薄膜晶体管所在区域分离地示出，然而在实际中，太阳能电池单元所在区域和薄膜晶体管所在区域之间可以设有其他组件或者没有其他组件，例如，在太阳能电池单元设置在周边区域时，二者之间会设置其他部件，这里为了图示简洁而没有示出，但如果二者之间没有其他组件，则图4(a)和图4(b)直接连接起来合成为一个图，本领域的技术人员可以根据实际需要而设置，本发明的实施例将不会其进行限定。
进一步地，在图4中，第一掺杂半导体层12上方被示出为设置有栅极绝缘层14、层间绝缘层16和平坦化层18，这仅是示例，在实际应用中，本领域的技术人员可以根据实际需要而设置各层在第一掺杂半导体层12上方，例如，可以仅形成平坦化层，或者可以形成有平坦化层和层间绝缘层而没有栅极绝缘层。
还需要注意的是，太阳能电池单元的两个电极20可以设置在栅极绝缘层上，或者可以设置在栅极绝缘层和层间绝缘层上，相应地可以仅在栅极绝缘层中形成通孔，或者可以在栅极绝缘层和层间绝缘层中形成通孔，本发明的实施例并不对此进行限定，本领域的技术人员可以根据实际需要进行选择。
此外，本发明实施例中的薄膜晶体管还可以为底栅型薄膜晶体管，也就是，栅极形成在薄膜晶体管的第二掺杂半导体层的下方。图5示出了包括底栅型薄膜晶体管的阵列基板的示意性截面图，其中(a)是太阳能电池单元所在区域的截面图，(b)是薄膜晶体管所在区域的截面图，如图5所示，栅极15和栅极绝缘层14顺次形成在衬底基板100上，第一掺杂半导体层12和第二掺杂半导体层13形成在栅极绝缘层14上，中间掺杂部分对应于栅极15，源电极和漏电极17通过层间绝缘层16中的通孔连接到侧掺杂部分131。进 一步地，薄膜晶体管所在区域还设置有像素电极19，其通过平坦化层18中的通孔191连接到源电极或漏电极17，太阳能电池单元所在区域还设置有两个电极20，分别通过平坦化层18和层间绝缘层16中的通孔201和202连接到P型或N型半导体121以及N型或P型半导体122。为了简洁，这里着重描述了与图4所示出的不同之处，相同之处便不再进行赘述。
类似地，第一掺杂半导体层12上方可以仅设置有平坦化层18，相应地，电极20仅通过平坦化层中的通孔而连接到第一掺杂半导体层12。
这里需要注意的是，连接到第一掺杂半导体层12的电极20也可以设置在其他位置处，例如，设置在第一掺杂半导体层下方，本发明的实施例并不对此进行限定，只要能实现电连接功能即可。类型地，薄膜晶体管的源电极和漏电极的位置也可以根据实际需要而进行设置，例如，位于第二掺杂半导体层下方等，本发明的实施例并不对此进行限定。
示例性地，第一掺杂半导体层和所述第二掺杂半导体层也可以不位于同一层而只是位于衬底基板100的同侧，例如，太阳能电池单元设置在周边区域时，可以与阵列基板的周边驱动电路叠置或者与阵列基板的周边驱动电路平行设置。
可选地，太阳能电池单元31还可以为PIN结构，其所包括的第一掺杂半导体层还可以包括设置在P型半导体与N型半导体之间的本征半导体。例如，如图6所示，本征半导体123位于P型半导体121与N型半导体122之间。
可选地，太阳能电池单元31还可以为串联的PN或PIN结构，第一掺杂半导体层可以包括交替设置的多个P型半导体和多个N型半导体，且所述多个P型半导体和所述多个N型半导体形成在同一层中；进一步地，第一掺杂半导体层还可以包括多个本征半导体，每个本征半导体设置在相邻的所述P型半导体与所述N型半导体之间。
示例性地，衬底基板100可以为可弯曲的柔性基板，例如，各种塑料膜，如聚对苯二甲酸乙二醇酯(PET)、聚醚砜(polyether sulfone，PES)、聚碳酸酯(Polycarbonate，PC)或聚酰亚胺(PI)及其衍生物等制成的基板。或者，衬底基板100可以刚性基板，例如，玻璃基板、不锈钢基板等。
示例性地，本发明实施例的第一和第二掺杂半导体层可以为掺杂多晶硅 层、掺杂单晶硅层等。
可选地，根据本发明实施例的阵列基板还可以包括位于衬底基板与其上所形成的各功能层之间的缓冲层。
根据第一实施例的阵列基板，通过将太阳能电池单元设置其中，例如，将太阳能电池单元与薄膜晶体管形成在衬底基板的同侧，这样，其可以与薄膜晶体管采用相同的工艺形成，从而可以在不增加工艺流程和制作材料的前提下，通过利用光刻工艺精细化的特点，将太阳能电池单元制作在薄膜晶体管阵列基板中，由此能够降低制作成本、提高良率且使得产品易于实现。
第二实施例
本发明的第二实施例提供了根据第一实施例的阵列基板的制造方法，包括：步骤S1，准备衬底基板，其中所述衬底基板包括：显示区域以及围绕所述显示区域的周边区域；以及步骤S2，在衬底基板的同一侧形成多条栅线、多条数据线、由多条栅线和数据线限定的多个像素区域、每个像素区域中的薄膜晶体管以及位于多个像素区域和周边区域至少之一中的至少一个太阳能电池单元。
示例性地，每个太阳能电池单元可以包括第一掺杂半导体层，薄膜晶体管可以包括第二掺杂半导体层，而且第一掺杂半导体层和所述第二掺杂半导体层位于同一层中。这样，步骤S2可以包括：通过构图工艺和掺杂工艺同时形成第一掺杂半导体层和第二掺杂半导体层。
进一步地，第一掺杂半导体层包括：P型半导体和N型半导体，第二掺杂半导体层包括中间掺杂部分和位于中间掺杂部分两侧且掺杂类型与中间掺杂部分相反的侧掺杂部分，通过构图工艺和掺杂工艺同时形成第一掺杂半导体层和第二掺杂半导体层可以包括：
在衬底基板上形成半导体材料层，利用第一构图工艺形成半导体层，其中薄膜晶体管区域和至少一个太阳能电池单元区域的半导体层彼此不连接；
示例性地，在本发明的实施例中，半导体层可以为多晶硅层或单晶硅层，当半导体层为多晶硅层时，在衬底基板上形成半导体材料层可以包括：在衬底基板上沉积非晶硅层；以及利用结晶化方法，例如，准分子激光退火(ELA,Excimer-Laser Annealing)或固相结晶化(SPC,Solid Phase Crystallization)等方法，使非晶硅层结晶形成多晶硅层。
在完成以上步骤后获得的衬底基板上利用第一掩模板向薄膜晶体管区域的半导体层掺杂P型/N型杂质而形成中间掺杂部分，同时向太阳能电池单元区域的半导体层掺杂P型/N型的杂质而形成P型/N型半导体；
在完成以上步骤之后的衬底基板上依次沉积栅极绝缘层和栅极金属层；
利用第二构图工艺图案化所述栅极金属层而在薄膜晶体管区域形成包括栅极、栅线的图形；
利用第二掩模板向薄膜晶体管区域的半导体层且在中间掺杂部分的两侧掺杂N型/P型的杂质而形成侧掺杂部分，同时向太阳能电池单元区域的半导体层的未进行掺杂的部分掺杂N型/P型的杂质而形成N型/P型半导体。
示例性地，根据本发明实施例的衬底基板可以是柔性基板，例如，各种塑料膜，如聚对苯二甲酸乙二醇酯(PET)、聚醚砜(polyether sulfone，PES)、聚碳酸酯(Polycarbonate，PC)或聚酰亚胺(PI)及其衍生物等制成的基板。或者，衬底基板100可以刚性基板，例如，玻璃基板、不锈钢基板等。
在衬底基板是柔性基板的情况下，步骤S1包括：准备玻璃基板；以及在玻璃基板上涂敷柔性衬底材料，例如，聚酰亚胺材料而形成柔性衬底。而且，在步骤S2之后，根据本发明实施例的阵列基板的制造方法还包括：将柔性衬底以及形成在其上的薄膜晶体管和至少一个太阳能电池单元从玻璃基板剥离。
进一步地，根据本发明实施例的制造方法，在步骤S1之后且在步骤S2之前，还包括：在衬底基板上形成缓冲层。
下面结合图7(a)-(j)对根据本发明实施例的阵列基板的示例性制造方法进行描述，这里以顶栅型薄膜晶体管为例且连续地示出了太阳能电池单元所在区域和薄膜晶体管所在区域，但二者的中间区域也可能有其他元件，为了简洁，而没有示出。
步骤S11，准备衬底基板100，衬底基板100包括显示区域102和围绕显示区域102的周边区域101；
步骤S12，在衬底基板100上沉积半导体材料层110，如图7(a)所示，然后，利用第一构图工艺形成半导体层120，其中薄膜晶体管区域A1的半导体层120-1和太阳能电池单元区域A2的半导体层120-2彼此不连接，如图7(b)所示；
步骤S13，在完成步骤S12之后获得的衬底基板100上利用第一掩模板向薄膜晶体管区域A1的半导体层120-1掺杂P型/N型杂质而形成中间掺杂部分132，同时向太阳能电池单元区域A2的半导体层120-2掺杂相同类型的P型/N型的杂质而形成P型/N型半导体122，如图7(c)所示；
步骤S14，在完成步骤S13之后的衬底基板100上依次沉积栅极绝缘层14和栅极金属层150，如图7(d)所示；
步骤S15，利用第二构图工艺图案化栅极金属层150而在所述薄膜晶体管区域形成包括栅极15、栅线(未示出)的图形，如图7(e)所示；
步骤S16，利用第二掩模板向薄膜晶体管区域A2的半导体层120-2且在中间掺杂部分132的两侧掺杂N型/P型的杂质而形成侧掺杂部分131，同时向太阳能电池单元区域A1的半导体层120-1的未进行掺杂的部分掺杂N型/P型的杂质而形成N型/P型半导体121，如图7(f)所示，这里侧掺杂部分131作为薄膜晶体管源极区域和漏极区域。示例性地，在形成侧掺杂部分时，也可以以栅极15作为掺杂掩模；
步骤S17，在完成步骤S16之后的衬底基板上沉积层间绝缘层16，然后利用第三构图工艺在层间绝缘层以及栅极绝缘层中对应于源极区域和所述漏极区域形成两个过孔171，图7(g)所示；
步骤S18，在层间绝缘层16上形成源漏电极金属层170，然后利用第四构图工艺形成连接到源极区域和漏极区域131的源电极和漏电极17，如图7(h)所示。
进一步地，还可以在薄膜晶体管区域形成连接到源电极或漏电极的像素电极，相应地，可以在太阳能电池单元区域形成分别连接到P型半导体和N型半导体的电极。
示例性地，在上述步骤S18之后，还包括以下步骤：
步骤S19，在完成步骤S18之后的衬底基板上沉积平坦化层18，且在平坦化层中利用第五构图工艺在源电极或漏电极上方形成过孔191以暴露源电极或漏电极17，且在太阳能电池单元区域A1的平坦化层18、层间绝缘层16和栅极绝缘层15中形成对应于P型半导体和N型半导体的过孔201和202，如图7(i)所示；
步骤20，在完成步骤19之后的衬底基板100上沉积金属层190，利用第 六构图工艺图案化金属层190，从而形成电连接到像素电极19以及电极20，如图7(j)所示。
以上仅是以顶栅型薄膜晶体管为例，对于底栅型薄膜晶体管，其制造方法类似，只是各层的形成顺序略有差异，但是构图工艺和层形成工艺都类似这里不进行赘述。
需要注意的是，本发明实施例所指的构图工艺包括通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。
第三实施例
本发明的第三实施例提供一种有机发光显示装置，包括：显示面板，包括根据第一实施例的阵列基板以及与阵列基板对置的相对基板。
进一步地，该有机发光显示装置还可以包括储能单元，其被构造为存储至少一个太阳能电池单元产生的电能。
示例性地，该储能单元的分别通过布线连接到太阳能电池单元的两个电极。
示例性地，太阳能电池单元也可以直接为栅极驱动器和/或源漏极驱动器提供电能，这样，其两个电极不需要连接到阵列基板外部的储能单元，而只需要内部布线进行连接即可。
示例性地，当该阵列基板具有柔性衬底基板时，该有机发光显示装置可以实现厚度薄、重量轻、可弯折甚至可卷曲的柔性显示，使其能够应用于手表、服装、背包等穿戴产品中。而且能够实现集成有太阳能电池的有机电致发光显示装置。
根据本发明实施例的阵列基板、其制造方法以及有机发光二极管显示装置，在该阵列基板中，至少一个太阳能电池单元与薄膜晶体管位于衬底基板的同一侧且形成在多个像素区域和周边区域至少之一中，由于太阳能电池设置在阵列基板中，所以太阳能电池单元可以采用光刻工艺形成，进一步地，太阳能电池与薄膜晶体管形成在衬底基板的同一侧，这样，其可以与薄膜晶体管采用相同的工艺形成，从而可以在不增加工艺流程和制作材料的前提下，通过利用光刻工艺精细化的特点，将太阳能电池单元制作在薄膜晶体管阵列基板中，由此能够降低制作成本、提高良率且使得产品易于实现。而且，采用该阵列基板的有机发光二极管显示装置能够将有机发光显示装置与太阳能 电池整合到一起，尤其是，当该阵列基板采用柔性衬底基板时，还能够与柔性显示整合到一起，从而实现了自供电、自发光、可弯折的显示装置。
以上所述，仅为本发明的具体实施方式，但本发明实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明实施例的保护范围之内。
本申请要求于2015年5月18日递交的中国专利申请第201510253423.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (22)

  1. 一种阵列基板，包括：
    衬底基板，包括：
    显示区域，包括：
    彼此交叉的多条数据线和多条栅线，
    多个像素区域，形成为矩阵且由形成在所述衬底基板上的彼此交叉的多条数据线和多条栅线限定，其中所述多个像素区域的每个中形成有薄膜晶体管；
    周边区域，围绕所述显示区域；以及
    至少一个太阳能电池单元，与所述薄膜晶体管位于所述衬底基板的同一侧且形成在所述多个像素区域和所述周边区域至少之一中。
  2. 根据权利要求1所述的阵列基板，其中所述至少一个太阳能电池单元的每个包括第一掺杂半导体层，所述薄膜晶体管包括第二掺杂半导体层，所述第一掺杂半导体层和所述第二掺杂半导体层位于同一层中。
  3. 根据权利要求2所述的阵列基板，其中所述至少一个太阳能电池单元设置在所述多个像素区域中。
  4. 根据权利要求2所述的阵列基板，其中所述至少一个太阳能电池单元设置在所述周边区域中。
  5. 根据权利要求2所述的阵列基板，其中所述太阳能电池单元的数量为两个或两个以上，所述多个像素区域至少之一和所述周边区域中均设置有所述太阳能电池单元。
  6. 根据权利要求3或5所述的阵列基板，其中一个所述像素区域中设置有一个所述太阳能电池单元。
  7. 根据权利要求2所述的阵列基板，其中所述第一掺杂半导体层包括P型半导体和N型半导体，且所述P型半导体和所述N型半导体形成在同一层中。
  8. 根据权利要求7所述的阵列基板，其中所述第一掺杂半导体层还包括本征半导体，设置在所述P型半导体与所述N型半导体之间。
  9. 根据权利要求2所述的阵列基板，其中所述第一掺杂半导体层包括交 替设置的多个P型半导体和多个N型半导体，且所述多个P型半导体和所述多个N型半导体形成在同一层中。
  10. 根据权利要求9所述的阵列基板，其中所述第一掺杂半导体层还包括多个本征半导体，所述多个本征半导体的每个设置在相邻的所述P型半导体与所述N型半导体之间。
  11. 根据权利要求7-10中任一项所述的阵列基板，其中所述第二掺杂半导体层包括：形成在同一层中的中间掺杂部分和位于所述中间掺杂部分两侧的侧掺杂部分，所述中间掺杂部分和所述侧掺杂部分的掺杂类型相反。
  12. 根据权利要求1或2所述的阵列基板，其中所述衬底基板为柔性基板或刚性基板。
  13. 根据权利要求2所述的阵列基板，其中所述第一和第二掺杂半导体层为掺杂多晶硅层或掺杂单晶硅层。
  14. 一种阵列基板的制造方法，包括：
    准备衬底基板，其中所述衬底基板包括：显示区域以及围绕所述显示区域的周边区域；
    在所述衬底基板的同一侧形成多条栅线、多条数据线、由所述多条栅线和数据线限定的多个像素区域、每个所述像素区域中的薄膜晶体管以及位于所述多个像素区域和所述周边区域至少之一中的至少一个太阳能电池单元。
  15. 根据权利要求14所述的制造方法，其中所述至少一个太阳能电池单元的每个包括第一掺杂半导体层，所述薄膜晶体管包括第二掺杂半导体层，所述第一掺杂半导体层和所述第二掺杂半导体层位于同一层中，
    其中在所述衬底基板的同一侧形成多条栅线、多条数据线、由所述多条栅线和数据线限定的多个像素区域、每个所述像素区域中的薄膜晶体管以及位于所述多个像素区域和所述周边区域至少之一中的至少一个太阳能电池单元，包括：
    通过构图工艺和掺杂工艺同时形成所述第一掺杂半导体层和所述第二掺杂半导体层。
  16. 根据权利要求15所述的制造方法，其中所述第一掺杂半导体层包括：P型半导体和N型半导体，所述第二掺杂半导体层包括中间掺杂部分和位于所述中间掺杂部分两侧且掺杂类型与所述中间掺杂部分相反的侧掺杂部分，
    在所述衬底基板的同一侧形成多条栅线、多条数据线、由所述多条栅线和数据线限定的多个像素区域、每个所述像素区域中的薄膜晶体管以及位于所述多个像素区域和所述周边区域至少之一中的至少一个太阳能电池单元，包括：
    步骤1，在所述衬底基板上形成半导体材料层，利用第一构图工艺形成半导体层，其中所述薄膜晶体管区域和所述至少一个太阳能电池单元区域的所述半导体层彼此不连接；
    步骤2，在完成步骤1之后获得的所述衬底基板上利用第一掩模板向所述薄膜晶体管区域的半导体层掺杂P型/N型杂质而形成所述中间掺杂部分，同时向太阳能电池单元区域的半导体层掺杂所述P型/N型的杂质而形成P型/N型半导体；
    步骤3，在完成步骤2之后的衬底基板上依次沉积栅极绝缘层和栅极金属层；
    步骤4，利用第二构图工艺图案化所述栅极金属层而在所述薄膜晶体管区域形成包括所述栅极、所述栅线的图形；
    步骤5，利用第二掩模板向所述薄膜晶体管区域的半导体层且在所述中间掺杂部分的两侧掺杂N型/P型的杂质而形成所述侧掺杂部分，同时向所述太阳能电池单元区域的半导体层的未进行掺杂的部分掺杂N型/P型的杂质而形成所述N型/P型半导体。
  17. 根据权利要求16所述的制造方法，其中所述半导体层为多晶硅层，在所述衬底基板上形成所述半导体层包括：
    在所述衬底基板上沉积非晶硅层；以及
    利用结晶化方法使所述非晶硅层结晶形成所述多晶硅层。
  18. 根据权利要求14所述的制造方法，其中所述准备衬底基板包括：
    准备玻璃基板；
    在所述玻璃基板上涂敷柔性衬底材料而形成柔性衬底，
    而且，在所述衬底基板的同一侧形成所述多条栅线、所述多条数据线、位于所述多个像素区域每个中的薄膜晶体管以及位于所述多个像素区域和所述周边区域至少之一中的至少一个太阳能电池单元之后，所述制造方法还包括：
    将所述柔性衬底以及形成在其上的所述薄膜晶体管和所述至少一个太阳能电池单元从所述玻璃基板剥离。
  19. 一种有机发光二极管显示装置，包括：
    阵列基板，包括：
    衬底基板，包括：
    显示区域，包括：
    彼此交叉的多条数据线和多条栅线，
    多个像素区域，形成为矩阵且由形成在所述衬底基板上的彼此交叉的多条数据线和多条栅线限定，其中所述多个像素区域的每个中形成有薄膜晶体管；
    周边区域，围绕所述显示区域；以及
    至少一个太阳能电池单元，与所述薄膜晶体管位于所述衬底基板的同一侧且形成在所述多个像素区域和所述周边区域至少之一中；以及
    相对基板，与所述阵列基板对置。
  20. 根据权利要求19所述的有机发光二极管显示装置，还包括：
    储能单元，构造为存储所述至少一个太阳能电池单元产生的电能。
  21. 根据权利要求19所述的有机发光二极管显示装置，其中所述至少一个太阳能电池单元的每个包括第一掺杂半导体层，所述薄膜晶体管包括第二掺杂半导体层，所述第一掺杂半导体层和所述第二掺杂半导体层位于同一层中。
  22. 根据权利要求20所述的有机发光二极管显示装置，其中所述第一掺杂半导体层包括P型半导体和N型半导体，且所述P型半导体和所述N型半导体形成在同一层中，所述太阳能电池单元还包括分别连接到所述P型半导体和所述N型半导体的第一电极和第二电极，所述储能单元分别电连接到所述第一电极和所述第二电极。
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