WO2015143836A1 - 阵列基板及其制备方法和显示面板 - Google Patents

阵列基板及其制备方法和显示面板 Download PDF

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Publication number
WO2015143836A1
WO2015143836A1 PCT/CN2014/085498 CN2014085498W WO2015143836A1 WO 2015143836 A1 WO2015143836 A1 WO 2015143836A1 CN 2014085498 W CN2014085498 W CN 2014085498W WO 2015143836 A1 WO2015143836 A1 WO 2015143836A1
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Prior art keywords
layer
electrode
solar cell
cell structure
array substrate
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PCT/CN2014/085498
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English (en)
French (fr)
Inventor
张家祥
郭建
陈旭
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/436,517 priority Critical patent/US9620578B2/en
Publication of WO2015143836A1 publication Critical patent/WO2015143836A1/zh

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    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display panel. Background technique
  • an organic light-emitting diode (OLED) display device does not require a backlight module, but is fabricated using a very thin light-emitting structure and a glass substrate.
  • the light emitting structure of the OLED includes a light emitting material layer, an electron transport layer, and a hole transport layer, and an electron transport layer and a hole transport layer are respectively disposed on an upper side and a lower side of the light emitting material layer, when an electric current passes In the case of the luminescent material layer, the luminescent structure emits light. Since the OLED display device eliminates the backlight module, the OLED display device can be made lighter, thinner, has a larger viewing angle, and can significantly save power. Therefore, the OLED display device is gaining popularity.
  • At least one embodiment of the present invention provides an array substrate including a substrate substrate, scan lines arranged on the substrate substrate, data lines, and divided by the scan lines and data lines a pixel unit arranged in a matrix, in which a thin film transistor, a common electrode, and a pixel electrode are disposed, wherein the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain; a light emitting structure of the source, a solar cell structure, and a power output line; wherein the light emitting structure is disposed between the common electrode and the pixel electrode, and the solar cell structure is disposed between the base substrate and the common electrode,
  • the power output line is disposed in the same layer as the common electrode, and is electrically connected to the solar cell structure to transmit the electrical energy generated by the solar cell structure to the external circuit.
  • the light emitting structure includes: an oppositely disposed anode and cathode, and a setting a layer of luminescent material between the anode and the cathode; wherein the cathode is served by a common electrode located below the luminescent structure.
  • the thin film transistor is a bottom gate thin film transistor; the gate is disposed in the same layer as the solar cell structure; the gate insulating layer is located above the layer where the gate and the solar cell structure are located, and covers the The gate and the solar cell structure.
  • the array substrate further includes a barrier layer disposed over the active layer below the source and drain layers. In one example, a position of the barrier layer corresponding to the source and the drain is respectively provided with a first via and a second via; wherein the source passes through the first via and the active The layer is electrically connected, and the drain is electrically connected to the active layer through the second via hole;
  • a third via is disposed in the barrier layer and the gate insulating layer corresponding to the power output line, and the positive electrode is electrically connected to the power output line through the third via.
  • the thin film transistor is a top gate thin film transistor; wherein the active layer is disposed in the same layer as the solar cell structure.
  • the array substrate further includes a barrier layer disposed above the source and drain layers, below the active layer.
  • a position corresponding to the source and the drain in the barrier layer is respectively provided with a first via and a second via; wherein the source passes through the first via and is active The layer is electrically connected, and the drain is electrically connected to the active layer through the second via hole;
  • a fourth via hole is disposed in the barrier layer at a position corresponding to the power output line, and the positive electrode is electrically connected to the power output line through the fourth via.
  • the array substrate further includes a passivation layer over the thin film transistor.
  • At least one embodiment of the present invention also provides a display panel, the display panel comprising the array substrate described above.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, the method comprising the steps of forming a scan line, a data line, a common electrode, a pixel electrode, and a thin film transistor, wherein the thin film transistor includes a gate and a gate An insulating layer, a source, a drain, and an active layer, the common electrode, the pixel electrode, and the thin film transistor are each formed in a plurality of pixel regions surrounded by the scan line and the data line; and on the base substrate a step of forming a light emitting structure, a solar cell structure, and a power output line above;
  • the light emitting structure is disposed between the common electrode and the pixel electrode;
  • the solar cell structure is disposed between the array substrate and the common electrode; and the power output line is disposed in the same layer as the common electrode, and the solar cell structure Electrically connecting, transferring electrical energy generated by the solar cell structure to an external circuit.
  • the light emitting structure includes: an oppositely disposed anode and cathode, and a layer of luminescent material disposed between the anode and the cathode; wherein the cathode is served by a common electrode located below the light emitting structure .
  • the source and the drain are formed over the pattern including the active layer and the source and the drain are disposed in the same layer.
  • the method further includes:
  • a pattern including a barrier layer is formed over the pattern including the active layer; the barrier layer is located under the layer where the source and drain are located.
  • a pattern including the gate is formed over the gate insulating layer.
  • the method further includes:
  • a pattern including a barrier layer is formed over the pattern including the gate, the barrier layer being located above the source and the drain layer, below the active layer.
  • the method further includes: forming a passivation layer over the thin film transistor.
  • FIG. 1 is a schematic plan view showing a planar structure of an array substrate according to Embodiment 1 of the present invention
  • 2 is a cross-sectional structural view of the array substrate along the direction of the broken line AB in FIG. 1;
  • FIG. 3 is a schematic cross-sectional structural view of a light emitting structure
  • FIG. 4 is a schematic plan view showing a planar structure of an array substrate according to Embodiment 2 of the present invention.
  • 5-12 are schematic diagrams showing a manufacturing process of an array substrate according to Embodiment 1 of the present invention.
  • FIGS. 13-23 are schematic diagrams showing a manufacturing process of an array substrate according to Embodiment 2 of the present invention. detailed description
  • the solar cell and the OLED display portion are usually two independent parts, so the manufacturing process of the solar cell and the OLED display device are separately performed; due to the manufacturing process of the OLED display device and The fabrication process of solar cells requires multiple patterning processes, making the fabrication of OLED display devices powered by solar cells more complicated; and, due to the increase in patterning processes, the production cost of OLED display devices powered by solar cells is also increased.
  • Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display panel, which are used to combine the fabrication of a solar cell structure with the fabrication of an OLED, and realize a combination of a solar energy technology and an OLED display technology to solve the prior art. Due to the independent existence of the solar structure and the OLED structure, the manufacturing process is complicated and the production cost is high.
  • FIG. 1 is a FIG. 2 is a schematic cross-sectional structural view of the array substrate along the AB direction of FIG. 1 .
  • the array substrate includes a base substrate 11, scan lines 12, data lines 13 interleaved on the base substrate 11, and the scan lines 12 and data lines 13
  • the divided pixel units arranged in a matrix in which the thin film transistor 15, the common electrode 16, and the pixel electrode 17 are disposed.
  • the thin film transistor 15 includes a gate electrode 151, a gate insulating layer 152, an active layer 153, a source electrode 154, and a drain electrode 155.
  • the array substrate further includes: a light emitting structure 18 for providing a backlight, a solar cell structure 19, and a power output line 20.
  • the light emitting structure 18 is disposed between the common electrode 16 and the pixel electrode 17.
  • the solar cell structure 19 is disposed between the base substrate 11 and the common electrode 16.
  • the power output line 20 is disposed in the same layer as the common electrode 16 and is electrically connected to the solar cell structure 19 to transfer the electrical energy generated by the solar cell structure 19 to an external circuit. Since the power output line 20 is disposed in the same layer as the common electrode 16, the power output line 20 and the common electrode 16 can be formed by one patterning process during the manufacturing process, which is advantageous for the manufacturing process and reduces the production cost.
  • the light emitting structure 18 includes: an oppositely disposed anode 32 and a cathode, and a luminescent material layer 31 disposed between the anode 32 and the cathode.
  • the cathode is acted upon by a common electrode 16 located below the light emitting structure.
  • the common electrode 16 is located below the light emitting structure 18 and serves as a cathode of the light emitting structure 18, which is advantageous for reducing the manufacturing process and reducing the production cost.
  • the anode 32 and the common electrode 16 for serving as a cathode of the light emitting structure 18 are commonly used to supply a driving voltage to the light emitting structure such that the light emitting structure produces white light.
  • the light emitting structure 18 further includes: an electron transport layer 33, a hole transport layer 34, a first barrier layer 35, and a second barrier layer 36.
  • An electron transport layer 33 is located between the common electrode 16 and the luminescent material layer 31 for introducing electrons into the luminescent material layer 31.
  • a hole transport layer 34 is located between the luminescent material layer 31 and the anode 32 for introducing holes into the luminescent material layer 31.
  • a first barrier layer 35 is located between the electron transport layer 33 and the luminescent material layer 31 for blocking the transport of holes to the common electrode 16.
  • a second barrier layer 36 is located between the hole transport layer 34 and the luminescent material layer 31 for blocking electron transport to the anode 32.
  • the luminescent material layer 31 includes: an orange phosphor layer 31a above the first barrier layer 35, a blue phosphor layer 31b above the orange phosphor layer 31a, and The green phosphor layer 31c above the blue phosphor layer 31b.
  • the light emitting structure 18 When the light emitting structure 18 is in operation, electrons are injected from the common electrode 16, holes are injected from the anode 32, electrons are introduced into the luminescent material layer 31 through the electron transport layer 33, and holes are transported through the holes.
  • the layer 34 is introduced into the luminescent material layer 31, and electrons and holes recombine in the luminescent material layer 31 to form singlet excitons and triplet excitons.
  • the energy is released in the form of photons and thermal energy, and some of the photons are used as backlights to provide light for image display.
  • blue fluorescent layer 31b when the singlet excitons transition from the excited state to the ground state, blue fluorescence is emitted.
  • orange phosphor layer 31a and the green phosphor layer 31c the triplet excitons move from the ground state to the excited state. During the transition, green phosphorescence and orange phosphorescence are emitted, and the blue fluorescence is combined with green phosphorescence and orange phosphorescence to form white light.
  • the solar cell structure 19 includes: a positive electrode 191 and a negative electrode 192 disposed opposite to each other, and an intrinsic silicon material layer 193 disposed between the positive electrode 191 and the negative electrode 192, disposed on the positive electrode 191 and the intrinsic silicon material layer 193 a p-type silicon material layer 194 between, and an n-type silicon material layer 195 disposed between the negative electrode 192 and the intrinsic silicon material layer 193;
  • the p-type silicon material layer 194 and the n-type silicon material layer 195 form a PN junction.
  • holes of the n-type silicon material layer 195 move toward the p-type silicon material layer 194, and electrons of the p-type silicon material layer 194 move toward the n-type silicon material.
  • the layer 195 is moved to form a current from the n-type silicon material layer 195 to the p-type silicon material layer 194, and then an electric potential is formed in the PN junction, and is connected to the external circuit through the positive electrode 191 and the negative electrode 192 to form a loop.
  • the thin film transistor 15 is a bottom gate thin film transistor.
  • the gate electrode 151 of the bottom gate thin film transistor is disposed in the same layer as the scan line 12, and is located above the base substrate 11, and the scan line 12 is used to provide a scan signal to the gate electrode 151.
  • the gate electrode 151 is made of the same material as the scan line 12 .
  • the materials used are generally non-transparent metals such as chromium (Cr), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), and copper (Cu), and alloys thereof.
  • the gate insulating layer 152 is located above the layer where the gate electrode 151 and the scan line 12 are located, and covers the upper portion of the gate electrode 151 and the scan line 12 for connecting the gate electrode 151 and the scan line 12 with other layers. insulation.
  • the gate insulating layer is formed of a transparent insulating material such as silicon oxide or silicon nitride.
  • the active layer 153 is located above the gate insulating layer 152, and is made of indium gallium oxide or He formed a transition metal oxide.
  • the active layer 153 may also be formed of an amorphous silicon material or a polysilicon material.
  • germanium is formed using indium gallium oxide or other transition metal oxide.
  • the source 154 and the drain 155 are disposed in the same layer as the data line 13 and are located above the layer where the active layer 153 is located, and are made of the same material.
  • the material used is generally a non-transparent metal material or alloy.
  • the data line 13 is electrically connected to the source 154.
  • the gate electrode 151 is provided in the same layer as the solar cell structure 19.
  • the gate insulating layer 152 is located above the gate 151 and the layer of the solar cell structure 19, covering the gate 151 and the solar cell structure 19. Such a design facilitates the solar cell structure to receive external light, improve light utilization, and improve the efficiency of the solar cell structure.
  • the array substrate further includes a barrier layer 21 disposed above the active layer 153, below the layer where the source 154 and the drain 155 are located.
  • the barrier layer 21 serves to protect the active layer 153 from being over-etched.
  • the barrier layer is made of a transparent insulating material such as silicon oxide or silicon nitride.
  • a first via 211 and a second via 212 are disposed in the barrier layer 21 at positions corresponding to the source 154 and the drain 155, respectively.
  • the source 154 is electrically connected to the active layer 153 through the first via 211
  • the drain 155 is electrically connected to the active layer 153 through the second via 212.
  • a third via 213 is disposed in the barrier layer 21 and the gate insulating layer 152 corresponding to the power output line 20, and the positive electrode 191 is electrically connected to the power output line 20 through the third via 213 .
  • the array substrate further includes a passivation layer 22.
  • the passivation layer 22 is disposed over the layer where the source 154 and the drain 155 are located, covering the upper region of the thin film transistor 15 for protecting the thin film transistor from corrosion.
  • a fifth via is disposed in the passivation layer 22 at a position corresponding to the drain 155
  • the pixel electrode 17 is electrically connected to the drain 155 through the fifth via 215.
  • the second embodiment of the present invention provides another array substrate.
  • the structure of the array substrate is substantially the same as that of the array substrate provided in the first embodiment, and the difference is that in the array substrate provided in the second embodiment,
  • the thin film transistor 15 is a top gate thin film transistor.
  • the solar cell structure 19 is located above the barrier layer 21 and below the gate insulating layer 152, and is disposed in the same layer as the active layer 153.
  • the source 154 and the drain 155 are located above the base substrate 11, and the source 154 and the drain 155 are disposed in the same layer.
  • the active layer 153 is located above the layer where the source 154 and the drain 155 are located.
  • the active layer 153 is generally made of a semiconductor material such as single crystal silicon or polycrystalline silicon. Since the active layer 153 is disposed in the same layer as the solar cell structure 19, the active layer and the intrinsic silicon material layer of the solar cell structure can be formed by one patterning process during the fabrication process, which is advantageous for reducing the manufacturing process. reduce manufacturing cost.
  • the gate insulating layer 152 is located above the active layer 153, covering the active layer 153, so that the active layer 153 is insulated from the gate 151.
  • the gate electrode 151 is located above the gate insulating layer 152.
  • the barrier layer 21 is located above the layer where the source 154 and the drain 155 are located, below the active layer 153, for protecting the source and drain from being over-etched.
  • a first via 211 and a second via 212 are respectively disposed in the barrier layer 21 at positions corresponding to the source 154 and the drain 155.
  • the source 154 is electrically connected to the active layer 153 through the first via 211
  • the drain 155 is electrically connected to the active layer 153 through the second via 212.
  • a fourth via 214 is disposed in the barrier layer 21 corresponding to the power output line 20, and the positive electrode 191 is electrically connected to the power output line 20 through the fourth via 214.
  • a sixth via 216 is disposed in the passivation layer 22 and the barrier layer 21 at a position corresponding to the drain 155, and the pixel electrode 17 is electrically connected to the drain 155 through the sixth via 216 .
  • the array substrate provided in Embodiments 1 and 2 of the present invention includes a light emitting structure for providing a backlight, a solar cell structure, and a power output line.
  • the light emitting structure is disposed between the common electrode and the pixel electrode; the solar cell structure is disposed between the base substrate and the common electrode; the power output line is disposed in the same layer as the common electrode, and
  • the solar cell structure is electrically connected, and the electric energy generated by the solar cell structure is transmitted to an external circuit, thereby realizing the combination of the solar energy technology and the OLED display technology.
  • the solar cell structure electrical energy can be generated and transmitted to an external circuit, and the external circuit stores the received electrical energy and then supplies the same to the array substrate, so that the array substrate does not need an external power source.
  • a third embodiment of the present invention provides a method for fabricating an array substrate, the method comprising the steps of forming a scan line, a data line, a common electrode, a pixel electrode, and a thin film transistor.
  • the step of forming a thin film transistor includes forming a gate and a gate insulating layer.
  • the method also includes the steps of forming a light emitting structure, a solar cell structure, and a power supply output line over the substrate.
  • the light emitting structure is disposed between the common electrode and the pixel electrode; the solar cell structure is disposed between the array substrate and the common electrode; the power output line is disposed in the same layer as the common electrode, and
  • the solar cell structure is electrically connected, and the electrical energy generated by the solar cell structure is transmitted to an external circuit.
  • the following is an example of the array substrate provided by the implementation of the present invention.
  • the method for preparing the array substrate in the actual manufacturing process is described in detail.
  • the method includes:
  • a metal thin film is deposited on the base substrate 11, and then processed by a patterning process to form a pattern including the gate electrode 151.
  • the material for forming the metal thin film is a non-transparent metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and an alloy thereof.
  • a pattern including a solar cell structure 19 is formed over the base substrate, and the solar cell structure 19 is insulated from the gate electrode 151 in the same layer.
  • a first transparent conductive material layer, a p-type silicon material layer, an intrinsic silicon material, an n-type silicon material layer and a second transparent conductive material layer are sequentially deposited on the base substrate 11.
  • the negative electrode 192, the p-type silicon material layer 194, the intrinsic silicon material layer 193, the n-type silicon material layer 195, and the positive electrode 191 of the solar cell structure 19 are sequentially formed by a patterning process.
  • a silicon nitride or silicon oxide layer is deposited over the pattern including the solar cell structure 19 to form a gate insulating layer 152.
  • a semiconductor material is deposited over the gate insulating layer 152, and then a pattern including the active layer 153 is formed by a patterning process.
  • the semiconductor material may be a polysilicon semiconductor material, an amorphous silicon semiconductor material, or a metal oxide semiconductor material.
  • a silicon nitride or silicon oxide layer is deposited over the pattern including the active layer 153 to form a barrier layer 21; and a corresponding source 154 and a drain are formed in the barrier layer by a patterning process.
  • the positions of 155 form a first via 211 and a second via 212, respectively, and a third via 213 extending through the barrier layer 21 and the gate insulating layer 152 corresponding to the power output line.
  • a metal film is deposited on the barrier layer, and then A pattern including the source electrode 154, the drain electrode 155, the common electrode 16, and the power source output line 20 is formed by a patterning process.
  • the source 154 is electrically connected to the active layer 153 through the first via 211
  • the drain 155 is electrically connected to the active layer 153 through the second via 212
  • the power output line 20 passes through
  • the third via 213 is electrically connected to the solar cell structure 19.
  • a pattern including the light emitting structure 18 is formed over the pattern including the source 154, the drain 155, the common electrode 16, and the power output line 20.
  • the step specifically includes: including the source An upper coating luminescent material layer and a transparent conductive material layer including a pattern of the light emitting structure 18 are formed over the pattern of the pole 154, the drain electrode 155, the common electrode 16 and the power source output line 20, and then the luminescent material layer of the light emitting structure is formed by a patterning process And an anode, the common electrode 16 is used to serve as a cathode of the light emitting structure 18.
  • a deposited silicon nitride or silicon oxide layer is formed over the thin film transistor to form a passivation layer 22 for protecting the thin film transistor from corrosion.
  • a fifth via hole 215 is formed in the passivation layer 22 by a patterning process, and the fifth via hole 215 passes through the passivation layer and corresponds to the position of the drain electrode 155.
  • a transparent conductive film of indium tin oxide is deposited on the passivation layer 22 by magnetron sputtering, and a pattern including the pixel electrode 17 is formed by a patterning process, the pixel electrode 17 is electrically connected to the drain electrode 155 through the fifth via hole 215, and the fifth via hole 215 is filled with a transparent conductive material for fabricating the pixel electrode 17.
  • an array substrate having a cross-sectional structure as shown in FIG. 2 according to the first embodiment of the present invention is formed.
  • the pattern including the pixel electrode 17 may be formed first, and then the passivation layer 22 may be formed.
  • the method for preparing the array substrate is similar to the method for preparing the array substrate provided in the first embodiment.
  • the method for preparing the array substrate includes:
  • a metal thin film is deposited on the base substrate 11, and then processed by a patterning process to form a pattern including the source electrode 154 and the drain electrode 155.
  • the material for forming the metal thin film is a non-transparent metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and an alloy thereof.
  • a silicon nitride or silicon oxide layer is deposited over the pattern including the source 154 and the drain 155 to form a barrier layer 21; and a corresponding source 154 is formed in the barrier layer by a patterning process. And a position of the drain electrode 155 respectively forming a first via hole 211 and a second via hole 212, through which the active layer 153 is electrically connected to the source electrode 154, through the second pass The holes electrically connect the active layer 153 with the drain 155.
  • a transparent conductive material and an n-type silicon material are sequentially deposited over the barrier layer 21, and a pattern including the negative electrode 192 of the solar cell structure 19 and the n-type silicon material layer 195 is formed by a patterning process. .
  • an intrinsic silicon material is deposited over the pattern of the n-type silicon material layer including the solar cell structure 19, and an intrinsic silicon material including the active layer 153 and the solar cell structure 19 is formed by a patterning process.
  • a silicon nitride or silicon oxide layer is deposited over the pattern of the intrinsic silicon material layer including the active layer 153 and the solar cell structure 19 to form a gate insulating layer 152.
  • a metal thin film is deposited over the gate insulating layer 152, and then processed by a patterning process to form a pattern including the gate electrode 151.
  • the material for forming the metal thin film is a non-transparent metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and an alloy thereof.
  • the seventh step uses ion implantation to dope the position corresponding to the source and the drain in the active layer by using PH 3 to increase the concentration of the carrier;
  • the intrinsic layer silicon material in 19 is doped to form the intrinsic silicon material layer 193 and the p-type silicon material layer 194 of the solar cell structure 19.
  • a fourth via hole 214 is formed in a position corresponding to the power output line 20 in the gate insulating layer 152 by a patterning process, and the power output line 20 is output through the fourth via hole 214.
  • the solar cell structure 19 is electrically connected; and a via hole is formed at a position corresponding to the drain electrode 155 in the gate insulating layer 152 and the barrier layer 21.
  • a metal thin film is deposited over the pattern including the gate electrode 151, and then a pattern including the common electrode 16 and the power supply output line 20 is formed by a patterning process.
  • a pattern including the light emitting structure 18 is formed over the pattern including the common electrode 16 and the power output line 20; in the process of forming the pattern including the light emitting structure 18, the common electrode is included A layer of luminescent material and a layer of transparent conductive material are deposited over the pattern of 16 and power output lines 20, and then a layer of luminescent material and an anode of the luminescent structure are formed by a patterning process; the common electrode 16 serves to serve as a cathode for the luminescent structure 18.
  • a transparent insulating material such as silicon nitride or silicon oxide is deposited over the pattern including the light emitting structure 18 to form a passivation layer 22; and the gate insulating layer 152 is formed by a patterning process. And a position corresponding to the drain 155 in the barrier layer 21 is formed through the blunt The via of the layer, that is, the sixth via 216 that penetrates the passivation layer 22, the gate insulating layer 152, and the barrier layer 21 is formed.
  • a transparent conductive film of indium tin oxide is deposited on the passivation layer 22 by magnetron sputtering, and a pattern including the pixel electrode 17 is formed by a patterning process, the pixel
  • the electrode 17 and the drain electrode 155 are electrically connected through the sixth via hole 216, and the sixth via hole 216 is filled with a metal conductive material for fabricating a common electrode and a transparent conductive material for fabricating a pixel electrode.
  • the array substrate provided in the second embodiment of the present invention has a cross-sectional structure as shown in FIG.
  • the embodiment of the invention further provides a display panel, wherein the display panel comprises the array substrate described above.
  • the solar cell structure is located on the substrate, which facilitates the solar cell structure to receive external light, improve the utilization of light, and improve the working efficiency of the solar cell structure.
  • an embodiment of the present invention provides an array substrate, a method for fabricating the same, and a display panel.
  • the array substrate includes a light emitting structure, a solar cell structure, and a power output line.
  • the light emitting structure is disposed between the common electrode and the pixel electrode; the solar cell structure is disposed between the base substrate and the common electrode; the power output line is disposed in the same layer as the common electrode, and
  • the solar cell structure is electrically connected, and the electric energy generated by the solar cell structure is transmitted to an external circuit, thereby realizing the combination of the solar energy technology and the OLED display technology.
  • the solar cell structure electrical energy can be generated and transmitted to an external circuit, and the external circuit stores the received electrical energy and then supplies the same to the array substrate, so that the array substrate does not need an external power supply; and, in the array substrate, Since the power output line is disposed in the same layer as the common electrode, the power output line can be formed with the common electrode by one patterning process, which simplifies the manufacturing process, reduces the production cost, and reduces the process time. .

Abstract

一种阵列基板及其制备方法和显示面板，用于将太阳能电池结构的制作与OLED的制作结合在一起，实现太阳能技术与OLED显示技术的结合，以解决该阵列基板包括衬底基板（11）、扫描线（12）、数据线（13）、薄膜晶体管（15）、公共电极（16）和像素电极（17），该阵列基板还包括：用于提供背光源的发光结构（18）、太阳能电池结构（19）和电源输出线（20）；该发光结构（18）设置在公共电极(16)和像素电极（17）之间；该太阳能电池结构（19）设置在衬底基板（11）和公共电极（16）之间；该电源输出线（20）与公共电极（16）同层设置，并且与所述太阳能电池结构（19）电连接，将太阳能电池结构（19）产生的电能传输给外电路。

Description

阵列基板及其制备方法和显示面板
技术领域
本发明的实施例涉及一种阵列基板及其制备方法和显示面板。 背景技术
相比于液晶显示（Liquid Crystal Display, LCD )装置， 有机发光二极管 ( Organic Light-Emitting Diode, OLED )显示装置不需要背光模组， 而是釆用 非常薄的发光结构和玻璃基板制作。一般的， OLED的所述发光结构包括发光 材料层、 电子传输层和空穴传输层， 电子传输层和空穴传输层分别设置在所 述发光材料层的上侧和下侧， 当有电流通过发光材料层时， 所述发光结构就 会发光。 由于 OLED显示装置省去了背光模组， 因此 OLED显示装置可以做得 更轻、 更薄， 可视角度更大， 并且能够显著节省电能， 因此， OLED显示装置 正曰益得到普及。
同时， 随着光伏技术的发展， 太阳能电池由于不受资源环境限制， 无环 保污染问题， 弱光性也能发光， 而且透光性强， 发电时间长， 产业链条短， 成本低， 回收期短， 受温度变化影响小， 应用领域广， 其应用和发展也已经 得到世界范围内的认同。 发明内容
本发明的至少一个实施例提供了一种阵列基板， 所述阵列基板包括衬底 基板、在所述衬底基板上交叉布置的扫描线、数据线以及由所述扫描线和数 据线划分出的呈矩阵排列的像素单元，所述像素单元内设置有薄膜晶体管、 公共电极和像素电极， 其中所述薄膜晶体管包括栅极、 栅绝缘层、 有源 层、 源极和漏极； 用于提供背光源的发光结构、 太阳能电池结构和电源输出 线； 其中所述发光结构设置在所述公共电极和像素电极之间， 所述太阳能电 池结构设置在所述衬底基板和公共电极之间， 所述电源输出线与公共电极同 层设置， 并且与所述太阳能电池结构电连接， 将所述太阳能电池结构产生的 电能传输给外电路。
在一个示例中， 所述发光结构包括： 相对设置的阳极和阴极， 以及设置 在所述阳极与阴极之间的发光材料层； 其中所述阴极由位于所述发光结构的 下方的公共电极来充当。
在一个示例中， 所述薄膜晶体管为底栅薄膜晶体管； 所述栅极与所述 太阳能电池结构同层设置； 所述栅绝缘层位于所述栅极和太阳能电池结 构所在层的上方， 覆盖所述栅极和所述太阳能电池结构。 在一个示例中， 所述阵列基板还包括设置在所述有源层上方、 所述源极和漏极所在层下 方的阻挡层。在一个示例中， 所述阻挡层中对应所述源极和漏极的位置分 别设置有第一过孔和第二过孔； 其中所述源极通过所述第一过孔与所述 有源层电连接， 所述漏极通过所述第二过孔与所述有源层电连接；
所述阻挡层和栅绝缘层中对应所述电源输出线的位置设置有第三过 孔， 所述正电极通过所述第三过孔与所述电源输出线电连接。
在一个示例中， 所述薄膜晶体管为顶栅薄膜晶体管； 其中所述有源层 与所述太阳能电池结构同层设置。在一个示例中，所述阵列基板还包括设 置在所述源极和漏极所在层的上方、 有源层的下方的阻挡层。
在一个示例中，所述阻挡层中与所述源极和漏极相对应的位置分别设 置有第一过孔和第二过孔； 其中所述源极通过所述第一过孔与有源层电 连接， 所述漏极通过所述第二过孔与所述有源层电连接；
所述阻挡层中与所述电源输出线相对应的位置设置有第四过孔， 所 述正电极通过所述第四过孔与所述电源输出线电连接。
在一个示例中， 所述阵列基板还包括位于薄膜晶体管上方的钝化层。 本发明的至少一个实施例还提供了一种显示面板， 所述显示面板包 括上述的阵列基板。
本发明的至少一个实施例还提供了一种阵列基板的制备方法， 所述 方法包括形成扫描线、 数据线、 公共电极、 像素电极和薄膜晶体管的步骤， 其中所述薄膜晶体管包括栅极、 栅绝缘层、 源极、 漏极和有源层， 所述 公共电极、 像素电极和薄膜晶体管均形成在由所述扫描线和所述数据线 围成的多个像素区域内； 以及在衬底基板的上方形成发光结构、 太阳能电 池结构和电源输出线的步骤； 其中，
所述发光结构设置在所述公共电极和像素电极之间；
所述太阳能电池结构设置在所述阵列基板和公共电极之间； 并且 所述电源输出线与所述公共电极同层设置， 并且与所述太阳能电池结构 电连接， 将所述太阳能电池结构产生的电能传输给外电路。
在一个示例中， 所述发光结构包括： 相对设置的阳极和阴极， 以及设置 在所述阳极与阴极之间的发光材料层； 其中所述阴极由位于所述发光结构的 下方的公共电极来充当。
在一个示例中， 在形成薄膜晶体管的过程中，
在衬底基板上方形成包括栅极的图形， 所述栅极与所述太阳能电池结构 同层设置；
在所述包括栅极的图形的上方形成栅绝缘层，完全覆盖所述栅极和所述 太阳能电池结构；
在所述栅绝缘层的上方形成包括所述有源层的图形， 以及
在所述包括所述有源层的图形的上方形成所述源极和所述漏极并且 所述源极和所述漏极同层设置。
在一个示例中， 所述方法还包括：
在所述包括有源层的图形的上方形成包括阻挡层的图形； 所述阻挡 层位于所述源极和漏极所在层的下方。
在一个示例中， 在形成薄膜晶体管的过程中，
在所述衬底基板的上方形成包括所述源极和所述漏极的图形， 所述源极 和所述漏极同层设置；
在所述包括源极和漏极的图形的上方形成包括所述有源层的图形， 所述 有源层位于所述栅绝缘层的下方；
在所述包括所述有源层的图形的上方形成所述栅绝缘层，所述栅绝缘 层位于所述栅极的下方； 以及
在所述栅绝缘层的上方形成包括所述栅极的图形。
在一个示例中， 所述方法还包括：
在所述包括所述栅极的图形的上方形成包括阻挡层的图形， 所述阻 挡层位于所述源极和所述漏极所在层的上方、 有源层的下方。
在一个示例中， 所述方法还包括： 在所述薄膜晶体管的上方形成钝化 层。 附图说明
图 1为本发明实施例一提供的一种阵列基板的平面结构示意图； 图 2为沿图 1中虚线 A-B方向的阵列基板的剖面结构示意图；
图 3为发光结构的剖面结构示意图；
图 4本发明实施例二提供的一种阵列基板的平面结构示意图；
图 5-12为本发明实施例一提供的阵列基板的制作流程示意图；
图 13-23为本发明实施例二提供的阵列基板的制作流程示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述。 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在无需创 造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 本文使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"、 "一" 或者 "该" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后 面列举的元件或者物件及其等同，而不排除其他元件或者物件。 "上"、 "下"、 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位 置关系也可能相应地改变。
在利用太阳能电池供电的 OLED显示装置中， 太阳能电池和 OLED显示部 分通常是独立的两部分，所以太阳能电池的制作过程与 OLED显示装置的制作 过程是分别进行的； 由于 OLED显示装置的制作工艺和太阳能电池的制作工艺 都需要多次构图工艺，使得利用太阳能电池供电的 OLED显示装置的制作比较 复杂； 并且， 由于构图工艺的增多， 也使得利用太阳能电池供电的 OLED显示 装置的生产成本增加。
本发明的实施例提供了一种阵列基板及其制备方法和显示面板， 用于将 太阳能电池结构的制作与 OLED的制作结合在一起，实现太阳能技术与 OLED 显示技术的结合， 以解决现有技术中因太阳能结构与 OLED结构独立存在而 引起的制作工艺复杂， 生产成本较高的问题。
本发明实施例一提供的一种阵列基板，参见图 1和图 2， 图 1为本发明实 施例一提供的阵列基板的平面结构示意图， 图 2为沿图 1中 A-B方向的阵列 基板的剖面结构示意图。 从图 1和图 2中可以看出， 所述阵列基板包括衬底 基板 11， 在所述衬底基板 11上交叉布置的扫描线 12、 数据线 13以及由所 述扫描线 12和数据线 13划分出的呈矩阵排列的像素单元， 所述像素单元内 设置有薄膜晶体管 15、 公共电极 16和像素电极 17。 所述薄膜晶体管 15 包括栅极 151、 栅绝缘层 152、 有源层 153、 源极 154和漏极 155。 所述 阵列基板还包括： 用于提供背光源的发光结构 18、 太阳能电池结构 19和 电源输出线 20。所述发光结构 18设置在所述公共电极 16和像素电极 17之间。 所述太阳能电池结构 19设置在所述衬底基板 11和公共电极 16之间。 所述电 源输出线 20与所述公共电极 16同层设置， 并且与所述太阳能电池结构 19电 连接， 将所述太阳能电池结构 19产生的电能传输给外电路。 由于所述电源输 出线 20与公共电极 16同层设置，因此在制作过程中可以通过一次构图工艺 形成所述电源输出线 20与公共电极 16， 有利于制作工艺， 降低生产成本。
参见图 3， 所述发光结构 18包括： 相对设置的阳极 32和阴极， 以及设置 在所述阳极 32与阴极之间的发光材料层 31。所述阴极由位于所述发光结构的 下方的公共电极 16来充当。 所述公共电极 16位于所述发光结构 18的下方， 充当所述发光结构 18的阴极， 有利于减少制作工艺， 降低生产成本。 所述阳 极 32和用于充当发光结构 18的阴极的公共电极 16共同用于向所述发光结构 提供驱动电压， 使得所述发光结构产生白光。
此外， 所述发光结构 18还包括： 电子传输层 33， 空穴传输层 34， 第一阻挡层 35， 以及第二阻挡层 36。
电子传输层 33位于所述公共电极 16与所述发光材料层 31之间，用 于将电子导入到发光材料层 31。
空穴传输层 34位于所述发光材料层 31与所述阳极 32之间，用于将 空穴导入到发光材料层 31。
第一阻挡层 35位于所述电子传输层 33与所述发光材料层 31之间， 用于阻挡空穴传输到所述公共电极 16。
第二阻挡层 36位于所述空穴传输层 34与所述发光材料层 31之间， 用于阻挡电子传输到所述阳极 32。
所述发光材料层 31 包括： 位于所述第一阻挡层 35上方的橙色磷光 层 31a， 位于所述橙色磷光层 31a上方的蓝色荧光层 31b， 以及位于所述 蓝色荧光层 31b上方的绿色磷光层 31c。
所述发光结构 18工作时， 从所述公共电极 16注入电子， 从所述阳 极 32注入空穴， 电子通过所述电子传输层 33导入到发光材料层 31中， 空穴通过所述空穴传输层 34导入到发光材料层 31中， 电子和空穴在所 述发光材料层 31中复合， 形成单重态激子和三重态激子。 所述单重态激 子和三重态激子由激发态向基态跃迁的过程中， 其能量以光子和热能的 方式释放， 其中的部分光子被用作背光源， 为实现图像的显示提供光线。 在蓝色荧光层 31b中， 单重态的激子由激发态向基态跃迁时， 发出蓝色 的荧光， 在橙色磷光层 31a和绿色磷光层 31c中， 三重态的激子由基态 向激发态跃迁时， 发出绿色磷光和橙色磷光， 所述蓝色荧光与绿色磷光、 橙色磷光复合， 形成白光。
所述太阳能电池结构 19包括： 相对设置的正电极 191和负电极 192， 设 置在正电极 191和负电极 192之间的本征硅材料层 193， 设置在正电极 191 与本征硅材料层 193之间的 p型硅材料层 194，以及设置在负电极 192与本征 硅材料层 193之间的 n型硅材料层 195;
所述太阳能电池结构 19中， p型硅材料层 194与 n型硅材料层 195形成 PN结。 当所述太阳能电池结构 19受到光照后， 在所述 PN结中， n型硅材料 层 195的空穴向 p型硅材料层 194移动， 而 p型硅材料层 194的电子向 n型 硅材料层 195移动， 从而形成由 n型硅材料层 195到 p型硅材料层 194的电 流， 然后在 PN结中形成电势， 通过正电极 191和负电极 192与外电路连接， 形成回路。
所述薄膜晶体管 15为底栅薄膜晶体管。
所述底栅薄膜晶体管的所述栅极 151与扫描线 12同层设置， 均位于所 述衬底基板 11的上方， 所述扫描线 12用于向所述栅极 151提供扫描信号。 所述栅极 151与所述扫描线 12釆用相同的制作材料。 所用制作材料一般为铬 ( Cr )、 钨（W )、 钛（Ti )、 钼 （Mo )、 铝 （Al )、 铜 （ Cu )等非透明金属及 其合金。
所述栅绝缘层 152位于所述栅极 151与扫描线 12所在层的上方， 覆盖所 述栅极 151与扫描线 12的上方区域， 用于将所述栅极 151与扫描线 12与其 它层绝缘。 所述栅绝缘层釆用氧化硅或氮化硅等透明绝缘材料形成。
所述有源层 153位于所述栅绝缘层 152的上方， 釆用铟镓辞氧化物或其 他过渡金属氧化物形成。 所述有源层 153还可以釆用非晶硅材料或多晶硅材 料形成。 但是在该实施例的一个示例中， 为减小漏电流的产生， 釆用铟镓辞 氧化物或其他过渡金属氧化物形成。
所述源极 154和漏极 155与数据线 13同层设置， 均位于所述有源层 153 所在层的上方， 且釆用相同的制作材料， 所用制作材料一般为非透明的金属 材料或其合金。
所述数据线 13与所述源极 154电连接。
在上述薄膜晶体管 15中， 所述栅极 151与所述太阳能电池结构 19 同层设置。 所述栅绝缘层 152位于所述栅极 151 和太阳能电池结构 19 所在层的上方， 覆盖所述栅极 151和所述太阳能电池结构 19。 这样的设 计有利于所述太阳能电池结构接收外部光的照射， 提高光的利用率， 提 高太阳能电池结构的工作效率。
所述阵列基板还包括设置在所述有源层 153 的上方、 所述源极 154 和漏极 155所在层的下方的阻挡层 21。 所述阻挡层 21用于保护有源层 153不被过度刻蚀。 所述阻挡层釆用氧化硅或氮化硅等透明绝缘材料。
所述阻挡层 21中对应所述源极 154和漏极 155的位置分别设置有第 一过孔 211和第二过孔 212。 所述源极 154通过所述第一过孔 211与所 述有源层 153电连接， 所述漏极 155通过所述第二过孔 212与所述有源 层 153电连接。
所述阻挡层 21和栅绝缘层 152中对应所述电源输出线 20的位置设 置有第三过孔 213， 所述正电极 191通过所述第三过孔 213与所述电源 输出线 20电连接。
所述阵列基板还包括钝化层 22。 所述钝化层 22设置在所述源极 154 和漏极 155所在层的上方，覆盖薄膜晶体管 15的上方区域， 用于保护薄膜晶 体管不被腐蚀。所述钝化层 22中与漏极 155对应的位置设置有第五过孔
215 , 通过所述第五过孔 215使得所述像素电极 17与所述漏极 155电连 接。
本发明实施二提供了另一种阵列基板，参见图 4，所述阵列基板的结构与 实施例一提供的阵列基板结构基本相同， 两者不同之处在于， 实施例二提供 的阵列基板中， 所述薄膜晶体管 15为顶栅薄膜晶体管， 所述太阳能电池结构 19位于阻挡层 21的上方、栅绝缘层 152的下方，与所述有源层 153同层设置。 所述源极 154和漏极 155位于所述衬底基板 11的上方， 且所述源极 154 和漏极 155同层设置。
所述有源层 153位于所述源极 154和漏极 155所在层的上方。 一般釆用 单晶硅或多晶硅等半导体材料制作所述有源层 153。由于所述有源层 153与所 述太阳能电池结构 19同层设置， 因此在制作过程中， 可以通过一次构图工 艺形成有源层和太阳能电池结构的本征硅材料层， 有利于减少制作工艺， 降低生产成本。
所述栅绝缘层 152位于所述有源层 153的上方，覆盖所述有源层 153，使 得所述有源层 153与所述栅极 151绝缘。
所述栅极 151位于所述栅绝缘层 152的上方。
所述阻挡层 21位于所述源极 154和漏极 155所在层的上方、所述有源层 153的下方， 用于保护所述源极和漏极不被过度刻蚀。 所述阻挡层 21中对 应所述源极 154和漏极 155的位置分别设置有第一过孔 211和第二过孔 212。 所述源极 154通过所述第一过孔 211与所述有源层 153电连接， 所 述漏极 155通过所述第二过孔 212与所述有源层 153电连接。
所述阻挡层 21 中对应所述电源输出线 20 的位置设置有第四过孔 214 , 所述正电极 191通过所述第四过孔 214与所述电源输出线 20电连 接。
所述钝化层 22和阻挡层 21 中与所述漏极 155对应的位置设置有第 六过孔 216，通过所述第六过孔 216使得所述像素电极 17与所述漏极 155 电连接。
本发明实施例一和二提供的阵列基板中， 包括用于提供背光源的发光结 构、 太阳能电池结构和电源输出线。 所述发光结构设置在所述公共电极和像 素电极之间； 所述太阳能电池结构设置在所述衬底基板和公共电极之间； 所 述电源输出线与所述公共电极同层设置， 并且与所述太阳能电池结构电连接， 将所述太阳能电池结构产生的电能传输给外电路，实现了太阳能技术与 OLED 显示技术的结合。 通过所述太阳能电池结构， 能够产生电能并传给外电路， 外电路对接收的电能进行存储， 然后提供给所述阵列基板， 使得该阵列基板 无需外接电源。 在所述阵列基板中， 由于所述电源输出线与所述公共电极同 层设置， 因此所述电源输出线可以与所述公共电极通过一次构图工艺形成， 简化了制作工艺， 降低了生产成本， 同时还减少了工艺制作时间。 本发明实施例三提供了一种阵列基板的制备方法， 所述方法包括形 成扫描线、 数据线、 公共电极、 像素电极和薄膜晶体管的步骤， 形成薄膜晶 体管的步骤包括形成栅极、 栅绝缘层、 源极、 漏极和有源层的步骤， 所 述公共电极、 像素电极和薄膜晶体管均形成在由所述扫描线和所述数据 线围成的多个像素区域内。 所述方法还包括在衬底基板的上方形成发光结 构、 太阳能电池结构和电源输出线的步骤。 所述发光结构设置在所述公共电 极和像素电极之间； 所述太阳能电池结构设置在所述阵列基板和公共电极之 间； 所述电源输出线与所述公共电极同层设置， 并且与所述太阳能电池结构 电连接， 将所述太阳能电池结构产生的电能传输给外电路。
下面以本发明实施一提供的阵列基板为例， 详细介绍实际制作工艺中， 所述阵列基板的制备方法， 该方法包括：
第一步， 参见图 5， 在所述衬底基板 11上沉积一层金属薄膜， 然后通 过构图工艺处理，形成包括栅极 151的图形。用于形成金属薄膜的材料为 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等非透明金属及其合金。
第二步， 参见图 6， 在衬底基板的上方形成包括太阳能电池结构 19的图 形， 所述太阳能电池结构 19与所述栅极 151同层绝缘设置。 在形成该太阳能 电池结构 19的过程中，在衬底基板 11上依次沉积第一透明导电材料层、 p 型硅材料层、 本征硅材料、 n 型硅材料层和第二透明导电材料层， 然后 通过构图工艺， 依次形成太阳能电池结构 19的负电极 192、 p型硅材料 层 194、 本征硅材料层 193、 n型硅材料层 195和正电极 191。
第三步， 参见图 7， 在所述包括太阳能电池结构 19的图形的上方沉 积氮化硅或氧化硅层， 形成栅绝缘层 152。
第四步， 参见图 8， 在所述栅绝缘层 152的上方沉积半导体材料， 然后 通过构图工艺形成包括有源层 153 的图形。 所述半导体材料可以为多晶硅半 导体材料、 非晶硅半导体材料或者金属氧化物半导体材料。
第五步， 参见图 9， 在所述包括有源层 153的图形的上方沉积氮化硅或 氧化硅层， 形成阻挡层 21 ; 并通过构图工艺， 在阻挡层中对应源极 154 和漏极 155的位置分别形成第一过孔 211和第二过孔 212， 以及与所述 电源输出线相对应的、 贯穿所述阻挡层 21 和栅绝缘层 152 的第三过孔 213。
第六步， 参见图 10， 在所述阻挡层的上方沉积一层金属薄膜， 然后 通过构图工艺处理， 形成包括源极 154、 漏极 155、 公共电极 16和电源输 出线 20的图形。所述源极 154通过所述第一过孔 211与有源层 153电连 接， 所述漏极 155通过所述第二过孔 212与有源层 153电连接， 所述电 源输出线 20通过所述第三过孔 213与太阳能电池结构 19电连接。
第七步， 参见图 11， 在所述包括源极 154、 漏极 155、 公共电极 16 和电源输出线 20的图形的上方形成包括发光结构 18的图形； 该步骤具 体包括： 在所述包括源极 154、 漏极 155、 公共电极 16和电源输出线 20 的图形的上方形成包括发光结构 18 的图形的上方涂覆发光材料层和透 明导电材料层， 然后通过构图工艺形成发光结构的发光材料层和阳极， 所述公共电极 16用于充当所述发光结构 18的阴极。
第八步， 参见图 12， 在所述薄膜晶体管的上方形成沉积氮化硅或氧 化硅层， 形成钝化层 22， 用于保护薄膜晶体管不被腐蚀。 利用构图工艺在该 钝化层 22中形成第五过孔 215， 所述第五过孔 215贯穿所述钝化层、 与漏极 155的位置相对应。
第九步， 参见图 2， 在所述钝化层 22的上方使用磁控溅射法沉积一层氧 化铟锡透明导电薄膜， 并通过构图工艺， 形成包括像素电极 17的图形， 所述 像素电极 17与所述漏极 155通过所述第五过孔 215电连接，所述第五过孔 215 中填充有用于制作像素电极 17的透明导电材料。
经过上述步骤， 即形成本发明实施例一提供的、 剖面结构如图 2所示的 阵列基板。
需指出的是， 在上述制备阵列基板的过程中， 也可先形成包括像素电极 17的图形， 然后再形成钝化层 22。
对于本发明实施例二提供的阵列基板， 其制备方法与制备实施例一提供 的阵列基板的方法类似， 该阵列基板的制备方法包括：
第一步， 参见图 13， 在所述衬底基板 11上沉积一层金属薄膜， 然后通 过构图工艺处理， 形成包括源极 154和漏极 155的图形。 用于形成金属薄膜 的材料为 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等非透明金属及其合金。
第二步， 参见图 14， 在所述包括源极 154和漏极 155的图形的上方沉积 氮化硅或氧化硅层， 形成阻挡层 21 ; 并通过构图工艺， 在阻挡层中对应源 极 154和漏极 155的位置分别形成第一过孔 211和第二过孔 212， 通过 所述第一过孔 211使得有源层 153与源极 154电连接， 通过所述第二过 孔使得有源层 153与所述漏极 155电连接。
第三步， 参见图 15， 在所述阻挡层 21的上方依次沉积透明导电材料 和 n型硅材料， 并通过构图工艺形成包括太阳能电池结构 19 的负电极 192和 n型硅材料层 195的图形。
第四步， 参见图 16， 在包括太阳能电池结构 19的 n型硅材料层的图 形的上方沉积本征硅材料， 并通过构图工艺形成包括有源层 153和太阳 能电池结构 19的本征硅材料层的图形，以及在本征硅材料层上方沉积一 层金属薄膜， 形成所述太阳能电池结构的正电极 191。
第五步， 参见图 17， 在所述包括有源层 153和太阳能电池结构 19的 本征硅材料层的图形的上方沉积氮化硅或氧化硅层， 形成栅绝缘层 152。
第六步， 参见图 18， 在所述栅绝缘层 152的上方沉积一层金属薄膜， 然 后通过构图工艺处理， 形成包括栅极 151 的图形。 用于形成金属薄膜的材料 为 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等非透明金属及其合金。
第七步， 参见图 19， 釆用离子注射的方式， 使用 PH3对有源层中与源极 和漏极相对应的位置进行掺杂， 增大载流子的浓度； 并对太阳能电池结构 19 中的本征层硅材料进行掺杂，以形成太阳能电池结构 19的本征硅材料层 193 和 p型硅材料层 194。
第八步， 参见图 20， 通过构图工艺， 在所述栅绝缘层 152中与所述 电源输出线 20相对应的位置形成第四过孔 214， 通过所述第四过孔 214 电源输出线 20与太阳能电池结构 19电连接； 以及，在所述栅绝缘层 152 和阻挡层 21中与漏极 155对应的位置形成过孔。
第九步， 参见图 21， 在所述包括栅极 151 的图形的上方沉积一层金 属薄膜， 然后通过构图工艺形成包括公共电极 16和电源输出线 20的图形。
第十步， 参见图 22， 在所述包括公共电极 16和电源输出线 20的图形的 上方形成包括发光结构 18的图形； 在形成包括发光结构 18的图形的过 程中， 在所述包括公共电极 16和电源输出线 20的图形的上方沉积发光 材料层和透明导电材料层， 然后通过构图工艺形成发光结构的发光材料 层和阳极； 所述公共电极 16用于充当所述发光结构 18的阴极。
第十一步， 参见图 23， 在所述包括发光结构 18的图形的上方沉积氮 化硅或氧化硅等透明绝缘材料， 形成钝化层 22; 并通过构图工艺， 使得 所述栅绝缘层 152和阻挡层 21中与漏极 155对应的位置形成贯穿所述钝 化层的过孔， 即， 形成贯穿钝化层 22、 栅绝缘层 152和阻挡层 21 的第 六过孔 216。
第十二步， 参见图 4，在所述钝化层 22的上方使用磁控溅射法沉积一层 氧化铟锡透明导电薄膜， 并通过构图工艺， 形成包括像素电极 17的图形， 所 述像素电极 17与所述漏极 155通过所述第六过孔 216电连接， 所述第六过孔 216 中填充有用于制作公共电极的金属导电材料和用于制作像素电极的透明 导电材料。
经过上述步骤， 即形成本发明实施例二提供的、 剖面结构如图 4所示的 阵列基板。
本发明实施例还提供了一种显示面板， 所述显示面板包括上述的阵 列基板。 所述太阳能电池结构位于衬底基板上， 有利于所述太阳能电池 结构接收外部光的照射， 提高光的利用率， 提高太阳能电池结构的工作 效率。
综上， 本发明实施例提供了一种阵列基板及其制备方法和显示面板； 所述阵列基板包括发光结构、 太阳能电池结构和电源输出线。 所述发光结构 设置在所述公共电极和像素电极之间； 所述太阳能电池结构设置在所述衬底 基板和公共电极之间； 所述电源输出线与所述公共电极同层设置， 并且与所 述太阳能电池结构电连接， 将所述太阳能电池结构产生的电能传输给外电路， 实现了太阳能技术与 OLED显示技术的结合。 通过所述太阳能电池结构， 能 够产生电能并传给外电路， 外电路对接收的电能进行存储， 然后提供给所述 阵列基板， 使得该阵列基板无需外接电源； 并且， 在所述阵列基板中， 由于 所述电源输出线与所述公共电极同层设置， 因此所述电源输出线可以与所述 公共电极通过一次构图工艺形成， 简化了制作工艺， 降低了生产成本， 同时 还减少了工艺制作时间。
以上实施例仅用于说明本发明， 而并非对本发明的限制， 有关技术领域 的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各种 变化和变型， 因此所有这样的变化和变形以及等同的技术方案也属于本发明 的范畴， 本发明的专利保护范围应由权利要求限定。
本申请要求于 2014年 03月 28日提交的名称为"一种阵列基板及其制备 方法和显示面板" 的中国专利申请 NO. 201410130738.X的优先权， 其全文以 引用方式合并于本文。

Claims

权 利 要 求 书
1、 一种阵列基板， 包括：
衬底基板、 在所述衬底基板上交叉布置的扫描线、 数据线以及由所述扫 描线和数据线划分出的呈矩阵排列的像素单元， 所述像素单元内设置有薄膜 晶体管、 公共电极和像素电极， 其中所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源极和漏极； 并且
用于提供背光源的发光结构、 太阳能电池结构和电源输出线； 其中， 所述发光结构设置在所述公共电极和所述像素电极之间；
所述太阳能电池结构设置在所述衬底基板和所述公共电极之间； 并且 所述电源输出线与所述公共电极同层设置， 并且与所述太阳能电池结构 电连接， 将所述太阳能电池结构产生的电能传输给外电路。
2、 如权利要求 1所述的阵列基板， 其中所述发光结构包括： 相对设置的 阳极和阴极， 以及设置在所述阳极与阴极之间的发光材料层； 其中所述阴极 由位于所述发光结构的下方的公共电极来充当。
3、 如权利要求 1或 2所述的阵列基板， 其中所述薄膜晶体管为底栅薄膜 晶体管； 所述栅极与所述太阳能电池结构同层设置； 并且所述栅绝缘层位于 所述栅极和太阳能电池结构所在层的上方， 覆盖所述栅极和所述太阳能电池 结构。
4、 如权利要求 1-3任一项所述的阵列基板， 还包括设置在所述有源层上 方、 所述源极和所述漏极所在层下方的阻挡层。
5、 如权利要求 4所述的阵列基板， 其中所述阻挡层中对应所述源极和漏 极的位置分别设置有第一过孔和第二过孔； 所述源极通过所述第一过孔与所 述有源层电连接， 所述漏极通过所述第二过孔与所述有源层电连接； 并且 所述阻挡层和所述栅绝缘层中对应所述电源输出线的位置设置有第三过 孔， 所述正电极通过所述第三过孔与所述电源输出线电连接。
6、 如权利要求 1或 2所述的阵列基板， 其中所述薄膜晶体管为顶栅薄膜 晶体管； 并且所述有源层与所述太阳能电池结构同层设置。
7、 如权利要求 6所述的阵列基板， 还包括设置在所述源极和所述漏极所 在层的上方、 有源层的下方的阻挡层。
8、 如权利要求 7所述的阵列基板， 其中所述阻挡层中与所述源极和漏极 相对应的位置分别设置有第一过孔和第二过孔； 所述源极通过所述第一过孔 与所述有源层电连接， 所述漏极通过所述第二过孔与所述有源层电连接； 并 且
所述阻挡层中与所述电源输出线相对应的位置设置有第四过孔， 所述正 电极通过所述第四过孔与所述电源输出线电连接。
9、 如权利要求 1~8任一权项所述的阵列基板， 还包括位于所述薄膜晶体 管上方的钝化层。
10、 一种显示面板， 包括权利要求 1~9任一权项所述的阵列基板。
11、 一种阵列基板的制备方法， 包括：
形成扫描线、 数据线、 公共电极、 像素电极和薄膜晶体管的步骤； 其中 所述薄膜晶体管包括栅极、 栅绝缘层、 源极、 漏极和有源层， 所述公共电极、 所述像素电极和所述薄膜晶体管均形成在由所述扫描线和所述数据线围成的 多个像素区域内； 以及
在衬底基板的上方形成用于提供背光源的发光结构、 太阳能电池结构和 电源输出线的步骤； 其中，
所述发光结构设置在所述公共电极和所述像素电极之间；
所述太阳能电池结构设置在所述阵列基板和所述公共电极之间； 并且 所述电源输出线与所述公共电极同层设置， 并且与所述太阳能电池结构 电连接， 将所述太阳能电池结构产生的电能传输给外电路。
12、 如权利要求 11所述的方法， 其中所述发光结构包括： 相对设置的阳 极和阴极， 以及设置在所述阳极与阴极之间的发光材料层； 并且所述阴极由 位于所述发光结构的下方的公共电极来充当。
13、 如权利要求 11或 12所述的方法， 其中形成薄膜晶体管的步骤包括： 在衬底基板上方形成包括所述栅极的图形， 所述栅极与所述太阳能电池 结构同层设置；
在所述包括栅极的图形的上方形成所述栅绝缘层， 所述栅绝缘层位于所 述栅极和所述太阳能电池结构的上方， 完全覆盖所述栅极和所述太阳能电池 结构；
在所述栅绝缘层的上方形成包括所述有源层的图形； 以及
在所述包括有源层的图形的上方形成所述源极和所述漏极， 并且所述源 极和所述漏极同层设置。
14、 如权利要求 13所述的方法， 还包括：
在所述包括所述有源层的图形的上方形成阻挡层， 并且所述阻挡层位于 所述源极和所述漏极所在层下方。
15、 如权利要求 11所述的方法， 其中形成薄膜晶体管的步骤包括： 在所述衬底基板的上方形成包括所述源极和所述漏极的图形， 所述源极 和所述漏极同层设置；
在所述包括源极和漏极的图形的上方形成包括所述有源层的图形， 并且 所述有源层位于所述栅绝缘层的下方；
在所述包括有源层的图形的上方形成所述栅绝缘层， 并且所述栅绝缘层 位于所述栅极的下方；
在所述栅绝缘层的上方形成包括所述栅极的图形。
16、 如权利要求 15所述的方法， 还包括：
在所述包括栅极的图形的上方形成阻挡层， 所述阻挡层位于所述源极和 漏极所在层的上方、 所述有源层的下方。
17、 如权利要求 11~16任一权项所述的方法， 还包括： 在所述薄膜晶体 管的上方形成钝化层。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928474B (zh) 2014-03-28 2017-03-15 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示面板
CN104201187B (zh) * 2014-08-18 2017-07-04 京东方科技集团股份有限公司 一种oled显示装置
CN104867964B (zh) * 2015-05-18 2019-02-22 京东方科技集团股份有限公司 阵列基板、其制造方法以及有机发光二极管显示装置
CN105655407A (zh) * 2016-03-11 2016-06-08 京东方科技集团股份有限公司 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置
CN106654048B (zh) * 2016-12-27 2019-01-25 武汉华星光电技术有限公司 顶发光型oled显示单元、制作方法及显示面板
CN107272235A (zh) * 2017-05-12 2017-10-20 惠科股份有限公司 显示设备及其主动式阵列开关基板
CN107425042B (zh) * 2017-07-27 2020-05-01 京东方科技集团股份有限公司 一种oled阵列基板、显示装置
CN107742627A (zh) * 2017-09-28 2018-02-27 京东方科技集团股份有限公司 显示面板以及显示面板的制备方法
CN109037303B (zh) * 2018-09-14 2020-11-24 京东方科技集团股份有限公司 有源矩阵有机发光二极管背板及其制造方法、显示面板
CN109755281B (zh) * 2019-01-14 2021-07-06 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法
CN110895374A (zh) * 2019-11-26 2020-03-20 上海天马微电子有限公司 显示面板及显示装置
CN110993616B (zh) 2019-11-28 2022-08-09 京东方科技集团股份有限公司 显示背板及其制备方法和显示装置
CN114913782A (zh) * 2021-02-09 2022-08-16 海信视像科技股份有限公司 一种显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090108757A1 (en) * 2007-10-22 2009-04-30 National Taiwan University One-piece organic light emitting diode display device with an energy-recycling feature and high contrast
CN102117825A (zh) * 2010-01-05 2011-07-06 三星移动显示器株式会社 有机发光显示装置
US20120326131A1 (en) * 2011-06-27 2012-12-27 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
CN103928474A (zh) * 2014-03-28 2014-07-16 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示面板
CN203760477U (zh) * 2014-03-28 2014-08-06 京东方科技集团股份有限公司 一种阵列基板和显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI234027B (en) * 2000-06-14 2005-06-11 Hannstar Display Corp Liquid crystal display device
US7262463B2 (en) * 2003-07-25 2007-08-28 Hewlett-Packard Development Company, L.P. Transistor including a deposited channel region having a doped portion
TWI406036B (zh) * 2010-06-28 2013-08-21 Au Optronics Corp 光電池整合液晶顯示器及光電池整合平面顯示器
TW201205150A (en) * 2010-07-16 2012-02-01 Wintek Corp Liquid crystal display panel
US9099560B2 (en) * 2012-01-20 2015-08-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP6147542B2 (ja) * 2013-04-01 2017-06-14 株式会社東芝 透明導電フィルムおよび電気素子

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090108757A1 (en) * 2007-10-22 2009-04-30 National Taiwan University One-piece organic light emitting diode display device with an energy-recycling feature and high contrast
CN102117825A (zh) * 2010-01-05 2011-07-06 三星移动显示器株式会社 有机发光显示装置
US20120326131A1 (en) * 2011-06-27 2012-12-27 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
CN103928474A (zh) * 2014-03-28 2014-07-16 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示面板
CN203760477U (zh) * 2014-03-28 2014-08-06 京东方科技集团股份有限公司 一种阵列基板和显示面板

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