WO2016183968A1 - 阵列基板及其制造方法、显示面板、掩模板 - Google Patents

阵列基板及其制造方法、显示面板、掩模板 Download PDF

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Publication number
WO2016183968A1
WO2016183968A1 PCT/CN2015/089363 CN2015089363W WO2016183968A1 WO 2016183968 A1 WO2016183968 A1 WO 2016183968A1 CN 2015089363 W CN2015089363 W CN 2015089363W WO 2016183968 A1 WO2016183968 A1 WO 2016183968A1
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Prior art keywords
mask
semi
substrate
region
pattern
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Ceased
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PCT/CN2015/089363
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English (en)
French (fr)
Inventor
张治超
郭总杰
刘正
张小祥
陈曦
刘明悬
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/105,175 priority Critical patent/US9899225B2/en
Publication of WO2016183968A1 publication Critical patent/WO2016183968A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate manufactured by the method, a display panel including the array substrate, and a mask.
  • Thin film transistor liquid crystal display (English: Thin-film transistor liquid crystal display; referred to as: TFT-LCD) is one of the most liquid crystal displays. In the lithography process of a TFT-LCD, it is necessary to use a mask for patterning.
  • the principle of patterning the TFT-LCD array substrate using the mask is as follows: first, the photoresist is coated on the substrate, and then the mask is irradiated with the light source, and the transmitted light is transmitted through the mask to the substrate. The photoresist is sensitized, and then developed (the sensitized photoresist is dissolved by chemical action) to cure the unphotosensitive photoresist, and finally the substrate is subjected to etching to obtain a pattern to be formed.
  • each mask uniquely corresponds to one pattern. Since the manufacturing process of the array substrate requires sequentially forming a plurality of patterns on the substrate, it is necessary to purchase a plurality of masks corresponding to the pattern to be formed, and the mask is expensive, and therefore, the manufacturing process of the array substrate It is cumbersome and has a high manufacturing cost.
  • the present invention provides a method for manufacturing an array substrate, an array substrate manufactured by the method, a display panel including the array substrate, and a mask.
  • the technical solution is as follows:
  • a method of fabricating an array substrate comprising:
  • a second mask pattern is formed on the base substrate on which the first mask pattern is formed by using the semi-transmissive region of the mask and the opaque region.
  • the forming the first mask pattern by using the opaque region of the mask on the substrate substrate comprises:
  • the negative photoresist is stripped.
  • the forming a second mask pattern by using the semi-transmissive region of the mask and the opaque region on the substrate formed with the first mask pattern comprises:
  • the positive photoresist is peeled off.
  • the first mask pattern is a via pattern.
  • the first film layer is a passivation layer film.
  • the second film layer is an indium tin oxide film.
  • the opaque region is located in the semi-transmissive region.
  • the shape of the opaque region is any one of a rectangle, a square, a triangle, and a circle.
  • the shape of the boundary of the semi-transmissive region is any one of a rectangle, a square, a triangle, and a circle.
  • an array substrate is provided that is fabricated using the method of any of the first aspects.
  • a display panel comprising the array substrate of the second aspect.
  • a mask comprising:
  • a transparent substrate on which a semi-transmissive region, an opaque region formed on the semi-transmissive region, and a total light transmission other than the semi-transmissive region and the opaque region are formed region;
  • the opaque region is used to form a first mask pattern of the array substrate, and the semi-transmissive region and the opaque region are used to jointly form a second mask pattern of the array substrate.
  • the mask further comprises a semi-permeable membrane formed on the transparent substrate, and the semi-transmissive region is formed on the semi-permeable membrane.
  • the first mask pattern is a via pattern.
  • the shape of the opaque region is any one of a rectangle, a square, a triangle, and a circle.
  • the shape of the boundary of the semi-transmissive region is any one of a rectangle, a square, a triangle, and a circle.
  • the invention provides an array substrate and a manufacturing method thereof, a display panel, a display device and a mask plate.
  • a first mask pattern is formed on the substrate substrate by using an opaque region of the mask, and then a first mask is formed.
  • the semi-transmissive region and the opaque region of the same mask are formed on the base substrate of the film pattern to form a second mask pattern.
  • the manufacturing process of the array substrate is simplified and reduced. Manufacturing costs.
  • FIG. 1 is a flow chart of a method of fabricating an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a mask provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural view showing a shape of an opaque region and a boundary shape of a semi-transmissive region of a mask according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of another mask provided by an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for forming a first mask pattern according to an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a base substrate formed with a first film layer according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of a base substrate coated with a negative photoresist on a first film layer according to an embodiment of the present invention
  • FIG. 8 is a schematic structural view showing exposure of a substrate by strong light according to an embodiment of the present invention.
  • FIG. 9 is a side view of a substrate after the negative photoresist is dissolved according to an embodiment of the present invention.
  • FIG. 10 is a top plan view of a substrate after the negative photoresist is dissolved according to an embodiment of the present invention
  • FIG. 11 is a schematic structural view of a substrate substrate after forming a first mask pattern according to an embodiment of the present invention.
  • FIG. 12 is a side view of a substrate after the negative photoresist is peeled off according to an embodiment of the present invention
  • FIG. 13 is a plan view of a substrate after the negative photoresist is peeled off according to an embodiment of the invention.
  • FIG. 14 is a flowchart of a method for forming a second mask pattern on a substrate according to an embodiment of the present invention.
  • FIG. 15 is a schematic structural view of a base substrate forming a second film layer according to an embodiment of the present invention.
  • FIG. 16 is a schematic structural view of a base substrate coated with a positive photoresist according to an embodiment of the present invention.
  • 17 is a schematic structural view showing exposure of a substrate by weak light according to an embodiment of the present invention.
  • FIG. 18 is a side view of a base substrate provided by an embodiment of the present invention after a positive photoresist is dissolved;
  • 19 is a plan view of a base substrate provided by an embodiment of the present invention after a positive photoresist is dissolved;
  • FIG. 20 is a schematic structural view of a substrate substrate after forming a second mask pattern according to an embodiment of the present invention.
  • 21 is a side view of a substrate substrate after stripping a positive photoresist according to an embodiment of the present invention.
  • FIG. 22 is a plan view of the base substrate provided by the embodiment of the present invention after stripping the positive photoresist.
  • the embodiment of the invention provides a method for manufacturing an array substrate. As shown in FIG. 1 , the method includes:
  • Step 100 Providing a mask including a transparent substrate on which a semi-transmissive region, an opaque region formed on the semi-transmissive region, and the semi-transmissive region and the impervious layer are formed A fully transparent area outside the light area.
  • Step 101 forming a first mask pattern on the base substrate by using an opaque region of the mask.
  • the mask comprises: a transparent substrate, a semi-transparent region is formed on the transparent substrate, and an opaque region is formed on the transparent substrate on which the semi-transmissive region is formed, and the transparent substrate is separated from the semi-transparent region and the opaque region.
  • the area is a fully transparent area.
  • Step 102 Form a second mask pattern on the base substrate on which the first mask pattern is formed by using the semi-transmissive region and the opaque region of the mask.
  • a first mask pattern is formed on the substrate substrate by using the opaque region of the mask, and then the same mask is used on the substrate substrate on which the first mask pattern is formed.
  • the semi-transmissive region and the opaque region of the diaphragm form a second mask pattern, which simplifies the manufacturing process of the array substrate and reduces the manufacturing cost compared to the existing array substrate manufacturing technology.
  • the mask 10 includes a transparent substrate 101, a semi-transmissive region 102 is formed on the transparent substrate 101, and an opaque region 103 is formed on the transparent substrate 101 on which the semi-transmissive region 102 is formed.
  • a region other than the semi-transmissive region 102 and the opaque region 103 on the transparent substrate 101 is the fully transparent region 104.
  • the opaque region 103 is located within the semi-transmissive region 102.
  • the shape of the opaque region may be any one of a rectangle, a square, a triangle, and a circle.
  • the shape of the boundary of the semi-transmissive region may be any one of a rectangle, a square, a triangle, and a circle.
  • FIG. 3 is a schematic view showing a shape of a shape of the opaque region and a boundary of the semi-transmissive region.
  • the opaque region 103 in FIG. 3 has a triangular shape, and the boundary of the semi-transmissive region 102 has a circular shape. shape.
  • the area indicated by 104 in Fig. 3 is a fully transparent region.
  • the first mask pattern may be a via pattern.
  • the second mask pattern can be a normal layout pattern.
  • the first mask pattern (via pattern) is used as the passivation layer pattern
  • the second mask pattern is 2 indium tin oxide (Indium-Tin Oxide; ITO).
  • ITO indium-Tin Oxide
  • Step 101 is as shown in FIG. 5, and may include:
  • Step 1011 forming a first film layer on the base substrate on which the active drain metal pattern is formed.
  • the first film layer can be a passivation layer film.
  • a first film layer 502 that is, a passivation layer film, is formed on the base substrate 501 on which the active drain metal pattern 504 is formed.
  • Step 1012 Apply a negative photoresist on the base substrate on which the first film layer is formed.
  • a negative photoresist 503 is coated on a base substrate 501 on which a first film layer 502, that is, a passivation film is formed.
  • 504 in Figure 7 is a source drain metal pattern.
  • the negative photoresist becomes insoluble after being exposed to light, and the unsensitized portion during development is dissolved in the developer.
  • Step 1013 using an opaque region of the mask, and exposing the substrate coated with the negative photoresist by strong light.
  • the opaque region 103 of the mask 10 is used, and the substrate 501 coated with the negative photoresist 503 is exposed by strong light.
  • the transmittance of the strong light to the semi-transmissive region of the mask is 1.
  • the base substrate coated with the negative photoresist is exposed by strong light. At this time, the opaque region cannot transmit light, and the corresponding negative photoresist cannot be sensitized.
  • Step 1014 developing and etching the exposed substrate to obtain a first mask pattern.
  • FIG. 9 is a side view of the substrate after the unphotosensitive negative photoresist is dissolved, the substrate is indicated by 501, the passivation film is indicated by 502, the negative photoresist is indicated by 503, and the source is represented by 504. Drain metal pattern.
  • Figure 10 is a plan view corresponding to Figure 9, in which a passivation film is indicated by 502 and a negative photoresist is indicated by 503. After etching, a first mask pattern, that is, a passivation layer pattern 5001, is obtained, as shown in FIG.
  • Step 1015 stripping the negative photoresist.
  • FIG. 12 is a side view of the base substrate after peeling off the negative photoresist, the passivation layer pattern is indicated by 5001, the base substrate is indicated by 501, and the source and drain metal patterns are indicated by 504.
  • 13 is a plan view corresponding to FIG. 12, in which reference numeral 504 denotes a source-drain metal pattern, and 5001 denotes a passivation layer pattern.
  • step 102 can include:
  • Step 1021 forming a second film layer on the base substrate on which the first mask pattern is formed.
  • Step 1022 Apply a positive photoresist on the base substrate on which the second film layer is formed.
  • a positive photoresist 506 is coated on the base substrate 501 on which the 2 ITO film 505 is formed.
  • a source drain metal pattern is indicated by 504, and a passivation layer pattern is indicated by 5001.
  • the positive photoresist becomes soluble after being exposed to light, and the photosensitive portion during development is dissolved in the developer.
  • Step 1023 using a semi-transmissive region and an opaque region of the mask, and exposing the substrate coated with the positive photoresist by weak light.
  • the opaque region 103 and the semi-transmissive region 102 of the mask 10 are used, and the substrate 501 coated with the positive photoresist 506 is exposed by weak light. Low light for the mask
  • the transmittance in the semi-transmissive region is 2/5 to 1/2.
  • the base substrate coated with the positive photoresist is exposed by weak light.
  • the opaque region 103 cannot transmit light, and the semi-transmissive region 102 partially transmits light, and the corresponding positive photoresist cannot be completely sensitized. .
  • Step 1024 developing and etching the exposed substrate to obtain a second mask pattern.
  • FIG. 18 is a side view of the base substrate after the positive photoresist is dissolved, and the base substrate is denoted by 501 in FIG. 18, the passivation layer pattern is indicated by 5001, the 2ITO film is indicated by 505, and the positive photoresist is indicated by 506.
  • the source drain metal pattern is indicated by 504.
  • Figure 19 is a plan view corresponding to Figure 18, in which reference numeral 505 denotes a 2ITO film, and 506 denotes a positive photoresist.
  • a second mask pattern that is, a 2ITO pattern 5002 is obtained, as shown in FIG. 20, in FIG. 20, a substrate is indicated by 501, a passivation layer pattern is indicated by 5001, and a source-drain metal pattern is indicated by 504. A positive photoresist is indicated by 506.
  • Step 1025 stripping the positive photoresist.
  • FIG. 21 is a side view of the base substrate after peeling off the positive photoresist
  • FIG. 22 is a plan view corresponding to FIG. 21.
  • a passivation layer pattern is indicated by 5001
  • a 2ITO pattern is indicated by 5002.
  • Embodiments of the present invention provide a technique for saving a mask.
  • Two masks are realized by using a semi-transparent film technique on a mask, using a positive photoresist and a negative photoresist in the process.
  • the purpose of combining the boards into a mask is to save at least one mask for each product, thereby saving the number of masks used and greatly reducing production costs.
  • the two mask patterns in the embodiment of the present invention are inclusive and included, and the first mask pattern should be smaller than the second mask pattern and completely covered by the second mask pattern.
  • the first mask pattern is a via pattern
  • the second mask pattern is a normal layout pattern
  • the two mask patterns are formed on a mask plate by using a semi-transmissive film (semi-transmissive material), which is opaque.
  • the area is used to form a first mask pattern
  • the semi-transmissive area and the opaque area are used to jointly form a second mask pattern.
  • the photoresist when the first mask pattern is exposed, the photoresist uses a negative photoresist; when the second mask pattern is exposed, the photoresist uses a positive photoresist.
  • the method for manufacturing an array substrate provided by the embodiment of the present invention first forms a first mask pattern on the substrate substrate by using an opaque region of the mask, and then forms a substrate on which the first mask pattern is formed.
  • Base The semi-transmissive region and the opaque region of the same mask plate form a second mask pattern on the board, which simplifies the manufacturing process of the array substrate and reduces the manufacturing cost compared with the existing array substrate manufacturing technology.
  • An embodiment of the present invention further provides an array substrate, as shown in FIG.
  • the array substrate is produced by the above manufacturing method.
  • an embodiment of the present invention provides a display panel including the array substrate as shown in FIG. 21 which is manufactured by the above manufacturing method. Therefore, the manufacturing process of the display panel is simpler and the manufacturing cost is lower.
  • an embodiment of the present invention provides a display device, which includes the above display panel. Therefore, the manufacturing process of the display device is simpler and the manufacturing cost is lower.
  • the display device may be any product or component having a display function such as a notebook computer, a mobile phone, a digital photo frame, a tablet computer, a navigator, a television, a display, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the invention.
  • the embodiment of the present invention provides a mask.
  • the mask 10 includes: a transparent substrate 101; a transparent substrate 101 is formed with a semi-transmissive region 102; and a semi-transparent region 102 is formed.
  • An opaque region 103 is formed on the substrate 101, and a region other than the semi-transmissive region 102 and the opaque region 103 on the transparent substrate 101 is the fully transparent region 104.
  • the opaque region 103 is used to form a first mask pattern of the array substrate, and the semi-transmissive region 102 and the opaque region 103 are used to form a second mask pattern of the array substrate.
  • the mask provided by the embodiment of the present invention forms a first mask pattern of the array substrate by using the opaque region by forming a semi-transmissive region, an opaque region, and a fully transparent region on the transparent substrate.
  • the use of the semi-transmissive region and the opaque region to form a second mask pattern of the array substrate simplifies the manufacturing process of the array substrate and reduces the manufacturing cost.
  • the mask further includes a semi-transparent film formed on the transparent substrate, and the semi-transmissive region is formed on the semi-permeable film.
  • the first mask pattern can be a via pattern.
  • the shape of the opaque region is any one of a rectangle, a square, a triangle, and a circle; the shape of the boundary of the semi-transmissive region is any one of a rectangle, a square, a triangle, and a circle.
  • the mask provided by the embodiment of the present invention forms a first mask pattern of the array substrate by using the opaque region by forming a semi-transmissive region, an opaque region, and a fully transparent region on the transparent substrate.
  • the use of the semi-transmissive region and the opaque region to form a second mask pattern of the array substrate simplifies the manufacturing process of the array substrate and reduces the manufacturing cost.

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Abstract

提供一种阵列基板的制造方法、由该方法制造的阵列基板、包括阵列基板的显示面板以及掩模板。阵列基板的制造方法包括：提供包括透明基板（101）的掩模板（10），透明基板（101）上形成有半透光区域（102）、形成在半透光区域（102）上的不透光区域（103）和除半透光区域（102）和不透光区域（103）之外的全透光区域（104）；在衬底基板（501）上采用掩模板（10）的不透光区域（103）形成第一掩膜图形（5001）；在形成有第一掩膜图形（5001）的衬底基板（501）上采用掩膜板（10）的半透光区域（102）和不透光区域（103）形成第二掩膜图形（5002）。

Description

阵列基板及其制造方法、显示面板、掩模板 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板的制造方法、由该方法制造的阵列基板、包括所述阵列基板的显示面板以及掩模板。
背景技术
薄膜晶体管液晶显示器(英文：Thin-film transistor liquid crystal display；简称：TFT-LCD)是多数液晶显示器的一种。在TFT-LCD的光刻工艺中，需要使用掩膜板进行图形制作。
使用掩膜板对TFT-LCD阵列基板进行构图的原理为：先将光刻胶涂覆在衬底基板上，接着利用光源照射掩膜板，透过掩膜板的透射光线使衬底基板上的光刻胶感光，再经过显影(通过化学作用将感光的光刻胶溶解掉)将未感光的光刻胶固化，最后经过刻蚀使衬底基板获得需要制作的图形。
由于现有技术中，每张掩膜板上的图形是固定不变的，即每张掩膜板唯一对应一种图形。由于阵列基板的制造过程需要在衬底基板上依次形成多个图形，需要购买与要形成的图形相对应的多个掩膜板，并且掩膜板的价格较为昂贵，因此，阵列基板的制造过程较繁琐，且制造成本较高。
发明内容
为了解决阵列基板的制造过程较繁琐，且制造成本较高的问题，本发明提供了一种阵列基板的制造方法、由该方法制造的阵列基板、包括这种阵列基板的显示面板以及掩模板。所述技术方案如下：
第一方面，提供了一种阵列基板的制造方法，所述方法包括：
提供包括透明基板的掩模板，所述透明基板上形成有半透光区域、形成在所述半透光区域上的不透光区域、和除所述半透光区域和所述不透光区域之外的全透光区域；
在衬底基板上采用所述掩模板的不透光区域形成第一掩膜图形；
在形成有所述第一掩膜图形的衬底基板上采用所述掩膜板的半透光区域和所述不透光区域形成第二掩膜图形。
可选的，所述在衬底基板上采用掩模板的不透光区域形成第一掩膜图形，包括：
在形成有源漏极金属图形的衬底基板上形成第一膜层；
在形成有所述第一膜层的衬底基板上涂覆负性光刻胶；
采用所述掩模板的不透光区域，且通过强光对涂覆有所述负性光刻胶的衬底基板进行曝光；
对曝光后的衬底基板进行显影、刻蚀，得到所述第一掩膜图形；
剥离所述负性光刻胶。
可选的，所述在形成有所述第一掩膜图形的衬底基板上采用所述掩膜板的半透光区域和所述不透光区域形成第二掩膜图形，包括：
在形成有所述第一掩膜图形的衬底基板上形成第二膜层；
在形成有所述第二膜层的衬底基板上涂覆正性光刻胶；
采用所述掩膜板的半透光区域和所述不透光区域，且通过弱光对涂覆有所述正性光刻胶的衬底基板进行曝光；
对曝光后的衬底基板进行显影、刻蚀，得到所述第二掩膜图形；
剥离所述正性光刻胶。
可选的，所述第一掩膜图形为过孔图形。
可选的，所述第一膜层为钝化层膜。
可选的，所述第二膜层为氧化铟锡膜。
可选的，所述不透光区域位于所述半透光区域内。
可选的，所述不透光区域的形状为长方形、正方形、三角形和圆形中的任意一种。
可选的，所述半透光区域边界的形状为长方形、正方形、三角形和圆形中的任意一种。
第二方面，提供了一种阵列基板，其采用如第一方面任一所述的方法制成。
第三方面，提供了一种显示面板，包括第二方面所述的阵列基板。
第四方面，提供了一种掩膜板，所述掩膜板包括：
透明基板，所述透明基板上形成有半透光区域、形成在所述半透光区域上的不透光区域和除所述半透光区域和所述不透光区域之外的全透光区域；
其中，所述不透光区域用于形成阵列基板的第一掩膜图形，所述半透光区域和所述不透光区域用于共同形成所述阵列基板的第二掩膜图形。
可选的，所述掩膜板还包括形成在所述透明基板上的半透膜，所述半透膜上形成所述半透光区域。
可选的，所述第一掩膜图形为过孔图形。
可选的，所述不透光区域的形状为长方形、正方形、三角形和圆形中的任意一种。
可选的，所述半透光区域边界的形状为长方形、正方形、三角形和圆形中的任意一种。
本发明提供了一种阵列基板及其制造方法、显示面板、显示装置、掩模板，先在衬底基板上采用掩模板的不透光区域形成第一掩膜图形，再在形成有第一掩膜图形的衬底基板上采用同一掩膜板的半透光区域和不透光区域形成第二掩膜图形，相较于现有的阵列基板制造技术，简化了阵列基板的制造过程，且降低了制造成本。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
图1是本发明实施例提供的阵列基板的制造方法的流程图；
图2是本发明实施例提供的掩膜板的结构示意图；
图3是本发明实施例提供的掩膜板的不透光区域形状和半透光区域边界形状的结构示意图；
图4是本发明实施例提供的另一种掩膜板的结构示意图；
图5是本发明实施例提供的形成第一掩膜图形方法的流程图；
图6是本发明实施例提供的形成有第一膜层的衬底基板的结构示意图；
图7是本发明实施例提供的在第一膜层上涂覆负性光刻胶的衬底基板的结构示意图；
图8是本发明实施例提供的通过强光对衬底基板进行曝光的结构示意图；
图9是本发明实施例提供的衬底基板在负性光刻胶溶解后的侧视图；
图10是本发明实施例提供的衬底基板在负性光刻胶溶解后的俯视图；
图11是本发明实施例提供的衬底基板在形成第一掩膜图形后的结构示意图；
图12是本发明实施例提供的衬底基板在剥离负性光刻胶后的侧视图；
图13是本发明实施例提供的衬底基板在剥离负性光刻胶后的俯视图；
图14是本发明实施例提供的在衬底基板上形成第二掩膜图形方法的流程图；
图15是本发明实施例提供的形成第二膜层的衬底基板的结构示意图；
图16是本发明实施例提供的涂覆正性光刻胶的衬底基板的结构示意图；
图17是本发明实施例提供的通过弱光对衬底基板进行曝光的结构示意图；
图18是本发明实施例提供的衬底基板在正性光刻胶溶解后的侧视图；
图19是本发明实施例提供的衬底基板在正性光刻胶溶解后的俯视图；
图20是本发明实施例提供的衬底基板在形成第二掩膜图形后的结构示意图；
图21是本发明实施例提供的衬底基板在剥离正性光刻胶后的侧视图；
图22是本发明实施例提供的衬底基板在剥离正性光刻胶后的俯视图。
通过上述附图，已示出本发明明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本发明构思的范围，而是通过参考特定实施例为本领域技术人员说明本发明的概念。
具体实施方式
下面结合附图，对本发明实施例的具体实施方式进行详细地说明。另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
本发明实施例提供了一种阵列基板的制造方法，如图1所示，该方法包括：
步骤100、提供包括透明基板的掩模板，所述透明基板上形成有半透光区域、形成在所述半透光区域上的不透光区域和除所述半透光区域和所述不透光区域之外的全透光区域。
步骤101、在衬底基板上采用掩模板的不透光区域形成第一掩膜图形，该 掩膜板包括：透明基板，透明基板上形成有半透光区域，形成有半透光区域的透明基板上形成有不透光区域，透明基板上除半透光区域和不透光区域之外的区域为全透光区域。
步骤102、在形成有第一掩膜图形的衬底基板上采用掩膜板的半透光区域和不透光区域形成第二掩膜图形。
本发明实施例提供的阵列基板的制造方法，先在衬底基板上采用掩模板的不透光区域形成第一掩膜图形，再在形成有第一掩膜图形的衬底基板上采用同一掩膜板的半透光区域和不透光区域形成第二掩膜图形，相较于现有的阵列基板制造技术，简化了阵列基板的制造过程，且降低了制造成本。
如图2所示，所述掩膜板10包括：透明基板101，透明基板101上形成有半透光区域102，形成有半透光区域102的透明基板101上形成有不透光区域103，透明基板101上除半透光区域102和不透光区域103之外的区域为全透光区域104。不透光区域103位于半透光区域102内。此外，不透光区域的形状可以为长方形、正方形、三角形和圆形中的任意一种。半透光区域边界的形状可以为长方形、正方形、三角形和圆形中的任意一种。图3示出了不透光区域的一种形状与半透光区域边界的一种形状的示意图，图3中的不透光区域103的形状为三角形，半透光区域102边界的形状为圆形。图3中的由104表示的区域是全透光区域。
示例的，第一掩膜图形可以为过孔图形。第二掩膜图形可以为正常版图图形。本发明实施例以第一掩膜图形(过孔图形)为钝化层图形，第二掩膜图形为2氧化铟锡(英文：Indium-Tin Oxide；简称：ITO)图形为例进行详细说明。形成这两个掩膜图形对应的掩膜板10的结构示意图如图4所示。图4中，102为半透光区域，103为不透光区域，104为全透光区域。
步骤101如图5所示，可以包括：
步骤1011、在形成有源漏极金属图形的衬底基板上形成第一膜层。
示例的，第一膜层可以为钝化层膜。如图6所示，在形成有源漏极金属图形504的衬底基板501上形成第一膜层502，即钝化层膜。
步骤1012、在形成有第一膜层的衬底基板上涂覆负性光刻胶。
如图7所示，在形成有第一膜层502即钝化层膜的衬底基板501上涂覆负性光刻胶503。图7中的504为源漏极金属图形。负性光刻胶在感光之后会变为不可溶，显影时未感光的部分会溶解于显影液。
步骤1013、采用掩模板的不透光区域，且通过强光对涂覆有负性光刻胶的衬底基板进行曝光。
如图8所示，采用掩膜板10的不透光区域103，且通过强光对涂覆有负性光刻胶503的衬底基板501进行曝光。强光对于掩膜板的半透光区域的透过率为1。采用强光对涂覆有负性光刻胶的衬底基板进行曝光。此时，不透光区域不能透光，对应的负性光刻胶无法感光。
步骤1014、对曝光后的衬底基板进行显影、刻蚀得到第一掩膜图形。
如图9所示，不透光区域对应的负性光刻胶无法感光，因此对曝光后的衬底基板进行显影，未感光的负性光刻胶溶解于显影液。图9为衬底基板在未感光的负性光刻胶被溶解后的侧视图，由501表示衬底基板，由502表示钝化层膜，由503表示负性光刻胶，由504表示源漏极金属图形。图10为图9对应的俯视图，图10中由502表示钝化层膜，由503表示负性光刻胶。经过刻蚀，即可得到第一掩膜图形即钝化层图形5001，如图11所示。
步骤1015、剥离负性光刻胶。
剥离负性光刻胶形成图12所示的结构。图12为衬底基板在剥离了负性光刻胶后的侧视图，由5001表示钝化层图形，由501表示衬底基板，由504表示源漏极金属图形。图13为图12对应的俯视图，图13中由504表示源漏极金属图形，由5001表示钝化层图形。
如图14所示，步骤102可以包括：
步骤1021、在形成有第一掩膜图形的衬底基板上形成第二膜层。
如图15所示，在形成有第一掩膜图形5001即钝化层图形的衬底基板501上形成第二膜层505即2ITO膜。
步骤1022、在形成有第二膜层的衬底基板上涂覆正性光刻胶。
如图16所示，在形成有2ITO膜505的衬底基板501上涂覆正性光刻胶506。图16中由504表示源漏极金属图形，由5001表示钝化层图形。与负性光刻胶相反，正性光刻胶感光之后会变为可溶，显影时感光的部分会溶解于显影液。
步骤1023、采用掩膜板的半透光区域和不透光区域，且通过弱光对涂覆有正性光刻胶的衬底基板进行曝光。
如图17所示，采用掩膜板10的不透光区域103和半透光区域102，且通过弱光对涂覆有正性光刻胶506的衬底基板501进行曝光。弱光对于掩膜板的 半透光区域的透过率为2/5～1/2。采用弱光对涂覆有正性光刻胶的衬底基板进行曝光，此时，不透光区域103无法透光，半透光区域102部分透光，对应的正性光刻胶无法全部感光。
步骤1024、对曝光后的衬底基板进行显影、刻蚀得到第二掩膜图形。
如图18所示，2ITO图形对应的正性光刻胶无法全部感光，因此对曝光后的衬底基板进行显影，无法全部感光的正性光刻胶得到保留。图18为衬底基板在正性光刻胶溶解后的侧视图，图18中由501表示衬底基板，由5001表示钝化层图形，由505表示2ITO膜，由506表示正性光刻胶，由504表示源漏极金属图形。图19为图18对应的俯视图，图19中的由505表示2ITO膜，由506表示正性光刻胶。经过刻蚀，即可得到第二掩膜图形即2ITO图形5002，如图20所示，图20中由501表示衬底基板，由5001表示钝化层图形，由504表示源漏极金属图形，由506表示正性光刻胶。
步骤1025、剥离正性光刻胶。
最后剥离正性光刻胶形成图21所示的结构，图21中由501表示衬底基板，由5001表示钝化层图形，由504表示源漏极金属图形，由5002表示2ITO图形。图21为衬底基板在剥离了正性光刻胶后的侧视图，图22为图21对应的俯视图，图22中由5001表示钝化层图形，由5002表示2ITO图形。
在TFT-LCD的Array工艺中，都需要使用掩膜板进行图形制作，而掩膜板的价格较为昂贵：数万到数十万美元，是新产品开发的主要成本之一。本发明实施例提供了一种节省掩膜板的技术，通过在掩膜板上使用半透膜技术，在工艺上使用正性光刻胶和负性光刻胶，实现了将两张掩膜板结合为一张掩膜板的目的，为每一款产品节省了至少一张掩膜板，从而节省了掩膜板的使用数量，大大节省了生产成本。本发明实施例中的两个掩膜图形为包含和被包含的关系，第一掩膜图形应该小于第二掩膜图形，且被第二掩膜图形全部覆盖。此外，第一掩膜图形为过孔图形，第二掩膜图形为正常版图图形，采用半透膜(半透光材料)将两个掩膜图形制作在一张掩膜板上，不透光区域用于形成第一掩膜图形，半透光区域和不透光区域用于共同形成第二掩膜图形。与掩膜板图形设计相对应，第一掩膜图形曝光时，光刻胶采用负性光刻胶；第二掩膜图形曝光时，光刻胶采用正性光刻胶。
综上所述，本发明实施例提供的阵列基板的制造方法，先在衬底基板上采用掩模板的不透光区域形成第一掩膜图形，再在形成有第一掩膜图形的衬底基 板上采用同一掩膜板的半透光区域和不透光区域形成第二掩膜图形，相较于现有的阵列基板制造技术，简化了阵列基板的制造过程，且降低了制造成本。
本发明实施例还提供了一种阵列基板，如图21所示。该阵列基板采用上述制造方法制成。
相应的，本发明实施例提供了一种显示面板，该显示面板包括由上述制造方法制成的如图21所示的阵列基板。因此，该显示面板的制造过程更简单，且制造成本更低。
相应的，本发明实施例提供了一种显示装置，该显示装置包括上述显示面板。因此，该显示装置的制造过程更简单，且制造成本更低。示例的，该显示装置可以为：笔记本电脑、手机、数码相框、平板电脑、导航仪、电视机、显示器等任何具有显示功能的产品或部件。对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
本发明实施例提供了一种掩膜板，如图2所示，该掩膜板10包括：透明基板101；透明基板101上形成有半透光区域102；形成有半透光区域102的透明基板101上形成有不透光区域103，透明基板101上除半透光区域102和不透光区域103之外的区域为全透光区域104。
其中，不透光区域103用于形成阵列基板的第一掩膜图形，半透光区域102和不透光区域103用于共同形成阵列基板的第二掩膜图形。
综上所述，本发明实施例提供的掩膜板，通过在透明基板上形成半透光区域、不透光区域和全透光区域，使用不透光区域形成阵列基板的第一掩膜图形，使用半透光区域和不透光区域共同形成阵列基板的第二掩膜图形，简化了阵列基板的制造过程，且降低了制造成本。
进一步的，所述掩膜板还包括形成在所述透明基板上的半透膜，所述半透膜上形成所述半透光区域。。
第一掩膜图形可以为过孔图形。不透光区域的形状为长方形、正方形、三角形和圆形中的任意一种；半透光区域边界的形状为长方形、正方形、三角形和圆形中的任意一种。
综上所述，本发明实施例提供的掩膜板，通过在透明基板上形成半透光区域、不透光区域和全透光区域，使用不透光区域形成阵列基板的第一掩膜图形， 使用半透光区域和不透光区域共同形成阵列基板的第二掩膜图形，简化了阵列基板的制造过程，且降低了制造成本。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (16)

  1. 一种阵列基板的制造方法，其特征在于，所述方法包括以下步骤：
    提供包括透明基板的掩模板，所述透明基板上形成有半透光区域、形成在所述半透光区域上的不透光区域和除所述半透光区域和所述不透光区域之外的全透光区域；
    在衬底基板上采用所述掩模板的不透光区域形成第一掩膜图形；
    在形成有所述第一掩膜图形的衬底基板上采用所述掩膜板的半透光区域和所述不透光区域形成第二掩膜图形。
  2. 根据权利要求1所述的方法，其特征在于，所述在衬底基板上采用掩模板的不透光区域形成第一掩膜图形的步骤包括：
    在形成有源漏极金属图形的衬底基板上形成第一膜层；
    在形成有所述第一膜层的衬底基板上涂覆负性光刻胶；
    采用所述掩模板的不透光区域，且通过强光对涂覆有所述负性光刻胶的衬底基板进行曝光；
    对曝光后的衬底基板进行显影、刻蚀，得到所述第一掩膜图形；
    剥离所述负性光刻胶。
  3. 根据权利要求2所述的方法，其特征在于，所述在形成有所述第一掩膜图形的衬底基板上采用所述掩膜板的半透光区域和所述不透光区域形成第二掩膜图形的步骤包括：
    在形成有所述第一掩膜图形的衬底基板上形成第二膜层；
    在形成有所述第二膜层的衬底基板上涂覆正性光刻胶；
    采用所述掩膜板的半透光区域和所述不透光区域，且通过弱光对涂覆有所述正性光刻胶的衬底基板进行曝光；
    对曝光后的衬底基板进行显影、刻蚀得到所述第二掩膜图形；
    剥离所述正性光刻胶。
  4. 根据权利要求1至3任一所述的方法，其特征在于，
    所述第一掩膜图形为过孔图形。
  5. 根据权利要求2所述的方法，其特征在于，
    所述第一膜层为钝化层膜。
  6. 根据权利要求3所述的方法，其特征在于，
    所述第二膜层为氧化铟锡膜。
  7. 根据权利要求1所述的方法，其特征在于，
    所述不透光区域位于所述半透光区域内。
  8. 根据权利要求1所述的方法，其特征在于，
    所述不透光区域的形状为长方形、正方形、三角形和圆形中的任意一种。
  9. 根据权利要求1所述的方法，其特征在于，
    所述半透光区域边界的形状为长方形、正方形、三角形和圆形中的任意一种。
  10. 一种阵列基板，其特征在于，其采用根据权利要求1至9任一项所述的方法制成。
  11. 一种显示面板，其特征在于，包括根据权利要求10所述的阵列基板。
  12. 一种掩膜板，其特征在于，所述掩膜板包括：
    透明基板，所述透明基板上形成有半透光区域、形成在所述半透光区域上的不透光区域和除所述半透光区域和所述不透光区域之外的全透光区域；
    其中，所述不透光区域用于形成阵列基板的第一掩膜图形，所述半透光区域和所述不透光区域用于共同形成所述阵列基板的第二掩膜图形。
  13. 根据权利要求12所述的掩膜板，其特征在于，
    所述掩膜板还包括形成在所述透明基板上的半透膜，所述半透膜上形成所述半透光区域。
  14. 根据权利要求12或13所述的掩膜板，其特征在于，
    所述第一掩膜图形为过孔图形。
  15. 根据权利要求12或13所述的掩膜板，其特征在于，
    所述不透光区域的形状为长方形、正方形、三角形和圆形中的任意一种。
  16. 根据权利要求12或13所述的掩膜板，其特征在于，
    所述半透光区域边界的形状为长方形、正方形、三角形和圆形中的任意一种。
PCT/CN2015/089363 2015-05-18 2015-09-10 阵列基板及其制造方法、显示面板、掩模板 Ceased WO2016183968A1 (zh)

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